Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46440

1

T4

574

T11

183

T26

342

auto[1]

16592

1

T4

51

T5

11

T9

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46032

1

T4

423

T5

11

T9

13

auto[1]

17000

1

T4

202

T11

64

T26

147

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32663	1			T4	312		T5	11		T9	13
others[1]	5304	1			T4	49		T11	17		T24	18
others[2]	5286	1			T4	51		T11	17		T24	25
others[3]	6029	1			T4	64		T11	32		T24	30
interest[1]	3440	1			T4	32		T11	10		T24	19
interest[4]	21311	1			T4	199		T5	11		T9	13
interest[64]	10310	1			T4	117		T11	42		T24	51

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15219	1			T4	188		T11	61		T26	105
auto[0]	auto[0]	others[1]	2499	1			T4	21		T11	6		T26	19
auto[0]	auto[0]	others[2]	2473	1			T4	27		T11	11		T26	12
auto[0]	auto[0]	others[3]	2750	1			T4	43		T11	18		T26	14
auto[0]	auto[0]	interest[1]	1659	1			T4	18		T11	5		T26	16
auto[0]	auto[0]	interest[4]	9915	1			T4	123		T11	40		T26	69
auto[0]	auto[0]	interest[64]	4840	1			T4	75		T11	18		T26	29
auto[0]	auto[1]	others[0]	8657	1			T4	20		T5	11		T9	13
auto[0]	auto[1]	others[1]	1358	1			T4	7		T11	5		T24	18
auto[0]	auto[1]	others[2]	1409	1			T4	6		T11	1		T24	25
auto[0]	auto[1]	others[3]	1611	1			T4	6		T11	5		T24	30
auto[0]	auto[1]	interest[1]	873	1			T4	3		T11	2		T24	19
auto[0]	auto[1]	interest[4]	5713	1			T4	12		T5	11		T9	13
auto[0]	auto[1]	interest[64]	2684	1			T4	9		T11	4		T24	51
auto[1]	auto[0]	others[0]	8787	1			T4	104		T11	21		T26	75
auto[1]	auto[0]	others[1]	1447	1			T4	21		T11	6		T26	6
auto[1]	auto[0]	others[2]	1404	1			T4	18		T11	5		T26	16
auto[1]	auto[0]	others[3]	1668	1			T4	15		T11	9		T26	18
auto[1]	auto[0]	interest[1]	908	1			T4	11		T11	3		T26	4
auto[1]	auto[0]	interest[4]	5683	1			T4	64		T11	17		T26	42
auto[1]	auto[0]	interest[64]	2786	1			T4	33		T11	20		T26	28

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal