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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T1032 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.488915821 Aug 01 06:41:16 PM PDT 24 Aug 01 06:41:19 PM PDT 24 103281290 ps
T127 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2139864047 Aug 01 06:41:31 PM PDT 24 Aug 01 06:41:35 PM PDT 24 687944761 ps
T73 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1958423477 Aug 01 06:40:38 PM PDT 24 Aug 01 06:40:40 PM PDT 24 73872231 ps
T1033 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2338706414 Aug 01 06:41:29 PM PDT 24 Aug 01 06:41:31 PM PDT 24 111144149 ps
T1034 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2074729431 Aug 01 06:41:33 PM PDT 24 Aug 01 06:41:35 PM PDT 24 48428160 ps
T1035 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1839001673 Aug 01 06:41:19 PM PDT 24 Aug 01 06:41:22 PM PDT 24 217713083 ps
T1036 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2717759640 Aug 01 06:41:42 PM PDT 24 Aug 01 06:41:43 PM PDT 24 34196551 ps
T128 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3604289978 Aug 01 06:41:18 PM PDT 24 Aug 01 06:41:21 PM PDT 24 569966162 ps
T1037 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3050830164 Aug 01 06:41:45 PM PDT 24 Aug 01 06:41:46 PM PDT 24 18754563 ps
T103 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2814437366 Aug 01 06:41:30 PM PDT 24 Aug 01 06:41:32 PM PDT 24 89814258 ps
T104 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.179198120 Aug 01 06:41:06 PM PDT 24 Aug 01 06:41:08 PM PDT 24 393731838 ps
T129 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1956749806 Aug 01 06:41:29 PM PDT 24 Aug 01 06:41:37 PM PDT 24 5956635122 ps
T157 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.273087255 Aug 01 06:41:31 PM PDT 24 Aug 01 06:41:54 PM PDT 24 832391399 ps
T105 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2391684044 Aug 01 06:41:07 PM PDT 24 Aug 01 06:41:10 PM PDT 24 95783122 ps
T106 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.287205691 Aug 01 06:41:16 PM PDT 24 Aug 01 06:41:18 PM PDT 24 1222652513 ps
T158 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2982973498 Aug 01 06:41:17 PM PDT 24 Aug 01 06:41:24 PM PDT 24 433155546 ps
T1038 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2728574618 Aug 01 06:41:31 PM PDT 24 Aug 01 06:41:34 PM PDT 24 216500669 ps
T160 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1340881349 Aug 01 06:40:51 PM PDT 24 Aug 01 06:40:58 PM PDT 24 196403222 ps
T1039 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3502416443 Aug 01 06:41:44 PM PDT 24 Aug 01 06:41:45 PM PDT 24 174006139 ps
T130 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3888048841 Aug 01 06:41:22 PM PDT 24 Aug 01 06:41:24 PM PDT 24 49568631 ps
T1040 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1980005812 Aug 01 06:41:41 PM PDT 24 Aug 01 06:41:42 PM PDT 24 24584027 ps
T1041 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3197376188 Aug 01 06:41:43 PM PDT 24 Aug 01 06:41:44 PM PDT 24 26986970 ps
T93 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.977932269 Aug 01 06:41:16 PM PDT 24 Aug 01 06:41:20 PM PDT 24 53822950 ps
T1042 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1569271764 Aug 01 06:41:39 PM PDT 24 Aug 01 06:41:41 PM PDT 24 99070818 ps
T1043 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2177189522 Aug 01 06:40:38 PM PDT 24 Aug 01 06:40:39 PM PDT 24 14193533 ps
T1044 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2998845827 Aug 01 06:41:42 PM PDT 24 Aug 01 06:41:43 PM PDT 24 59776272 ps
T1045 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3844368640 Aug 01 06:40:51 PM PDT 24 Aug 01 06:40:53 PM PDT 24 56760198 ps
T1046 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2246022068 Aug 01 06:41:21 PM PDT 24 Aug 01 06:41:21 PM PDT 24 47757440 ps
T107 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.382907413 Aug 01 06:41:39 PM PDT 24 Aug 01 06:41:41 PM PDT 24 29053094 ps
T152 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4265810604 Aug 01 06:40:41 PM PDT 24 Aug 01 06:40:55 PM PDT 24 3686485083 ps
T108 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2644378405 Aug 01 06:41:05 PM PDT 24 Aug 01 06:41:26 PM PDT 24 1203071087 ps
T161 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1334776212 Aug 01 06:41:19 PM PDT 24 Aug 01 06:41:35 PM PDT 24 3523836564 ps
T92 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3093237272 Aug 01 06:41:19 PM PDT 24 Aug 01 06:41:22 PM PDT 24 528575812 ps
T1047 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2074291899 Aug 01 06:40:52 PM PDT 24 Aug 01 06:40:54 PM PDT 24 72381299 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4080263409 Aug 01 06:40:40 PM PDT 24 Aug 01 06:40:44 PM PDT 24 207584984 ps
T1049 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3699842819 Aug 01 06:40:51 PM PDT 24 Aug 01 06:41:03 PM PDT 24 812763748 ps
T1050 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2847382378 Aug 01 06:41:42 PM PDT 24 Aug 01 06:41:43 PM PDT 24 28284092 ps
T153 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1304662196 Aug 01 06:41:18 PM PDT 24 Aug 01 06:41:31 PM PDT 24 2090758513 ps
T1051 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2624069861 Aug 01 06:41:08 PM PDT 24 Aug 01 06:41:09 PM PDT 24 31849702 ps
T1052 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2006729172 Aug 01 06:41:39 PM PDT 24 Aug 01 06:41:43 PM PDT 24 320992691 ps
T1053 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1742210604 Aug 01 06:41:17 PM PDT 24 Aug 01 06:41:18 PM PDT 24 19916928 ps
T1054 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3593467501 Aug 01 06:40:52 PM PDT 24 Aug 01 06:40:54 PM PDT 24 47439307 ps
T154 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3747605821 Aug 01 06:41:07 PM PDT 24 Aug 01 06:41:20 PM PDT 24 568940795 ps
T74 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.836454097 Aug 01 06:40:52 PM PDT 24 Aug 01 06:40:54 PM PDT 24 36520122 ps
T1055 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1267093335 Aug 01 06:41:20 PM PDT 24 Aug 01 06:41:21 PM PDT 24 15193001 ps
T155 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2991946502 Aug 01 06:41:43 PM PDT 24 Aug 01 06:42:04 PM PDT 24 1033708951 ps
T1056 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3949860611 Aug 01 06:41:39 PM PDT 24 Aug 01 06:41:40 PM PDT 24 32079326 ps
T1057 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1657100966 Aug 01 06:41:21 PM PDT 24 Aug 01 06:41:23 PM PDT 24 175934659 ps
T1058 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3314027601 Aug 01 06:41:17 PM PDT 24 Aug 01 06:41:22 PM PDT 24 1688736882 ps
T1059 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3734164013 Aug 01 06:41:32 PM PDT 24 Aug 01 06:41:34 PM PDT 24 263783324 ps
T1060 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1078593755 Aug 01 06:41:39 PM PDT 24 Aug 01 06:41:40 PM PDT 24 16923519 ps
T1061 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3894027023 Aug 01 06:41:32 PM PDT 24 Aug 01 06:41:32 PM PDT 24 12294814 ps
T1062 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3824318398 Aug 01 06:41:10 PM PDT 24 Aug 01 06:41:11 PM PDT 24 174973558 ps
T1063 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.165349954 Aug 01 06:41:19 PM PDT 24 Aug 01 06:41:21 PM PDT 24 113080987 ps
T1064 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1336646003 Aug 01 06:41:29 PM PDT 24 Aug 01 06:41:32 PM PDT 24 98800373 ps
T109 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3105253558 Aug 01 06:40:38 PM PDT 24 Aug 01 06:40:54 PM PDT 24 1537111593 ps
T110 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2437381541 Aug 01 06:41:21 PM PDT 24 Aug 01 06:41:23 PM PDT 24 128123323 ps
T1065 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1484634280 Aug 01 06:41:08 PM PDT 24 Aug 01 06:41:12 PM PDT 24 295721461 ps
T1066 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2906536618 Aug 01 06:41:40 PM PDT 24 Aug 01 06:41:41 PM PDT 24 19221841 ps
T1067 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1667781495 Aug 01 06:40:43 PM PDT 24 Aug 01 06:40:44 PM PDT 24 65287326 ps
T1068 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1030295798 Aug 01 06:41:40 PM PDT 24 Aug 01 06:41:41 PM PDT 24 27786287 ps
T1069 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3426623673 Aug 01 06:41:21 PM PDT 24 Aug 01 06:41:22 PM PDT 24 19484506 ps
T1070 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3568280737 Aug 01 06:40:53 PM PDT 24 Aug 01 06:40:55 PM PDT 24 150178307 ps
T91 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2565800489 Aug 01 06:41:28 PM PDT 24 Aug 01 06:41:32 PM PDT 24 124796556 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1771517645 Aug 01 06:40:41 PM PDT 24 Aug 01 06:40:42 PM PDT 24 63606309 ps
T1072 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1206142371 Aug 01 06:40:40 PM PDT 24 Aug 01 06:40:40 PM PDT 24 11615464 ps
T1073 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2052888634 Aug 01 06:40:53 PM PDT 24 Aug 01 06:40:54 PM PDT 24 10960578 ps
T150 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1270526519 Aug 01 06:40:57 PM PDT 24 Aug 01 06:41:03 PM PDT 24 483667276 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4088601346 Aug 01 06:40:41 PM PDT 24 Aug 01 06:40:44 PM PDT 24 46025678 ps
T1075 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4063300851 Aug 01 06:41:30 PM PDT 24 Aug 01 06:41:38 PM PDT 24 597510650 ps
T1076 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1030879719 Aug 01 06:41:42 PM PDT 24 Aug 01 06:41:43 PM PDT 24 104245769 ps
T1077 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3217834418 Aug 01 06:40:52 PM PDT 24 Aug 01 06:40:53 PM PDT 24 37865613 ps
T1078 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1360691307 Aug 01 06:40:52 PM PDT 24 Aug 01 06:40:55 PM PDT 24 44202088 ps
T1079 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2318905991 Aug 01 06:41:20 PM PDT 24 Aug 01 06:41:22 PM PDT 24 160501419 ps
T1080 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3903938494 Aug 01 06:41:08 PM PDT 24 Aug 01 06:41:33 PM PDT 24 929140598 ps
T156 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2977771107 Aug 01 06:41:44 PM PDT 24 Aug 01 06:41:51 PM PDT 24 98657131 ps
T159 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2311707166 Aug 01 06:41:32 PM PDT 24 Aug 01 06:41:44 PM PDT 24 212589839 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1662512619 Aug 01 06:40:50 PM PDT 24 Aug 01 06:40:51 PM PDT 24 24582063 ps
T1082 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1299531148 Aug 01 06:41:06 PM PDT 24 Aug 01 06:41:09 PM PDT 24 51801047 ps
T1083 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.631877531 Aug 01 06:40:42 PM PDT 24 Aug 01 06:40:55 PM PDT 24 3298046704 ps
T1084 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3813946976 Aug 01 06:41:32 PM PDT 24 Aug 01 06:41:33 PM PDT 24 139038726 ps
T1085 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3346821347 Aug 01 06:41:30 PM PDT 24 Aug 01 06:41:31 PM PDT 24 14746170 ps
T151 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1601066983 Aug 01 06:41:28 PM PDT 24 Aug 01 06:41:31 PM PDT 24 70051779 ps
T1086 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.657808160 Aug 01 06:41:44 PM PDT 24 Aug 01 06:41:45 PM PDT 24 32911025 ps
T1087 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2231280525 Aug 01 06:41:32 PM PDT 24 Aug 01 06:41:33 PM PDT 24 132818965 ps
T1088 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2468169729 Aug 01 06:41:18 PM PDT 24 Aug 01 06:41:20 PM PDT 24 331204485 ps
T1089 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4148436317 Aug 01 06:41:32 PM PDT 24 Aug 01 06:41:36 PM PDT 24 1029987051 ps
T1090 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2629329082 Aug 01 06:41:40 PM PDT 24 Aug 01 06:41:41 PM PDT 24 55110297 ps
T1091 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3470916753 Aug 01 06:41:16 PM PDT 24 Aug 01 06:41:19 PM PDT 24 556733658 ps
T1092 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3261241600 Aug 01 06:40:41 PM PDT 24 Aug 01 06:40:43 PM PDT 24 349474894 ps
T1093 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1267809622 Aug 01 06:41:17 PM PDT 24 Aug 01 06:41:31 PM PDT 24 1595699978 ps
T1094 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1971610803 Aug 01 06:41:21 PM PDT 24 Aug 01 06:41:25 PM PDT 24 2638352951 ps
T1095 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1810684793 Aug 01 06:41:06 PM PDT 24 Aug 01 06:41:07 PM PDT 24 104983541 ps
T1096 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.546191018 Aug 01 06:41:32 PM PDT 24 Aug 01 06:41:36 PM PDT 24 589155918 ps
T1097 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.590221038 Aug 01 06:41:39 PM PDT 24 Aug 01 06:41:40 PM PDT 24 37832084 ps
T1098 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.266759794 Aug 01 06:41:50 PM PDT 24 Aug 01 06:41:51 PM PDT 24 55466997 ps
T1099 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2250724777 Aug 01 06:41:39 PM PDT 24 Aug 01 06:41:40 PM PDT 24 48065244 ps
T1100 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1606544752 Aug 01 06:41:06 PM PDT 24 Aug 01 06:41:08 PM PDT 24 38054153 ps
T1101 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1982509168 Aug 01 06:41:31 PM PDT 24 Aug 01 06:41:35 PM PDT 24 226099707 ps
T1102 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2006154172 Aug 01 06:41:31 PM PDT 24 Aug 01 06:41:35 PM PDT 24 166269206 ps
T1103 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2235383710 Aug 01 06:41:06 PM PDT 24 Aug 01 06:41:07 PM PDT 24 27392366 ps
T1104 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1381929061 Aug 01 06:41:39 PM PDT 24 Aug 01 06:41:40 PM PDT 24 38661418 ps
T1105 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2690331928 Aug 01 06:41:18 PM PDT 24 Aug 01 06:41:26 PM PDT 24 449306520 ps
T1106 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.511484578 Aug 01 06:41:08 PM PDT 24 Aug 01 06:41:16 PM PDT 24 734261865 ps
T1107 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3318738633 Aug 01 06:41:40 PM PDT 24 Aug 01 06:41:41 PM PDT 24 30500523 ps
T1108 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2426131 Aug 01 06:41:33 PM PDT 24 Aug 01 06:41:36 PM PDT 24 91156808 ps
T1109 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2333817333 Aug 01 06:41:43 PM PDT 24 Aug 01 06:41:43 PM PDT 24 11703273 ps
T1110 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2684166497 Aug 01 06:41:28 PM PDT 24 Aug 01 06:41:30 PM PDT 24 61547298 ps
T1111 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3389626187 Aug 01 06:41:08 PM PDT 24 Aug 01 06:41:12 PM PDT 24 118761296 ps
T1112 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3139967779 Aug 01 06:41:41 PM PDT 24 Aug 01 06:41:41 PM PDT 24 13386708 ps
T1113 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2716064805 Aug 01 06:41:49 PM PDT 24 Aug 01 06:41:50 PM PDT 24 45222980 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4248531045 Aug 01 06:41:07 PM PDT 24 Aug 01 06:41:08 PM PDT 24 72608153 ps
T1115 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2363450474 Aug 01 06:41:30 PM PDT 24 Aug 01 06:41:32 PM PDT 24 58384750 ps
T75 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.986371125 Aug 01 06:41:06 PM PDT 24 Aug 01 06:41:07 PM PDT 24 32516264 ps
T1116 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.547293551 Aug 01 06:41:07 PM PDT 24 Aug 01 06:41:12 PM PDT 24 371125091 ps
T1117 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.305990640 Aug 01 06:40:42 PM PDT 24 Aug 01 06:40:43 PM PDT 24 13912028 ps
T1118 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3111074004 Aug 01 06:41:41 PM PDT 24 Aug 01 06:41:43 PM PDT 24 80853614 ps
T1119 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.407712606 Aug 01 06:40:56 PM PDT 24 Aug 01 06:40:57 PM PDT 24 22627090 ps
T162 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1986883996 Aug 01 06:41:30 PM PDT 24 Aug 01 06:41:44 PM PDT 24 1359062325 ps
T1120 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3680629714 Aug 01 06:41:33 PM PDT 24 Aug 01 06:41:37 PM PDT 24 324932141 ps
T1121 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1806987279 Aug 01 06:40:39 PM PDT 24 Aug 01 06:40:40 PM PDT 24 32490149 ps
T1122 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2846437208 Aug 01 06:41:05 PM PDT 24 Aug 01 06:41:18 PM PDT 24 622593977 ps
T1123 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.129969999 Aug 01 06:41:40 PM PDT 24 Aug 01 06:41:43 PM PDT 24 1025879677 ps
T1124 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1360490718 Aug 01 06:41:17 PM PDT 24 Aug 01 06:41:20 PM PDT 24 120092203 ps
T1125 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1754150217 Aug 01 06:41:43 PM PDT 24 Aug 01 06:41:43 PM PDT 24 40580317 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1227467235 Aug 01 06:40:39 PM PDT 24 Aug 01 06:41:19 PM PDT 24 3766372632 ps
T1127 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2151810428 Aug 01 06:41:53 PM PDT 24 Aug 01 06:41:54 PM PDT 24 36242076 ps
T1128 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1795674307 Aug 01 06:40:42 PM PDT 24 Aug 01 06:40:57 PM PDT 24 1226856705 ps
T1129 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3489109958 Aug 01 06:41:42 PM PDT 24 Aug 01 06:41:43 PM PDT 24 14541432 ps
T1130 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2076854647 Aug 01 06:41:32 PM PDT 24 Aug 01 06:41:34 PM PDT 24 36076344 ps
T1131 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.156667377 Aug 01 06:41:28 PM PDT 24 Aug 01 06:41:29 PM PDT 24 64357423 ps

Test location /workspace/coverage/default/34.spi_device_stress_all.1776741399
Short name T4
Test name
Test status
Simulation time 659058205080 ps
CPU time 539.01 seconds
Started Aug 01 06:47:25 PM PDT 24
Finished Aug 01 06:56:24 PM PDT 24
Peak memory 273688 kb
Host smart-80bacc31-a193-4075-ad45-40ad9a701f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776741399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1776741399
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1849558667
Short name T21
Test name
Test status
Simulation time 63997452095 ps
CPU time 536.62 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:55:56 PM PDT 24
Peak memory 249668 kb
Host smart-fd62bcdc-35c1-455c-a46f-2759e2f0bbd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849558667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1849558667
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.132562293
Short name T13
Test name
Test status
Simulation time 18780784324 ps
CPU time 222.81 seconds
Started Aug 01 06:46:41 PM PDT 24
Finished Aug 01 06:50:24 PM PDT 24
Peak memory 281492 kb
Host smart-5987bf99-1e57-4e5e-b0d0-856238d40d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132562293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.132562293
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.909280811
Short name T96
Test name
Test status
Simulation time 326415380 ps
CPU time 1.49 seconds
Started Aug 01 06:41:30 PM PDT 24
Finished Aug 01 06:41:31 PM PDT 24
Peak memory 215160 kb
Host smart-4a1650c7-3c73-4038-babb-bf172a6a3587
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909280811 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.909280811
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1423057876
Short name T57
Test name
Test status
Simulation time 23227902 ps
CPU time 0.74 seconds
Started Aug 01 06:44:54 PM PDT 24
Finished Aug 01 06:44:55 PM PDT 24
Peak memory 216376 kb
Host smart-a9dbed51-0870-4a58-a931-38f983027e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423057876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1423057876
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1064567149
Short name T166
Test name
Test status
Simulation time 4658287584 ps
CPU time 127.87 seconds
Started Aug 01 06:48:06 PM PDT 24
Finished Aug 01 06:50:14 PM PDT 24
Peak memory 264644 kb
Host smart-f9d25193-8e39-404d-a788-19119999ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064567149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1064567149
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3547376366
Short name T175
Test name
Test status
Simulation time 4693435799 ps
CPU time 112.73 seconds
Started Aug 01 06:47:42 PM PDT 24
Finished Aug 01 06:49:35 PM PDT 24
Peak memory 249656 kb
Host smart-cdd6932a-6a8c-4f2a-a7e6-3e5e3d53c6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547376366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3547376366
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3366556734
Short name T188
Test name
Test status
Simulation time 192025588124 ps
CPU time 1038.88 seconds
Started Aug 01 06:44:58 PM PDT 24
Finished Aug 01 07:02:17 PM PDT 24
Peak memory 306940 kb
Host smart-5a24c180-ae6c-4c42-8a7e-d17626c0abaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366556734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3366556734
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1168924047
Short name T16
Test name
Test status
Simulation time 64606292 ps
CPU time 1.1 seconds
Started Aug 01 06:44:50 PM PDT 24
Finished Aug 01 06:44:52 PM PDT 24
Peak memory 236776 kb
Host smart-becac05f-685d-4197-81cb-82164d717f07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168924047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1168924047
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.306410140
Short name T6
Test name
Test status
Simulation time 1205104958 ps
CPU time 8.22 seconds
Started Aug 01 06:48:02 PM PDT 24
Finished Aug 01 06:48:10 PM PDT 24
Peak memory 241188 kb
Host smart-c15b5d83-2055-4749-a4e9-8d94f90e3cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306410140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.306410140
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1415791237
Short name T182
Test name
Test status
Simulation time 49445262443 ps
CPU time 117.17 seconds
Started Aug 01 06:48:03 PM PDT 24
Finished Aug 01 06:50:01 PM PDT 24
Peak memory 261720 kb
Host smart-ee514783-e930-4047-96a9-14e202454647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415791237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1415791237
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.775143416
Short name T26
Test name
Test status
Simulation time 54749694556 ps
CPU time 262.86 seconds
Started Aug 01 06:45:02 PM PDT 24
Finished Aug 01 06:49:25 PM PDT 24
Peak memory 249596 kb
Host smart-16ca2e15-92cb-4b2a-a0a6-c13cdd725196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775143416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
775143416
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2478363174
Short name T144
Test name
Test status
Simulation time 20296678321 ps
CPU time 247.2 seconds
Started Aug 01 06:47:16 PM PDT 24
Finished Aug 01 06:51:23 PM PDT 24
Peak memory 250616 kb
Host smart-3baedfd7-7c08-499c-ae67-e464a56c02ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478363174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2478363174
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2638519454
Short name T53
Test name
Test status
Simulation time 377615183 ps
CPU time 5.98 seconds
Started Aug 01 06:41:07 PM PDT 24
Finished Aug 01 06:41:13 PM PDT 24
Peak memory 215212 kb
Host smart-3fda28a9-10b6-4327-a007-5b337568f728
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638519454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
638519454
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.212266634
Short name T126
Test name
Test status
Simulation time 651414160 ps
CPU time 13.83 seconds
Started Aug 01 06:41:15 PM PDT 24
Finished Aug 01 06:41:29 PM PDT 24
Peak memory 215232 kb
Host smart-83dbc156-dd8e-497c-af41-939faec5cd08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212266634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.212266634
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3742600301
Short name T226
Test name
Test status
Simulation time 198287773878 ps
CPU time 665.82 seconds
Started Aug 01 06:47:17 PM PDT 24
Finished Aug 01 06:58:23 PM PDT 24
Peak memory 265920 kb
Host smart-1d5b55ac-cab3-42b7-b262-7621b77aa920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742600301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3742600301
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3470374159
Short name T99
Test name
Test status
Simulation time 5518720531 ps
CPU time 40.67 seconds
Started Aug 01 06:41:06 PM PDT 24
Finished Aug 01 06:41:47 PM PDT 24
Peak memory 206980 kb
Host smart-79411158-143e-4c34-9f76-3b90dcbdfb7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470374159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3470374159
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.65012409
Short name T78
Test name
Test status
Simulation time 44914259538 ps
CPU time 129.01 seconds
Started Aug 01 06:45:40 PM PDT 24
Finished Aug 01 06:47:49 PM PDT 24
Peak memory 251580 kb
Host smart-1b510f5d-4696-428d-bef9-0e118a6e2c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65012409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.65012409
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.688410760
Short name T19
Test name
Test status
Simulation time 5270885877 ps
CPU time 130.78 seconds
Started Aug 01 06:48:10 PM PDT 24
Finished Aug 01 06:50:21 PM PDT 24
Peak memory 289760 kb
Host smart-97f0d324-f2d6-4193-ad69-7e30cb14474c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688410760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.688410760
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3242896097
Short name T40
Test name
Test status
Simulation time 8880573356 ps
CPU time 125.96 seconds
Started Aug 01 06:47:51 PM PDT 24
Finished Aug 01 06:49:57 PM PDT 24
Peak memory 265272 kb
Host smart-d89880e1-4635-46a9-b0ab-a12e52daa1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242896097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3242896097
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2668392636
Short name T242
Test name
Test status
Simulation time 357800454746 ps
CPU time 834.18 seconds
Started Aug 01 06:46:14 PM PDT 24
Finished Aug 01 07:00:09 PM PDT 24
Peak memory 266080 kb
Host smart-823b3fad-e5c6-4f66-845e-bd9d043dcb4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668392636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2668392636
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3131039634
Short name T133
Test name
Test status
Simulation time 16326581073 ps
CPU time 101.5 seconds
Started Aug 01 06:45:05 PM PDT 24
Finished Aug 01 06:46:47 PM PDT 24
Peak memory 249628 kb
Host smart-01ba1867-5016-49b5-a3b7-82870304df49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131039634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3131039634
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1005638525
Short name T291
Test name
Test status
Simulation time 94407351 ps
CPU time 0.75 seconds
Started Aug 01 06:45:36 PM PDT 24
Finished Aug 01 06:45:37 PM PDT 24
Peak memory 204788 kb
Host smart-63410613-3f47-4e64-bae8-5f1fd1edcf2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005638525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1005638525
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2124402892
Short name T233
Test name
Test status
Simulation time 11795381962 ps
CPU time 74.81 seconds
Started Aug 01 06:44:53 PM PDT 24
Finished Aug 01 06:46:08 PM PDT 24
Peak memory 267008 kb
Host smart-e57ec590-6315-43ea-a3f9-bd99c45b0a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124402892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2124402892
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3216670740
Short name T35
Test name
Test status
Simulation time 6408295941 ps
CPU time 121.53 seconds
Started Aug 01 06:46:21 PM PDT 24
Finished Aug 01 06:48:22 PM PDT 24
Peak memory 255032 kb
Host smart-ed047a4b-77a3-4f8d-866b-8f3fd4a89596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216670740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3216670740
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2385257231
Short name T683
Test name
Test status
Simulation time 117215711189 ps
CPU time 682.28 seconds
Started Aug 01 06:45:14 PM PDT 24
Finished Aug 01 06:56:37 PM PDT 24
Peak memory 290268 kb
Host smart-e0898205-f01d-4323-8489-d749ce3bbdb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385257231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2385257231
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2991946502
Short name T155
Test name
Test status
Simulation time 1033708951 ps
CPU time 21.01 seconds
Started Aug 01 06:41:43 PM PDT 24
Finished Aug 01 06:42:04 PM PDT 24
Peak memory 215148 kb
Host smart-0618f130-74eb-4ebc-a61d-ed6eaf731a98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991946502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2991946502
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1902241662
Short name T258
Test name
Test status
Simulation time 4328407180 ps
CPU time 49.95 seconds
Started Aug 01 06:45:01 PM PDT 24
Finished Aug 01 06:45:51 PM PDT 24
Peak memory 233428 kb
Host smart-965a1a78-0f12-40bb-93c5-c7062b73de6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902241662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1902241662
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1270526519
Short name T150
Test name
Test status
Simulation time 483667276 ps
CPU time 5.91 seconds
Started Aug 01 06:40:57 PM PDT 24
Finished Aug 01 06:41:03 PM PDT 24
Peak memory 215300 kb
Host smart-c266069c-30e2-4dc5-99dc-ab715d201567
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270526519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
270526519
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1304662196
Short name T153
Test name
Test status
Simulation time 2090758513 ps
CPU time 13.73 seconds
Started Aug 01 06:41:18 PM PDT 24
Finished Aug 01 06:41:31 PM PDT 24
Peak memory 215232 kb
Host smart-3c49157f-eaa7-4b4f-8579-708535444c34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304662196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1304662196
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1582535051
Short name T240
Test name
Test status
Simulation time 75112235613 ps
CPU time 92.16 seconds
Started Aug 01 06:46:25 PM PDT 24
Finished Aug 01 06:47:57 PM PDT 24
Peak memory 257148 kb
Host smart-625a5315-906b-4496-928a-653153a190ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582535051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1582535051
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1280946626
Short name T148
Test name
Test status
Simulation time 20518759521 ps
CPU time 116.37 seconds
Started Aug 01 06:46:49 PM PDT 24
Finished Aug 01 06:48:46 PM PDT 24
Peak memory 255636 kb
Host smart-0e7d8ec2-d939-4205-9a4d-bdb3fde3debe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280946626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1280946626
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1012016510
Short name T239
Test name
Test status
Simulation time 72861260831 ps
CPU time 71.63 seconds
Started Aug 01 06:45:27 PM PDT 24
Finished Aug 01 06:46:38 PM PDT 24
Peak memory 253392 kb
Host smart-bde0783d-23a1-4b7b-8902-02712a089a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012016510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1012016510
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3214063626
Short name T46
Test name
Test status
Simulation time 1323936950 ps
CPU time 6.26 seconds
Started Aug 01 06:45:41 PM PDT 24
Finished Aug 01 06:45:47 PM PDT 24
Peak memory 233088 kb
Host smart-6db8fdab-9a6f-49db-89cd-71eface09835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214063626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3214063626
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3934683533
Short name T76
Test name
Test status
Simulation time 2155969076 ps
CPU time 31.42 seconds
Started Aug 01 06:45:51 PM PDT 24
Finished Aug 01 06:46:22 PM PDT 24
Peak memory 233764 kb
Host smart-99d096fb-fb6a-4555-963c-b635639bd74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934683533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3934683533
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.273087255
Short name T157
Test name
Test status
Simulation time 832391399 ps
CPU time 22.74 seconds
Started Aug 01 06:41:31 PM PDT 24
Finished Aug 01 06:41:54 PM PDT 24
Peak memory 215192 kb
Host smart-5e51e9e6-773f-4e21-b0d7-c3b5c4565b30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273087255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.273087255
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1142786673
Short name T259
Test name
Test status
Simulation time 28388558829 ps
CPU time 90.34 seconds
Started Aug 01 06:46:15 PM PDT 24
Finished Aug 01 06:47:46 PM PDT 24
Peak memory 249588 kb
Host smart-538b0a02-5bcd-4f94-a260-c32176751bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142786673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1142786673
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1150638243
Short name T72
Test name
Test status
Simulation time 22396962 ps
CPU time 1.11 seconds
Started Aug 01 06:40:50 PM PDT 24
Finished Aug 01 06:40:51 PM PDT 24
Peak memory 206976 kb
Host smart-d70eeeae-3fff-4686-9200-34ab33e27c33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150638243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1150638243
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4088601346
Short name T1074
Test name
Test status
Simulation time 46025678 ps
CPU time 2.98 seconds
Started Aug 01 06:40:41 PM PDT 24
Finished Aug 01 06:40:44 PM PDT 24
Peak memory 215232 kb
Host smart-70fc13dd-a245-4f8d-b09d-eb621a679f02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088601346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
088601346
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3105253558
Short name T109
Test name
Test status
Simulation time 1537111593 ps
CPU time 16.54 seconds
Started Aug 01 06:40:38 PM PDT 24
Finished Aug 01 06:40:54 PM PDT 24
Peak memory 215156 kb
Host smart-31414edb-a10e-4d9c-95dc-94ac480fd46a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105253558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3105253558
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.631877531
Short name T1083
Test name
Test status
Simulation time 3298046704 ps
CPU time 12.94 seconds
Started Aug 01 06:40:42 PM PDT 24
Finished Aug 01 06:40:55 PM PDT 24
Peak memory 207016 kb
Host smart-7ed3b00b-cb7b-4cbc-8e8b-bc2c0cf88644
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631877531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.631877531
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1958423477
Short name T73
Test name
Test status
Simulation time 73872231 ps
CPU time 1.35 seconds
Started Aug 01 06:40:38 PM PDT 24
Finished Aug 01 06:40:40 PM PDT 24
Peak memory 206908 kb
Host smart-ffd8eaae-9474-4022-9aaa-0544bb6660ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958423477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1958423477
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4080263409
Short name T1048
Test name
Test status
Simulation time 207584984 ps
CPU time 3.36 seconds
Started Aug 01 06:40:40 PM PDT 24
Finished Aug 01 06:40:44 PM PDT 24
Peak memory 217212 kb
Host smart-c45da49e-016a-484c-bd2e-bef3d80b2b58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080263409 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4080263409
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1771517645
Short name T1071
Test name
Test status
Simulation time 63606309 ps
CPU time 1.22 seconds
Started Aug 01 06:40:41 PM PDT 24
Finished Aug 01 06:40:42 PM PDT 24
Peak memory 215100 kb
Host smart-9761d278-2512-4306-93b3-c72236258b34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771517645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
771517645
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2177189522
Short name T1043
Test name
Test status
Simulation time 14193533 ps
CPU time 0.75 seconds
Started Aug 01 06:40:38 PM PDT 24
Finished Aug 01 06:40:39 PM PDT 24
Peak memory 203564 kb
Host smart-e709203e-e21f-406a-92be-5c8449774910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177189522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
177189522
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3762503007
Short name T102
Test name
Test status
Simulation time 121258574 ps
CPU time 1.29 seconds
Started Aug 01 06:40:42 PM PDT 24
Finished Aug 01 06:40:43 PM PDT 24
Peak memory 215080 kb
Host smart-000ded7f-4bb1-4b59-bb45-4d0f0315fe4a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762503007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3762503007
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1667781495
Short name T1067
Test name
Test status
Simulation time 65287326 ps
CPU time 0.7 seconds
Started Aug 01 06:40:43 PM PDT 24
Finished Aug 01 06:40:44 PM PDT 24
Peak memory 203916 kb
Host smart-2a2e6511-ea3a-4c56-9a45-7cfaa257bc2b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667781495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1667781495
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3261241600
Short name T1092
Test name
Test status
Simulation time 349474894 ps
CPU time 1.95 seconds
Started Aug 01 06:40:41 PM PDT 24
Finished Aug 01 06:40:43 PM PDT 24
Peak memory 206280 kb
Host smart-75402541-8b24-4a7f-ad9d-60d194872aa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261241600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3261241600
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.697344622
Short name T90
Test name
Test status
Simulation time 80846852 ps
CPU time 3.2 seconds
Started Aug 01 06:40:39 PM PDT 24
Finished Aug 01 06:40:43 PM PDT 24
Peak memory 216592 kb
Host smart-aec8b7dc-ca6e-4bf2-86da-dca515b0fbc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697344622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.697344622
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3815238213
Short name T87
Test name
Test status
Simulation time 113963254 ps
CPU time 7.16 seconds
Started Aug 01 06:40:41 PM PDT 24
Finished Aug 01 06:40:48 PM PDT 24
Peak memory 215120 kb
Host smart-a7fc2dbc-d1e0-47c7-90c3-b84b3d6c0ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815238213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3815238213
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1795674307
Short name T1128
Test name
Test status
Simulation time 1226856705 ps
CPU time 14.71 seconds
Started Aug 01 06:40:42 PM PDT 24
Finished Aug 01 06:40:57 PM PDT 24
Peak memory 206916 kb
Host smart-6766a02a-1840-4be0-b2b5-13d604ecbe1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795674307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1795674307
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1227467235
Short name T1126
Test name
Test status
Simulation time 3766372632 ps
CPU time 39.4 seconds
Started Aug 01 06:40:39 PM PDT 24
Finished Aug 01 06:41:19 PM PDT 24
Peak memory 206972 kb
Host smart-23c65a2e-7aed-40f8-b6e7-3c2b56849fb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227467235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1227467235
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1483951936
Short name T71
Test name
Test status
Simulation time 68224535 ps
CPU time 0.96 seconds
Started Aug 01 06:40:41 PM PDT 24
Finished Aug 01 06:40:42 PM PDT 24
Peak memory 206668 kb
Host smart-8b34b3c7-4b8c-428b-97b1-eb79b3447e61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483951936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1483951936
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3844368640
Short name T1045
Test name
Test status
Simulation time 56760198 ps
CPU time 1.73 seconds
Started Aug 01 06:40:51 PM PDT 24
Finished Aug 01 06:40:53 PM PDT 24
Peak memory 215148 kb
Host smart-3996ff1b-dabd-4a75-81fe-677079d258c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844368640 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3844368640
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3392948710
Short name T1027
Test name
Test status
Simulation time 59781289 ps
CPU time 1.3 seconds
Started Aug 01 06:40:39 PM PDT 24
Finished Aug 01 06:40:41 PM PDT 24
Peak memory 206880 kb
Host smart-63c63ea2-d4f2-4a6f-bae5-fe8c9cd9c8f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392948710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
392948710
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.305990640
Short name T1117
Test name
Test status
Simulation time 13912028 ps
CPU time 0.68 seconds
Started Aug 01 06:40:42 PM PDT 24
Finished Aug 01 06:40:43 PM PDT 24
Peak memory 203596 kb
Host smart-d6564f99-35b2-41a7-ae08-99e1d7062de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305990640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.305990640
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1806987279
Short name T1121
Test name
Test status
Simulation time 32490149 ps
CPU time 1.32 seconds
Started Aug 01 06:40:39 PM PDT 24
Finished Aug 01 06:40:40 PM PDT 24
Peak memory 215076 kb
Host smart-41ace378-3455-4489-b6b9-c2b3d9af86f7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806987279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1806987279
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1206142371
Short name T1072
Test name
Test status
Simulation time 11615464 ps
CPU time 0.67 seconds
Started Aug 01 06:40:40 PM PDT 24
Finished Aug 01 06:40:40 PM PDT 24
Peak memory 203568 kb
Host smart-96285a22-5606-489c-b63f-80d693ac4c58
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206142371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1206142371
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2074291899
Short name T1047
Test name
Test status
Simulation time 72381299 ps
CPU time 1.79 seconds
Started Aug 01 06:40:52 PM PDT 24
Finished Aug 01 06:40:54 PM PDT 24
Peak memory 206940 kb
Host smart-0ab6f18a-8db9-4f48-a659-91be7293b257
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074291899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2074291899
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4265810604
Short name T152
Test name
Test status
Simulation time 3686485083 ps
CPU time 14.12 seconds
Started Aug 01 06:40:41 PM PDT 24
Finished Aug 01 06:40:55 PM PDT 24
Peak memory 215236 kb
Host smart-d5693074-b67f-4d3c-bfae-58425b990d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265810604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.4265810604
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.488915821
Short name T1032
Test name
Test status
Simulation time 103281290 ps
CPU time 2.03 seconds
Started Aug 01 06:41:16 PM PDT 24
Finished Aug 01 06:41:19 PM PDT 24
Peak memory 215168 kb
Host smart-55b2976c-6212-4038-ae82-d0bf767ed67f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488915821 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.488915821
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2468169729
Short name T1088
Test name
Test status
Simulation time 331204485 ps
CPU time 2.18 seconds
Started Aug 01 06:41:18 PM PDT 24
Finished Aug 01 06:41:20 PM PDT 24
Peak memory 206888 kb
Host smart-3f2ded9b-5016-4dbf-b8bc-b56da107f15e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468169729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2468169729
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2774798474
Short name T1015
Test name
Test status
Simulation time 48083992 ps
CPU time 0.72 seconds
Started Aug 01 06:41:19 PM PDT 24
Finished Aug 01 06:41:19 PM PDT 24
Peak memory 202884 kb
Host smart-0a0dbd0e-502e-4afd-ac0b-998fa8c72ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774798474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2774798474
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1279538049
Short name T1020
Test name
Test status
Simulation time 121571655 ps
CPU time 1.84 seconds
Started Aug 01 06:41:18 PM PDT 24
Finished Aug 01 06:41:20 PM PDT 24
Peak memory 215052 kb
Host smart-31dd7287-2783-490f-aa2f-ca94cb0bd93e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279538049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1279538049
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3314027601
Short name T1058
Test name
Test status
Simulation time 1688736882 ps
CPU time 4.2 seconds
Started Aug 01 06:41:17 PM PDT 24
Finished Aug 01 06:41:22 PM PDT 24
Peak memory 215156 kb
Host smart-53e87e8e-b558-43f1-af7b-a8bfa9219ef1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314027601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3314027601
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1267809622
Short name T1093
Test name
Test status
Simulation time 1595699978 ps
CPU time 13.49 seconds
Started Aug 01 06:41:17 PM PDT 24
Finished Aug 01 06:41:31 PM PDT 24
Peak memory 215436 kb
Host smart-3480a4cc-a577-44a0-86c4-7af1ad9f794e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267809622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1267809622
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1336646003
Short name T1064
Test name
Test status
Simulation time 98800373 ps
CPU time 2.52 seconds
Started Aug 01 06:41:29 PM PDT 24
Finished Aug 01 06:41:32 PM PDT 24
Peak memory 216664 kb
Host smart-500e91aa-cafe-470d-bbe0-46172bfcfb13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336646003 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1336646003
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2437381541
Short name T110
Test name
Test status
Simulation time 128123323 ps
CPU time 2.09 seconds
Started Aug 01 06:41:21 PM PDT 24
Finished Aug 01 06:41:23 PM PDT 24
Peak memory 215168 kb
Host smart-75ffb963-b506-4cf2-af28-6a1270065210
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437381541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2437381541
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2246022068
Short name T1046
Test name
Test status
Simulation time 47757440 ps
CPU time 0.72 seconds
Started Aug 01 06:41:21 PM PDT 24
Finished Aug 01 06:41:21 PM PDT 24
Peak memory 203624 kb
Host smart-57e50b8b-9d0d-48c2-b1cf-a93070306540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246022068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2246022068
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1204061616
Short name T1021
Test name
Test status
Simulation time 217363242 ps
CPU time 2.95 seconds
Started Aug 01 06:41:17 PM PDT 24
Finished Aug 01 06:41:20 PM PDT 24
Peak memory 215380 kb
Host smart-a4e93352-cdef-44ff-9bd7-ff84b08c6afe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204061616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1204061616
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.977932269
Short name T93
Test name
Test status
Simulation time 53822950 ps
CPU time 3.07 seconds
Started Aug 01 06:41:16 PM PDT 24
Finished Aug 01 06:41:20 PM PDT 24
Peak memory 216304 kb
Host smart-54edf946-0f33-4210-b182-f4564b94147c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977932269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.977932269
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2006154172
Short name T1102
Test name
Test status
Simulation time 166269206 ps
CPU time 3.85 seconds
Started Aug 01 06:41:31 PM PDT 24
Finished Aug 01 06:41:35 PM PDT 24
Peak memory 217588 kb
Host smart-7fae4364-d7ba-4c97-bff1-c9b99860e7ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006154172 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2006154172
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2076854647
Short name T1130
Test name
Test status
Simulation time 36076344 ps
CPU time 2.34 seconds
Started Aug 01 06:41:32 PM PDT 24
Finished Aug 01 06:41:34 PM PDT 24
Peak memory 215128 kb
Host smart-159aaf8c-d342-4973-8387-4d24a3cf02e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076854647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2076854647
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4045624380
Short name T1024
Test name
Test status
Simulation time 41555109 ps
CPU time 0.74 seconds
Started Aug 01 06:41:32 PM PDT 24
Finished Aug 01 06:41:33 PM PDT 24
Peak memory 203968 kb
Host smart-39562116-ff95-440a-a51c-0098a848222a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045624380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4045624380
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4189241015
Short name T1025
Test name
Test status
Simulation time 419747916 ps
CPU time 2.96 seconds
Started Aug 01 06:41:28 PM PDT 24
Finished Aug 01 06:41:31 PM PDT 24
Peak memory 215156 kb
Host smart-034c90fd-5539-47b5-888b-6589cd0d373d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189241015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4189241015
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2565800489
Short name T91
Test name
Test status
Simulation time 124796556 ps
CPU time 3.47 seconds
Started Aug 01 06:41:28 PM PDT 24
Finished Aug 01 06:41:32 PM PDT 24
Peak memory 215208 kb
Host smart-1ff28f63-ec63-429a-a8a3-0f4255bae332
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565800489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2565800489
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2363450474
Short name T1115
Test name
Test status
Simulation time 58384750 ps
CPU time 1.64 seconds
Started Aug 01 06:41:30 PM PDT 24
Finished Aug 01 06:41:32 PM PDT 24
Peak memory 215160 kb
Host smart-2595ff04-ade5-41f0-b7dd-75c635d174eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363450474 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2363450474
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3813946976
Short name T1084
Test name
Test status
Simulation time 139038726 ps
CPU time 1.27 seconds
Started Aug 01 06:41:32 PM PDT 24
Finished Aug 01 06:41:33 PM PDT 24
Peak memory 215088 kb
Host smart-541f6519-8c7d-430b-b6c9-15f60e10479e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813946976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3813946976
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.343618035
Short name T1031
Test name
Test status
Simulation time 35958154 ps
CPU time 0.76 seconds
Started Aug 01 06:41:33 PM PDT 24
Finished Aug 01 06:41:34 PM PDT 24
Peak memory 203564 kb
Host smart-fd50abc7-0c7b-4da4-a62c-a9f19c89f168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343618035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.343618035
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2139864047
Short name T127
Test name
Test status
Simulation time 687944761 ps
CPU time 4.42 seconds
Started Aug 01 06:41:31 PM PDT 24
Finished Aug 01 06:41:35 PM PDT 24
Peak memory 214952 kb
Host smart-220a90de-f26f-41de-9f9c-04a387bb87b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139864047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2139864047
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1601066983
Short name T151
Test name
Test status
Simulation time 70051779 ps
CPU time 2 seconds
Started Aug 01 06:41:28 PM PDT 24
Finished Aug 01 06:41:31 PM PDT 24
Peak memory 215364 kb
Host smart-c42ba6b3-c187-4839-9cf8-7009cd8d7171
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601066983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1601066983
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1986883996
Short name T162
Test name
Test status
Simulation time 1359062325 ps
CPU time 14.53 seconds
Started Aug 01 06:41:30 PM PDT 24
Finished Aug 01 06:41:44 PM PDT 24
Peak memory 215348 kb
Host smart-c18367d1-cf39-4709-9712-e6e19663afb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986883996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1986883996
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2728574618
Short name T1038
Test name
Test status
Simulation time 216500669 ps
CPU time 3.52 seconds
Started Aug 01 06:41:31 PM PDT 24
Finished Aug 01 06:41:34 PM PDT 24
Peak memory 217980 kb
Host smart-5da4ff4c-89d8-4895-af51-1a03d7ee0c54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728574618 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2728574618
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2814437366
Short name T103
Test name
Test status
Simulation time 89814258 ps
CPU time 2.5 seconds
Started Aug 01 06:41:30 PM PDT 24
Finished Aug 01 06:41:32 PM PDT 24
Peak memory 215168 kb
Host smart-a86226bf-ddca-4280-9105-5c42eccb79ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814437366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2814437366
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2231280525
Short name T1087
Test name
Test status
Simulation time 132818965 ps
CPU time 0.72 seconds
Started Aug 01 06:41:32 PM PDT 24
Finished Aug 01 06:41:33 PM PDT 24
Peak memory 203628 kb
Host smart-262e5c4c-f590-4483-b5c7-2f1e4031eb3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231280525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2231280525
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2074729431
Short name T1034
Test name
Test status
Simulation time 48428160 ps
CPU time 1.84 seconds
Started Aug 01 06:41:33 PM PDT 24
Finished Aug 01 06:41:35 PM PDT 24
Peak memory 215116 kb
Host smart-db894381-0692-4839-a423-1497c1de88de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074729431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2074729431
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.546191018
Short name T1096
Test name
Test status
Simulation time 589155918 ps
CPU time 4.07 seconds
Started Aug 01 06:41:32 PM PDT 24
Finished Aug 01 06:41:36 PM PDT 24
Peak memory 215272 kb
Host smart-b4453cb2-0c12-44f9-97c0-f98167a29930
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546191018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.546191018
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3023519256
Short name T85
Test name
Test status
Simulation time 1992224897 ps
CPU time 6.83 seconds
Started Aug 01 06:41:30 PM PDT 24
Finished Aug 01 06:41:37 PM PDT 24
Peak memory 215244 kb
Host smart-b8015c7f-bfcf-45aa-b9c2-bbd86cb0a9d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023519256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3023519256
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3680629714
Short name T1120
Test name
Test status
Simulation time 324932141 ps
CPU time 3.51 seconds
Started Aug 01 06:41:33 PM PDT 24
Finished Aug 01 06:41:37 PM PDT 24
Peak memory 217092 kb
Host smart-4709557c-88f4-4850-aef2-5dcfb821a6e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680629714 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3680629714
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3699950866
Short name T1029
Test name
Test status
Simulation time 124343344 ps
CPU time 2.09 seconds
Started Aug 01 06:41:30 PM PDT 24
Finished Aug 01 06:41:33 PM PDT 24
Peak memory 215080 kb
Host smart-e8e4495a-7d13-449f-a017-ce0117858f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699950866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3699950866
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.156667377
Short name T1131
Test name
Test status
Simulation time 64357423 ps
CPU time 0.71 seconds
Started Aug 01 06:41:28 PM PDT 24
Finished Aug 01 06:41:29 PM PDT 24
Peak memory 203904 kb
Host smart-8350ad09-729c-4af1-9228-af1d655347ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156667377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.156667377
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2338706414
Short name T1033
Test name
Test status
Simulation time 111144149 ps
CPU time 2.39 seconds
Started Aug 01 06:41:29 PM PDT 24
Finished Aug 01 06:41:31 PM PDT 24
Peak memory 215168 kb
Host smart-622b3b82-25bf-4bd6-8ed2-46491eafb1c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338706414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2338706414
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3971588203
Short name T54
Test name
Test status
Simulation time 391795342 ps
CPU time 5.23 seconds
Started Aug 01 06:41:30 PM PDT 24
Finished Aug 01 06:41:35 PM PDT 24
Peak memory 215216 kb
Host smart-22e8fca2-46ea-441b-a541-687d8e92d0a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971588203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3971588203
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4063300851
Short name T1075
Test name
Test status
Simulation time 597510650 ps
CPU time 7.97 seconds
Started Aug 01 06:41:30 PM PDT 24
Finished Aug 01 06:41:38 PM PDT 24
Peak memory 215180 kb
Host smart-6dd482ec-b757-4b48-a068-0cf31c252ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063300851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.4063300851
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4148436317
Short name T1089
Test name
Test status
Simulation time 1029987051 ps
CPU time 3.91 seconds
Started Aug 01 06:41:32 PM PDT 24
Finished Aug 01 06:41:36 PM PDT 24
Peak memory 217248 kb
Host smart-57883907-57dd-4ff2-ac46-a0f537ac3da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148436317 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.4148436317
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2426131
Short name T1108
Test name
Test status
Simulation time 91156808 ps
CPU time 2.32 seconds
Started Aug 01 06:41:33 PM PDT 24
Finished Aug 01 06:41:36 PM PDT 24
Peak memory 206988 kb
Host smart-bfeb52f6-4ec3-421f-9bdd-a7ce3157bcbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.2426131
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3894027023
Short name T1061
Test name
Test status
Simulation time 12294814 ps
CPU time 0.76 seconds
Started Aug 01 06:41:32 PM PDT 24
Finished Aug 01 06:41:32 PM PDT 24
Peak memory 203904 kb
Host smart-d82fa0e5-e2cc-4101-8570-c58f1e0dd6bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894027023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3894027023
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3886280635
Short name T117
Test name
Test status
Simulation time 104866069 ps
CPU time 2.83 seconds
Started Aug 01 06:41:32 PM PDT 24
Finished Aug 01 06:41:35 PM PDT 24
Peak memory 215108 kb
Host smart-0958bd24-6884-4106-b199-f88cfa64672c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886280635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3886280635
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3734164013
Short name T1059
Test name
Test status
Simulation time 263783324 ps
CPU time 1.79 seconds
Started Aug 01 06:41:32 PM PDT 24
Finished Aug 01 06:41:34 PM PDT 24
Peak memory 215252 kb
Host smart-fb90ecc4-668b-4b0c-ad3e-df94a8604ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734164013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3734164013
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2311707166
Short name T159
Test name
Test status
Simulation time 212589839 ps
CPU time 11.76 seconds
Started Aug 01 06:41:32 PM PDT 24
Finished Aug 01 06:41:44 PM PDT 24
Peak memory 215172 kb
Host smart-8892c9e9-aec2-4b51-9238-0cc1b0df5c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311707166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2311707166
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2684166497
Short name T1110
Test name
Test status
Simulation time 61547298 ps
CPU time 1.63 seconds
Started Aug 01 06:41:28 PM PDT 24
Finished Aug 01 06:41:30 PM PDT 24
Peak memory 206872 kb
Host smart-d4df806f-bdb0-47c9-aa4f-705f1bc268f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684166497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2684166497
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3346821347
Short name T1085
Test name
Test status
Simulation time 14746170 ps
CPU time 0.74 seconds
Started Aug 01 06:41:30 PM PDT 24
Finished Aug 01 06:41:31 PM PDT 24
Peak memory 203612 kb
Host smart-7d853150-41e8-4536-b784-5e4e167c36f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346821347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3346821347
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3917729780
Short name T114
Test name
Test status
Simulation time 104475752 ps
CPU time 2.81 seconds
Started Aug 01 06:41:29 PM PDT 24
Finished Aug 01 06:41:32 PM PDT 24
Peak memory 215080 kb
Host smart-70854054-7b43-4682-8128-02623b798036
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917729780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3917729780
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.49509304
Short name T89
Test name
Test status
Simulation time 58842607 ps
CPU time 3.67 seconds
Started Aug 01 06:41:31 PM PDT 24
Finished Aug 01 06:41:35 PM PDT 24
Peak memory 215200 kb
Host smart-e5381b26-9198-4424-b905-c693f7c5fd6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49509304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.49509304
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1956749806
Short name T129
Test name
Test status
Simulation time 5956635122 ps
CPU time 8.25 seconds
Started Aug 01 06:41:29 PM PDT 24
Finished Aug 01 06:41:37 PM PDT 24
Peak memory 215212 kb
Host smart-40f44b19-072b-4c1d-9c65-abc65f5daf1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956749806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1956749806
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4065235239
Short name T95
Test name
Test status
Simulation time 320084016 ps
CPU time 2.42 seconds
Started Aug 01 06:41:41 PM PDT 24
Finished Aug 01 06:41:44 PM PDT 24
Peak memory 216160 kb
Host smart-1ae8fd39-aad5-4dd3-b7f0-c0d9ea29b342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065235239 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4065235239
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.382907413
Short name T107
Test name
Test status
Simulation time 29053094 ps
CPU time 1.88 seconds
Started Aug 01 06:41:39 PM PDT 24
Finished Aug 01 06:41:41 PM PDT 24
Peak memory 206868 kb
Host smart-0ddb7677-01f9-4d5c-a740-f3352090b2e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382907413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.382907413
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1078593755
Short name T1060
Test name
Test status
Simulation time 16923519 ps
CPU time 0.76 seconds
Started Aug 01 06:41:39 PM PDT 24
Finished Aug 01 06:41:40 PM PDT 24
Peak memory 203936 kb
Host smart-b4fda286-271d-49e0-93be-641080ee7b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078593755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1078593755
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2006729172
Short name T1052
Test name
Test status
Simulation time 320992691 ps
CPU time 4.1 seconds
Started Aug 01 06:41:39 PM PDT 24
Finished Aug 01 06:41:43 PM PDT 24
Peak memory 215132 kb
Host smart-0bd5d676-dc93-4fef-88ef-cdcfcffa45b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006729172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2006729172
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1982509168
Short name T1101
Test name
Test status
Simulation time 226099707 ps
CPU time 3.97 seconds
Started Aug 01 06:41:31 PM PDT 24
Finished Aug 01 06:41:35 PM PDT 24
Peak memory 215244 kb
Host smart-5493b7c2-809d-4324-84e3-2b7bb5b31a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982509168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1982509168
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2977771107
Short name T156
Test name
Test status
Simulation time 98657131 ps
CPU time 6.29 seconds
Started Aug 01 06:41:44 PM PDT 24
Finished Aug 01 06:41:51 PM PDT 24
Peak memory 215560 kb
Host smart-03b78747-b335-4173-844f-e4d8bf07dcc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977771107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2977771107
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.129969999
Short name T1123
Test name
Test status
Simulation time 1025879677 ps
CPU time 2.61 seconds
Started Aug 01 06:41:40 PM PDT 24
Finished Aug 01 06:41:43 PM PDT 24
Peak memory 216364 kb
Host smart-11b4631b-537b-4791-9209-883331245cf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129969999 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.129969999
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3111074004
Short name T1118
Test name
Test status
Simulation time 80853614 ps
CPU time 1.97 seconds
Started Aug 01 06:41:41 PM PDT 24
Finished Aug 01 06:41:43 PM PDT 24
Peak memory 215096 kb
Host smart-6bdc0917-65c9-4c33-be84-38b34a4f5a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111074004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3111074004
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.500599070
Short name T1017
Test name
Test status
Simulation time 13855892 ps
CPU time 0.72 seconds
Started Aug 01 06:41:41 PM PDT 24
Finished Aug 01 06:41:42 PM PDT 24
Peak memory 203920 kb
Host smart-f939798b-813f-4c9e-8bae-5bdee3ae833f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500599070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.500599070
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1569271764
Short name T1042
Test name
Test status
Simulation time 99070818 ps
CPU time 1.83 seconds
Started Aug 01 06:41:39 PM PDT 24
Finished Aug 01 06:41:41 PM PDT 24
Peak memory 215136 kb
Host smart-51bc1d75-c731-4d17-9044-6af643f5a22e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569271764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1569271764
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2567811670
Short name T88
Test name
Test status
Simulation time 127517616 ps
CPU time 5.05 seconds
Started Aug 01 06:41:41 PM PDT 24
Finished Aug 01 06:41:46 PM PDT 24
Peak memory 215364 kb
Host smart-bb42c8c1-ad06-4b76-a79f-66e705a8e1c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567811670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2567811670
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2874101586
Short name T125
Test name
Test status
Simulation time 9587035149 ps
CPU time 16.62 seconds
Started Aug 01 06:40:50 PM PDT 24
Finished Aug 01 06:41:07 PM PDT 24
Peak memory 206892 kb
Host smart-bc238899-6e55-4943-9e08-3ac440b03c17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874101586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2874101586
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3699842819
Short name T1049
Test name
Test status
Simulation time 812763748 ps
CPU time 12.23 seconds
Started Aug 01 06:40:51 PM PDT 24
Finished Aug 01 06:41:03 PM PDT 24
Peak memory 206872 kb
Host smart-f1558ff9-7130-4c33-bf85-d423c45bd71d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699842819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3699842819
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.836454097
Short name T74
Test name
Test status
Simulation time 36520122 ps
CPU time 1.22 seconds
Started Aug 01 06:40:52 PM PDT 24
Finished Aug 01 06:40:54 PM PDT 24
Peak memory 215052 kb
Host smart-3e46c3fc-bb1c-4ff2-8b3c-1b1dd36e0966
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836454097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.836454097
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3593467501
Short name T1054
Test name
Test status
Simulation time 47439307 ps
CPU time 1.57 seconds
Started Aug 01 06:40:52 PM PDT 24
Finished Aug 01 06:40:54 PM PDT 24
Peak memory 215256 kb
Host smart-3757860c-d7b0-4c33-94a6-b07648012155
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593467501 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3593467501
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3568280737
Short name T1070
Test name
Test status
Simulation time 150178307 ps
CPU time 1.98 seconds
Started Aug 01 06:40:53 PM PDT 24
Finished Aug 01 06:40:55 PM PDT 24
Peak memory 215176 kb
Host smart-26ebca6f-dc4a-4888-99d5-9bfa6b572530
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568280737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
568280737
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1662512619
Short name T1081
Test name
Test status
Simulation time 24582063 ps
CPU time 0.7 seconds
Started Aug 01 06:40:50 PM PDT 24
Finished Aug 01 06:40:51 PM PDT 24
Peak memory 203616 kb
Host smart-60c4cd7c-d98e-436a-97ac-709b566a91c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662512619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
662512619
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2147650288
Short name T1018
Test name
Test status
Simulation time 266397075 ps
CPU time 2.17 seconds
Started Aug 01 06:40:57 PM PDT 24
Finished Aug 01 06:40:59 PM PDT 24
Peak memory 215112 kb
Host smart-5cc4a115-2d07-400f-8ce3-f3a32c055bb4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147650288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2147650288
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.407712606
Short name T1119
Test name
Test status
Simulation time 22627090 ps
CPU time 0.65 seconds
Started Aug 01 06:40:56 PM PDT 24
Finished Aug 01 06:40:57 PM PDT 24
Peak memory 203560 kb
Host smart-28753c36-29be-4c96-bc65-80e13e330e03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407712606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.407712606
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1360691307
Short name T1078
Test name
Test status
Simulation time 44202088 ps
CPU time 2.73 seconds
Started Aug 01 06:40:52 PM PDT 24
Finished Aug 01 06:40:55 PM PDT 24
Peak memory 215112 kb
Host smart-c3077096-d589-4428-be9c-72f20cec6ca2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360691307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1360691307
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.344486546
Short name T84
Test name
Test status
Simulation time 245726075 ps
CPU time 3.45 seconds
Started Aug 01 06:40:51 PM PDT 24
Finished Aug 01 06:40:55 PM PDT 24
Peak memory 215224 kb
Host smart-d9863bb4-0a42-4bae-9ef0-12501e388b01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344486546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.344486546
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1340881349
Short name T160
Test name
Test status
Simulation time 196403222 ps
CPU time 7 seconds
Started Aug 01 06:40:51 PM PDT 24
Finished Aug 01 06:40:58 PM PDT 24
Peak memory 215152 kb
Host smart-6ece7864-cd40-49f6-bf28-9d0c8f2c1229
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340881349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1340881349
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1030295798
Short name T1068
Test name
Test status
Simulation time 27786287 ps
CPU time 0.77 seconds
Started Aug 01 06:41:40 PM PDT 24
Finished Aug 01 06:41:41 PM PDT 24
Peak memory 203608 kb
Host smart-a38f1534-c1b8-451f-8a23-3c324f8b84ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030295798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1030295798
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2766682503
Short name T1016
Test name
Test status
Simulation time 55435864 ps
CPU time 0.74 seconds
Started Aug 01 06:41:40 PM PDT 24
Finished Aug 01 06:41:40 PM PDT 24
Peak memory 203584 kb
Host smart-bb7f8413-d41f-4dde-b0d0-d5bdcbc3c4bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766682503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2766682503
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1980005812
Short name T1040
Test name
Test status
Simulation time 24584027 ps
CPU time 0.76 seconds
Started Aug 01 06:41:41 PM PDT 24
Finished Aug 01 06:41:42 PM PDT 24
Peak memory 203932 kb
Host smart-0625fb78-9ae0-400a-8ae5-275c5f39e8fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980005812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1980005812
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3949860611
Short name T1056
Test name
Test status
Simulation time 32079326 ps
CPU time 0.7 seconds
Started Aug 01 06:41:39 PM PDT 24
Finished Aug 01 06:41:40 PM PDT 24
Peak memory 203924 kb
Host smart-f6b1c9ee-9290-4e17-93b6-0203172d384f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949860611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3949860611
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1381929061
Short name T1104
Test name
Test status
Simulation time 38661418 ps
CPU time 0.73 seconds
Started Aug 01 06:41:39 PM PDT 24
Finished Aug 01 06:41:40 PM PDT 24
Peak memory 203624 kb
Host smart-86a41ad4-6cc4-4c47-af83-a434bc829eed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381929061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1381929061
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2847382378
Short name T1050
Test name
Test status
Simulation time 28284092 ps
CPU time 0.77 seconds
Started Aug 01 06:41:42 PM PDT 24
Finished Aug 01 06:41:43 PM PDT 24
Peak memory 203600 kb
Host smart-004c746c-3cef-4f8d-b993-c6b0dddec7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847382378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2847382378
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3197376188
Short name T1041
Test name
Test status
Simulation time 26986970 ps
CPU time 0.73 seconds
Started Aug 01 06:41:43 PM PDT 24
Finished Aug 01 06:41:44 PM PDT 24
Peak memory 203580 kb
Host smart-5699e94c-6916-4734-b4d3-25058c3a8b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197376188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3197376188
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3502416443
Short name T1039
Test name
Test status
Simulation time 174006139 ps
CPU time 0.71 seconds
Started Aug 01 06:41:44 PM PDT 24
Finished Aug 01 06:41:45 PM PDT 24
Peak memory 203612 kb
Host smart-a1e0db12-f41e-4783-bcdc-ac15db57f759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502416443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3502416443
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2250724777
Short name T1099
Test name
Test status
Simulation time 48065244 ps
CPU time 0.76 seconds
Started Aug 01 06:41:39 PM PDT 24
Finished Aug 01 06:41:40 PM PDT 24
Peak memory 203600 kb
Host smart-a52ec325-a809-4c49-88a8-bbf6cb044aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250724777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2250724777
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2333817333
Short name T1109
Test name
Test status
Simulation time 11703273 ps
CPU time 0.74 seconds
Started Aug 01 06:41:43 PM PDT 24
Finished Aug 01 06:41:43 PM PDT 24
Peak memory 203572 kb
Host smart-948fa81c-6c71-43d6-ab92-99850da89727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333817333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2333817333
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2644378405
Short name T108
Test name
Test status
Simulation time 1203071087 ps
CPU time 20.2 seconds
Started Aug 01 06:41:05 PM PDT 24
Finished Aug 01 06:41:26 PM PDT 24
Peak memory 207004 kb
Host smart-047bd00c-a718-455b-9c28-0c7eba1b9622
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644378405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2644378405
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3824318398
Short name T1062
Test name
Test status
Simulation time 174973558 ps
CPU time 1.57 seconds
Started Aug 01 06:41:10 PM PDT 24
Finished Aug 01 06:41:11 PM PDT 24
Peak memory 216152 kb
Host smart-a9dccb90-252c-4c9b-bec4-8c76451ba71d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824318398 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3824318398
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2711205316
Short name T124
Test name
Test status
Simulation time 294630383 ps
CPU time 1.35 seconds
Started Aug 01 06:41:06 PM PDT 24
Finished Aug 01 06:41:07 PM PDT 24
Peak memory 207096 kb
Host smart-50cc868a-c58b-48ac-b653-35543028176c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711205316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
711205316
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3217834418
Short name T1077
Test name
Test status
Simulation time 37865613 ps
CPU time 0.74 seconds
Started Aug 01 06:40:52 PM PDT 24
Finished Aug 01 06:40:53 PM PDT 24
Peak memory 203896 kb
Host smart-818a87de-ad0e-42d3-8b02-ab5a14cf9de3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217834418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
217834418
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2517737372
Short name T100
Test name
Test status
Simulation time 87713349 ps
CPU time 1.63 seconds
Started Aug 01 06:40:51 PM PDT 24
Finished Aug 01 06:40:52 PM PDT 24
Peak memory 215044 kb
Host smart-0a319231-0aaa-49a1-86e1-659e99bb4cd4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517737372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2517737372
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2052888634
Short name T1073
Test name
Test status
Simulation time 10960578 ps
CPU time 0.7 seconds
Started Aug 01 06:40:53 PM PDT 24
Finished Aug 01 06:40:54 PM PDT 24
Peak memory 203880 kb
Host smart-ab5574c5-0dcb-4d4e-99dc-1dce50deb9bc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052888634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2052888634
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3389626187
Short name T1111
Test name
Test status
Simulation time 118761296 ps
CPU time 3.18 seconds
Started Aug 01 06:41:08 PM PDT 24
Finished Aug 01 06:41:12 PM PDT 24
Peak memory 215072 kb
Host smart-4dbc53d4-97ba-491e-a961-35c6de5e18b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389626187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3389626187
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.673349094
Short name T86
Test name
Test status
Simulation time 209556217 ps
CPU time 12.73 seconds
Started Aug 01 06:40:53 PM PDT 24
Finished Aug 01 06:41:06 PM PDT 24
Peak memory 215060 kb
Host smart-81003d82-5a02-4d1a-96c6-1dee3877b390
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673349094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.673349094
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2906536618
Short name T1066
Test name
Test status
Simulation time 19221841 ps
CPU time 0.72 seconds
Started Aug 01 06:41:40 PM PDT 24
Finished Aug 01 06:41:41 PM PDT 24
Peak memory 203936 kb
Host smart-3234760b-45f5-4a8d-a268-292b3fa4219d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906536618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2906536618
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.657808160
Short name T1086
Test name
Test status
Simulation time 32911025 ps
CPU time 0.74 seconds
Started Aug 01 06:41:44 PM PDT 24
Finished Aug 01 06:41:45 PM PDT 24
Peak memory 203936 kb
Host smart-fd46b92c-9ea2-4e56-8699-7c1f1ab5c4bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657808160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.657808160
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1754150217
Short name T1125
Test name
Test status
Simulation time 40580317 ps
CPU time 0.7 seconds
Started Aug 01 06:41:43 PM PDT 24
Finished Aug 01 06:41:43 PM PDT 24
Peak memory 203596 kb
Host smart-62086ab0-384e-45f7-84d8-3d19ea7528f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754150217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1754150217
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3432614990
Short name T1022
Test name
Test status
Simulation time 13148097 ps
CPU time 0.72 seconds
Started Aug 01 06:41:43 PM PDT 24
Finished Aug 01 06:41:44 PM PDT 24
Peak memory 203632 kb
Host smart-061d92fb-a27c-4d82-8acd-fbe1e96e93ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432614990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3432614990
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1862542220
Short name T1028
Test name
Test status
Simulation time 28726559 ps
CPU time 0.76 seconds
Started Aug 01 06:41:40 PM PDT 24
Finished Aug 01 06:41:41 PM PDT 24
Peak memory 203876 kb
Host smart-41c63890-0f0f-490f-b83c-dc7204a6a97a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862542220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1862542220
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3318738633
Short name T1107
Test name
Test status
Simulation time 30500523 ps
CPU time 0.74 seconds
Started Aug 01 06:41:40 PM PDT 24
Finished Aug 01 06:41:41 PM PDT 24
Peak memory 203932 kb
Host smart-61d7ec39-4fa1-4224-aa1f-d28c3eb4b490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318738633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3318738633
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2717759640
Short name T1036
Test name
Test status
Simulation time 34196551 ps
CPU time 0.76 seconds
Started Aug 01 06:41:42 PM PDT 24
Finished Aug 01 06:41:43 PM PDT 24
Peak memory 203612 kb
Host smart-0be71743-e29c-4427-8390-449d10dc96f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717759640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2717759640
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.552092326
Short name T1023
Test name
Test status
Simulation time 57336608 ps
CPU time 0.66 seconds
Started Aug 01 06:41:39 PM PDT 24
Finished Aug 01 06:41:40 PM PDT 24
Peak memory 203604 kb
Host smart-9560a114-437c-4f40-9571-f9010b3744a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552092326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.552092326
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3489109958
Short name T1129
Test name
Test status
Simulation time 14541432 ps
CPU time 0.73 seconds
Started Aug 01 06:41:42 PM PDT 24
Finished Aug 01 06:41:43 PM PDT 24
Peak memory 203588 kb
Host smart-dc1f5d46-3388-42ae-88f5-b7687767cbc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489109958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3489109958
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1222939708
Short name T1030
Test name
Test status
Simulation time 45705685 ps
CPU time 0.77 seconds
Started Aug 01 06:41:43 PM PDT 24
Finished Aug 01 06:41:44 PM PDT 24
Peak memory 203568 kb
Host smart-504a5c52-216d-4dc8-b57e-3d8c8c89fb1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222939708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1222939708
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3903938494
Short name T1080
Test name
Test status
Simulation time 929140598 ps
CPU time 24.32 seconds
Started Aug 01 06:41:08 PM PDT 24
Finished Aug 01 06:41:33 PM PDT 24
Peak memory 215088 kb
Host smart-1a24e0e3-a675-4aec-a0d5-7cce0343a2c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903938494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3903938494
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2846437208
Short name T1122
Test name
Test status
Simulation time 622593977 ps
CPU time 12.61 seconds
Started Aug 01 06:41:05 PM PDT 24
Finished Aug 01 06:41:18 PM PDT 24
Peak memory 215168 kb
Host smart-274e5c41-79dd-4a08-b031-8c94ad732316
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846437208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2846437208
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.986371125
Short name T75
Test name
Test status
Simulation time 32516264 ps
CPU time 1.2 seconds
Started Aug 01 06:41:06 PM PDT 24
Finished Aug 01 06:41:07 PM PDT 24
Peak memory 216144 kb
Host smart-9222fb70-47e9-4ef1-8771-2aa3811c5691
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986371125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.986371125
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1484634280
Short name T1065
Test name
Test status
Simulation time 295721461 ps
CPU time 3.74 seconds
Started Aug 01 06:41:08 PM PDT 24
Finished Aug 01 06:41:12 PM PDT 24
Peak memory 217564 kb
Host smart-d0756a0f-7a24-4e9e-a1f3-7e82b6dd0c8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484634280 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1484634280
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4248531045
Short name T1114
Test name
Test status
Simulation time 72608153 ps
CPU time 1.34 seconds
Started Aug 01 06:41:07 PM PDT 24
Finished Aug 01 06:41:08 PM PDT 24
Peak memory 215156 kb
Host smart-180891c1-59d6-4219-bfeb-ac21ecd0ae9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248531045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
248531045
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1810684793
Short name T1095
Test name
Test status
Simulation time 104983541 ps
CPU time 0.76 seconds
Started Aug 01 06:41:06 PM PDT 24
Finished Aug 01 06:41:07 PM PDT 24
Peak memory 203620 kb
Host smart-bc3812c0-077a-41b0-90d2-cc2dc026c6e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810684793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
810684793
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.179198120
Short name T104
Test name
Test status
Simulation time 393731838 ps
CPU time 1.7 seconds
Started Aug 01 06:41:06 PM PDT 24
Finished Aug 01 06:41:08 PM PDT 24
Peak memory 215020 kb
Host smart-f8bcd960-7085-471d-a22f-3ed4113f30a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179198120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.179198120
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2235383710
Short name T1103
Test name
Test status
Simulation time 27392366 ps
CPU time 0.68 seconds
Started Aug 01 06:41:06 PM PDT 24
Finished Aug 01 06:41:07 PM PDT 24
Peak memory 203484 kb
Host smart-8123e53e-d6b2-4ce2-a6ea-515fd3c12b08
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235383710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2235383710
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3915331255
Short name T116
Test name
Test status
Simulation time 44587000 ps
CPU time 2.76 seconds
Started Aug 01 06:41:08 PM PDT 24
Finished Aug 01 06:41:11 PM PDT 24
Peak memory 215080 kb
Host smart-ecf801e9-7a63-4aea-ab21-8ae1482cc199
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915331255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3915331255
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.547293551
Short name T1116
Test name
Test status
Simulation time 371125091 ps
CPU time 4.99 seconds
Started Aug 01 06:41:07 PM PDT 24
Finished Aug 01 06:41:12 PM PDT 24
Peak memory 215348 kb
Host smart-add59392-8be1-4a3c-81d4-df0754090cfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547293551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.547293551
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.511484578
Short name T1106
Test name
Test status
Simulation time 734261865 ps
CPU time 8 seconds
Started Aug 01 06:41:08 PM PDT 24
Finished Aug 01 06:41:16 PM PDT 24
Peak memory 215132 kb
Host smart-8f5f802d-64d9-4705-aa00-0ec80022c171
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511484578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.511484578
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.590221038
Short name T1097
Test name
Test status
Simulation time 37832084 ps
CPU time 0.74 seconds
Started Aug 01 06:41:39 PM PDT 24
Finished Aug 01 06:41:40 PM PDT 24
Peak memory 203624 kb
Host smart-a7d6e06c-bc14-49a7-8b26-812c1d0ec59b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590221038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.590221038
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1654836993
Short name T1014
Test name
Test status
Simulation time 19761090 ps
CPU time 0.77 seconds
Started Aug 01 06:41:42 PM PDT 24
Finished Aug 01 06:41:43 PM PDT 24
Peak memory 203612 kb
Host smart-deb6e608-4740-4604-ab63-a83cee91e67f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654836993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1654836993
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3050830164
Short name T1037
Test name
Test status
Simulation time 18754563 ps
CPU time 0.75 seconds
Started Aug 01 06:41:45 PM PDT 24
Finished Aug 01 06:41:46 PM PDT 24
Peak memory 203924 kb
Host smart-e407c3f5-2ed7-4882-bd38-7f677cdfe66b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050830164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3050830164
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3139967779
Short name T1112
Test name
Test status
Simulation time 13386708 ps
CPU time 0.7 seconds
Started Aug 01 06:41:41 PM PDT 24
Finished Aug 01 06:41:41 PM PDT 24
Peak memory 203916 kb
Host smart-5b23c885-6efd-4efb-be9b-b41e4da76a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139967779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3139967779
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1030879719
Short name T1076
Test name
Test status
Simulation time 104245769 ps
CPU time 0.69 seconds
Started Aug 01 06:41:42 PM PDT 24
Finished Aug 01 06:41:43 PM PDT 24
Peak memory 203908 kb
Host smart-3b4f9466-4359-4a43-902d-fed1e82d1672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030879719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1030879719
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2629329082
Short name T1090
Test name
Test status
Simulation time 55110297 ps
CPU time 0.76 seconds
Started Aug 01 06:41:40 PM PDT 24
Finished Aug 01 06:41:41 PM PDT 24
Peak memory 203604 kb
Host smart-b19e24bf-e58a-4b9f-9717-b62e8ea7a0af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629329082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2629329082
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2998845827
Short name T1044
Test name
Test status
Simulation time 59776272 ps
CPU time 0.75 seconds
Started Aug 01 06:41:42 PM PDT 24
Finished Aug 01 06:41:43 PM PDT 24
Peak memory 203924 kb
Host smart-f0266074-312c-40d6-a859-baef10dbfa10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998845827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2998845827
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.266759794
Short name T1098
Test name
Test status
Simulation time 55466997 ps
CPU time 0.78 seconds
Started Aug 01 06:41:50 PM PDT 24
Finished Aug 01 06:41:51 PM PDT 24
Peak memory 203564 kb
Host smart-d1c61f31-57b5-4141-a5ab-5091b7bfdc9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266759794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.266759794
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2151810428
Short name T1127
Test name
Test status
Simulation time 36242076 ps
CPU time 0.7 seconds
Started Aug 01 06:41:53 PM PDT 24
Finished Aug 01 06:41:54 PM PDT 24
Peak memory 203612 kb
Host smart-847969bc-5cea-42aa-89cb-8eb6b209dc0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151810428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2151810428
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2716064805
Short name T1113
Test name
Test status
Simulation time 45222980 ps
CPU time 0.77 seconds
Started Aug 01 06:41:49 PM PDT 24
Finished Aug 01 06:41:50 PM PDT 24
Peak memory 203604 kb
Host smart-6fef937a-ff6b-4031-9c25-a4ff5b3fbfd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716064805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2716064805
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.862155739
Short name T94
Test name
Test status
Simulation time 79820039 ps
CPU time 2.59 seconds
Started Aug 01 06:41:10 PM PDT 24
Finished Aug 01 06:41:12 PM PDT 24
Peak memory 216840 kb
Host smart-86acfc1e-49c3-4b29-8cfd-750e24fbc2fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862155739 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.862155739
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2391684044
Short name T105
Test name
Test status
Simulation time 95783122 ps
CPU time 2.59 seconds
Started Aug 01 06:41:07 PM PDT 24
Finished Aug 01 06:41:10 PM PDT 24
Peak memory 215100 kb
Host smart-d356e2c8-693f-45ba-85cd-e0ef530e430e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391684044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
391684044
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2624069861
Short name T1051
Test name
Test status
Simulation time 31849702 ps
CPU time 0.76 seconds
Started Aug 01 06:41:08 PM PDT 24
Finished Aug 01 06:41:09 PM PDT 24
Peak memory 203920 kb
Host smart-2550487d-a36f-4861-920d-cce8c27bfd1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624069861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
624069861
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1299531148
Short name T1082
Test name
Test status
Simulation time 51801047 ps
CPU time 2.83 seconds
Started Aug 01 06:41:06 PM PDT 24
Finished Aug 01 06:41:09 PM PDT 24
Peak memory 215168 kb
Host smart-b1991c4c-8b86-43b8-9979-c679eacd020a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299531148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1299531148
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1606544752
Short name T1100
Test name
Test status
Simulation time 38054153 ps
CPU time 2.09 seconds
Started Aug 01 06:41:06 PM PDT 24
Finished Aug 01 06:41:08 PM PDT 24
Peak memory 215416 kb
Host smart-9ebaa0b3-0e26-49f2-9d3b-d774f5b733c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606544752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
606544752
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3747605821
Short name T154
Test name
Test status
Simulation time 568940795 ps
CPU time 13.01 seconds
Started Aug 01 06:41:07 PM PDT 24
Finished Aug 01 06:41:20 PM PDT 24
Peak memory 215072 kb
Host smart-714b32eb-1fa6-41f8-8c9b-8d8c27459f08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747605821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3747605821
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.165349954
Short name T1063
Test name
Test status
Simulation time 113080987 ps
CPU time 1.88 seconds
Started Aug 01 06:41:19 PM PDT 24
Finished Aug 01 06:41:21 PM PDT 24
Peak memory 214444 kb
Host smart-ec9f03ce-6c47-4d1c-bde7-b19946366f8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165349954 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.165349954
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1360490718
Short name T1124
Test name
Test status
Simulation time 120092203 ps
CPU time 2.13 seconds
Started Aug 01 06:41:17 PM PDT 24
Finished Aug 01 06:41:20 PM PDT 24
Peak memory 215152 kb
Host smart-de3beb3b-c809-4a51-b53c-52d59c50ec28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360490718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
360490718
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1742210604
Short name T1053
Test name
Test status
Simulation time 19916928 ps
CPU time 0.73 seconds
Started Aug 01 06:41:17 PM PDT 24
Finished Aug 01 06:41:18 PM PDT 24
Peak memory 203604 kb
Host smart-ec8ef855-2ead-4afa-9156-5582e654cf9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742210604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
742210604
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.242400095
Short name T1026
Test name
Test status
Simulation time 67147230 ps
CPU time 3.78 seconds
Started Aug 01 06:41:17 PM PDT 24
Finished Aug 01 06:41:21 PM PDT 24
Peak memory 215332 kb
Host smart-11aa60f2-a103-4ece-a094-6d3de034fe4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242400095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.242400095
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3604289978
Short name T128
Test name
Test status
Simulation time 569966162 ps
CPU time 2.91 seconds
Started Aug 01 06:41:18 PM PDT 24
Finished Aug 01 06:41:21 PM PDT 24
Peak memory 217868 kb
Host smart-1297fe28-c5d2-4869-b6ef-39b1163970f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604289978 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3604289978
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.287205691
Short name T106
Test name
Test status
Simulation time 1222652513 ps
CPU time 1.94 seconds
Started Aug 01 06:41:16 PM PDT 24
Finished Aug 01 06:41:18 PM PDT 24
Peak memory 215088 kb
Host smart-255562a0-f456-48ae-80ea-7929777763a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287205691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.287205691
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1267093335
Short name T1055
Test name
Test status
Simulation time 15193001 ps
CPU time 0.68 seconds
Started Aug 01 06:41:20 PM PDT 24
Finished Aug 01 06:41:21 PM PDT 24
Peak memory 203956 kb
Host smart-256a4c1a-3fcf-483d-8cb2-fd8c2175b91f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267093335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
267093335
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.638595066
Short name T115
Test name
Test status
Simulation time 543681798 ps
CPU time 3.12 seconds
Started Aug 01 06:41:19 PM PDT 24
Finished Aug 01 06:41:22 PM PDT 24
Peak memory 215204 kb
Host smart-c48dfc90-1a4a-4ee5-99e2-9da1e2bf3a4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638595066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.638595066
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4066999221
Short name T55
Test name
Test status
Simulation time 372316237 ps
CPU time 4.61 seconds
Started Aug 01 06:41:21 PM PDT 24
Finished Aug 01 06:41:25 PM PDT 24
Peak memory 215140 kb
Host smart-4b6b53be-7a5a-4a1f-9fe6-fb32423615e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066999221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.4
066999221
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2690331928
Short name T1105
Test name
Test status
Simulation time 449306520 ps
CPU time 7.4 seconds
Started Aug 01 06:41:18 PM PDT 24
Finished Aug 01 06:41:26 PM PDT 24
Peak memory 215180 kb
Host smart-88d3a9a8-bb0b-4d44-9deb-65902cd1a172
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690331928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2690331928
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1657100966
Short name T1057
Test name
Test status
Simulation time 175934659 ps
CPU time 2.69 seconds
Started Aug 01 06:41:21 PM PDT 24
Finished Aug 01 06:41:23 PM PDT 24
Peak memory 217732 kb
Host smart-b0058f81-0c71-4779-8a58-f2a31142532c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657100966 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1657100966
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3888048841
Short name T130
Test name
Test status
Simulation time 49568631 ps
CPU time 1.43 seconds
Started Aug 01 06:41:22 PM PDT 24
Finished Aug 01 06:41:24 PM PDT 24
Peak memory 215148 kb
Host smart-7915514a-4204-47c1-b393-874553f1f4d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888048841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
888048841
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3426623673
Short name T1069
Test name
Test status
Simulation time 19484506 ps
CPU time 0.7 seconds
Started Aug 01 06:41:21 PM PDT 24
Finished Aug 01 06:41:22 PM PDT 24
Peak memory 203908 kb
Host smart-e063f8dc-41c8-41c6-b886-bd8baef380ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426623673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
426623673
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3470916753
Short name T1091
Test name
Test status
Simulation time 556733658 ps
CPU time 3.12 seconds
Started Aug 01 06:41:16 PM PDT 24
Finished Aug 01 06:41:19 PM PDT 24
Peak memory 215136 kb
Host smart-889bf7bd-5c48-4ada-8a0c-14ac9b0373f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470916753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3470916753
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3093237272
Short name T92
Test name
Test status
Simulation time 528575812 ps
CPU time 3.79 seconds
Started Aug 01 06:41:19 PM PDT 24
Finished Aug 01 06:41:22 PM PDT 24
Peak memory 215332 kb
Host smart-8ca93c1c-0514-4d29-b10a-b3b70688b953
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093237272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
093237272
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2982973498
Short name T158
Test name
Test status
Simulation time 433155546 ps
CPU time 6.52 seconds
Started Aug 01 06:41:17 PM PDT 24
Finished Aug 01 06:41:24 PM PDT 24
Peak memory 215224 kb
Host smart-367df7b1-5162-43cd-ae30-7c2659430a61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982973498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2982973498
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1839001673
Short name T1035
Test name
Test status
Simulation time 217713083 ps
CPU time 2.52 seconds
Started Aug 01 06:41:19 PM PDT 24
Finished Aug 01 06:41:22 PM PDT 24
Peak memory 216068 kb
Host smart-036a45fd-1a2e-4f79-8dad-4fe02cbd20e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839001673 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1839001673
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1069395524
Short name T101
Test name
Test status
Simulation time 267687042 ps
CPU time 1.99 seconds
Started Aug 01 06:41:19 PM PDT 24
Finished Aug 01 06:41:21 PM PDT 24
Peak memory 215088 kb
Host smart-5c8a1d29-4991-42f1-8441-8d772c910f4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069395524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
069395524
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3658266318
Short name T1019
Test name
Test status
Simulation time 32556728 ps
CPU time 0.72 seconds
Started Aug 01 06:41:21 PM PDT 24
Finished Aug 01 06:41:22 PM PDT 24
Peak memory 203920 kb
Host smart-f9542357-920c-4319-94b0-60ef736196dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658266318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
658266318
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2318905991
Short name T1079
Test name
Test status
Simulation time 160501419 ps
CPU time 1.69 seconds
Started Aug 01 06:41:20 PM PDT 24
Finished Aug 01 06:41:22 PM PDT 24
Peak memory 214324 kb
Host smart-0c2454e9-4406-4fad-ab52-e234591d0985
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318905991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2318905991
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1971610803
Short name T1094
Test name
Test status
Simulation time 2638352951 ps
CPU time 4.31 seconds
Started Aug 01 06:41:21 PM PDT 24
Finished Aug 01 06:41:25 PM PDT 24
Peak memory 215256 kb
Host smart-bba76873-10ae-43cd-8474-3274fb0917a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971610803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
971610803
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1334776212
Short name T161
Test name
Test status
Simulation time 3523836564 ps
CPU time 16.12 seconds
Started Aug 01 06:41:19 PM PDT 24
Finished Aug 01 06:41:35 PM PDT 24
Peak memory 215240 kb
Host smart-c093bdf4-5f46-4620-97b3-80d00201aa9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334776212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1334776212
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.341430027
Short name T850
Test name
Test status
Simulation time 49311163 ps
CPU time 0.74 seconds
Started Aug 01 06:44:51 PM PDT 24
Finished Aug 01 06:44:52 PM PDT 24
Peak memory 205212 kb
Host smart-de16be4e-ba6d-4ef5-96f8-77737da1523d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341430027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.341430027
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3573354593
Short name T318
Test name
Test status
Simulation time 764433942 ps
CPU time 10.11 seconds
Started Aug 01 06:44:57 PM PDT 24
Finished Aug 01 06:45:07 PM PDT 24
Peak memory 233072 kb
Host smart-1d1bffce-44d6-4694-943c-32fd2a795b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573354593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3573354593
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2466709114
Short name T290
Test name
Test status
Simulation time 26467401 ps
CPU time 0.73 seconds
Started Aug 01 06:44:50 PM PDT 24
Finished Aug 01 06:44:51 PM PDT 24
Peak memory 205872 kb
Host smart-d529f57b-8453-4239-a7e2-b1eddc7ea7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466709114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2466709114
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1632857703
Short name T191
Test name
Test status
Simulation time 27583753466 ps
CPU time 117.4 seconds
Started Aug 01 06:44:59 PM PDT 24
Finished Aug 01 06:46:57 PM PDT 24
Peak memory 250980 kb
Host smart-eb1cf224-7d6c-42db-8fd3-ddd05615e2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632857703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1632857703
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1921379720
Short name T980
Test name
Test status
Simulation time 32832547615 ps
CPU time 31.83 seconds
Started Aug 01 06:44:52 PM PDT 24
Finished Aug 01 06:45:24 PM PDT 24
Peak memory 239516 kb
Host smart-b335b0db-b090-4c04-83fd-b4e1280f36d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921379720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1921379720
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3275122362
Short name T932
Test name
Test status
Simulation time 6201227350 ps
CPU time 15.88 seconds
Started Aug 01 06:44:53 PM PDT 24
Finished Aug 01 06:45:09 PM PDT 24
Peak memory 249672 kb
Host smart-884f6d48-9650-4de1-ba5f-92aca744e6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275122362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3275122362
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3127021147
Short name T411
Test name
Test status
Simulation time 913225821 ps
CPU time 4.68 seconds
Started Aug 01 06:44:54 PM PDT 24
Finished Aug 01 06:44:59 PM PDT 24
Peak memory 233076 kb
Host smart-5f68ff2c-fffc-42a3-a8f8-8bd3c273501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127021147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3127021147
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4190385697
Short name T755
Test name
Test status
Simulation time 587794171 ps
CPU time 6.9 seconds
Started Aug 01 06:44:59 PM PDT 24
Finished Aug 01 06:45:06 PM PDT 24
Peak memory 224800 kb
Host smart-e47ada57-5564-4668-bb46-eff64d518425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190385697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4190385697
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3322713841
Short name T227
Test name
Test status
Simulation time 32600452370 ps
CPU time 93.99 seconds
Started Aug 01 06:44:53 PM PDT 24
Finished Aug 01 06:46:27 PM PDT 24
Peak memory 235488 kb
Host smart-d4942a75-09ab-46b5-a512-5fae0a4c2f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322713841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3322713841
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.961212287
Short name T835
Test name
Test status
Simulation time 384973742 ps
CPU time 5.63 seconds
Started Aug 01 06:44:54 PM PDT 24
Finished Aug 01 06:45:00 PM PDT 24
Peak memory 233140 kb
Host smart-826b61f1-0e18-4b7a-9e3b-2232c452baf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961212287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
961212287
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3089330607
Short name T236
Test name
Test status
Simulation time 208656274 ps
CPU time 2.3 seconds
Started Aug 01 06:44:51 PM PDT 24
Finished Aug 01 06:44:53 PM PDT 24
Peak memory 233052 kb
Host smart-73b0d6ca-7df4-4255-83da-7b2c9b879a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089330607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3089330607
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3596339521
Short name T759
Test name
Test status
Simulation time 1301654961 ps
CPU time 12.76 seconds
Started Aug 01 06:44:53 PM PDT 24
Finished Aug 01 06:45:06 PM PDT 24
Peak memory 221948 kb
Host smart-9d1d4b15-f446-45b0-829b-aca827c64a1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3596339521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3596339521
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1168717615
Short name T565
Test name
Test status
Simulation time 56305401610 ps
CPU time 136.75 seconds
Started Aug 01 06:44:52 PM PDT 24
Finished Aug 01 06:47:09 PM PDT 24
Peak memory 257712 kb
Host smart-a300b56e-736d-4ffe-b990-e5b181e866f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168717615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1168717615
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.937338321
Short name T528
Test name
Test status
Simulation time 3584932758 ps
CPU time 23.76 seconds
Started Aug 01 06:44:51 PM PDT 24
Finished Aug 01 06:45:15 PM PDT 24
Peak memory 216684 kb
Host smart-508b52ee-99ef-4432-adbd-ca0dacc144af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937338321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.937338321
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3732831598
Short name T293
Test name
Test status
Simulation time 3274910349 ps
CPU time 11.85 seconds
Started Aug 01 06:44:50 PM PDT 24
Finished Aug 01 06:45:02 PM PDT 24
Peak memory 216724 kb
Host smart-3adc657a-4bd7-462f-a5f6-4b7aaabac217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732831598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3732831598
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2856514866
Short name T784
Test name
Test status
Simulation time 1262340516 ps
CPU time 8.36 seconds
Started Aug 01 06:44:51 PM PDT 24
Finished Aug 01 06:44:59 PM PDT 24
Peak memory 216680 kb
Host smart-07abd748-4e0a-4076-8d49-04afd531a294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856514866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2856514866
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2209903737
Short name T455
Test name
Test status
Simulation time 54493781 ps
CPU time 0.99 seconds
Started Aug 01 06:44:59 PM PDT 24
Finished Aug 01 06:45:00 PM PDT 24
Peak memory 206312 kb
Host smart-dc301aa0-20f9-4a0f-b3d1-1fff981ba777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209903737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2209903737
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1511799970
Short name T480
Test name
Test status
Simulation time 5851506775 ps
CPU time 5.13 seconds
Started Aug 01 06:44:51 PM PDT 24
Finished Aug 01 06:44:56 PM PDT 24
Peak memory 224992 kb
Host smart-cb22a9e2-110b-429a-9964-82bc547d6b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511799970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1511799970
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4005296167
Short name T441
Test name
Test status
Simulation time 12194225 ps
CPU time 0.73 seconds
Started Aug 01 06:45:00 PM PDT 24
Finished Aug 01 06:45:01 PM PDT 24
Peak memory 205216 kb
Host smart-fb919e75-2cd7-4ef5-81c5-bd3a66a25d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005296167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
005296167
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2229208053
Short name T804
Test name
Test status
Simulation time 91758066 ps
CPU time 2.85 seconds
Started Aug 01 06:44:55 PM PDT 24
Finished Aug 01 06:44:58 PM PDT 24
Peak memory 233160 kb
Host smart-f5e3e0b4-3551-46c7-9528-642ad9f94980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229208053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2229208053
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2215391620
Short name T704
Test name
Test status
Simulation time 60552627 ps
CPU time 0.82 seconds
Started Aug 01 06:44:50 PM PDT 24
Finished Aug 01 06:44:51 PM PDT 24
Peak memory 206920 kb
Host smart-8a5eadee-8a33-4574-aca9-d5a669592085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215391620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2215391620
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1321021947
Short name T705
Test name
Test status
Simulation time 43637802957 ps
CPU time 348.16 seconds
Started Aug 01 06:44:52 PM PDT 24
Finished Aug 01 06:50:40 PM PDT 24
Peak memory 265880 kb
Host smart-82936b7d-2c73-4431-96fd-20ae9207d49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321021947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1321021947
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1730951172
Short name T956
Test name
Test status
Simulation time 423490571405 ps
CPU time 360.13 seconds
Started Aug 01 06:44:53 PM PDT 24
Finished Aug 01 06:50:54 PM PDT 24
Peak memory 249548 kb
Host smart-4118a417-2b4d-4fee-84e8-ce9a1495a392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730951172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1730951172
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.146555813
Short name T42
Test name
Test status
Simulation time 109730214234 ps
CPU time 263.77 seconds
Started Aug 01 06:44:56 PM PDT 24
Finished Aug 01 06:49:20 PM PDT 24
Peak memory 257672 kb
Host smart-ac42cf2c-a6e7-4406-a64a-0877810f1ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146555813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
146555813
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1165365974
Short name T499
Test name
Test status
Simulation time 2293941335 ps
CPU time 31.09 seconds
Started Aug 01 06:44:59 PM PDT 24
Finished Aug 01 06:45:30 PM PDT 24
Peak memory 224988 kb
Host smart-c0fde4d9-89d1-4392-a964-9abfef53c0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165365974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1165365974
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1081866652
Short name T442
Test name
Test status
Simulation time 42020635375 ps
CPU time 284.17 seconds
Started Aug 01 06:44:50 PM PDT 24
Finished Aug 01 06:49:34 PM PDT 24
Peak memory 255760 kb
Host smart-533ef921-d0bc-4375-a0f5-3f838814b671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081866652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1081866652
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3613133798
Short name T405
Test name
Test status
Simulation time 287095157 ps
CPU time 3.68 seconds
Started Aug 01 06:44:52 PM PDT 24
Finished Aug 01 06:44:56 PM PDT 24
Peak memory 233084 kb
Host smart-24daff28-e305-4064-9821-57b780dca3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613133798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3613133798
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3954258769
Short name T923
Test name
Test status
Simulation time 7779363857 ps
CPU time 19.54 seconds
Started Aug 01 06:44:56 PM PDT 24
Finished Aug 01 06:45:15 PM PDT 24
Peak memory 224992 kb
Host smart-f729690e-6862-4ef4-b09e-768aec7e587b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954258769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3954258769
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3603304835
Short name T298
Test name
Test status
Simulation time 62562668 ps
CPU time 2.28 seconds
Started Aug 01 06:44:56 PM PDT 24
Finished Aug 01 06:44:59 PM PDT 24
Peak memory 232844 kb
Host smart-833b7070-8b34-4f79-be25-8b12a581a35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603304835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3603304835
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4233622867
Short name T346
Test name
Test status
Simulation time 2719882964 ps
CPU time 9.51 seconds
Started Aug 01 06:44:56 PM PDT 24
Finished Aug 01 06:45:06 PM PDT 24
Peak memory 240832 kb
Host smart-d5e859c5-fcef-4217-949a-7b7cc651a3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233622867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4233622867
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3818207423
Short name T556
Test name
Test status
Simulation time 173937378 ps
CPU time 3.85 seconds
Started Aug 01 06:44:51 PM PDT 24
Finished Aug 01 06:44:55 PM PDT 24
Peak memory 219180 kb
Host smart-c33dfad8-4129-4ca3-9882-1ee536837891
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3818207423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3818207423
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1247473802
Short name T60
Test name
Test status
Simulation time 147385678 ps
CPU time 0.96 seconds
Started Aug 01 06:44:50 PM PDT 24
Finished Aug 01 06:44:51 PM PDT 24
Peak memory 236836 kb
Host smart-f69754e4-da08-479d-83fd-1e27d271ce87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247473802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1247473802
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.295768986
Short name T438
Test name
Test status
Simulation time 8104473857 ps
CPU time 8.78 seconds
Started Aug 01 06:44:56 PM PDT 24
Finished Aug 01 06:45:05 PM PDT 24
Peak memory 216736 kb
Host smart-435e21c2-9702-4be2-aecd-b6f7506535d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295768986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.295768986
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1210898453
Short name T335
Test name
Test status
Simulation time 3200410800 ps
CPU time 10.38 seconds
Started Aug 01 06:44:54 PM PDT 24
Finished Aug 01 06:45:04 PM PDT 24
Peak memory 216736 kb
Host smart-9705334d-a95e-4c72-8635-b7362226991c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210898453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1210898453
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4292745169
Short name T27
Test name
Test status
Simulation time 36503150 ps
CPU time 1.43 seconds
Started Aug 01 06:44:52 PM PDT 24
Finished Aug 01 06:44:54 PM PDT 24
Peak memory 216664 kb
Host smart-2ac68e3c-0f38-47d2-aece-550782206e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292745169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4292745169
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.716937720
Short name T709
Test name
Test status
Simulation time 22902867 ps
CPU time 0.76 seconds
Started Aug 01 06:44:57 PM PDT 24
Finished Aug 01 06:44:58 PM PDT 24
Peak memory 206340 kb
Host smart-d5df18b3-cea0-43e7-bac5-182a37b682c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716937720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.716937720
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.274446185
Short name T887
Test name
Test status
Simulation time 3157974535 ps
CPU time 9.58 seconds
Started Aug 01 06:44:56 PM PDT 24
Finished Aug 01 06:45:06 PM PDT 24
Peak memory 239240 kb
Host smart-db898b8d-e65a-4a6c-86e9-ee970a8eef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274446185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.274446185
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2693049502
Short name T846
Test name
Test status
Simulation time 4753920857 ps
CPU time 10.19 seconds
Started Aug 01 06:45:33 PM PDT 24
Finished Aug 01 06:45:44 PM PDT 24
Peak memory 224916 kb
Host smart-4d55b73b-4e11-48ed-b9e7-6811611e9fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693049502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2693049502
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.133215434
Short name T1011
Test name
Test status
Simulation time 22141514 ps
CPU time 0.8 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:45:40 PM PDT 24
Peak memory 207296 kb
Host smart-026a9da3-1ddd-4be8-8d65-ab21127e737c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133215434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.133215434
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.361409746
Short name T350
Test name
Test status
Simulation time 1677774158 ps
CPU time 16.16 seconds
Started Aug 01 06:45:36 PM PDT 24
Finished Aug 01 06:45:52 PM PDT 24
Peak memory 241296 kb
Host smart-42b89816-2798-4f56-ab80-2d6d1e8a6c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361409746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.361409746
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1885589152
Short name T680
Test name
Test status
Simulation time 8385775885 ps
CPU time 46.11 seconds
Started Aug 01 06:45:50 PM PDT 24
Finished Aug 01 06:46:37 PM PDT 24
Peak memory 252840 kb
Host smart-e20a46b0-3ba4-43ce-8617-c4d85decdddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885589152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1885589152
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1952413705
Short name T177
Test name
Test status
Simulation time 115444585525 ps
CPU time 267.41 seconds
Started Aug 01 06:45:35 PM PDT 24
Finished Aug 01 06:50:03 PM PDT 24
Peak memory 264024 kb
Host smart-fcdbca48-94b5-49b3-b452-725fa132d99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952413705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1952413705
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3631484203
Short name T879
Test name
Test status
Simulation time 46036892 ps
CPU time 3.21 seconds
Started Aug 01 06:45:38 PM PDT 24
Finished Aug 01 06:45:41 PM PDT 24
Peak memory 233076 kb
Host smart-5e70ca90-849c-42d6-a399-db4a4625a0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631484203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3631484203
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2078460126
Short name T32
Test name
Test status
Simulation time 5147364366 ps
CPU time 26.59 seconds
Started Aug 01 06:45:40 PM PDT 24
Finished Aug 01 06:46:07 PM PDT 24
Peak memory 240684 kb
Host smart-d8f2a396-926e-4a14-a2d3-2cff66b4bd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078460126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2078460126
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1954144394
Short name T641
Test name
Test status
Simulation time 4185525455 ps
CPU time 11.79 seconds
Started Aug 01 06:45:45 PM PDT 24
Finished Aug 01 06:45:57 PM PDT 24
Peak memory 233252 kb
Host smart-5e6d922b-38f3-45b8-a1ec-908a0c539230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954144394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1954144394
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1524647494
Short name T660
Test name
Test status
Simulation time 6749515534 ps
CPU time 11.44 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:45:50 PM PDT 24
Peak memory 233168 kb
Host smart-5c26c74b-fa6a-4290-b140-407399b9109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524647494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1524647494
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.285935308
Short name T365
Test name
Test status
Simulation time 106491516 ps
CPU time 2.36 seconds
Started Aug 01 06:45:40 PM PDT 24
Finished Aug 01 06:45:43 PM PDT 24
Peak memory 224476 kb
Host smart-7bab0101-9ee1-4d80-9288-65e0bfb3ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285935308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.285935308
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3960716430
Short name T3
Test name
Test status
Simulation time 1967490055 ps
CPU time 8.72 seconds
Started Aug 01 06:45:49 PM PDT 24
Finished Aug 01 06:45:58 PM PDT 24
Peak memory 233088 kb
Host smart-6206d9f9-8004-415f-abef-411f3d6f4b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960716430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3960716430
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.169352459
Short name T370
Test name
Test status
Simulation time 2393418226 ps
CPU time 6.89 seconds
Started Aug 01 06:45:45 PM PDT 24
Finished Aug 01 06:45:53 PM PDT 24
Peak memory 221276 kb
Host smart-48619af4-8451-4d01-a987-7329227e4b4b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=169352459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.169352459
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.279025735
Short name T246
Test name
Test status
Simulation time 124677718538 ps
CPU time 471.11 seconds
Started Aug 01 06:45:45 PM PDT 24
Finished Aug 01 06:53:36 PM PDT 24
Peak memory 282168 kb
Host smart-5e9f8c7d-0a30-4ef4-a2b2-964b0909a001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279025735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.279025735
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2010196519
Short name T269
Test name
Test status
Simulation time 8198311282 ps
CPU time 21.06 seconds
Started Aug 01 06:45:37 PM PDT 24
Finished Aug 01 06:45:58 PM PDT 24
Peak memory 216668 kb
Host smart-e814ba7e-65cd-498b-b6bd-f4acf4013d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010196519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2010196519
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1366844195
Short name T359
Test name
Test status
Simulation time 4864289281 ps
CPU time 2.52 seconds
Started Aug 01 06:45:34 PM PDT 24
Finished Aug 01 06:45:37 PM PDT 24
Peak memory 208288 kb
Host smart-beca330c-4dcf-49d8-872e-0dea94476e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366844195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1366844195
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.539265148
Short name T588
Test name
Test status
Simulation time 169647699 ps
CPU time 2.18 seconds
Started Aug 01 06:45:41 PM PDT 24
Finished Aug 01 06:45:43 PM PDT 24
Peak memory 216564 kb
Host smart-254a17f9-9a33-49ce-84a9-af119d4956c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539265148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.539265148
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.412222115
Short name T913
Test name
Test status
Simulation time 16981503 ps
CPU time 0.72 seconds
Started Aug 01 06:45:45 PM PDT 24
Finished Aug 01 06:45:46 PM PDT 24
Peak memory 206372 kb
Host smart-a1a27732-0580-4abe-8cc0-4cb5cba3edaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412222115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.412222115
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.4122965185
Short name T643
Test name
Test status
Simulation time 1359236945 ps
CPU time 4.14 seconds
Started Aug 01 06:45:40 PM PDT 24
Finished Aug 01 06:45:44 PM PDT 24
Peak memory 224872 kb
Host smart-4eea688c-53a6-4f3c-afef-fa279758be44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122965185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4122965185
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.69538194
Short name T538
Test name
Test status
Simulation time 14819810 ps
CPU time 0.74 seconds
Started Aug 01 06:45:42 PM PDT 24
Finished Aug 01 06:45:42 PM PDT 24
Peak memory 205232 kb
Host smart-8de396ed-4bc4-4d2d-a96a-742afa508088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69538194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.69538194
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1327456617
Short name T558
Test name
Test status
Simulation time 139806473 ps
CPU time 2.85 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:45:42 PM PDT 24
Peak memory 224928 kb
Host smart-cdd5bd58-0756-40a5-82c9-28fbf7902012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327456617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1327456617
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2916618690
Short name T316
Test name
Test status
Simulation time 66705634 ps
CPU time 0.74 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:45:39 PM PDT 24
Peak memory 206960 kb
Host smart-a2fa5715-6a30-4847-9683-e71f298443a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916618690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2916618690
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1331018877
Short name T39
Test name
Test status
Simulation time 36780211994 ps
CPU time 90.07 seconds
Started Aug 01 06:45:41 PM PDT 24
Finished Aug 01 06:47:12 PM PDT 24
Peak memory 255784 kb
Host smart-3904c722-9fd5-4f17-94c1-ea57ca8f6f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331018877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1331018877
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2695785796
Short name T517
Test name
Test status
Simulation time 6507224404 ps
CPU time 27.28 seconds
Started Aug 01 06:45:40 PM PDT 24
Finished Aug 01 06:46:07 PM PDT 24
Peak memory 251264 kb
Host smart-c18ee53f-24cb-4ba8-bcd2-1290b5f085a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695785796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2695785796
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2951217399
Short name T197
Test name
Test status
Simulation time 113564467708 ps
CPU time 531.17 seconds
Started Aug 01 06:45:36 PM PDT 24
Finished Aug 01 06:54:28 PM PDT 24
Peak memory 272544 kb
Host smart-1da00ff0-36c4-4f04-985f-13e6fc4f0245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951217399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2951217399
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.867832553
Short name T257
Test name
Test status
Simulation time 1165073211 ps
CPU time 19.42 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:45:59 PM PDT 24
Peak memory 249504 kb
Host smart-bf3f03fb-ebbb-4c7f-88a1-b01938844449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867832553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.867832553
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1381104946
Short name T620
Test name
Test status
Simulation time 8583772073 ps
CPU time 77.85 seconds
Started Aug 01 06:45:36 PM PDT 24
Finished Aug 01 06:46:54 PM PDT 24
Peak memory 251748 kb
Host smart-ee2ac6b7-836d-440c-b7ac-880c6521cfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381104946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1381104946
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2972943322
Short name T176
Test name
Test status
Simulation time 400526823 ps
CPU time 6.56 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:45:46 PM PDT 24
Peak memory 233124 kb
Host smart-a486f54e-e9f2-4061-a3e5-f1b80effed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972943322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2972943322
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3259382086
Short name T312
Test name
Test status
Simulation time 2310003602 ps
CPU time 19.36 seconds
Started Aug 01 06:45:37 PM PDT 24
Finished Aug 01 06:45:57 PM PDT 24
Peak memory 233832 kb
Host smart-16e71dd9-2811-4253-915b-e61892873b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259382086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3259382086
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.4253894852
Short name T255
Test name
Test status
Simulation time 17937135623 ps
CPU time 15.93 seconds
Started Aug 01 06:45:45 PM PDT 24
Finished Aug 01 06:46:01 PM PDT 24
Peak memory 233264 kb
Host smart-f6945ca6-30d4-43f5-ac57-0fbe7abd4b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253894852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.4253894852
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2780610036
Short name T586
Test name
Test status
Simulation time 409417777 ps
CPU time 3.4 seconds
Started Aug 01 06:45:46 PM PDT 24
Finished Aug 01 06:45:49 PM PDT 24
Peak memory 233176 kb
Host smart-4a08caae-dffd-474b-ab48-5ed1ef1ddd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780610036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2780610036
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2871441141
Short name T123
Test name
Test status
Simulation time 127799146 ps
CPU time 3.99 seconds
Started Aug 01 06:45:40 PM PDT 24
Finished Aug 01 06:45:44 PM PDT 24
Peak memory 223204 kb
Host smart-6c45e368-39ed-4135-893e-397aa5439128
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2871441141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2871441141
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1100978718
Short name T132
Test name
Test status
Simulation time 18682040154 ps
CPU time 155.46 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:48:15 PM PDT 24
Peak memory 249656 kb
Host smart-519624c1-82d1-4328-a993-fa9e482f0644
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100978718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1100978718
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2996140184
Short name T273
Test name
Test status
Simulation time 2476408553 ps
CPU time 29.76 seconds
Started Aug 01 06:45:44 PM PDT 24
Finished Aug 01 06:46:14 PM PDT 24
Peak memory 216808 kb
Host smart-1c417c9a-fa37-4041-963e-5cfe36d4a582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996140184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2996140184
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3165828984
Short name T876
Test name
Test status
Simulation time 782480461 ps
CPU time 1.68 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:45:41 PM PDT 24
Peak memory 208240 kb
Host smart-179a508d-f216-4fef-aa56-0c9da2d6108f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165828984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3165828984
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2741907131
Short name T917
Test name
Test status
Simulation time 1207503444 ps
CPU time 2.2 seconds
Started Aug 01 06:45:38 PM PDT 24
Finished Aug 01 06:45:40 PM PDT 24
Peak memory 216588 kb
Host smart-efa5864b-339d-4417-b30e-8e8c27d6c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741907131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2741907131
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1471431659
Short name T918
Test name
Test status
Simulation time 18972848 ps
CPU time 0.76 seconds
Started Aug 01 06:45:40 PM PDT 24
Finished Aug 01 06:45:41 PM PDT 24
Peak memory 206324 kb
Host smart-e9b20e6b-e237-4fe4-9b5d-9c21848baadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471431659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1471431659
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.91983588
Short name T885
Test name
Test status
Simulation time 640243156 ps
CPU time 2.34 seconds
Started Aug 01 06:45:49 PM PDT 24
Finished Aug 01 06:45:52 PM PDT 24
Peak memory 224440 kb
Host smart-b61dcb41-8fbb-4b6c-9fc8-8854ef75b4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91983588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.91983588
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3670898199
Short name T960
Test name
Test status
Simulation time 33722175 ps
CPU time 0.72 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:45:40 PM PDT 24
Peak memory 205192 kb
Host smart-d14a8af5-2bcc-4f01-85a5-8764913d8884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670898199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3670898199
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.689957151
Short name T460
Test name
Test status
Simulation time 33645390 ps
CPU time 2.51 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:45:42 PM PDT 24
Peak memory 232756 kb
Host smart-fd6f4a68-2500-4042-abd2-b6cfd43dc5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689957151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.689957151
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.962192566
Short name T48
Test name
Test status
Simulation time 17029927 ps
CPU time 0.78 seconds
Started Aug 01 06:45:50 PM PDT 24
Finished Aug 01 06:45:50 PM PDT 24
Peak memory 207340 kb
Host smart-389606f0-da3e-4d14-952f-7c5e1746d479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962192566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.962192566
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.4011261212
Short name T254
Test name
Test status
Simulation time 3403693888 ps
CPU time 71.46 seconds
Started Aug 01 06:45:40 PM PDT 24
Finished Aug 01 06:46:52 PM PDT 24
Peak memory 254452 kb
Host smart-a395b2af-4d48-48e2-90dd-6cb314d363ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011261212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.4011261212
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3780944320
Short name T145
Test name
Test status
Simulation time 4008144362 ps
CPU time 58.99 seconds
Started Aug 01 06:45:36 PM PDT 24
Finished Aug 01 06:46:35 PM PDT 24
Peak memory 252284 kb
Host smart-87bb8bdc-2dec-4dbe-825f-0ddb1b08bfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780944320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3780944320
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2790859303
Short name T672
Test name
Test status
Simulation time 3801034820 ps
CPU time 39.62 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:46:19 PM PDT 24
Peak memory 252892 kb
Host smart-cf5d5939-1476-4a3d-bafa-58b65bc2f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790859303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2790859303
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2245573430
Short name T893
Test name
Test status
Simulation time 1001338626 ps
CPU time 8.09 seconds
Started Aug 01 06:45:50 PM PDT 24
Finished Aug 01 06:45:58 PM PDT 24
Peak memory 221660 kb
Host smart-b7b1c428-4577-4468-9686-2c2c8943b4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245573430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2245573430
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.580663957
Short name T343
Test name
Test status
Simulation time 30766992 ps
CPU time 2.66 seconds
Started Aug 01 06:45:50 PM PDT 24
Finished Aug 01 06:45:52 PM PDT 24
Peak memory 232864 kb
Host smart-ee4099f9-45f0-4443-9c92-1dfdcdc1ca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580663957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.580663957
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1944275289
Short name T419
Test name
Test status
Simulation time 75513382 ps
CPU time 2.25 seconds
Started Aug 01 06:45:41 PM PDT 24
Finished Aug 01 06:45:43 PM PDT 24
Peak memory 224148 kb
Host smart-0fb35624-b118-46fe-a30d-3ceaa2d78505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944275289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1944275289
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3544538330
Short name T214
Test name
Test status
Simulation time 6565478393 ps
CPU time 10.17 seconds
Started Aug 01 06:45:50 PM PDT 24
Finished Aug 01 06:46:01 PM PDT 24
Peak memory 233124 kb
Host smart-3045a5c5-90a4-4309-8fdd-6dec465a410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544538330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3544538330
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3905563506
Short name T317
Test name
Test status
Simulation time 7588283250 ps
CPU time 11.2 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:45:50 PM PDT 24
Peak memory 221008 kb
Host smart-67b9a461-35da-4f5e-b574-dec248731952
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3905563506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3905563506
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1127899715
Short name T249
Test name
Test status
Simulation time 114756935670 ps
CPU time 295.32 seconds
Started Aug 01 06:45:49 PM PDT 24
Finished Aug 01 06:50:44 PM PDT 24
Peak memory 270316 kb
Host smart-03185fc0-aabf-473d-913a-0331c63cfd4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127899715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1127899715
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2800579894
Short name T663
Test name
Test status
Simulation time 2827145815 ps
CPU time 27.17 seconds
Started Aug 01 06:45:49 PM PDT 24
Finished Aug 01 06:46:16 PM PDT 24
Peak memory 216936 kb
Host smart-b59efb12-caab-46ca-a1ae-762e0a564a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800579894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2800579894
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.635928028
Short name T811
Test name
Test status
Simulation time 618143858 ps
CPU time 4.02 seconds
Started Aug 01 06:45:42 PM PDT 24
Finished Aug 01 06:45:46 PM PDT 24
Peak memory 216652 kb
Host smart-98fb5854-a8ea-4e75-92dc-a73d9f81533c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635928028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.635928028
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1963086614
Short name T472
Test name
Test status
Simulation time 43801232 ps
CPU time 1.5 seconds
Started Aug 01 06:45:41 PM PDT 24
Finished Aug 01 06:45:42 PM PDT 24
Peak memory 216600 kb
Host smart-27e28d2a-2234-4d5d-b83c-578ba6b57d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963086614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1963086614
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3562249397
Short name T506
Test name
Test status
Simulation time 60714841 ps
CPU time 0.71 seconds
Started Aug 01 06:45:50 PM PDT 24
Finished Aug 01 06:45:51 PM PDT 24
Peak memory 206356 kb
Host smart-6143c357-55d2-4a44-b9eb-8ce6e17f0aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562249397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3562249397
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1012984258
Short name T429
Test name
Test status
Simulation time 3354024055 ps
CPU time 11.55 seconds
Started Aug 01 06:45:38 PM PDT 24
Finished Aug 01 06:45:50 PM PDT 24
Peak memory 233136 kb
Host smart-5887b222-5c00-49a3-a656-5e112bf9bf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012984258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1012984258
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.30083656
Short name T560
Test name
Test status
Simulation time 27403415 ps
CPU time 0.73 seconds
Started Aug 01 06:46:06 PM PDT 24
Finished Aug 01 06:46:07 PM PDT 24
Peak memory 205816 kb
Host smart-b63d01cd-1f71-4d68-bd70-212fbfda8681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30083656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.30083656
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3405157058
Short name T783
Test name
Test status
Simulation time 2856489540 ps
CPU time 16.35 seconds
Started Aug 01 06:45:49 PM PDT 24
Finished Aug 01 06:46:06 PM PDT 24
Peak memory 224988 kb
Host smart-ac6d347a-6158-45ed-a69d-8fbc3bbddfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405157058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3405157058
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.794736202
Short name T878
Test name
Test status
Simulation time 17963060 ps
CPU time 0.81 seconds
Started Aug 01 06:45:41 PM PDT 24
Finished Aug 01 06:45:42 PM PDT 24
Peak memory 206960 kb
Host smart-731b4d37-77c0-4ccd-9fb1-32850272ccaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794736202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.794736202
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3214405632
Short name T979
Test name
Test status
Simulation time 10210566094 ps
CPU time 26.07 seconds
Started Aug 01 06:45:49 PM PDT 24
Finished Aug 01 06:46:15 PM PDT 24
Peak memory 241364 kb
Host smart-fc15a5cf-765d-4a98-a26a-77d517d2ebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214405632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3214405632
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1201882918
Short name T581
Test name
Test status
Simulation time 13656484988 ps
CPU time 145.03 seconds
Started Aug 01 06:45:48 PM PDT 24
Finished Aug 01 06:48:13 PM PDT 24
Peak memory 249664 kb
Host smart-f468accf-8714-46d5-bffe-aeea8e07db92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201882918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1201882918
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.780746131
Short name T509
Test name
Test status
Simulation time 59874095011 ps
CPU time 99.8 seconds
Started Aug 01 06:45:47 PM PDT 24
Finished Aug 01 06:47:27 PM PDT 24
Peak memory 249712 kb
Host smart-1a7c1761-c145-4ed3-a23c-5e8f1db3b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780746131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.780746131
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4139819392
Short name T382
Test name
Test status
Simulation time 234125637 ps
CPU time 5.18 seconds
Started Aug 01 06:45:46 PM PDT 24
Finished Aug 01 06:45:52 PM PDT 24
Peak memory 233072 kb
Host smart-f88c4288-29a3-43c4-bbc8-970e55068258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139819392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4139819392
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3761846213
Short name T511
Test name
Test status
Simulation time 4014010557 ps
CPU time 30.28 seconds
Started Aug 01 06:45:47 PM PDT 24
Finished Aug 01 06:46:17 PM PDT 24
Peak memory 240964 kb
Host smart-6c22b423-8249-47b9-800b-a24f3ec333c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761846213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3761846213
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2063551151
Short name T47
Test name
Test status
Simulation time 13281683260 ps
CPU time 29.61 seconds
Started Aug 01 06:45:48 PM PDT 24
Finished Aug 01 06:46:18 PM PDT 24
Peak memory 233424 kb
Host smart-c4396553-de43-4eba-b86b-779355a52c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063551151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2063551151
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3610617176
Short name T333
Test name
Test status
Simulation time 40163395113 ps
CPU time 40.09 seconds
Started Aug 01 06:45:45 PM PDT 24
Finished Aug 01 06:46:25 PM PDT 24
Peak memory 235100 kb
Host smart-ef4007cd-b384-4d55-9035-6cb2274ced03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610617176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3610617176
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1962098021
Short name T651
Test name
Test status
Simulation time 12367234293 ps
CPU time 10.49 seconds
Started Aug 01 06:45:46 PM PDT 24
Finished Aug 01 06:45:57 PM PDT 24
Peak memory 233184 kb
Host smart-f533d5fb-7736-4cb8-8043-a2930e204000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962098021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1962098021
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1310046024
Short name T942
Test name
Test status
Simulation time 5740723170 ps
CPU time 15.15 seconds
Started Aug 01 06:45:47 PM PDT 24
Finished Aug 01 06:46:02 PM PDT 24
Peak memory 233072 kb
Host smart-713407fc-fd07-4daf-a855-f705a7786b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310046024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1310046024
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2097746689
Short name T2
Test name
Test status
Simulation time 1584615336 ps
CPU time 12.37 seconds
Started Aug 01 06:45:49 PM PDT 24
Finished Aug 01 06:46:01 PM PDT 24
Peak memory 223520 kb
Host smart-2edee1d2-431c-44d4-9b9b-ffceefbd04a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2097746689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2097746689
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.868200635
Short name T869
Test name
Test status
Simulation time 112615296031 ps
CPU time 462.21 seconds
Started Aug 01 06:45:48 PM PDT 24
Finished Aug 01 06:53:30 PM PDT 24
Peak memory 264944 kb
Host smart-e6ecceb6-3160-4200-9239-f8e825847a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868200635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.868200635
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3676999542
Short name T295
Test name
Test status
Simulation time 210125791 ps
CPU time 2.23 seconds
Started Aug 01 06:45:44 PM PDT 24
Finished Aug 01 06:45:46 PM PDT 24
Peak memory 216688 kb
Host smart-9a86b61d-2571-4625-9683-9be3010c4cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676999542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3676999542
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3716809368
Short name T574
Test name
Test status
Simulation time 24748767988 ps
CPU time 16.63 seconds
Started Aug 01 06:45:48 PM PDT 24
Finished Aug 01 06:46:05 PM PDT 24
Peak memory 216640 kb
Host smart-523c72a4-fd56-422d-85ad-ed8e496461f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716809368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3716809368
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3976942539
Short name T445
Test name
Test status
Simulation time 639963565 ps
CPU time 9.86 seconds
Started Aug 01 06:45:48 PM PDT 24
Finished Aug 01 06:45:59 PM PDT 24
Peak memory 216652 kb
Host smart-302d304e-fdcc-4a4c-9745-56dc4b101fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976942539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3976942539
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2023326315
Short name T49
Test name
Test status
Simulation time 21672883 ps
CPU time 0.74 seconds
Started Aug 01 06:45:49 PM PDT 24
Finished Aug 01 06:45:50 PM PDT 24
Peak memory 206284 kb
Host smart-975cdefc-0029-44ad-820e-35677d70e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023326315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2023326315
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1766767374
Short name T68
Test name
Test status
Simulation time 605335009 ps
CPU time 5.37 seconds
Started Aug 01 06:45:47 PM PDT 24
Finished Aug 01 06:45:53 PM PDT 24
Peak memory 224856 kb
Host smart-f66d222c-4229-48a3-bde6-148d8b33367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766767374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1766767374
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2496313996
Short name T808
Test name
Test status
Simulation time 16124040 ps
CPU time 0.7 seconds
Started Aug 01 06:45:57 PM PDT 24
Finished Aug 01 06:45:58 PM PDT 24
Peak memory 206116 kb
Host smart-c5a343bc-1e3c-4637-a9b5-3f5637e31def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496313996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2496313996
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.869218185
Short name T748
Test name
Test status
Simulation time 76227946 ps
CPU time 2.87 seconds
Started Aug 01 06:45:52 PM PDT 24
Finished Aug 01 06:45:55 PM PDT 24
Peak memory 233056 kb
Host smart-7a295379-5eb1-4657-9769-e5423a72e67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869218185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.869218185
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2015115245
Short name T299
Test name
Test status
Simulation time 13148932 ps
CPU time 0.78 seconds
Started Aug 01 06:45:49 PM PDT 24
Finished Aug 01 06:45:50 PM PDT 24
Peak memory 206964 kb
Host smart-353dc858-4f20-48c3-a87e-bdf6913e22fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015115245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2015115245
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1419760549
Short name T33
Test name
Test status
Simulation time 26200091033 ps
CPU time 90.5 seconds
Started Aug 01 06:45:51 PM PDT 24
Finished Aug 01 06:47:22 PM PDT 24
Peak memory 255944 kb
Host smart-77a129ef-2ba0-4c9b-a15d-1484058d2111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419760549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1419760549
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2395242832
Short name T167
Test name
Test status
Simulation time 47414287738 ps
CPU time 169.03 seconds
Started Aug 01 06:45:45 PM PDT 24
Finished Aug 01 06:48:34 PM PDT 24
Peak memory 249652 kb
Host smart-954ab10f-e784-4961-9e1b-aec59f3023c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395242832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2395242832
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2129178955
Short name T288
Test name
Test status
Simulation time 39412529 ps
CPU time 0.79 seconds
Started Aug 01 06:45:48 PM PDT 24
Finished Aug 01 06:45:49 PM PDT 24
Peak memory 217284 kb
Host smart-e930765a-0a95-4322-9b85-1fe26391ac2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129178955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2129178955
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3242003377
Short name T401
Test name
Test status
Simulation time 75303988400 ps
CPU time 103.7 seconds
Started Aug 01 06:45:52 PM PDT 24
Finished Aug 01 06:47:36 PM PDT 24
Peak memory 255096 kb
Host smart-3b0c31a2-46ae-46cd-870b-c1924d69256d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242003377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3242003377
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1816015125
Short name T702
Test name
Test status
Simulation time 446948922 ps
CPU time 3.23 seconds
Started Aug 01 06:45:47 PM PDT 24
Finished Aug 01 06:45:50 PM PDT 24
Peak memory 228436 kb
Host smart-1d0f4ef3-05d5-4dad-9013-761639e740f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816015125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1816015125
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2264683577
Short name T933
Test name
Test status
Simulation time 355254694 ps
CPU time 3.02 seconds
Started Aug 01 06:45:51 PM PDT 24
Finished Aug 01 06:45:54 PM PDT 24
Peak memory 233100 kb
Host smart-0a62a9ab-c5d0-4201-b101-83689f758ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264683577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2264683577
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3777826996
Short name T859
Test name
Test status
Simulation time 9574332700 ps
CPU time 8.47 seconds
Started Aug 01 06:45:53 PM PDT 24
Finished Aug 01 06:46:02 PM PDT 24
Peak memory 224996 kb
Host smart-b6085f8f-800a-43a1-84ad-667a09bec83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777826996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3777826996
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.98498571
Short name T740
Test name
Test status
Simulation time 30398517585 ps
CPU time 26.29 seconds
Started Aug 01 06:45:49 PM PDT 24
Finished Aug 01 06:46:15 PM PDT 24
Peak memory 249120 kb
Host smart-b4a58a12-56d2-4bc3-98a3-6fa48c6939d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98498571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.98498571
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3507062859
Short name T481
Test name
Test status
Simulation time 1350125680 ps
CPU time 8.51 seconds
Started Aug 01 06:45:48 PM PDT 24
Finished Aug 01 06:45:57 PM PDT 24
Peak memory 221144 kb
Host smart-10b4867b-254b-49ba-a0ed-397d048770f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3507062859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3507062859
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3204953700
Short name T710
Test name
Test status
Simulation time 180156908 ps
CPU time 1.05 seconds
Started Aug 01 06:45:58 PM PDT 24
Finished Aug 01 06:45:59 PM PDT 24
Peak memory 208132 kb
Host smart-702bd68d-58c9-4138-969d-ef7ce394ca61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204953700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3204953700
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3582039278
Short name T637
Test name
Test status
Simulation time 12901192636 ps
CPU time 26.06 seconds
Started Aug 01 06:45:48 PM PDT 24
Finished Aug 01 06:46:15 PM PDT 24
Peak memory 220720 kb
Host smart-ab3d92b6-f5bb-4f9e-95e7-867f373b2a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582039278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3582039278
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3971862587
Short name T337
Test name
Test status
Simulation time 861091469 ps
CPU time 3.84 seconds
Started Aug 01 06:45:51 PM PDT 24
Finished Aug 01 06:45:55 PM PDT 24
Peak memory 216664 kb
Host smart-6aedb8b1-6e1a-4814-82e3-f16872157057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971862587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3971862587
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4069334544
Short name T332
Test name
Test status
Simulation time 142651190 ps
CPU time 2 seconds
Started Aug 01 06:45:48 PM PDT 24
Finished Aug 01 06:45:50 PM PDT 24
Peak memory 216684 kb
Host smart-50f53ca7-9434-466e-b524-9fa8c67c9ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069334544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4069334544
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.280133804
Short name T25
Test name
Test status
Simulation time 37607610 ps
CPU time 0.85 seconds
Started Aug 01 06:45:52 PM PDT 24
Finished Aug 01 06:45:53 PM PDT 24
Peak memory 206288 kb
Host smart-49b05745-e2bc-4208-994a-28c564e6aab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280133804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.280133804
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3279639109
Short name T610
Test name
Test status
Simulation time 554895888 ps
CPU time 5.52 seconds
Started Aug 01 06:45:47 PM PDT 24
Finished Aug 01 06:45:53 PM PDT 24
Peak memory 233092 kb
Host smart-f2cb211f-d007-47a0-9753-7bf80e6900b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279639109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3279639109
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3724937720
Short name T576
Test name
Test status
Simulation time 15753287 ps
CPU time 0.78 seconds
Started Aug 01 06:45:56 PM PDT 24
Finished Aug 01 06:45:57 PM PDT 24
Peak memory 205836 kb
Host smart-33b80584-9cb8-45d5-b72c-76555af9c10f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724937720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3724937720
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.659382337
Short name T294
Test name
Test status
Simulation time 2534668533 ps
CPU time 8.57 seconds
Started Aug 01 06:45:58 PM PDT 24
Finished Aug 01 06:46:06 PM PDT 24
Peak memory 233096 kb
Host smart-040e8248-491a-487e-809b-bd3aa39f3518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659382337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.659382337
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2855516241
Short name T543
Test name
Test status
Simulation time 21471374 ps
CPU time 0.81 seconds
Started Aug 01 06:45:56 PM PDT 24
Finished Aug 01 06:45:57 PM PDT 24
Peak memory 206984 kb
Host smart-5b82a126-5b31-47b2-910c-1761889a4b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855516241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2855516241
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1009566291
Short name T694
Test name
Test status
Simulation time 1255960203 ps
CPU time 9.58 seconds
Started Aug 01 06:45:59 PM PDT 24
Finished Aug 01 06:46:09 PM PDT 24
Peak memory 241308 kb
Host smart-1d117a6a-98fc-4a06-a14c-df0f2ae51887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009566291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1009566291
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.205701116
Short name T204
Test name
Test status
Simulation time 17471622435 ps
CPU time 30.02 seconds
Started Aug 01 06:45:58 PM PDT 24
Finished Aug 01 06:46:29 PM PDT 24
Peak memory 237800 kb
Host smart-29bbe480-b76d-410d-8695-348a21ab10f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205701116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.205701116
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.951736391
Short name T700
Test name
Test status
Simulation time 2444337674 ps
CPU time 43.76 seconds
Started Aug 01 06:46:01 PM PDT 24
Finished Aug 01 06:46:45 PM PDT 24
Peak memory 249684 kb
Host smart-1c7735d2-bc6f-443d-af93-904f55ef16e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951736391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.951736391
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3031120898
Short name T599
Test name
Test status
Simulation time 53688357 ps
CPU time 2.93 seconds
Started Aug 01 06:46:00 PM PDT 24
Finished Aug 01 06:46:03 PM PDT 24
Peak memory 233048 kb
Host smart-a8f1c528-d885-4169-818b-92cb93f7d6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031120898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3031120898
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3952472314
Short name T992
Test name
Test status
Simulation time 2664293615 ps
CPU time 23.86 seconds
Started Aug 01 06:45:59 PM PDT 24
Finished Aug 01 06:46:23 PM PDT 24
Peak memory 249796 kb
Host smart-fcf63a85-2874-4f93-a610-8e3e709ad2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952472314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3952472314
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.230859433
Short name T861
Test name
Test status
Simulation time 22162193472 ps
CPU time 15.39 seconds
Started Aug 01 06:45:59 PM PDT 24
Finished Aug 01 06:46:14 PM PDT 24
Peak memory 224948 kb
Host smart-cb9d2be6-153c-4ec1-82f0-c79e93c8ea63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230859433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.230859433
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1221633795
Short name T801
Test name
Test status
Simulation time 43604704 ps
CPU time 2.33 seconds
Started Aug 01 06:46:00 PM PDT 24
Finished Aug 01 06:46:03 PM PDT 24
Peak memory 232812 kb
Host smart-4157299f-b73f-4690-8972-08de90a72aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221633795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1221633795
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1699502995
Short name T61
Test name
Test status
Simulation time 642298768 ps
CPU time 2.49 seconds
Started Aug 01 06:46:01 PM PDT 24
Finished Aug 01 06:46:03 PM PDT 24
Peak memory 224828 kb
Host smart-593e0499-8872-483b-8737-bcc89d691e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699502995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1699502995
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2991164574
Short name T882
Test name
Test status
Simulation time 34739049043 ps
CPU time 19.69 seconds
Started Aug 01 06:46:07 PM PDT 24
Finished Aug 01 06:46:27 PM PDT 24
Peak memory 224980 kb
Host smart-1d16332a-8e54-4693-afea-12c54a91c1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991164574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2991164574
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3621453800
Short name T734
Test name
Test status
Simulation time 2746318982 ps
CPU time 6.65 seconds
Started Aug 01 06:46:02 PM PDT 24
Finished Aug 01 06:46:08 PM PDT 24
Peak memory 221560 kb
Host smart-721b3219-072d-4fd7-b32b-e777bebfcdfe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3621453800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3621453800
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3733346845
Short name T18
Test name
Test status
Simulation time 7490478719 ps
CPU time 19.09 seconds
Started Aug 01 06:46:07 PM PDT 24
Finished Aug 01 06:46:26 PM PDT 24
Peak memory 249556 kb
Host smart-e3587baf-42e7-4e52-978d-10953d5c5d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733346845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3733346845
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4237141917
Short name T1005
Test name
Test status
Simulation time 4187290384 ps
CPU time 26.19 seconds
Started Aug 01 06:46:00 PM PDT 24
Finished Aug 01 06:46:27 PM PDT 24
Peak memory 216716 kb
Host smart-7c9a6940-8ca5-46c3-9555-050646fc5cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237141917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4237141917
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1529227616
Short name T362
Test name
Test status
Simulation time 15731934039 ps
CPU time 12.64 seconds
Started Aug 01 06:45:57 PM PDT 24
Finished Aug 01 06:46:10 PM PDT 24
Peak memory 216644 kb
Host smart-0527aa57-956d-4c33-8352-ddbc57f21833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529227616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1529227616
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1928766621
Short name T719
Test name
Test status
Simulation time 375236449 ps
CPU time 2.48 seconds
Started Aug 01 06:46:02 PM PDT 24
Finished Aug 01 06:46:04 PM PDT 24
Peak memory 216736 kb
Host smart-5673eb6c-f30e-46eb-acc4-134ecc2883e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928766621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1928766621
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3901057062
Short name T502
Test name
Test status
Simulation time 506765543 ps
CPU time 0.81 seconds
Started Aug 01 06:45:57 PM PDT 24
Finished Aug 01 06:45:58 PM PDT 24
Peak memory 206320 kb
Host smart-913af9ce-8e89-4fb9-912b-f32aa426c268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901057062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3901057062
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.358386212
Short name T468
Test name
Test status
Simulation time 7225586134 ps
CPU time 10.7 seconds
Started Aug 01 06:46:01 PM PDT 24
Finished Aug 01 06:46:11 PM PDT 24
Peak memory 249548 kb
Host smart-df12752f-6ccc-4421-99a9-0ccf1dab6d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358386212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.358386212
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1277032711
Short name T418
Test name
Test status
Simulation time 38300291 ps
CPU time 0.7 seconds
Started Aug 01 06:46:14 PM PDT 24
Finished Aug 01 06:46:15 PM PDT 24
Peak memory 205804 kb
Host smart-7d85908b-33c5-4865-8785-773f5a762f25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277032711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1277032711
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1029983243
Short name T746
Test name
Test status
Simulation time 558173035 ps
CPU time 5.17 seconds
Started Aug 01 06:45:59 PM PDT 24
Finished Aug 01 06:46:04 PM PDT 24
Peak memory 224892 kb
Host smart-640f08d6-f8f0-4e4a-8076-657bfed76f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029983243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1029983243
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.4265648502
Short name T800
Test name
Test status
Simulation time 154388962 ps
CPU time 0.8 seconds
Started Aug 01 06:45:59 PM PDT 24
Finished Aug 01 06:46:00 PM PDT 24
Peak memory 207296 kb
Host smart-9d2522b1-4bd1-4709-8caf-53695caea54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265648502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4265648502
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.916819983
Short name T851
Test name
Test status
Simulation time 13516365960 ps
CPU time 87.52 seconds
Started Aug 01 06:46:19 PM PDT 24
Finished Aug 01 06:47:47 PM PDT 24
Peak memory 266072 kb
Host smart-a873b84c-4cd1-4df2-a915-bb7b8dee472b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916819983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.916819983
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3323419157
Short name T727
Test name
Test status
Simulation time 3419831738 ps
CPU time 39.46 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:46:56 PM PDT 24
Peak memory 249656 kb
Host smart-edd103f2-60d0-409a-90ef-a8804856e130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323419157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3323419157
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3405376731
Short name T62
Test name
Test status
Simulation time 75198813412 ps
CPU time 535.64 seconds
Started Aug 01 06:46:15 PM PDT 24
Finished Aug 01 06:55:11 PM PDT 24
Peak memory 257500 kb
Host smart-5844c35e-1530-46a1-9e49-cd766602d575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405376731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3405376731
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1106388958
Short name T819
Test name
Test status
Simulation time 1906442970 ps
CPU time 27.57 seconds
Started Aug 01 06:46:07 PM PDT 24
Finished Aug 01 06:46:35 PM PDT 24
Peak memory 224912 kb
Host smart-94933788-c021-491f-ba34-cfe08f1d3e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106388958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1106388958
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2152415893
Short name T163
Test name
Test status
Simulation time 17997845294 ps
CPU time 60.35 seconds
Started Aug 01 06:46:07 PM PDT 24
Finished Aug 01 06:47:08 PM PDT 24
Peak memory 251004 kb
Host smart-006f3a12-09a6-4e8d-95ce-e09b8c6babf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152415893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2152415893
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3001890686
Short name T847
Test name
Test status
Simulation time 1976480235 ps
CPU time 7.19 seconds
Started Aug 01 06:46:00 PM PDT 24
Finished Aug 01 06:46:08 PM PDT 24
Peak memory 233032 kb
Host smart-c9d3eb6f-a7ad-4dde-bcba-58f95c9ca5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001890686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3001890686
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1079314571
Short name T432
Test name
Test status
Simulation time 18500260792 ps
CPU time 86.84 seconds
Started Aug 01 06:45:58 PM PDT 24
Finished Aug 01 06:47:25 PM PDT 24
Peak memory 249284 kb
Host smart-1ad7ff4e-59c0-4c2f-8dbf-7ee2f3a70684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079314571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1079314571
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.576828911
Short name T590
Test name
Test status
Simulation time 2311471103 ps
CPU time 5.94 seconds
Started Aug 01 06:46:00 PM PDT 24
Finished Aug 01 06:46:06 PM PDT 24
Peak memory 224936 kb
Host smart-e876d438-b34a-4277-bea7-ac62d24f1efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576828911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.576828911
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2966455788
Short name T67
Test name
Test status
Simulation time 7145502555 ps
CPU time 8.66 seconds
Started Aug 01 06:46:00 PM PDT 24
Finished Aug 01 06:46:09 PM PDT 24
Peak memory 233192 kb
Host smart-197365b1-423f-41b4-b8e7-471a6a54a355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966455788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2966455788
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1480722441
Short name T857
Test name
Test status
Simulation time 195035019 ps
CPU time 5.85 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:46:22 PM PDT 24
Peak memory 219832 kb
Host smart-67574d8e-cc50-4422-9e65-4aacb5284f5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1480722441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1480722441
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2175967222
Short name T689
Test name
Test status
Simulation time 143368959578 ps
CPU time 334.61 seconds
Started Aug 01 06:46:17 PM PDT 24
Finished Aug 01 06:51:52 PM PDT 24
Peak memory 259748 kb
Host smart-393a0967-4bdc-44c3-8d51-a3f26749a49e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175967222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2175967222
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3157974589
Short name T750
Test name
Test status
Simulation time 2144012980 ps
CPU time 26.04 seconds
Started Aug 01 06:45:58 PM PDT 24
Finished Aug 01 06:46:25 PM PDT 24
Peak memory 218068 kb
Host smart-cc99c001-8efb-468d-92ad-1d7436b751b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157974589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3157974589
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1023367296
Short name T711
Test name
Test status
Simulation time 273193310 ps
CPU time 1.74 seconds
Started Aug 01 06:45:59 PM PDT 24
Finished Aug 01 06:46:01 PM PDT 24
Peak memory 208216 kb
Host smart-46106652-0888-418a-8ac1-7b82c719a1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023367296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1023367296
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.188124532
Short name T782
Test name
Test status
Simulation time 95566165 ps
CPU time 0.98 seconds
Started Aug 01 06:46:01 PM PDT 24
Finished Aug 01 06:46:02 PM PDT 24
Peak memory 207984 kb
Host smart-2629dc2d-be88-442e-b697-9f66be608319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188124532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.188124532
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1439502844
Short name T584
Test name
Test status
Simulation time 89217023 ps
CPU time 0.97 seconds
Started Aug 01 06:45:58 PM PDT 24
Finished Aug 01 06:45:59 PM PDT 24
Peak memory 206800 kb
Host smart-491f9335-507e-43db-98d9-882746ddc486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439502844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1439502844
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3490581009
Short name T873
Test name
Test status
Simulation time 38609542 ps
CPU time 2.07 seconds
Started Aug 01 06:46:01 PM PDT 24
Finished Aug 01 06:46:03 PM PDT 24
Peak memory 224668 kb
Host smart-cd0ce0c0-1204-4a2d-969f-3cf07b886fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490581009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3490581009
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2585838584
Short name T52
Test name
Test status
Simulation time 15421038 ps
CPU time 0.78 seconds
Started Aug 01 06:46:19 PM PDT 24
Finished Aug 01 06:46:20 PM PDT 24
Peak memory 206116 kb
Host smart-e0d62bf3-d062-4c51-b4ed-28cd044bb48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585838584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2585838584
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.924497976
Short name T12
Test name
Test status
Simulation time 320326910 ps
CPU time 2.46 seconds
Started Aug 01 06:46:15 PM PDT 24
Finished Aug 01 06:46:17 PM PDT 24
Peak memory 225060 kb
Host smart-5a4b2fff-97b4-46b0-915e-01ea0769a087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924497976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.924497976
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.392179306
Short name T890
Test name
Test status
Simulation time 81329395 ps
CPU time 0.87 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:46:17 PM PDT 24
Peak memory 206976 kb
Host smart-083804eb-e152-40b9-9d71-8cdc6326570d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392179306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.392179306
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2674946629
Short name T69
Test name
Test status
Simulation time 42857680770 ps
CPU time 115.85 seconds
Started Aug 01 06:46:14 PM PDT 24
Finished Aug 01 06:48:10 PM PDT 24
Peak memory 249616 kb
Host smart-c07b1882-3d91-4a1f-abbd-682372765058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674946629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2674946629
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2492901661
Short name T731
Test name
Test status
Simulation time 3882465637 ps
CPU time 103.6 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:48:00 PM PDT 24
Peak memory 265900 kb
Host smart-f4c77118-0547-4943-b451-5ec897201a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492901661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2492901661
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1658988312
Short name T463
Test name
Test status
Simulation time 17682750008 ps
CPU time 63.35 seconds
Started Aug 01 06:46:15 PM PDT 24
Finished Aug 01 06:47:18 PM PDT 24
Peak memory 241376 kb
Host smart-ad275fbe-2e66-4342-9b1e-0f01206e2261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658988312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1658988312
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3609967357
Short name T406
Test name
Test status
Simulation time 35093533 ps
CPU time 0.78 seconds
Started Aug 01 06:46:14 PM PDT 24
Finished Aug 01 06:46:15 PM PDT 24
Peak memory 216200 kb
Host smart-e4a572b8-4c86-4d43-bea4-53802cac3d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609967357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3609967357
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4276633318
Short name T434
Test name
Test status
Simulation time 288808230 ps
CPU time 2.17 seconds
Started Aug 01 06:46:15 PM PDT 24
Finished Aug 01 06:46:17 PM PDT 24
Peak memory 223464 kb
Host smart-39d75eb8-7bab-4a94-96c9-de4271fd2a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276633318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4276633318
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1557684032
Short name T779
Test name
Test status
Simulation time 324901157 ps
CPU time 8.39 seconds
Started Aug 01 06:46:20 PM PDT 24
Finished Aug 01 06:46:28 PM PDT 24
Peak memory 224896 kb
Host smart-0d528785-73ba-4940-82f8-ee467e6cbdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557684032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1557684032
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.513546596
Short name T202
Test name
Test status
Simulation time 3276635151 ps
CPU time 12.66 seconds
Started Aug 01 06:46:13 PM PDT 24
Finished Aug 01 06:46:26 PM PDT 24
Peak memory 233132 kb
Host smart-cefcdc76-7a10-4651-8df1-281660628efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513546596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.513546596
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.682505579
Short name T235
Test name
Test status
Simulation time 1954048387 ps
CPU time 9.71 seconds
Started Aug 01 06:46:15 PM PDT 24
Finished Aug 01 06:46:25 PM PDT 24
Peak memory 240412 kb
Host smart-fa556808-961e-493e-8cdb-4be8d5e60465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682505579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.682505579
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1351071640
Short name T935
Test name
Test status
Simulation time 370451651 ps
CPU time 5.11 seconds
Started Aug 01 06:46:17 PM PDT 24
Finished Aug 01 06:46:23 PM PDT 24
Peak memory 219264 kb
Host smart-4411ed7f-0a2b-4eb1-a978-0b94282e84f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1351071640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1351071640
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3268375362
Short name T655
Test name
Test status
Simulation time 7655677928 ps
CPU time 23.47 seconds
Started Aug 01 06:46:15 PM PDT 24
Finished Aug 01 06:46:38 PM PDT 24
Peak memory 216668 kb
Host smart-3ef998a6-ae46-43dc-8dd4-b18b41998b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268375362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3268375362
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1403250958
Short name T930
Test name
Test status
Simulation time 6963206190 ps
CPU time 5.37 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:46:21 PM PDT 24
Peak memory 216680 kb
Host smart-d5aeaf74-e3cc-40ba-a072-a9b8add17c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403250958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1403250958
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4124359188
Short name T984
Test name
Test status
Simulation time 152713504 ps
CPU time 6.26 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:46:22 PM PDT 24
Peak memory 216628 kb
Host smart-b5435d62-d806-4026-89be-f1e3676f0ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124359188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4124359188
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.266932137
Short name T5
Test name
Test status
Simulation time 94181870 ps
CPU time 1.03 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:46:17 PM PDT 24
Peak memory 206324 kb
Host smart-833dcdac-9157-4353-af67-bb46991094de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266932137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.266932137
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2708698489
Short name T790
Test name
Test status
Simulation time 29208376038 ps
CPU time 16.11 seconds
Started Aug 01 06:46:12 PM PDT 24
Finished Aug 01 06:46:28 PM PDT 24
Peak memory 233140 kb
Host smart-0c703f75-f721-40ae-9a44-7b06877415d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708698489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2708698489
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3755699656
Short name T549
Test name
Test status
Simulation time 11686744 ps
CPU time 0.75 seconds
Started Aug 01 06:46:15 PM PDT 24
Finished Aug 01 06:46:16 PM PDT 24
Peak memory 205796 kb
Host smart-86b59c8b-897f-423f-964b-df834fc113f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755699656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3755699656
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.79070154
Short name T378
Test name
Test status
Simulation time 2363748313 ps
CPU time 7.38 seconds
Started Aug 01 06:46:18 PM PDT 24
Finished Aug 01 06:46:25 PM PDT 24
Peak memory 224892 kb
Host smart-f0babf8c-94c0-41b2-a5ff-453b096c569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79070154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.79070154
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1810929975
Short name T624
Test name
Test status
Simulation time 21480897 ps
CPU time 0.79 seconds
Started Aug 01 06:46:13 PM PDT 24
Finished Aug 01 06:46:14 PM PDT 24
Peak memory 207012 kb
Host smart-5ac6daf8-bb55-4932-b7b7-0b446f453492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810929975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1810929975
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3588971377
Short name T664
Test name
Test status
Simulation time 72700885521 ps
CPU time 134.73 seconds
Started Aug 01 06:46:14 PM PDT 24
Finished Aug 01 06:48:29 PM PDT 24
Peak memory 249540 kb
Host smart-a12fe3a2-5c71-46bc-95c3-daef85bd6bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588971377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3588971377
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1720301519
Short name T970
Test name
Test status
Simulation time 10615649331 ps
CPU time 43.64 seconds
Started Aug 01 06:46:17 PM PDT 24
Finished Aug 01 06:47:01 PM PDT 24
Peak memory 241500 kb
Host smart-2a317e41-7972-4285-8581-5770c37f139f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720301519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1720301519
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2224470196
Short name T640
Test name
Test status
Simulation time 6747239564 ps
CPU time 105.19 seconds
Started Aug 01 06:46:17 PM PDT 24
Finished Aug 01 06:48:02 PM PDT 24
Peak memory 257872 kb
Host smart-4a865fdd-1d8b-44ba-a0bf-db12cb18ef5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224470196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2224470196
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1880826482
Short name T306
Test name
Test status
Simulation time 2703121175 ps
CPU time 13.56 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:46:30 PM PDT 24
Peak memory 234212 kb
Host smart-45fb7ff9-8cfe-4002-9992-1b1675d1d26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880826482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1880826482
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2272643041
Short name T611
Test name
Test status
Simulation time 49394388353 ps
CPU time 51.48 seconds
Started Aug 01 06:46:17 PM PDT 24
Finished Aug 01 06:47:08 PM PDT 24
Peak memory 241572 kb
Host smart-e288351f-c696-4546-8f94-adea9a6835e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272643041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2272643041
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3404156906
Short name T964
Test name
Test status
Simulation time 2123067853 ps
CPU time 11.1 seconds
Started Aug 01 06:46:14 PM PDT 24
Finished Aug 01 06:46:25 PM PDT 24
Peak memory 233116 kb
Host smart-5af5a590-894f-400c-8786-a92ceb3f0625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404156906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3404156906
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.352824139
Short name T10
Test name
Test status
Simulation time 62336227978 ps
CPU time 32.69 seconds
Started Aug 01 06:46:17 PM PDT 24
Finished Aug 01 06:46:49 PM PDT 24
Peak memory 233100 kb
Host smart-c947def3-19a4-42ff-ab64-d63f50dd4c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352824139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.352824139
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.615823582
Short name T665
Test name
Test status
Simulation time 561538994 ps
CPU time 4.25 seconds
Started Aug 01 06:46:12 PM PDT 24
Finished Aug 01 06:46:17 PM PDT 24
Peak memory 224816 kb
Host smart-c43c1498-975a-4fc3-8964-dd50e5365561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615823582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.615823582
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1503095082
Short name T606
Test name
Test status
Simulation time 21176270329 ps
CPU time 19.3 seconds
Started Aug 01 06:46:13 PM PDT 24
Finished Aug 01 06:46:32 PM PDT 24
Peak memory 225016 kb
Host smart-6725f45e-a7ba-4ca7-ba1f-76cbc19ee256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503095082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1503095082
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1699029538
Short name T896
Test name
Test status
Simulation time 182358030 ps
CPU time 4.52 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:46:21 PM PDT 24
Peak memory 220516 kb
Host smart-889e9ef3-b120-4bd5-9f0e-df12b59b5bdf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1699029538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1699029538
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.956050026
Short name T981
Test name
Test status
Simulation time 174205172488 ps
CPU time 415.52 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:53:11 PM PDT 24
Peak memory 266060 kb
Host smart-cf1e93c2-8e7f-47f4-a89b-cdfdb63c9a27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956050026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.956050026
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.363861575
Short name T383
Test name
Test status
Simulation time 983251794 ps
CPU time 13.16 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:46:30 PM PDT 24
Peak memory 216868 kb
Host smart-04dba3d2-c986-4360-9fd3-2909be7c971a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363861575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.363861575
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1178243315
Short name T630
Test name
Test status
Simulation time 890144056 ps
CPU time 3.8 seconds
Started Aug 01 06:46:19 PM PDT 24
Finished Aug 01 06:46:23 PM PDT 24
Peak memory 216648 kb
Host smart-7b4a48ff-bb8f-4f3c-92d1-d2261d62ae47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178243315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1178243315
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4233937270
Short name T684
Test name
Test status
Simulation time 11618674 ps
CPU time 0.74 seconds
Started Aug 01 06:46:19 PM PDT 24
Finished Aug 01 06:46:20 PM PDT 24
Peak memory 206012 kb
Host smart-276550d5-cc36-45ec-9334-d02a5d8c11cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233937270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4233937270
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1635267498
Short name T426
Test name
Test status
Simulation time 32540705 ps
CPU time 0.75 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:46:17 PM PDT 24
Peak memory 206340 kb
Host smart-5ddce824-7008-4a28-84bf-92ddcc14344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635267498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1635267498
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.626289146
Short name T638
Test name
Test status
Simulation time 414926049 ps
CPU time 3.51 seconds
Started Aug 01 06:46:14 PM PDT 24
Finished Aug 01 06:46:17 PM PDT 24
Peak memory 233076 kb
Host smart-14f45344-b4da-489a-8f9e-e5ca9d2f8f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626289146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.626289146
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3274723939
Short name T376
Test name
Test status
Simulation time 13916301 ps
CPU time 0.77 seconds
Started Aug 01 06:46:17 PM PDT 24
Finished Aug 01 06:46:18 PM PDT 24
Peak memory 205240 kb
Host smart-174e999c-aebb-4ab6-a05d-adb322b30047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274723939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3274723939
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4202656761
Short name T563
Test name
Test status
Simulation time 31766415 ps
CPU time 2.13 seconds
Started Aug 01 06:46:23 PM PDT 24
Finished Aug 01 06:46:25 PM PDT 24
Peak memory 224908 kb
Host smart-a7c41e25-0abc-486f-b2fb-7f2831ffdd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202656761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4202656761
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4064392335
Short name T969
Test name
Test status
Simulation time 19638208 ps
CPU time 0.8 seconds
Started Aug 01 06:46:16 PM PDT 24
Finished Aug 01 06:46:17 PM PDT 24
Peak memory 206956 kb
Host smart-05f215a1-5092-4346-897f-629a3d8a05ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064392335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4064392335
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2402898781
Short name T572
Test name
Test status
Simulation time 20871868765 ps
CPU time 177.96 seconds
Started Aug 01 06:46:21 PM PDT 24
Finished Aug 01 06:49:19 PM PDT 24
Peak memory 249640 kb
Host smart-2cb61dbb-9034-4bd2-8d57-3aeba374f12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402898781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2402898781
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.52440777
Short name T941
Test name
Test status
Simulation time 1441271680 ps
CPU time 11.32 seconds
Started Aug 01 06:46:23 PM PDT 24
Finished Aug 01 06:46:35 PM PDT 24
Peak memory 233116 kb
Host smart-5dcde1a0-7589-4836-ae68-8b1ab3a2dcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52440777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.52440777
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.4056899560
Short name T997
Test name
Test status
Simulation time 6897958120 ps
CPU time 16.19 seconds
Started Aug 01 06:46:27 PM PDT 24
Finished Aug 01 06:46:43 PM PDT 24
Peak memory 241328 kb
Host smart-43f7e1bf-3f04-46cb-962a-09688d0c8f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056899560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.4056899560
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1258561256
Short name T657
Test name
Test status
Simulation time 1146344497 ps
CPU time 4.38 seconds
Started Aug 01 06:46:22 PM PDT 24
Finished Aug 01 06:46:27 PM PDT 24
Peak memory 233104 kb
Host smart-86f34251-0f63-4010-a659-2ea45daf98ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258561256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1258561256
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3210085376
Short name T701
Test name
Test status
Simulation time 1514626223 ps
CPU time 20.23 seconds
Started Aug 01 06:46:18 PM PDT 24
Finished Aug 01 06:46:39 PM PDT 24
Peak memory 239712 kb
Host smart-bc9f3f78-d20b-456c-9689-472721af3e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210085376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3210085376
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.613108632
Short name T862
Test name
Test status
Simulation time 6736456298 ps
CPU time 14.81 seconds
Started Aug 01 06:46:19 PM PDT 24
Finished Aug 01 06:46:34 PM PDT 24
Peak memory 233124 kb
Host smart-5e752969-9dec-4296-ab88-588890b14899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613108632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.613108632
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3804946917
Short name T447
Test name
Test status
Simulation time 356360390 ps
CPU time 2.28 seconds
Started Aug 01 06:46:20 PM PDT 24
Finished Aug 01 06:46:23 PM PDT 24
Peak memory 224488 kb
Host smart-322afeb4-ddf4-44f0-a7dd-5e579040ae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804946917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3804946917
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.783283507
Short name T756
Test name
Test status
Simulation time 842701297 ps
CPU time 7.68 seconds
Started Aug 01 06:46:18 PM PDT 24
Finished Aug 01 06:46:26 PM PDT 24
Peak memory 223520 kb
Host smart-ed1db45f-6934-477d-a8b9-1068254f9cb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=783283507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.783283507
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1904083620
Short name T761
Test name
Test status
Simulation time 47491351412 ps
CPU time 464.89 seconds
Started Aug 01 06:46:25 PM PDT 24
Finished Aug 01 06:54:10 PM PDT 24
Peak memory 289836 kb
Host smart-6c81eb2c-b916-4e16-b21c-e6ac6f579855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904083620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1904083620
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1831476070
Short name T582
Test name
Test status
Simulation time 8547818145 ps
CPU time 23.85 seconds
Started Aug 01 06:46:25 PM PDT 24
Finished Aug 01 06:46:49 PM PDT 24
Peak memory 216736 kb
Host smart-7db234ac-cabe-4322-81be-f905a9446d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831476070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1831476070
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2064790765
Short name T583
Test name
Test status
Simulation time 3205645452 ps
CPU time 7.89 seconds
Started Aug 01 06:46:23 PM PDT 24
Finished Aug 01 06:46:31 PM PDT 24
Peak memory 216624 kb
Host smart-1c27d32a-e1cf-44b1-9452-7d5917ffbc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064790765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2064790765
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3638211422
Short name T747
Test name
Test status
Simulation time 393612972 ps
CPU time 1.59 seconds
Started Aug 01 06:46:22 PM PDT 24
Finished Aug 01 06:46:24 PM PDT 24
Peak memory 216592 kb
Host smart-f4e72db5-b5a4-4930-9e09-8e3c446f438b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638211422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3638211422
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.756026433
Short name T772
Test name
Test status
Simulation time 37618322 ps
CPU time 0.8 seconds
Started Aug 01 06:46:25 PM PDT 24
Finished Aug 01 06:46:26 PM PDT 24
Peak memory 206312 kb
Host smart-02c578fb-3da6-44ff-a506-db97b969baa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756026433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.756026433
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3902324143
Short name T965
Test name
Test status
Simulation time 2623258982 ps
CPU time 5.07 seconds
Started Aug 01 06:46:18 PM PDT 24
Finished Aug 01 06:46:23 PM PDT 24
Peak memory 234240 kb
Host smart-e638cea6-41cc-4387-8c50-9427daf7dc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902324143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3902324143
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2321440893
Short name T305
Test name
Test status
Simulation time 44506492 ps
CPU time 0.78 seconds
Started Aug 01 06:45:02 PM PDT 24
Finished Aug 01 06:45:03 PM PDT 24
Peak memory 205876 kb
Host smart-856baf11-0c75-4a68-803c-6c73f3a939aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321440893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
321440893
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1453626569
Short name T79
Test name
Test status
Simulation time 1207906510 ps
CPU time 6.99 seconds
Started Aug 01 06:45:03 PM PDT 24
Finished Aug 01 06:45:11 PM PDT 24
Peak memory 224916 kb
Host smart-a613863a-ea79-4bf1-b9fd-40a028d5d215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453626569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1453626569
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1773593261
Short name T591
Test name
Test status
Simulation time 15093024 ps
CPU time 0.8 seconds
Started Aug 01 06:45:02 PM PDT 24
Finished Aug 01 06:45:03 PM PDT 24
Peak memory 206156 kb
Host smart-cd487d34-2c2b-4a4a-82cb-c99a77cef080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773593261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1773593261
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1820863492
Short name T945
Test name
Test status
Simulation time 65680308599 ps
CPU time 129.71 seconds
Started Aug 01 06:45:01 PM PDT 24
Finished Aug 01 06:47:10 PM PDT 24
Peak memory 265924 kb
Host smart-6fb21035-227e-4e03-8514-daf393f910d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820863492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1820863492
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2315105876
Short name T902
Test name
Test status
Simulation time 40167402436 ps
CPU time 125.66 seconds
Started Aug 01 06:45:05 PM PDT 24
Finished Aug 01 06:47:10 PM PDT 24
Peak memory 251680 kb
Host smart-f0d7dfb4-8388-4459-aef7-a362a6c61158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315105876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2315105876
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.389221607
Short name T178
Test name
Test status
Simulation time 67793094473 ps
CPU time 354.04 seconds
Started Aug 01 06:45:02 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 263888 kb
Host smart-372285ad-62ee-4d06-9faf-cffe3c2eba57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389221607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
389221607
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3476735552
Short name T391
Test name
Test status
Simulation time 8993200323 ps
CPU time 9.12 seconds
Started Aug 01 06:45:03 PM PDT 24
Finished Aug 01 06:45:13 PM PDT 24
Peak memory 224924 kb
Host smart-d8564225-aa48-43ef-8862-f6e37f9b80d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476735552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3476735552
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3220451953
Short name T671
Test name
Test status
Simulation time 9230037817 ps
CPU time 92.2 seconds
Started Aug 01 06:45:04 PM PDT 24
Finished Aug 01 06:46:36 PM PDT 24
Peak memory 233164 kb
Host smart-2a4136be-635e-41a8-b230-f9f33e2b5071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220451953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3220451953
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1038408747
Short name T690
Test name
Test status
Simulation time 296426418 ps
CPU time 4.25 seconds
Started Aug 01 06:45:02 PM PDT 24
Finished Aug 01 06:45:06 PM PDT 24
Peak memory 224896 kb
Host smart-fa0aaad4-7640-4ec3-a962-93a5bf890d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038408747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1038408747
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2919467382
Short name T309
Test name
Test status
Simulation time 198861541 ps
CPU time 2.49 seconds
Started Aug 01 06:45:02 PM PDT 24
Finished Aug 01 06:45:05 PM PDT 24
Peak memory 233148 kb
Host smart-50e603eb-87d5-41d8-b180-41aa0f742bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919467382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2919467382
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4069195436
Short name T724
Test name
Test status
Simulation time 1398029058 ps
CPU time 14.04 seconds
Started Aug 01 06:45:04 PM PDT 24
Finished Aug 01 06:45:18 PM PDT 24
Peak memory 219692 kb
Host smart-da9d3da7-3aeb-4982-b6bf-57d95ff8d614
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4069195436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4069195436
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1324910349
Short name T17
Test name
Test status
Simulation time 460453156 ps
CPU time 1.26 seconds
Started Aug 01 06:45:02 PM PDT 24
Finished Aug 01 06:45:04 PM PDT 24
Peak memory 236836 kb
Host smart-ab88db9a-fb71-4dd6-94f5-93c95c4fabff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324910349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1324910349
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2971460266
Short name T841
Test name
Test status
Simulation time 13553115698 ps
CPU time 27.92 seconds
Started Aug 01 06:45:00 PM PDT 24
Finished Aug 01 06:45:28 PM PDT 24
Peak memory 216640 kb
Host smart-c5603f34-3c8f-4e62-99be-235ef64eeded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971460266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2971460266
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1989446589
Short name T703
Test name
Test status
Simulation time 856588074 ps
CPU time 3.64 seconds
Started Aug 01 06:45:00 PM PDT 24
Finished Aug 01 06:45:04 PM PDT 24
Peak memory 216620 kb
Host smart-e4065036-9734-4769-b7b5-7e6e1bc96136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989446589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1989446589
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4012234876
Short name T529
Test name
Test status
Simulation time 20736379 ps
CPU time 0.87 seconds
Started Aug 01 06:45:01 PM PDT 24
Finished Aug 01 06:45:02 PM PDT 24
Peak memory 207048 kb
Host smart-16d034c5-18d6-4d1a-b12c-a0dafddbc403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012234876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4012234876
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3591866823
Short name T328
Test name
Test status
Simulation time 105267459 ps
CPU time 0.95 seconds
Started Aug 01 06:44:58 PM PDT 24
Finished Aug 01 06:44:59 PM PDT 24
Peak memory 206332 kb
Host smart-d8672153-5888-4eb0-ace9-30edc32de7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591866823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3591866823
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3719753444
Short name T994
Test name
Test status
Simulation time 2475744715 ps
CPU time 4.59 seconds
Started Aug 01 06:45:01 PM PDT 24
Finished Aug 01 06:45:06 PM PDT 24
Peak memory 224972 kb
Host smart-dd175a0e-3a43-481d-a400-24b260a612c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719753444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3719753444
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3658564518
Short name T541
Test name
Test status
Simulation time 19880540 ps
CPU time 0.73 seconds
Started Aug 01 06:46:27 PM PDT 24
Finished Aug 01 06:46:28 PM PDT 24
Peak memory 205732 kb
Host smart-8dd1de9c-58aa-4fe5-9249-b016a99c8501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658564518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3658564518
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.945253443
Short name T866
Test name
Test status
Simulation time 264706252 ps
CPU time 2.38 seconds
Started Aug 01 06:46:20 PM PDT 24
Finished Aug 01 06:46:23 PM PDT 24
Peak memory 224020 kb
Host smart-9f30dcfe-6e91-42f4-949a-0877e7cdcb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945253443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.945253443
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1070897405
Short name T852
Test name
Test status
Simulation time 55767241 ps
CPU time 0.75 seconds
Started Aug 01 06:46:22 PM PDT 24
Finished Aug 01 06:46:23 PM PDT 24
Peak memory 205912 kb
Host smart-9fd0263b-fb7b-49df-b42a-34034f498df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070897405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1070897405
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2328104650
Short name T205
Test name
Test status
Simulation time 1834560451 ps
CPU time 39.62 seconds
Started Aug 01 06:46:18 PM PDT 24
Finished Aug 01 06:46:58 PM PDT 24
Peak memory 257652 kb
Host smart-5a4fa8af-d76b-47bc-810e-d5d5e5df6531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328104650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2328104650
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1894730792
Short name T248
Test name
Test status
Simulation time 6299952936 ps
CPU time 153.26 seconds
Started Aug 01 06:46:19 PM PDT 24
Finished Aug 01 06:48:52 PM PDT 24
Peak memory 268128 kb
Host smart-9258ff4f-1fd5-40dc-b8eb-faa9cff962c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894730792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1894730792
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1360047239
Short name T775
Test name
Test status
Simulation time 8361047452 ps
CPU time 82.62 seconds
Started Aug 01 06:46:17 PM PDT 24
Finished Aug 01 06:47:40 PM PDT 24
Peak memory 257500 kb
Host smart-444d4720-cb87-4b1f-8ab7-5dfc08934eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360047239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1360047239
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2725635591
Short name T946
Test name
Test status
Simulation time 3377960918 ps
CPU time 13.85 seconds
Started Aug 01 06:46:24 PM PDT 24
Finished Aug 01 06:46:38 PM PDT 24
Peak memory 233136 kb
Host smart-4ca45157-2f6d-4fe7-a945-2411fefc4374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725635591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2725635591
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.998714891
Short name T508
Test name
Test status
Simulation time 6694037833 ps
CPU time 33.37 seconds
Started Aug 01 06:46:26 PM PDT 24
Finished Aug 01 06:47:00 PM PDT 24
Peak memory 249500 kb
Host smart-1e79a412-8322-42ef-b96d-a6c90a7194f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998714891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.998714891
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3743469439
Short name T754
Test name
Test status
Simulation time 79343450 ps
CPU time 3.2 seconds
Started Aug 01 06:46:25 PM PDT 24
Finished Aug 01 06:46:28 PM PDT 24
Peak memory 233116 kb
Host smart-228393c1-8a25-45f5-a431-8ee127a80075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743469439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3743469439
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3902799750
Short name T909
Test name
Test status
Simulation time 4596266627 ps
CPU time 13.02 seconds
Started Aug 01 06:46:25 PM PDT 24
Finished Aug 01 06:46:39 PM PDT 24
Peak memory 224904 kb
Host smart-ad0e7129-64c2-4d64-8f72-63d47714155a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902799750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3902799750
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3417551560
Short name T495
Test name
Test status
Simulation time 1620053224 ps
CPU time 9.19 seconds
Started Aug 01 06:46:27 PM PDT 24
Finished Aug 01 06:46:36 PM PDT 24
Peak memory 240984 kb
Host smart-1107cc97-c238-45ee-8621-73862a3805bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417551560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3417551560
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2744469737
Short name T825
Test name
Test status
Simulation time 2554020833 ps
CPU time 18.83 seconds
Started Aug 01 06:46:26 PM PDT 24
Finished Aug 01 06:46:45 PM PDT 24
Peak memory 249384 kb
Host smart-c243895b-4c84-485b-8e9d-6905042abc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744469737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2744469737
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.719140609
Short name T587
Test name
Test status
Simulation time 236836423 ps
CPU time 3.87 seconds
Started Aug 01 06:46:24 PM PDT 24
Finished Aug 01 06:46:28 PM PDT 24
Peak memory 223508 kb
Host smart-11e8d869-a647-4f5d-b21b-33f595945c29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=719140609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.719140609
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.893059242
Short name T1012
Test name
Test status
Simulation time 63458514 ps
CPU time 1.13 seconds
Started Aug 01 06:46:20 PM PDT 24
Finished Aug 01 06:46:21 PM PDT 24
Peak memory 208160 kb
Host smart-e20cf5cd-c92e-49b3-b2f9-a6b7ec4cec42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893059242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.893059242
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.621697270
Short name T414
Test name
Test status
Simulation time 21579966432 ps
CPU time 39.68 seconds
Started Aug 01 06:46:26 PM PDT 24
Finished Aug 01 06:47:06 PM PDT 24
Peak memory 216928 kb
Host smart-3b711c69-5ae9-4d52-bb59-6a17df3adb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621697270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.621697270
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4037897405
Short name T534
Test name
Test status
Simulation time 1619099280 ps
CPU time 5.99 seconds
Started Aug 01 06:46:20 PM PDT 24
Finished Aug 01 06:46:26 PM PDT 24
Peak memory 216696 kb
Host smart-dd977de2-de9c-4236-b98b-4fb1240c464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037897405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4037897405
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.700228505
Short name T417
Test name
Test status
Simulation time 71394847 ps
CPU time 0.93 seconds
Started Aug 01 06:46:25 PM PDT 24
Finished Aug 01 06:46:26 PM PDT 24
Peak memory 207536 kb
Host smart-ce06dc25-cd22-42b0-8116-4c2b1106002b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700228505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.700228505
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3061295811
Short name T897
Test name
Test status
Simulation time 187084272 ps
CPU time 0.79 seconds
Started Aug 01 06:46:25 PM PDT 24
Finished Aug 01 06:46:26 PM PDT 24
Peak memory 206344 kb
Host smart-906be53c-5ac2-48f8-9574-228bc7283918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061295811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3061295811
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1409619149
Short name T617
Test name
Test status
Simulation time 1041799961 ps
CPU time 4.22 seconds
Started Aug 01 06:46:21 PM PDT 24
Finished Aug 01 06:46:25 PM PDT 24
Peak memory 233104 kb
Host smart-40d56920-4a3f-4ff2-9b72-196c596637f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409619149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1409619149
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.52977331
Short name T325
Test name
Test status
Simulation time 13926050 ps
CPU time 0.69 seconds
Started Aug 01 06:46:29 PM PDT 24
Finished Aug 01 06:46:30 PM PDT 24
Peak memory 206148 kb
Host smart-8b509334-97c5-4e5d-9ab3-79d20a237d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52977331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.52977331
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1876875496
Short name T1006
Test name
Test status
Simulation time 169875917 ps
CPU time 2.98 seconds
Started Aug 01 06:46:26 PM PDT 24
Finished Aug 01 06:46:29 PM PDT 24
Peak memory 233188 kb
Host smart-4d25d25f-a01d-467c-b737-113a52e6e970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876875496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1876875496
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3678533687
Short name T805
Test name
Test status
Simulation time 19966314 ps
CPU time 0.82 seconds
Started Aug 01 06:46:25 PM PDT 24
Finished Aug 01 06:46:26 PM PDT 24
Peak memory 207036 kb
Host smart-bf7c48d5-23af-4785-a8b2-5bc2a5a72f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678533687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3678533687
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.4030098767
Short name T810
Test name
Test status
Simulation time 39818247082 ps
CPU time 138.12 seconds
Started Aug 01 06:46:34 PM PDT 24
Finished Aug 01 06:48:52 PM PDT 24
Peak memory 264296 kb
Host smart-7ba20783-f256-4c0e-95f7-fa0bcc47f55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030098767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4030098767
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3537826095
Short name T487
Test name
Test status
Simulation time 5623444732 ps
CPU time 68.34 seconds
Started Aug 01 06:46:34 PM PDT 24
Finished Aug 01 06:47:43 PM PDT 24
Peak memory 269608 kb
Host smart-d3c3c6d8-5fa7-4efd-b7cc-0b5670e29d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537826095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3537826095
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3867315085
Short name T265
Test name
Test status
Simulation time 4477765931 ps
CPU time 48.22 seconds
Started Aug 01 06:46:33 PM PDT 24
Finished Aug 01 06:47:21 PM PDT 24
Peak memory 252716 kb
Host smart-7d39b829-72eb-4fe0-be7c-2b5d7ddf6b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867315085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3867315085
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2953617233
Short name T858
Test name
Test status
Simulation time 3377946276 ps
CPU time 18.15 seconds
Started Aug 01 06:46:21 PM PDT 24
Finished Aug 01 06:46:39 PM PDT 24
Peak memory 224772 kb
Host smart-9a86dc30-7fbc-4e87-9770-613fa4eece10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953617233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2953617233
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1485439462
Short name T682
Test name
Test status
Simulation time 10543413 ps
CPU time 0.72 seconds
Started Aug 01 06:46:17 PM PDT 24
Finished Aug 01 06:46:18 PM PDT 24
Peak memory 207876 kb
Host smart-add05905-7fd1-46fa-8469-396baaffd2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485439462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1485439462
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3024471107
Short name T598
Test name
Test status
Simulation time 869088238 ps
CPU time 8.38 seconds
Started Aug 01 06:46:20 PM PDT 24
Finished Aug 01 06:46:29 PM PDT 24
Peak memory 224904 kb
Host smart-0de05f76-53b3-4bcb-b58f-d19aeade749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024471107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3024471107
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3051116859
Short name T696
Test name
Test status
Simulation time 44358816638 ps
CPU time 79.77 seconds
Started Aug 01 06:46:20 PM PDT 24
Finished Aug 01 06:47:40 PM PDT 24
Peak memory 240428 kb
Host smart-b8f71cba-a284-44e9-81db-cf4e5b2f8510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051116859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3051116859
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1354782044
Short name T510
Test name
Test status
Simulation time 2051980178 ps
CPU time 9.41 seconds
Started Aug 01 06:46:28 PM PDT 24
Finished Aug 01 06:46:37 PM PDT 24
Peak memory 241172 kb
Host smart-cf097421-089e-47ad-b30d-a7a02130a3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354782044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1354782044
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3361686011
Short name T688
Test name
Test status
Simulation time 127693510 ps
CPU time 2.41 seconds
Started Aug 01 06:46:23 PM PDT 24
Finished Aug 01 06:46:25 PM PDT 24
Peak memory 232792 kb
Host smart-29d12fd6-40e3-4d62-a49d-0cb8e95a712d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361686011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3361686011
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.547449359
Short name T458
Test name
Test status
Simulation time 436724934 ps
CPU time 4.07 seconds
Started Aug 01 06:46:34 PM PDT 24
Finished Aug 01 06:46:38 PM PDT 24
Peak memory 223092 kb
Host smart-60d871e6-5d93-45bd-bbb2-701b9902efe6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=547449359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.547449359
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1075245916
Short name T134
Test name
Test status
Simulation time 12012291679 ps
CPU time 128.97 seconds
Started Aug 01 06:46:30 PM PDT 24
Finished Aug 01 06:48:39 PM PDT 24
Peak memory 249576 kb
Host smart-7c7ba13c-3936-434e-96f8-a244b2274fe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075245916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1075245916
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.852039982
Short name T607
Test name
Test status
Simulation time 5710316212 ps
CPU time 14.97 seconds
Started Aug 01 06:46:24 PM PDT 24
Finished Aug 01 06:46:39 PM PDT 24
Peak memory 216228 kb
Host smart-3f60c30a-f8be-4ff1-a97d-5d4379eff9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852039982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.852039982
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3078919244
Short name T589
Test name
Test status
Simulation time 9945694611 ps
CPU time 16.51 seconds
Started Aug 01 06:46:27 PM PDT 24
Finished Aug 01 06:46:43 PM PDT 24
Peak memory 216684 kb
Host smart-1eab23e7-a99c-4750-a224-6388ead41b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078919244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3078919244
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.951856149
Short name T728
Test name
Test status
Simulation time 13046124 ps
CPU time 0.69 seconds
Started Aug 01 06:46:30 PM PDT 24
Finished Aug 01 06:46:31 PM PDT 24
Peak memory 205968 kb
Host smart-3f101dbd-38be-4f16-8251-184bdb9488e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951856149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.951856149
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2022805014
Short name T733
Test name
Test status
Simulation time 46409121 ps
CPU time 0.86 seconds
Started Aug 01 06:46:25 PM PDT 24
Finished Aug 01 06:46:26 PM PDT 24
Peak memory 206340 kb
Host smart-b5a178a2-1f47-4239-babb-a3c476dc632a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022805014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2022805014
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2196838425
Short name T477
Test name
Test status
Simulation time 229734049 ps
CPU time 2.66 seconds
Started Aug 01 06:46:22 PM PDT 24
Finished Aug 01 06:46:25 PM PDT 24
Peak memory 224940 kb
Host smart-2cba97d1-8d81-4a8d-b804-f530c4db7ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196838425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2196838425
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2046902403
Short name T681
Test name
Test status
Simulation time 13535021 ps
CPU time 0.7 seconds
Started Aug 01 06:46:31 PM PDT 24
Finished Aug 01 06:46:32 PM PDT 24
Peak memory 205256 kb
Host smart-d331938a-f10d-428d-91cc-c9f45f67d207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046902403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2046902403
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2122489984
Short name T208
Test name
Test status
Simulation time 1067199214 ps
CPU time 6.06 seconds
Started Aug 01 06:46:29 PM PDT 24
Finished Aug 01 06:46:35 PM PDT 24
Peak memory 224932 kb
Host smart-e8feeb08-089e-4c37-8ff7-eb44f2e341e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122489984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2122489984
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3812381842
Short name T474
Test name
Test status
Simulation time 47713124 ps
CPU time 0.8 seconds
Started Aug 01 06:46:31 PM PDT 24
Finished Aug 01 06:46:32 PM PDT 24
Peak memory 206916 kb
Host smart-9812385d-c0ec-4f04-b26a-3dbca4cc9d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812381842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3812381842
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2174506747
Short name T592
Test name
Test status
Simulation time 34933765619 ps
CPU time 89.19 seconds
Started Aug 01 06:46:32 PM PDT 24
Finished Aug 01 06:48:01 PM PDT 24
Peak memory 257736 kb
Host smart-2fc5031b-5803-4d9d-b435-e639432b7719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174506747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2174506747
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4026635007
Short name T111
Test name
Test status
Simulation time 4023204564 ps
CPU time 82.36 seconds
Started Aug 01 06:46:29 PM PDT 24
Finished Aug 01 06:47:52 PM PDT 24
Peak memory 254440 kb
Host smart-44a68ca5-0110-4737-848f-13197caea04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026635007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4026635007
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.298982232
Short name T602
Test name
Test status
Simulation time 3940905024 ps
CPU time 66.19 seconds
Started Aug 01 06:46:30 PM PDT 24
Finished Aug 01 06:47:37 PM PDT 24
Peak memory 252036 kb
Host smart-ce16652d-9864-4ea3-b145-1b22ffb57aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298982232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.298982232
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2776348819
Short name T262
Test name
Test status
Simulation time 3573994544 ps
CPU time 12.89 seconds
Started Aug 01 06:46:33 PM PDT 24
Finished Aug 01 06:46:46 PM PDT 24
Peak memory 241336 kb
Host smart-e42008b5-d338-489b-aa3c-e6149d0dfbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776348819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2776348819
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1463100029
Short name T243
Test name
Test status
Simulation time 49779236394 ps
CPU time 351.4 seconds
Started Aug 01 06:46:28 PM PDT 24
Finished Aug 01 06:52:20 PM PDT 24
Peak memory 265200 kb
Host smart-fe48df40-ca1a-4bb4-b655-c8b704210619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463100029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1463100029
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3228163809
Short name T314
Test name
Test status
Simulation time 172742308 ps
CPU time 3 seconds
Started Aug 01 06:46:31 PM PDT 24
Finished Aug 01 06:46:35 PM PDT 24
Peak memory 233184 kb
Host smart-ec96cdd9-0a59-4cd8-b03d-f24914a80910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228163809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3228163809
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1978124469
Short name T670
Test name
Test status
Simulation time 4357035733 ps
CPU time 12.78 seconds
Started Aug 01 06:46:31 PM PDT 24
Finished Aug 01 06:46:44 PM PDT 24
Peak memory 249508 kb
Host smart-1c4c0246-9fad-4a8b-8c17-678308c2924b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978124469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1978124469
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.154957536
Short name T82
Test name
Test status
Simulation time 69538891607 ps
CPU time 28.6 seconds
Started Aug 01 06:46:33 PM PDT 24
Finished Aug 01 06:47:02 PM PDT 24
Peak memory 224956 kb
Host smart-7d256882-2156-461e-9068-a208a325eda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154957536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.154957536
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.931791114
Short name T880
Test name
Test status
Simulation time 909610118 ps
CPU time 6.96 seconds
Started Aug 01 06:46:33 PM PDT 24
Finished Aug 01 06:46:40 PM PDT 24
Peak memory 249216 kb
Host smart-d4e3e25c-d0e8-4311-98d6-bb9c704a7ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931791114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.931791114
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1947095689
Short name T537
Test name
Test status
Simulation time 2985315790 ps
CPU time 7.11 seconds
Started Aug 01 06:46:29 PM PDT 24
Finished Aug 01 06:46:37 PM PDT 24
Peak memory 223632 kb
Host smart-64e35d9c-a3ad-4d68-9fd6-9ecbe02349bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1947095689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1947095689
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.770550857
Short name T44
Test name
Test status
Simulation time 23855198735 ps
CPU time 142.2 seconds
Started Aug 01 06:46:30 PM PDT 24
Finished Aug 01 06:48:53 PM PDT 24
Peak memory 274196 kb
Host smart-f65e1436-f75a-491c-bd78-958733930688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770550857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.770550857
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.686385958
Short name T279
Test name
Test status
Simulation time 19841715224 ps
CPU time 27.22 seconds
Started Aug 01 06:46:34 PM PDT 24
Finished Aug 01 06:47:01 PM PDT 24
Peak memory 217052 kb
Host smart-1bf835f8-dd73-4cca-8e81-a907580cccc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686385958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.686385958
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3669630739
Short name T889
Test name
Test status
Simulation time 3984878008 ps
CPU time 5.08 seconds
Started Aug 01 06:46:31 PM PDT 24
Finished Aug 01 06:46:36 PM PDT 24
Peak memory 216704 kb
Host smart-beb3ee02-9f7b-4c14-a0dc-e14970de8c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669630739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3669630739
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1880096658
Short name T900
Test name
Test status
Simulation time 115227184 ps
CPU time 1.05 seconds
Started Aug 01 06:46:29 PM PDT 24
Finished Aug 01 06:46:31 PM PDT 24
Peak memory 207784 kb
Host smart-05f543b6-d737-4446-ae19-57c39357100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880096658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1880096658
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2572480738
Short name T310
Test name
Test status
Simulation time 307589179 ps
CPU time 1 seconds
Started Aug 01 06:46:31 PM PDT 24
Finished Aug 01 06:46:32 PM PDT 24
Peak memory 207384 kb
Host smart-3b635d79-1c26-4ca5-9f8d-2df985df2fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572480738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2572480738
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.834589242
Short name T431
Test name
Test status
Simulation time 20059361738 ps
CPU time 6.51 seconds
Started Aug 01 06:46:31 PM PDT 24
Finished Aug 01 06:46:37 PM PDT 24
Peak memory 233148 kb
Host smart-286b2551-3f19-4287-a6b4-b63236838a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834589242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.834589242
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.67096334
Short name T603
Test name
Test status
Simulation time 13842648 ps
CPU time 0.7 seconds
Started Aug 01 06:46:41 PM PDT 24
Finished Aug 01 06:46:41 PM PDT 24
Peak memory 205756 kb
Host smart-c77949ef-0d63-4531-b778-695aa7926ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67096334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.67096334
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4155642144
Short name T686
Test name
Test status
Simulation time 153488694 ps
CPU time 2.48 seconds
Started Aug 01 06:46:33 PM PDT 24
Finished Aug 01 06:46:35 PM PDT 24
Peak memory 233112 kb
Host smart-1da7c740-bb91-4280-9628-e82da7c46c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155642144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4155642144
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1092752478
Short name T407
Test name
Test status
Simulation time 44514776 ps
CPU time 0.79 seconds
Started Aug 01 06:46:33 PM PDT 24
Finished Aug 01 06:46:34 PM PDT 24
Peak memory 206924 kb
Host smart-1e3258e4-3ae8-489c-a6a2-0f1d33f76b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092752478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1092752478
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.318357632
Short name T608
Test name
Test status
Simulation time 31121835484 ps
CPU time 179.21 seconds
Started Aug 01 06:46:30 PM PDT 24
Finished Aug 01 06:49:30 PM PDT 24
Peak memory 249516 kb
Host smart-2d472ef6-30cc-4166-8390-73dbbdd7dc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318357632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.318357632
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3725286523
Short name T218
Test name
Test status
Simulation time 2146089505 ps
CPU time 38.67 seconds
Started Aug 01 06:46:33 PM PDT 24
Finished Aug 01 06:47:12 PM PDT 24
Peak memory 249580 kb
Host smart-94da83b4-df72-4dde-a62c-85d026cf810c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725286523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3725286523
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3214213161
Short name T749
Test name
Test status
Simulation time 5697638855 ps
CPU time 57.34 seconds
Started Aug 01 06:46:34 PM PDT 24
Finished Aug 01 06:47:31 PM PDT 24
Peak memory 249556 kb
Host smart-694654c2-bfc0-4aa6-aacc-cc1352ae9862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214213161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3214213161
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.470781070
Short name T551
Test name
Test status
Simulation time 4168648285 ps
CPU time 22.84 seconds
Started Aug 01 06:46:34 PM PDT 24
Finished Aug 01 06:46:57 PM PDT 24
Peak memory 233176 kb
Host smart-4602f048-b004-4cb5-8c6c-c963ad12f6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470781070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.470781070
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3256672223
Short name T785
Test name
Test status
Simulation time 75021019070 ps
CPU time 168.88 seconds
Started Aug 01 06:46:33 PM PDT 24
Finished Aug 01 06:49:22 PM PDT 24
Peak memory 250524 kb
Host smart-7a277601-9618-48da-960b-fb0a1ffbb1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256672223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3256672223
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.589407325
Short name T616
Test name
Test status
Simulation time 1661732277 ps
CPU time 18.07 seconds
Started Aug 01 06:46:33 PM PDT 24
Finished Aug 01 06:46:51 PM PDT 24
Peak memory 233100 kb
Host smart-5dfdb957-26cd-4967-978c-43021cdfe563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589407325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.589407325
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1364111300
Short name T206
Test name
Test status
Simulation time 1053586492 ps
CPU time 6.62 seconds
Started Aug 01 06:46:32 PM PDT 24
Finished Aug 01 06:46:39 PM PDT 24
Peak memory 224876 kb
Host smart-53582f3c-b547-4600-80f8-aa301add0e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364111300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1364111300
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.642336719
Short name T224
Test name
Test status
Simulation time 1642673767 ps
CPU time 8.28 seconds
Started Aug 01 06:46:35 PM PDT 24
Finished Aug 01 06:46:43 PM PDT 24
Peak memory 233092 kb
Host smart-211d73e4-e105-4cd9-9124-7cd4dab6a887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642336719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.642336719
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1469440892
Short name T738
Test name
Test status
Simulation time 15817164764 ps
CPU time 13.41 seconds
Started Aug 01 06:46:29 PM PDT 24
Finished Aug 01 06:46:43 PM PDT 24
Peak memory 224984 kb
Host smart-5b4e303f-6997-480a-8472-36c915b6dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469440892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1469440892
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3919386839
Short name T514
Test name
Test status
Simulation time 3793121242 ps
CPU time 11.06 seconds
Started Aug 01 06:46:31 PM PDT 24
Finished Aug 01 06:46:43 PM PDT 24
Peak memory 220296 kb
Host smart-f1b6809b-babe-48a3-acc5-d5d97ae6dd41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3919386839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3919386839
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2805607708
Short name T137
Test name
Test status
Simulation time 6937858577 ps
CPU time 41.93 seconds
Started Aug 01 06:46:49 PM PDT 24
Finished Aug 01 06:47:31 PM PDT 24
Peak memory 249752 kb
Host smart-1c17914b-9521-4197-9e7f-f949946b8fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805607708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2805607708
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1497672817
Short name T393
Test name
Test status
Simulation time 8174330203 ps
CPU time 24.52 seconds
Started Aug 01 06:46:33 PM PDT 24
Finished Aug 01 06:46:58 PM PDT 24
Peak memory 216720 kb
Host smart-baea5477-82a3-4d0f-a9bf-a91a3a25d413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497672817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1497672817
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.529860793
Short name T319
Test name
Test status
Simulation time 1508704211 ps
CPU time 6.75 seconds
Started Aug 01 06:46:33 PM PDT 24
Finished Aug 01 06:46:40 PM PDT 24
Peak memory 216616 kb
Host smart-2765cd0d-1e9b-49ee-a562-91027d70395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529860793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.529860793
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1139152913
Short name T743
Test name
Test status
Simulation time 178728085 ps
CPU time 2.98 seconds
Started Aug 01 06:46:34 PM PDT 24
Finished Aug 01 06:46:37 PM PDT 24
Peak memory 216660 kb
Host smart-d729a9e2-082a-4832-a9a4-d94b4b0c27f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139152913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1139152913
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3299954988
Short name T903
Test name
Test status
Simulation time 20666516 ps
CPU time 0.75 seconds
Started Aug 01 06:46:31 PM PDT 24
Finished Aug 01 06:46:32 PM PDT 24
Peak memory 206324 kb
Host smart-b986569c-cb04-49e7-a870-7aac1fa12024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299954988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3299954988
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1602360195
Short name T220
Test name
Test status
Simulation time 4357159352 ps
CPU time 4.61 seconds
Started Aug 01 06:46:32 PM PDT 24
Finished Aug 01 06:46:37 PM PDT 24
Peak memory 224928 kb
Host smart-6af08c85-faa7-4b1d-b09b-8274ed0efabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602360195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1602360195
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2219514480
Short name T388
Test name
Test status
Simulation time 41780609 ps
CPU time 0.75 seconds
Started Aug 01 06:46:46 PM PDT 24
Finished Aug 01 06:46:47 PM PDT 24
Peak memory 205256 kb
Host smart-df8b7589-07c5-46ae-b6ab-310d545feff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219514480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2219514480
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3789316643
Short name T503
Test name
Test status
Simulation time 114821390 ps
CPU time 2.37 seconds
Started Aug 01 06:46:40 PM PDT 24
Finished Aug 01 06:46:43 PM PDT 24
Peak memory 224856 kb
Host smart-92edd0a4-41df-4b66-b0db-ac814eeb4227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789316643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3789316643
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3980662975
Short name T139
Test name
Test status
Simulation time 69321292 ps
CPU time 0.77 seconds
Started Aug 01 06:46:40 PM PDT 24
Finished Aug 01 06:46:41 PM PDT 24
Peak memory 206920 kb
Host smart-1a01204d-1583-4dfd-b505-18139f0dd4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980662975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3980662975
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.244151262
Short name T831
Test name
Test status
Simulation time 12295650 ps
CPU time 0.75 seconds
Started Aug 01 06:46:50 PM PDT 24
Finished Aug 01 06:46:50 PM PDT 24
Peak memory 216176 kb
Host smart-0f146842-f987-496d-bbcd-76ecc8c163f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244151262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.244151262
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4093641634
Short name T554
Test name
Test status
Simulation time 23427997520 ps
CPU time 206.15 seconds
Started Aug 01 06:46:43 PM PDT 24
Finished Aug 01 06:50:09 PM PDT 24
Peak memory 257540 kb
Host smart-81bf28eb-a0c8-475b-a7ef-f794d0328090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093641634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4093641634
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1653996345
Short name T225
Test name
Test status
Simulation time 1028406703532 ps
CPU time 499.29 seconds
Started Aug 01 06:46:46 PM PDT 24
Finished Aug 01 06:55:05 PM PDT 24
Peak memory 265724 kb
Host smart-63427f96-630e-428b-b264-32dfe93ea339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653996345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1653996345
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.166367243
Short name T285
Test name
Test status
Simulation time 1745051242 ps
CPU time 7.9 seconds
Started Aug 01 06:46:49 PM PDT 24
Finished Aug 01 06:46:57 PM PDT 24
Peak memory 233156 kb
Host smart-8b35e226-f82e-43bd-8066-19885dce7c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166367243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.166367243
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.153072558
Short name T692
Test name
Test status
Simulation time 140649775092 ps
CPU time 244.32 seconds
Started Aug 01 06:46:43 PM PDT 24
Finished Aug 01 06:50:47 PM PDT 24
Peak memory 250592 kb
Host smart-fd4d49fe-127c-4ca1-8253-de0d8a879a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153072558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.153072558
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3246943342
Short name T636
Test name
Test status
Simulation time 7815388346 ps
CPU time 23.29 seconds
Started Aug 01 06:46:42 PM PDT 24
Finished Aug 01 06:47:06 PM PDT 24
Peak memory 224992 kb
Host smart-566cb181-6c1a-4f0e-b69b-fa44600da9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246943342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3246943342
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.369810987
Short name T959
Test name
Test status
Simulation time 739460284 ps
CPU time 7.95 seconds
Started Aug 01 06:46:40 PM PDT 24
Finished Aug 01 06:46:48 PM PDT 24
Peak memory 224868 kb
Host smart-164ee5fe-dd0d-4d00-b859-a45bf0e94140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369810987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.369810987
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.268093600
Short name T413
Test name
Test status
Simulation time 4692660682 ps
CPU time 11.9 seconds
Started Aug 01 06:46:43 PM PDT 24
Finished Aug 01 06:46:55 PM PDT 24
Peak memory 233204 kb
Host smart-467e6d20-9845-4ad3-909a-d542d4c64dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268093600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.268093600
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1840961620
Short name T361
Test name
Test status
Simulation time 31240050893 ps
CPU time 6.33 seconds
Started Aug 01 06:46:44 PM PDT 24
Finished Aug 01 06:46:50 PM PDT 24
Peak memory 224948 kb
Host smart-e3b9b08a-3c62-429c-ac27-60681dd31837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840961620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1840961620
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4236057842
Short name T864
Test name
Test status
Simulation time 1092786034 ps
CPU time 5.23 seconds
Started Aug 01 06:46:49 PM PDT 24
Finished Aug 01 06:46:54 PM PDT 24
Peak memory 221152 kb
Host smart-5ba92afb-59a0-47c5-a7e3-44dfa03e440a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4236057842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4236057842
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.129104941
Short name T601
Test name
Test status
Simulation time 8306990221 ps
CPU time 40.53 seconds
Started Aug 01 06:46:43 PM PDT 24
Finished Aug 01 06:47:24 PM PDT 24
Peak memory 216688 kb
Host smart-7259715a-fcb6-4523-ac52-11dd68f60aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129104941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.129104941
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4075028560
Short name T947
Test name
Test status
Simulation time 2607893213 ps
CPU time 8.48 seconds
Started Aug 01 06:46:41 PM PDT 24
Finished Aug 01 06:46:50 PM PDT 24
Peak memory 216736 kb
Host smart-e5db39dc-37ec-4da7-a10e-dcb4d3f1413c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075028560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4075028560
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2066574449
Short name T539
Test name
Test status
Simulation time 146269936 ps
CPU time 1.02 seconds
Started Aug 01 06:46:50 PM PDT 24
Finished Aug 01 06:46:51 PM PDT 24
Peak memory 207344 kb
Host smart-65de64fe-f687-4029-808c-76ccb2b568f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066574449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2066574449
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1013038233
Short name T304
Test name
Test status
Simulation time 169354589 ps
CPU time 0.89 seconds
Started Aug 01 06:46:44 PM PDT 24
Finished Aug 01 06:46:45 PM PDT 24
Peak memory 206300 kb
Host smart-12882a0a-2e51-45f4-bf9d-cd8103145a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013038233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1013038233
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.168288732
Short name T569
Test name
Test status
Simulation time 6456160510 ps
CPU time 7.51 seconds
Started Aug 01 06:46:41 PM PDT 24
Finished Aug 01 06:46:49 PM PDT 24
Peak memory 233228 kb
Host smart-88259299-a834-40eb-bbb9-3ea3f4a16cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168288732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.168288732
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1148606856
Short name T282
Test name
Test status
Simulation time 35142258 ps
CPU time 0.72 seconds
Started Aug 01 06:46:41 PM PDT 24
Finished Aug 01 06:46:42 PM PDT 24
Peak memory 206128 kb
Host smart-e30870a4-96af-4483-ba5b-60908fed1d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148606856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1148606856
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.989695883
Short name T975
Test name
Test status
Simulation time 321912224 ps
CPU time 2.98 seconds
Started Aug 01 06:46:42 PM PDT 24
Finished Aug 01 06:46:46 PM PDT 24
Peak memory 233060 kb
Host smart-ebbb4588-3094-4405-ae1d-f68eceed542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989695883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.989695883
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3251556244
Short name T729
Test name
Test status
Simulation time 87152578 ps
CPU time 0.77 seconds
Started Aug 01 06:46:40 PM PDT 24
Finished Aug 01 06:46:41 PM PDT 24
Peak memory 207272 kb
Host smart-1286d394-6283-47f6-9061-2a5719030406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251556244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3251556244
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.4050057402
Short name T814
Test name
Test status
Simulation time 40363811348 ps
CPU time 83.61 seconds
Started Aug 01 06:46:41 PM PDT 24
Finished Aug 01 06:48:05 PM PDT 24
Peak memory 249536 kb
Host smart-3346d5ed-2b50-480e-82ec-1a797a55141b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050057402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4050057402
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3899870323
Short name T809
Test name
Test status
Simulation time 15062527207 ps
CPU time 104.36 seconds
Started Aug 01 06:46:40 PM PDT 24
Finished Aug 01 06:48:25 PM PDT 24
Peak memory 249332 kb
Host smart-1e17d69b-2dad-4e32-b9b2-816f6a3f0d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899870323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3899870323
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.522486823
Short name T253
Test name
Test status
Simulation time 22260231778 ps
CPU time 110.55 seconds
Started Aug 01 06:46:42 PM PDT 24
Finished Aug 01 06:48:33 PM PDT 24
Peak memory 265952 kb
Host smart-baa06abe-120c-4653-bbf9-24dc7ca330ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522486823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.522486823
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3305887142
Short name T518
Test name
Test status
Simulation time 3515584033 ps
CPU time 48.08 seconds
Started Aug 01 06:46:43 PM PDT 24
Finished Aug 01 06:47:31 PM PDT 24
Peak memory 241440 kb
Host smart-da2b0655-3f09-4ca4-a481-bdbe760c62d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305887142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3305887142
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2895722458
Short name T351
Test name
Test status
Simulation time 3763144594 ps
CPU time 28.19 seconds
Started Aug 01 06:46:43 PM PDT 24
Finished Aug 01 06:47:12 PM PDT 24
Peak memory 237628 kb
Host smart-abc36933-3f1a-443b-8d97-42fab21a9367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895722458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2895722458
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.436874422
Short name T384
Test name
Test status
Simulation time 101121733 ps
CPU time 3.73 seconds
Started Aug 01 06:46:42 PM PDT 24
Finished Aug 01 06:46:46 PM PDT 24
Peak memory 233160 kb
Host smart-23844a10-55d4-4ff6-91ff-30ffa0bd0bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436874422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.436874422
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.899267869
Short name T207
Test name
Test status
Simulation time 862404746 ps
CPU time 6.69 seconds
Started Aug 01 06:46:43 PM PDT 24
Finished Aug 01 06:46:50 PM PDT 24
Peak memory 224936 kb
Host smart-48834f4b-f2c1-482c-b8c7-71062693abd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899267869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.899267869
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2077934111
Short name T505
Test name
Test status
Simulation time 5991148907 ps
CPU time 15.95 seconds
Started Aug 01 06:46:42 PM PDT 24
Finished Aug 01 06:46:58 PM PDT 24
Peak memory 233136 kb
Host smart-fa0fac01-6a5c-4a90-b7a4-320c0a97df13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077934111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2077934111
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1782952002
Short name T544
Test name
Test status
Simulation time 11323535836 ps
CPU time 9.39 seconds
Started Aug 01 06:46:39 PM PDT 24
Finished Aug 01 06:46:48 PM PDT 24
Peak memory 233136 kb
Host smart-f9a3f691-7262-4fb5-8b4d-b01a2f526a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782952002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1782952002
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.308582036
Short name T722
Test name
Test status
Simulation time 211761365 ps
CPU time 5.41 seconds
Started Aug 01 06:46:44 PM PDT 24
Finished Aug 01 06:46:49 PM PDT 24
Peak memory 223516 kb
Host smart-073c786c-a4a0-41b3-b9b6-408277e9b36d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=308582036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.308582036
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1359257429
Short name T652
Test name
Test status
Simulation time 21525412067 ps
CPU time 195.09 seconds
Started Aug 01 06:46:42 PM PDT 24
Finished Aug 01 06:49:57 PM PDT 24
Peak memory 250656 kb
Host smart-38d5cffa-a4a0-467f-87e5-e7304ec9e2b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359257429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1359257429
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.541737953
Short name T525
Test name
Test status
Simulation time 8073041662 ps
CPU time 18.88 seconds
Started Aug 01 06:46:39 PM PDT 24
Finished Aug 01 06:46:58 PM PDT 24
Peak memory 216844 kb
Host smart-1d1ea65d-1b40-407e-8719-43ac084a4d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541737953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.541737953
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3508064903
Short name T368
Test name
Test status
Simulation time 6392550136 ps
CPU time 15.9 seconds
Started Aug 01 06:46:44 PM PDT 24
Finished Aug 01 06:47:00 PM PDT 24
Peak memory 216616 kb
Host smart-310ea16e-7307-4e64-9e83-d808f29d5931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508064903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3508064903
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3782301539
Short name T645
Test name
Test status
Simulation time 41398332 ps
CPU time 1.12 seconds
Started Aug 01 06:46:43 PM PDT 24
Finished Aug 01 06:46:45 PM PDT 24
Peak memory 208016 kb
Host smart-7dfb4ab2-6818-4024-8ae6-8217fac7eb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782301539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3782301539
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.853021046
Short name T381
Test name
Test status
Simulation time 13312035 ps
CPU time 0.7 seconds
Started Aug 01 06:46:40 PM PDT 24
Finished Aug 01 06:46:41 PM PDT 24
Peak memory 205992 kb
Host smart-15873bdc-fa02-4534-8ec5-9812c48056e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853021046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.853021046
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2587214324
Short name T491
Test name
Test status
Simulation time 1943806403 ps
CPU time 14.31 seconds
Started Aug 01 06:46:40 PM PDT 24
Finished Aug 01 06:46:55 PM PDT 24
Peak memory 233152 kb
Host smart-10633ff8-3a5d-4b11-93c5-2a13ef6cad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587214324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2587214324
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4281441915
Short name T394
Test name
Test status
Simulation time 14465553 ps
CPU time 0.72 seconds
Started Aug 01 06:46:51 PM PDT 24
Finished Aug 01 06:46:52 PM PDT 24
Peak memory 205744 kb
Host smart-f483eab8-1d13-41d3-86b7-da341a3634c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281441915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4281441915
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2563886318
Short name T342
Test name
Test status
Simulation time 176219437 ps
CPU time 3.48 seconds
Started Aug 01 06:46:47 PM PDT 24
Finished Aug 01 06:46:50 PM PDT 24
Peak memory 233096 kb
Host smart-0908d585-a32f-4ca5-a1db-42a241c87e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563886318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2563886318
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.524235654
Short name T954
Test name
Test status
Simulation time 17939901 ps
CPU time 0.78 seconds
Started Aug 01 06:46:40 PM PDT 24
Finished Aug 01 06:46:41 PM PDT 24
Peak memory 206916 kb
Host smart-ffde1a45-150e-42e1-be78-b286a8a28a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524235654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.524235654
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2066122527
Short name T29
Test name
Test status
Simulation time 144619965823 ps
CPU time 267.24 seconds
Started Aug 01 06:46:46 PM PDT 24
Finished Aug 01 06:51:13 PM PDT 24
Peak memory 265924 kb
Host smart-6bbaef93-e54d-4df2-8309-662d032295b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066122527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2066122527
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.401830222
Short name T173
Test name
Test status
Simulation time 9818471263 ps
CPU time 109.52 seconds
Started Aug 01 06:46:43 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 251760 kb
Host smart-ee0f1761-3ab1-47d4-8319-27d18923f8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401830222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.401830222
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.457905488
Short name T821
Test name
Test status
Simulation time 52624832897 ps
CPU time 472.79 seconds
Started Aug 01 06:46:44 PM PDT 24
Finished Aug 01 06:54:37 PM PDT 24
Peak memory 264904 kb
Host smart-051c3e80-8715-4d3e-9386-d9e8752851a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457905488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.457905488
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2204683699
Short name T848
Test name
Test status
Simulation time 752043452 ps
CPU time 6.65 seconds
Started Aug 01 06:46:47 PM PDT 24
Finished Aug 01 06:46:53 PM PDT 24
Peak memory 238112 kb
Host smart-9bb1b272-6669-48b2-bb82-24bdea1e77d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204683699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2204683699
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1455993291
Short name T231
Test name
Test status
Simulation time 55981020453 ps
CPU time 287.11 seconds
Started Aug 01 06:46:46 PM PDT 24
Finished Aug 01 06:51:33 PM PDT 24
Peak memory 249572 kb
Host smart-3b2bca9f-9bb1-421c-bbf8-730a6baa2fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455993291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1455993291
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2903530611
Short name T867
Test name
Test status
Simulation time 583937591 ps
CPU time 6.31 seconds
Started Aug 01 06:46:46 PM PDT 24
Finished Aug 01 06:46:52 PM PDT 24
Peak memory 224868 kb
Host smart-53cc488a-3c26-4002-87e8-5bd706f2c086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903530611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2903530611
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3795730602
Short name T141
Test name
Test status
Simulation time 1018629470 ps
CPU time 11.32 seconds
Started Aug 01 06:47:01 PM PDT 24
Finished Aug 01 06:47:12 PM PDT 24
Peak memory 235136 kb
Host smart-6b995747-c34a-4d3f-8c32-de3f6d262397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795730602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3795730602
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.969544463
Short name T344
Test name
Test status
Simulation time 3857125046 ps
CPU time 19.31 seconds
Started Aug 01 06:46:47 PM PDT 24
Finished Aug 01 06:47:06 PM PDT 24
Peak memory 241360 kb
Host smart-3190814e-a79f-46e4-abcd-4f795495defa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969544463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.969544463
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1598462500
Short name T718
Test name
Test status
Simulation time 2173765288 ps
CPU time 5.27 seconds
Started Aug 01 06:46:50 PM PDT 24
Finished Aug 01 06:46:55 PM PDT 24
Peak memory 219312 kb
Host smart-700b23d6-5271-4d06-a661-02c46d755b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598462500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1598462500
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2393783475
Short name T371
Test name
Test status
Simulation time 1646025435 ps
CPU time 16.55 seconds
Started Aug 01 06:46:44 PM PDT 24
Finished Aug 01 06:47:01 PM PDT 24
Peak memory 220912 kb
Host smart-accea52f-9c81-4974-a2db-fcdc3dd1a536
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2393783475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2393783475
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2074032258
Short name T45
Test name
Test status
Simulation time 445326610985 ps
CPU time 790.11 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 07:00:13 PM PDT 24
Peak memory 290532 kb
Host smart-59490ec1-b73f-4957-8642-a30fdc5621a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074032258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2074032258
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1185880313
Short name T673
Test name
Test status
Simulation time 18706318622 ps
CPU time 34.69 seconds
Started Aug 01 06:46:41 PM PDT 24
Finished Aug 01 06:47:16 PM PDT 24
Peak memory 216800 kb
Host smart-ebf9ba7c-b3b9-41a5-a167-1a284d6e2bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185880313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1185880313
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4050444948
Short name T397
Test name
Test status
Simulation time 752451738 ps
CPU time 6.08 seconds
Started Aug 01 06:46:43 PM PDT 24
Finished Aug 01 06:46:50 PM PDT 24
Peak memory 216728 kb
Host smart-3a351db9-1ccd-44b8-b0f6-431c79ed7b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050444948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4050444948
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.4197575714
Short name T360
Test name
Test status
Simulation time 118158067 ps
CPU time 1.37 seconds
Started Aug 01 06:46:45 PM PDT 24
Finished Aug 01 06:46:46 PM PDT 24
Peak memory 208400 kb
Host smart-89f43e2c-58fd-4ecd-be57-32b605102731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197575714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4197575714
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1998271145
Short name T444
Test name
Test status
Simulation time 83495467 ps
CPU time 0.94 seconds
Started Aug 01 06:46:43 PM PDT 24
Finished Aug 01 06:46:44 PM PDT 24
Peak memory 206340 kb
Host smart-1e670335-2117-46ce-b942-ce00a7135dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998271145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1998271145
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.335514244
Short name T478
Test name
Test status
Simulation time 22731028276 ps
CPU time 17.38 seconds
Started Aug 01 06:46:46 PM PDT 24
Finished Aug 01 06:47:03 PM PDT 24
Peak memory 241336 kb
Host smart-612ebb6e-bed5-4fe1-8907-2113124acf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335514244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.335514244
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3663475423
Short name T373
Test name
Test status
Simulation time 212020427 ps
CPU time 0.73 seconds
Started Aug 01 06:46:50 PM PDT 24
Finished Aug 01 06:46:51 PM PDT 24
Peak memory 205256 kb
Host smart-588d4dc6-afcc-429c-9dc1-0bf3b95f992c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663475423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3663475423
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2407102326
Short name T985
Test name
Test status
Simulation time 107721987 ps
CPU time 3.32 seconds
Started Aug 01 06:46:49 PM PDT 24
Finished Aug 01 06:46:53 PM PDT 24
Peak memory 224856 kb
Host smart-412a29fa-e4aa-4a9c-926f-ad5e13ce4990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407102326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2407102326
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.63984548
Short name T940
Test name
Test status
Simulation time 42012038 ps
CPU time 0.79 seconds
Started Aug 01 06:47:01 PM PDT 24
Finished Aug 01 06:47:02 PM PDT 24
Peak memory 205940 kb
Host smart-49fe8e41-1206-4f80-b729-e122f17f2b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63984548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.63984548
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3923381251
Short name T904
Test name
Test status
Simulation time 69657520005 ps
CPU time 128.74 seconds
Started Aug 01 06:46:52 PM PDT 24
Finished Aug 01 06:49:01 PM PDT 24
Peak memory 252044 kb
Host smart-4086f660-3b80-4268-8df4-dfc9bf0e933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923381251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3923381251
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.538301272
Short name T884
Test name
Test status
Simulation time 21555292015 ps
CPU time 61.9 seconds
Started Aug 01 06:46:52 PM PDT 24
Finished Aug 01 06:47:54 PM PDT 24
Peak memory 240980 kb
Host smart-e2440ecf-5271-4666-b3dc-497480a7b3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538301272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.538301272
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1105178729
Short name T185
Test name
Test status
Simulation time 11174090569 ps
CPU time 79.77 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:48:20 PM PDT 24
Peak memory 266492 kb
Host smart-6eec077d-fb87-46e6-9ef5-46dfe3891315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105178729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1105178729
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3863522443
Short name T264
Test name
Test status
Simulation time 10103365822 ps
CPU time 28.2 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:31 PM PDT 24
Peak memory 246568 kb
Host smart-8ee03786-babc-4046-b0de-bfcf0c59a6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863522443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3863522443
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1765582802
Short name T412
Test name
Test status
Simulation time 12692332283 ps
CPU time 86.59 seconds
Started Aug 01 06:47:01 PM PDT 24
Finished Aug 01 06:48:28 PM PDT 24
Peak memory 240816 kb
Host smart-bc975f3e-2102-4bfa-a7a8-7547bb47ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765582802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1765582802
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4202326204
Short name T183
Test name
Test status
Simulation time 4558912498 ps
CPU time 16.57 seconds
Started Aug 01 06:46:52 PM PDT 24
Finished Aug 01 06:47:09 PM PDT 24
Peak memory 233240 kb
Host smart-ecc06901-fc54-4873-a987-b87ea92aed7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202326204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4202326204
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3308602415
Short name T404
Test name
Test status
Simulation time 8310652514 ps
CPU time 82.9 seconds
Started Aug 01 06:46:50 PM PDT 24
Finished Aug 01 06:48:13 PM PDT 24
Peak memory 233188 kb
Host smart-1dc96698-7985-493f-afab-e4ae83304ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308602415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3308602415
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3397597468
Short name T473
Test name
Test status
Simulation time 7956707470 ps
CPU time 19.57 seconds
Started Aug 01 06:46:51 PM PDT 24
Finished Aug 01 06:47:10 PM PDT 24
Peak memory 249216 kb
Host smart-b1d284f0-ce91-4832-9743-8c3b10e38d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397597468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3397597468
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.197270124
Short name T787
Test name
Test status
Simulation time 745209627 ps
CPU time 6.07 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:06 PM PDT 24
Peak memory 233064 kb
Host smart-6a15b4b5-529a-493e-98d1-70280078ee56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197270124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.197270124
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4210719436
Short name T120
Test name
Test status
Simulation time 1070857208 ps
CPU time 4.41 seconds
Started Aug 01 06:47:01 PM PDT 24
Finished Aug 01 06:47:05 PM PDT 24
Peak memory 221016 kb
Host smart-9d81577b-db88-4dc3-a9bc-2c77e1708ca8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4210719436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4210719436
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3386775763
Short name T844
Test name
Test status
Simulation time 49102492 ps
CPU time 1.14 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:01 PM PDT 24
Peak memory 207336 kb
Host smart-15ce85b5-4518-47e1-9482-a6bac81e59a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386775763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3386775763
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2984302706
Short name T605
Test name
Test status
Simulation time 2009424162 ps
CPU time 7.8 seconds
Started Aug 01 06:46:49 PM PDT 24
Finished Aug 01 06:46:57 PM PDT 24
Peak memory 216868 kb
Host smart-d0525d97-72f8-49a6-90d7-01197cd9ef5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984302706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2984302706
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1827399740
Short name T278
Test name
Test status
Simulation time 1180850080 ps
CPU time 6.9 seconds
Started Aug 01 06:46:51 PM PDT 24
Finished Aug 01 06:46:58 PM PDT 24
Peak memory 216552 kb
Host smart-925711bc-b865-44d5-9754-270be8e57313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827399740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1827399740
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3113354055
Short name T375
Test name
Test status
Simulation time 108443719 ps
CPU time 3.43 seconds
Started Aug 01 06:46:50 PM PDT 24
Finished Aug 01 06:46:54 PM PDT 24
Peak memory 216644 kb
Host smart-e560e72f-883c-480a-9aa5-84fdd2fbc5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113354055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3113354055
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2466631300
Short name T712
Test name
Test status
Simulation time 65018776 ps
CPU time 0.78 seconds
Started Aug 01 06:46:51 PM PDT 24
Finished Aug 01 06:46:52 PM PDT 24
Peak memory 206360 kb
Host smart-2d33391b-e9bf-496c-a227-aec87fd5ba64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466631300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2466631300
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1243379030
Short name T649
Test name
Test status
Simulation time 528912641 ps
CPU time 3.11 seconds
Started Aug 01 06:46:50 PM PDT 24
Finished Aug 01 06:46:53 PM PDT 24
Peak memory 233100 kb
Host smart-80656685-8bf3-4e87-9bd7-a05de33ec4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243379030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1243379030
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.100623653
Short name T523
Test name
Test status
Simulation time 14323554 ps
CPU time 0.71 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:01 PM PDT 24
Peak memory 205348 kb
Host smart-26189a10-d4ff-4694-91ee-cfa98adccb9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100623653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.100623653
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1709652478
Short name T585
Test name
Test status
Simulation time 259787205 ps
CPU time 3.1 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:04 PM PDT 24
Peak memory 233136 kb
Host smart-65853c45-3e80-4ae1-967e-c1eaf7cd8c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709652478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1709652478
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.264290531
Short name T796
Test name
Test status
Simulation time 105738590 ps
CPU time 0.78 seconds
Started Aug 01 06:46:50 PM PDT 24
Finished Aug 01 06:46:51 PM PDT 24
Peak memory 207276 kb
Host smart-ea93d218-4971-484f-8acd-e6ca5a44b89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264290531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.264290531
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3029739685
Short name T990
Test name
Test status
Simulation time 24809231241 ps
CPU time 169.6 seconds
Started Aug 01 06:46:52 PM PDT 24
Finished Aug 01 06:49:42 PM PDT 24
Peak memory 257732 kb
Host smart-7684cae2-898f-4728-9fd6-0da12a364a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029739685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3029739685
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2889024720
Short name T70
Test name
Test status
Simulation time 11130942868 ps
CPU time 51.29 seconds
Started Aug 01 06:47:01 PM PDT 24
Finished Aug 01 06:47:52 PM PDT 24
Peak memory 255640 kb
Host smart-fe26d847-1d45-4a3d-b472-4871d650f5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889024720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2889024720
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3813964840
Short name T931
Test name
Test status
Simulation time 41202463 ps
CPU time 3.09 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:05 PM PDT 24
Peak memory 233076 kb
Host smart-75b3b733-8b8e-49a0-b1ba-b6253a5e9d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813964840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3813964840
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3858394254
Short name T758
Test name
Test status
Simulation time 32955918274 ps
CPU time 105.66 seconds
Started Aug 01 06:46:55 PM PDT 24
Finished Aug 01 06:48:40 PM PDT 24
Peak memory 249576 kb
Host smart-c36a9af0-0a94-4bfa-8922-404dde38e25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858394254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3858394254
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3617068300
Short name T1010
Test name
Test status
Simulation time 3405108756 ps
CPU time 4.24 seconds
Started Aug 01 06:46:50 PM PDT 24
Finished Aug 01 06:46:55 PM PDT 24
Peak memory 224968 kb
Host smart-36c893b6-8155-4626-a260-b97a9740de80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617068300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3617068300
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1795279601
Short name T752
Test name
Test status
Simulation time 4979249801 ps
CPU time 28.73 seconds
Started Aug 01 06:46:52 PM PDT 24
Finished Aug 01 06:47:20 PM PDT 24
Peak memory 233172 kb
Host smart-ef497afb-bf0e-4d52-89af-260546b344af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795279601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1795279601
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1577329556
Short name T83
Test name
Test status
Simulation time 1888236935 ps
CPU time 7.75 seconds
Started Aug 01 06:46:52 PM PDT 24
Finished Aug 01 06:47:00 PM PDT 24
Peak memory 233152 kb
Host smart-c5c72b78-f2a0-4283-a2b9-a4dfbdf60aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577329556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1577329556
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.848882319
Short name T774
Test name
Test status
Simulation time 3886400086 ps
CPU time 11.67 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:12 PM PDT 24
Peak memory 233196 kb
Host smart-3c6c9b33-dc42-4de7-9987-c5c0b4c84787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848882319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.848882319
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2055067383
Short name T119
Test name
Test status
Simulation time 7503167043 ps
CPU time 18.15 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:20 PM PDT 24
Peak memory 222432 kb
Host smart-3f5e94d2-de31-4adb-8e93-892cd096f0b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2055067383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2055067383
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3593583012
Short name T131
Test name
Test status
Simulation time 4118792858 ps
CPU time 6.87 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:09 PM PDT 24
Peak memory 224988 kb
Host smart-0c097412-d2d4-45a0-9322-86ce8c9a6162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593583012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3593583012
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3327361711
Short name T911
Test name
Test status
Simulation time 733670443 ps
CPU time 7.42 seconds
Started Aug 01 06:46:56 PM PDT 24
Finished Aug 01 06:47:03 PM PDT 24
Peak memory 216856 kb
Host smart-2dd61ff8-317f-4ee8-b56f-22c1e8003eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327361711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3327361711
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3398345506
Short name T973
Test name
Test status
Simulation time 598094613 ps
CPU time 4.33 seconds
Started Aug 01 06:46:51 PM PDT 24
Finished Aug 01 06:46:55 PM PDT 24
Peak memory 216576 kb
Host smart-0d252e68-88de-4aab-b6b8-44d56ecc7e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398345506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3398345506
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2452398934
Short name T416
Test name
Test status
Simulation time 125456065 ps
CPU time 1.32 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:02 PM PDT 24
Peak memory 216780 kb
Host smart-5907a1e9-e492-4358-9e4d-d87cdef6101f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452398934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2452398934
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2828649959
Short name T773
Test name
Test status
Simulation time 110246944 ps
CPU time 0.84 seconds
Started Aug 01 06:46:51 PM PDT 24
Finished Aug 01 06:46:52 PM PDT 24
Peak memory 206316 kb
Host smart-460c10b4-78d6-4f1a-93ac-ade6240a52c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828649959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2828649959
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2780990976
Short name T501
Test name
Test status
Simulation time 1129586828 ps
CPU time 5.31 seconds
Started Aug 01 06:46:52 PM PDT 24
Finished Aug 01 06:46:57 PM PDT 24
Peak memory 224880 kb
Host smart-138919f0-7bad-4b86-9796-b5c94d083035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780990976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2780990976
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3909228658
Short name T527
Test name
Test status
Simulation time 43162033 ps
CPU time 0.71 seconds
Started Aug 01 06:46:59 PM PDT 24
Finished Aug 01 06:47:00 PM PDT 24
Peak memory 205252 kb
Host smart-21cd4ca3-26d4-4e76-95cd-3bed63edaf08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909228658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3909228658
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3831650540
Short name T770
Test name
Test status
Simulation time 2442877973 ps
CPU time 13.39 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:13 PM PDT 24
Peak memory 224972 kb
Host smart-07b2da2a-6493-424b-bdc1-93c018a46ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831650540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3831650540
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.943265203
Short name T926
Test name
Test status
Simulation time 13510813 ps
CPU time 0.8 seconds
Started Aug 01 06:47:03 PM PDT 24
Finished Aug 01 06:47:04 PM PDT 24
Peak memory 205908 kb
Host smart-6be90635-3b6d-454e-8b39-529e4a8b30f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943265203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.943265203
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2633953857
Short name T827
Test name
Test status
Simulation time 186882621716 ps
CPU time 179.22 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:50:01 PM PDT 24
Peak memory 254664 kb
Host smart-513c2594-0908-42a5-a954-2bb46fd92399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633953857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2633953857
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1119042378
Short name T535
Test name
Test status
Simulation time 109246163179 ps
CPU time 65.42 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:48:07 PM PDT 24
Peak memory 249764 kb
Host smart-824aa628-3c77-4b9c-8b85-0b4b7237d23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119042378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1119042378
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2908814189
Short name T803
Test name
Test status
Simulation time 4801681340 ps
CPU time 43.55 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:46 PM PDT 24
Peak memory 251380 kb
Host smart-f5d50032-9050-48bd-a236-d466d0399218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908814189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2908814189
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3369044439
Short name T767
Test name
Test status
Simulation time 161212626 ps
CPU time 6.76 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:07 PM PDT 24
Peak memory 224908 kb
Host smart-c2fcde91-42dc-4c52-ae99-c58860c995f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369044439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3369044439
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.792701273
Short name T184
Test name
Test status
Simulation time 129683381360 ps
CPU time 224.9 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:50:47 PM PDT 24
Peak memory 253236 kb
Host smart-7a805d1a-7cc2-436b-a563-0476ef6fdfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792701273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.792701273
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3270373036
Short name T403
Test name
Test status
Simulation time 423037328 ps
CPU time 7.64 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:07 PM PDT 24
Peak memory 233096 kb
Host smart-c99500e0-7e65-48b7-8140-06584a57265c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270373036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3270373036
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2355890259
Short name T436
Test name
Test status
Simulation time 427790800 ps
CPU time 8.05 seconds
Started Aug 01 06:47:05 PM PDT 24
Finished Aug 01 06:47:13 PM PDT 24
Peak memory 233136 kb
Host smart-2e88e776-cb76-48a2-9caf-83e7011d545e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355890259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2355890259
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.392457171
Short name T906
Test name
Test status
Simulation time 3522805921 ps
CPU time 15.69 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:18 PM PDT 24
Peak memory 224960 kb
Host smart-ac216b55-5622-4c80-b49c-26f321a20a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392457171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.392457171
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1984790231
Short name T968
Test name
Test status
Simulation time 2506789721 ps
CPU time 9.83 seconds
Started Aug 01 06:47:03 PM PDT 24
Finished Aug 01 06:47:13 PM PDT 24
Peak memory 233168 kb
Host smart-ce659ed2-889f-4eaf-887a-db344cf10487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984790231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1984790231
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.527826077
Short name T387
Test name
Test status
Simulation time 148541719 ps
CPU time 4.19 seconds
Started Aug 01 06:47:03 PM PDT 24
Finished Aug 01 06:47:08 PM PDT 24
Peak memory 220892 kb
Host smart-75196cb2-a5ac-45f3-bc61-06d4dfc3755a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=527826077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.527826077
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1466316566
Short name T855
Test name
Test status
Simulation time 5385977964 ps
CPU time 85.64 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:48:27 PM PDT 24
Peak memory 251524 kb
Host smart-b17265c8-888a-4d06-929e-e94a7b61ece1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466316566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1466316566
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3497373582
Short name T352
Test name
Test status
Simulation time 1826560302 ps
CPU time 14.51 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:15 PM PDT 24
Peak memory 216816 kb
Host smart-f7429a2f-efcd-476d-9dda-e30f38ce0338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497373582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3497373582
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3557371034
Short name T843
Test name
Test status
Simulation time 3113416130 ps
CPU time 7.84 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:10 PM PDT 24
Peak memory 216720 kb
Host smart-4ab1792b-962b-49d5-b571-5eab139493e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557371034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3557371034
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1900266274
Short name T996
Test name
Test status
Simulation time 178606890 ps
CPU time 4.19 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:05 PM PDT 24
Peak memory 216620 kb
Host smart-0761d5ee-b585-40a2-bd55-cf35a5effa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900266274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1900266274
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2368928192
Short name T595
Test name
Test status
Simulation time 257058997 ps
CPU time 0.8 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:03 PM PDT 24
Peak memory 206316 kb
Host smart-d01d52de-6669-4c0e-8ec2-ba754a72c9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368928192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2368928192
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1592239042
Short name T795
Test name
Test status
Simulation time 109460819 ps
CPU time 2.68 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:05 PM PDT 24
Peak memory 224896 kb
Host smart-ed7c5717-2d85-4bce-a1b5-69f72f14304e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592239042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1592239042
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1181077610
Short name T658
Test name
Test status
Simulation time 15440785 ps
CPU time 0.76 seconds
Started Aug 01 06:45:14 PM PDT 24
Finished Aug 01 06:45:15 PM PDT 24
Peak memory 205812 kb
Host smart-06da564b-f903-4b7a-8c3f-0ee4574388fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181077610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
181077610
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3855690029
Short name T515
Test name
Test status
Simulation time 107665125 ps
CPU time 2.42 seconds
Started Aug 01 06:45:04 PM PDT 24
Finished Aug 01 06:45:07 PM PDT 24
Peak memory 224840 kb
Host smart-762bb7c5-5d01-48ba-8374-3719749be128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855690029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3855690029
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1279551190
Short name T623
Test name
Test status
Simulation time 81653819 ps
CPU time 0.77 seconds
Started Aug 01 06:45:03 PM PDT 24
Finished Aug 01 06:45:04 PM PDT 24
Peak memory 205924 kb
Host smart-9ec41f13-170e-4389-bb94-fe2e82a5f49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279551190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1279551190
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.982839911
Short name T830
Test name
Test status
Simulation time 777092706 ps
CPU time 5 seconds
Started Aug 01 06:45:06 PM PDT 24
Finished Aug 01 06:45:11 PM PDT 24
Peak memory 218584 kb
Host smart-fd429f6b-bdfd-42c4-8d26-5a739fa37301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982839911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.982839911
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1460796241
Short name T899
Test name
Test status
Simulation time 8818380362 ps
CPU time 60.24 seconds
Started Aug 01 06:45:14 PM PDT 24
Finished Aug 01 06:46:15 PM PDT 24
Peak memory 248652 kb
Host smart-42e730a8-ed27-48ec-bcb0-a9783af2ed8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460796241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1460796241
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.295621986
Short name T675
Test name
Test status
Simulation time 2186059787 ps
CPU time 23.3 seconds
Started Aug 01 06:45:09 PM PDT 24
Finished Aug 01 06:45:32 PM PDT 24
Peak memory 251320 kb
Host smart-320c30c4-edb9-4a06-ac82-89e80318c007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295621986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
295621986
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2979784806
Short name T192
Test name
Test status
Simulation time 3211047535 ps
CPU time 22.1 seconds
Started Aug 01 06:45:04 PM PDT 24
Finished Aug 01 06:45:27 PM PDT 24
Peak memory 234180 kb
Host smart-83d14f58-3c62-42d0-b57e-95316ded4548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979784806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2979784806
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1207883363
Short name T763
Test name
Test status
Simulation time 98038751939 ps
CPU time 159.67 seconds
Started Aug 01 06:45:03 PM PDT 24
Finished Aug 01 06:47:43 PM PDT 24
Peak memory 249660 kb
Host smart-9ddf6ec7-3dd9-4a55-a088-12289dac5f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207883363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1207883363
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2408424769
Short name T713
Test name
Test status
Simulation time 1064819269 ps
CPU time 5.53 seconds
Started Aug 01 06:45:08 PM PDT 24
Finished Aug 01 06:45:13 PM PDT 24
Peak memory 233136 kb
Host smart-d532f9b4-5f45-476b-9fe9-50561b021c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408424769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2408424769
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3797100109
Short name T327
Test name
Test status
Simulation time 14608460225 ps
CPU time 24.78 seconds
Started Aug 01 06:45:08 PM PDT 24
Finished Aug 01 06:45:33 PM PDT 24
Peak memory 224944 kb
Host smart-94d14cc9-f3fd-4ac4-bf96-425a74bfc651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797100109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3797100109
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2799323078
Short name T437
Test name
Test status
Simulation time 4222205749 ps
CPU time 16.37 seconds
Started Aug 01 06:45:09 PM PDT 24
Finished Aug 01 06:45:25 PM PDT 24
Peak memory 224920 kb
Host smart-f6c511fe-739f-4dc8-b69a-73dfb715b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799323078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2799323078
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.787248490
Short name T555
Test name
Test status
Simulation time 11119698364 ps
CPU time 6.59 seconds
Started Aug 01 06:45:05 PM PDT 24
Finished Aug 01 06:45:12 PM PDT 24
Peak memory 233116 kb
Host smart-491ae1a5-a8c7-4422-be67-d4bf11c4a687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787248490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.787248490
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1447801624
Short name T815
Test name
Test status
Simulation time 1564517648 ps
CPU time 6.23 seconds
Started Aug 01 06:45:08 PM PDT 24
Finished Aug 01 06:45:14 PM PDT 24
Peak memory 220132 kb
Host smart-83624709-23cf-4b16-bc26-c9f65a6fd1ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1447801624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1447801624
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1819500796
Short name T59
Test name
Test status
Simulation time 145087783 ps
CPU time 1.23 seconds
Started Aug 01 06:45:08 PM PDT 24
Finished Aug 01 06:45:09 PM PDT 24
Peak memory 236432 kb
Host smart-b449ba2f-d4bf-4f7a-861c-43ce90325f05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819500796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1819500796
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1446892630
Short name T957
Test name
Test status
Simulation time 140803231 ps
CPU time 0.92 seconds
Started Aug 01 06:45:08 PM PDT 24
Finished Aug 01 06:45:09 PM PDT 24
Peak memory 207000 kb
Host smart-ff7c6e67-5aca-4e90-ba51-001487657fe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446892630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1446892630
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1843930608
Short name T372
Test name
Test status
Simulation time 3103022183 ps
CPU time 2.35 seconds
Started Aug 01 06:45:05 PM PDT 24
Finished Aug 01 06:45:08 PM PDT 24
Peak memory 216704 kb
Host smart-18d33a7f-e93c-445f-84f2-62d2f8071d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843930608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1843930608
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3514556475
Short name T311
Test name
Test status
Simulation time 3255984937 ps
CPU time 8.71 seconds
Started Aug 01 06:45:09 PM PDT 24
Finished Aug 01 06:45:18 PM PDT 24
Peak memory 216712 kb
Host smart-ae751881-1ff5-4b5e-b0a2-53f03e751d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514556475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3514556475
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1395372784
Short name T519
Test name
Test status
Simulation time 56671073 ps
CPU time 0.78 seconds
Started Aug 01 06:45:03 PM PDT 24
Finished Aug 01 06:45:04 PM PDT 24
Peak memory 206308 kb
Host smart-e492d9a0-4839-421b-802e-eaaab14fe040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395372784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1395372784
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3997234328
Short name T409
Test name
Test status
Simulation time 188189004 ps
CPU time 0.88 seconds
Started Aug 01 06:45:08 PM PDT 24
Finished Aug 01 06:45:09 PM PDT 24
Peak memory 206320 kb
Host smart-2908b8ab-b7c4-4590-b838-744a8c26e6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997234328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3997234328
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3186999488
Short name T507
Test name
Test status
Simulation time 11974231202 ps
CPU time 18.76 seconds
Started Aug 01 06:45:06 PM PDT 24
Finished Aug 01 06:45:25 PM PDT 24
Peak memory 233076 kb
Host smart-7affccb4-6a99-4997-9d23-5e64d1ceaf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186999488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3186999488
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2821332050
Short name T908
Test name
Test status
Simulation time 13374085 ps
CPU time 0.69 seconds
Started Aug 01 06:47:01 PM PDT 24
Finished Aug 01 06:47:02 PM PDT 24
Peak memory 205840 kb
Host smart-88891595-133b-4384-be07-aa8868bc3834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821332050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2821332050
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2286180618
Short name T666
Test name
Test status
Simulation time 454389064 ps
CPU time 6.26 seconds
Started Aug 01 06:47:05 PM PDT 24
Finished Aug 01 06:47:11 PM PDT 24
Peak memory 233104 kb
Host smart-1d4b9c4f-6599-4a18-9a48-aa893296d8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286180618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2286180618
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4045492588
Short name T988
Test name
Test status
Simulation time 19932724 ps
CPU time 0.87 seconds
Started Aug 01 06:47:01 PM PDT 24
Finished Aug 01 06:47:02 PM PDT 24
Peak memory 207008 kb
Host smart-5722fb6d-a750-48a3-ad7c-2a7b2f6a3a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045492588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4045492588
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2407634098
Short name T816
Test name
Test status
Simulation time 172414067 ps
CPU time 0.9 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:03 PM PDT 24
Peak memory 216360 kb
Host smart-0ffbd818-ae5d-4880-9044-ea6cdf1eab89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407634098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2407634098
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1037704838
Short name T466
Test name
Test status
Simulation time 8185530715 ps
CPU time 29.39 seconds
Started Aug 01 06:47:03 PM PDT 24
Finished Aug 01 06:47:33 PM PDT 24
Peak memory 236628 kb
Host smart-457a70d4-2c9f-4440-bd1f-f9a9a294aab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037704838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1037704838
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3679437526
Short name T989
Test name
Test status
Simulation time 35743618404 ps
CPU time 296.39 seconds
Started Aug 01 06:47:05 PM PDT 24
Finished Aug 01 06:52:02 PM PDT 24
Peak memory 265348 kb
Host smart-e525bfc3-8a1e-4b89-bc2b-9e45360b4035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679437526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3679437526
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3871149002
Short name T338
Test name
Test status
Simulation time 2036623383 ps
CPU time 6.85 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:09 PM PDT 24
Peak memory 224924 kb
Host smart-539382be-0d3c-4932-a9e3-74c3e096e1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871149002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3871149002
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.561275007
Short name T736
Test name
Test status
Simulation time 17124764828 ps
CPU time 62.58 seconds
Started Aug 01 06:46:59 PM PDT 24
Finished Aug 01 06:48:02 PM PDT 24
Peak memory 254688 kb
Host smart-295e8b26-9d21-41ab-b83a-2865e6277d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561275007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.561275007
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.282227136
Short name T647
Test name
Test status
Simulation time 624258602 ps
CPU time 2.37 seconds
Started Aug 01 06:47:03 PM PDT 24
Finished Aug 01 06:47:06 PM PDT 24
Peak memory 223396 kb
Host smart-63f56357-7570-4434-9e67-80d3c68ddfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282227136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.282227136
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3138667634
Short name T389
Test name
Test status
Simulation time 5266821499 ps
CPU time 58.49 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:48:01 PM PDT 24
Peak memory 241280 kb
Host smart-70b79c54-23f1-491b-b04f-e32904200d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138667634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3138667634
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3311244401
Short name T872
Test name
Test status
Simulation time 2699797682 ps
CPU time 12.25 seconds
Started Aug 01 06:47:01 PM PDT 24
Finished Aug 01 06:47:14 PM PDT 24
Peak memory 233084 kb
Host smart-700607dc-be5e-45ba-ace4-3551361cda12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311244401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3311244401
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3927361673
Short name T912
Test name
Test status
Simulation time 611368214 ps
CPU time 4.7 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:05 PM PDT 24
Peak memory 233064 kb
Host smart-71b80732-3897-485c-a9db-dbed2069109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927361673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3927361673
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1783613086
Short name T377
Test name
Test status
Simulation time 6906027054 ps
CPU time 15.2 seconds
Started Aug 01 06:46:59 PM PDT 24
Finished Aug 01 06:47:15 PM PDT 24
Peak memory 219488 kb
Host smart-6b494565-69b0-44f7-af53-1a778a3cae7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1783613086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1783613086
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3574557585
Short name T986
Test name
Test status
Simulation time 4884527172 ps
CPU time 33.27 seconds
Started Aug 01 06:47:03 PM PDT 24
Finished Aug 01 06:47:36 PM PDT 24
Peak memory 216640 kb
Host smart-59d0240d-4b92-4fed-84f7-8c22d24d9154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574557585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3574557585
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1421713008
Short name T422
Test name
Test status
Simulation time 10700204853 ps
CPU time 17.51 seconds
Started Aug 01 06:47:01 PM PDT 24
Finished Aug 01 06:47:19 PM PDT 24
Peak memory 216620 kb
Host smart-60df4c5e-1fdf-4060-af77-8c26719a6e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421713008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1421713008
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1752241428
Short name T492
Test name
Test status
Simulation time 94113762 ps
CPU time 1.76 seconds
Started Aug 01 06:47:00 PM PDT 24
Finished Aug 01 06:47:02 PM PDT 24
Peak memory 216568 kb
Host smart-1cb8fffc-bac0-488b-b7df-21a089219b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752241428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1752241428
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.485226218
Short name T676
Test name
Test status
Simulation time 16445631 ps
CPU time 0.74 seconds
Started Aug 01 06:47:01 PM PDT 24
Finished Aug 01 06:47:02 PM PDT 24
Peak memory 206340 kb
Host smart-ab801bad-e68d-48c3-bd99-63edccca22ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485226218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.485226218
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1766524430
Short name T654
Test name
Test status
Simulation time 205477021 ps
CPU time 2.81 seconds
Started Aug 01 06:47:03 PM PDT 24
Finished Aug 01 06:47:06 PM PDT 24
Peak memory 233140 kb
Host smart-0e6f7833-8637-4130-ac1b-b6a3c1a786a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766524430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1766524430
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3909951719
Short name T776
Test name
Test status
Simulation time 41182798 ps
CPU time 0.71 seconds
Started Aug 01 06:47:15 PM PDT 24
Finished Aug 01 06:47:16 PM PDT 24
Peak memory 205784 kb
Host smart-2e225f0f-55b5-42e8-84a1-07198932160f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909951719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3909951719
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4069929986
Short name T521
Test name
Test status
Simulation time 953219460 ps
CPU time 9.86 seconds
Started Aug 01 06:47:13 PM PDT 24
Finished Aug 01 06:47:23 PM PDT 24
Peak memory 233032 kb
Host smart-a9911fc0-18a7-46af-843f-e8cc16d573e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069929986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4069929986
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1150546514
Short name T778
Test name
Test status
Simulation time 25008076 ps
CPU time 0.82 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:03 PM PDT 24
Peak memory 207292 kb
Host smart-29a06f5d-a933-4d10-a81a-02f10d6527c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150546514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1150546514
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.4275379279
Short name T546
Test name
Test status
Simulation time 2759876148 ps
CPU time 55.97 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:48:11 PM PDT 24
Peak memory 256048 kb
Host smart-c230bc64-8750-4a62-9699-4ba6cd33330b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275379279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4275379279
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.684088594
Short name T573
Test name
Test status
Simulation time 18527501761 ps
CPU time 25.53 seconds
Started Aug 01 06:47:15 PM PDT 24
Finished Aug 01 06:47:41 PM PDT 24
Peak memory 218036 kb
Host smart-5a6963b2-42b1-4b1b-8e49-c99a9663c912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684088594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.684088594
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1110730878
Short name T631
Test name
Test status
Simulation time 58986710790 ps
CPU time 255.49 seconds
Started Aug 01 06:47:13 PM PDT 24
Finished Aug 01 06:51:29 PM PDT 24
Peak memory 249688 kb
Host smart-ae9928b5-b824-4647-aee1-68ae5399ab58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110730878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1110730878
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.298937533
Short name T1007
Test name
Test status
Simulation time 101539782 ps
CPU time 3.54 seconds
Started Aug 01 06:47:11 PM PDT 24
Finished Aug 01 06:47:15 PM PDT 24
Peak memory 224928 kb
Host smart-b786fe2e-f89e-4a69-b458-da89346c998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298937533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.298937533
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1891507868
Short name T439
Test name
Test status
Simulation time 2650489153 ps
CPU time 14.57 seconds
Started Aug 01 06:47:17 PM PDT 24
Finished Aug 01 06:47:32 PM PDT 24
Peak memory 233156 kb
Host smart-b052729c-0532-4d61-8c7f-ce8593030f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891507868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1891507868
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.748252441
Short name T98
Test name
Test status
Simulation time 43169953124 ps
CPU time 106.67 seconds
Started Aug 01 06:47:13 PM PDT 24
Finished Aug 01 06:49:00 PM PDT 24
Peak memory 241044 kb
Host smart-2f2cde65-2d33-47aa-b92d-426892b390a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748252441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.748252441
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3697915071
Short name T395
Test name
Test status
Simulation time 5302163552 ps
CPU time 6.54 seconds
Started Aug 01 06:47:12 PM PDT 24
Finished Aug 01 06:47:18 PM PDT 24
Peak memory 241360 kb
Host smart-913053ee-13be-409a-ae24-d8afdab335e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697915071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3697915071
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1447504014
Short name T308
Test name
Test status
Simulation time 163438675 ps
CPU time 3.24 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:17 PM PDT 24
Peak memory 232552 kb
Host smart-313da0c1-e588-4162-b86f-d724f42b418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447504014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1447504014
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1656103605
Short name T435
Test name
Test status
Simulation time 152660917 ps
CPU time 4.62 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:18 PM PDT 24
Peak memory 223036 kb
Host smart-ace53e37-334f-4982-ab7b-11d741130fcb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1656103605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1656103605
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2020524729
Short name T786
Test name
Test status
Simulation time 15424984571 ps
CPU time 9.42 seconds
Started Aug 01 06:47:16 PM PDT 24
Finished Aug 01 06:47:25 PM PDT 24
Peak memory 216908 kb
Host smart-b4b04733-f562-4068-b0c2-ad233b934851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020524729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2020524729
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1207688866
Short name T330
Test name
Test status
Simulation time 6440401490 ps
CPU time 17.89 seconds
Started Aug 01 06:47:02 PM PDT 24
Finished Aug 01 06:47:20 PM PDT 24
Peak memory 216700 kb
Host smart-81a665bf-c48a-4e3e-8818-f68a89b80713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207688866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1207688866
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.323157398
Short name T433
Test name
Test status
Simulation time 31339169 ps
CPU time 0.92 seconds
Started Aug 01 06:47:13 PM PDT 24
Finished Aug 01 06:47:14 PM PDT 24
Peak memory 207616 kb
Host smart-8ddd0e1d-f2a1-4a77-bca7-d204d99aa708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323157398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.323157398
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.949117374
Short name T531
Test name
Test status
Simulation time 41833104 ps
CPU time 0.78 seconds
Started Aug 01 06:47:16 PM PDT 24
Finished Aug 01 06:47:17 PM PDT 24
Peak memory 206376 kb
Host smart-a9b5fe61-433c-4411-a481-63d742fe870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949117374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.949117374
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1861881747
Short name T662
Test name
Test status
Simulation time 9586872770 ps
CPU time 14.12 seconds
Started Aug 01 06:47:18 PM PDT 24
Finished Aug 01 06:47:32 PM PDT 24
Peak memory 233176 kb
Host smart-0e439be4-1e70-4cc6-9bdd-c49419a802e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861881747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1861881747
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1739222176
Short name T953
Test name
Test status
Simulation time 138252444 ps
CPU time 0.75 seconds
Started Aug 01 06:47:16 PM PDT 24
Finished Aug 01 06:47:18 PM PDT 24
Peak memory 205088 kb
Host smart-613c2b6c-54b1-4200-87e4-325d6abacc17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739222176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1739222176
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4248725713
Short name T8
Test name
Test status
Simulation time 9943847222 ps
CPU time 23.56 seconds
Started Aug 01 06:47:16 PM PDT 24
Finished Aug 01 06:47:40 PM PDT 24
Peak memory 233104 kb
Host smart-a2107058-fd83-4547-b5fb-f032101f7fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248725713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4248725713
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3712774409
Short name T741
Test name
Test status
Simulation time 24907135 ps
CPU time 0.8 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:15 PM PDT 24
Peak memory 205900 kb
Host smart-86985149-751e-4f79-84c7-92322aed9639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712774409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3712774409
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1787316550
Short name T174
Test name
Test status
Simulation time 1777491743 ps
CPU time 23.39 seconds
Started Aug 01 06:47:15 PM PDT 24
Finished Aug 01 06:47:39 PM PDT 24
Peak memory 252876 kb
Host smart-70ffa6f7-1a1b-4a05-b274-42cb161e7d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787316550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1787316550
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3070296412
Short name T575
Test name
Test status
Simulation time 2085873300 ps
CPU time 16.09 seconds
Started Aug 01 06:47:16 PM PDT 24
Finished Aug 01 06:47:33 PM PDT 24
Peak memory 233960 kb
Host smart-037393c8-d7f0-4011-8b28-f1bf610acd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070296412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3070296412
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4000053768
Short name T721
Test name
Test status
Simulation time 13758490868 ps
CPU time 41.81 seconds
Started Aug 01 06:47:18 PM PDT 24
Finished Aug 01 06:48:00 PM PDT 24
Peak memory 249568 kb
Host smart-4398a57b-a8bf-438f-8652-9d44bc42365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000053768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4000053768
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3631087072
Short name T522
Test name
Test status
Simulation time 1539612681 ps
CPU time 14.66 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:29 PM PDT 24
Peak memory 235420 kb
Host smart-d554a868-9c6d-4b0f-8a38-bf24376dee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631087072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3631087072
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3056421775
Short name T886
Test name
Test status
Simulation time 94544452832 ps
CPU time 161.41 seconds
Started Aug 01 06:47:15 PM PDT 24
Finished Aug 01 06:49:57 PM PDT 24
Peak memory 249512 kb
Host smart-7be4a564-4d26-4ca3-8b22-61e31aafa0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056421775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3056421775
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3714451588
Short name T199
Test name
Test status
Simulation time 435412207 ps
CPU time 4.31 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:19 PM PDT 24
Peak memory 224916 kb
Host smart-5a34aef7-83a8-41cc-8210-e3bf1e8f6c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714451588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3714451588
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2341983993
Short name T633
Test name
Test status
Simulation time 132809833 ps
CPU time 2.32 seconds
Started Aug 01 06:47:17 PM PDT 24
Finished Aug 01 06:47:20 PM PDT 24
Peak memory 232780 kb
Host smart-ed4a1273-0cf5-4124-a0ba-777b3c2ca840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341983993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2341983993
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2619072268
Short name T837
Test name
Test status
Simulation time 5831474748 ps
CPU time 11.6 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:26 PM PDT 24
Peak memory 241348 kb
Host smart-176a7a7b-b6b2-4609-b34b-d4a17dc42121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619072268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2619072268
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4215715280
Short name T938
Test name
Test status
Simulation time 1065062980 ps
CPU time 7.6 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:22 PM PDT 24
Peak memory 241252 kb
Host smart-8854ab39-a371-41a1-8fc4-1525982af151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215715280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4215715280
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4096432848
Short name T392
Test name
Test status
Simulation time 4499902959 ps
CPU time 9.57 seconds
Started Aug 01 06:47:18 PM PDT 24
Finished Aug 01 06:47:28 PM PDT 24
Peak memory 223620 kb
Host smart-d614d611-d59d-4633-babc-91b697a9a0b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4096432848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4096432848
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2218718638
Short name T1013
Test name
Test status
Simulation time 70151300919 ps
CPU time 257.31 seconds
Started Aug 01 06:47:20 PM PDT 24
Finished Aug 01 06:51:38 PM PDT 24
Peak memory 254140 kb
Host smart-a178c2e7-ee0d-4d8d-9d42-f53f683c60cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218718638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2218718638
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2465855429
Short name T28
Test name
Test status
Simulation time 2483313498 ps
CPU time 12.5 seconds
Started Aug 01 06:47:12 PM PDT 24
Finished Aug 01 06:47:24 PM PDT 24
Peak memory 219876 kb
Host smart-1f989025-1254-45b5-925c-4883ad02eae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465855429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2465855429
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3735358945
Short name T766
Test name
Test status
Simulation time 1087575935 ps
CPU time 5.12 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:19 PM PDT 24
Peak memory 216676 kb
Host smart-80c6064e-4939-4361-861d-f75c9873ac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735358945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3735358945
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3898554908
Short name T936
Test name
Test status
Simulation time 208558600 ps
CPU time 2 seconds
Started Aug 01 06:47:15 PM PDT 24
Finished Aug 01 06:47:17 PM PDT 24
Peak memory 216628 kb
Host smart-ab9dc6a4-3356-4687-ba81-24b0e8dd3875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898554908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3898554908
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.314367882
Short name T723
Test name
Test status
Simulation time 16192650 ps
CPU time 0.74 seconds
Started Aug 01 06:47:17 PM PDT 24
Finished Aug 01 06:47:18 PM PDT 24
Peak memory 206300 kb
Host smart-7f369e1e-867e-4dab-9104-6b2326ad5f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314367882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.314367882
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1654194847
Short name T625
Test name
Test status
Simulation time 874420042 ps
CPU time 3.79 seconds
Started Aug 01 06:47:15 PM PDT 24
Finished Aug 01 06:47:19 PM PDT 24
Peak memory 224888 kb
Host smart-0dee1a15-c764-4f15-ad70-23a820bfee41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654194847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1654194847
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.551101735
Short name T839
Test name
Test status
Simulation time 65050704 ps
CPU time 0.73 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:15 PM PDT 24
Peak memory 206132 kb
Host smart-07aa67fb-9b96-4471-ba48-034d5e821e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551101735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.551101735
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2565465399
Short name T77
Test name
Test status
Simulation time 2013567376 ps
CPU time 6.23 seconds
Started Aug 01 06:47:13 PM PDT 24
Finished Aug 01 06:47:19 PM PDT 24
Peak memory 224828 kb
Host smart-f2eeacbb-dea6-4e33-a272-c8f9869be918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565465399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2565465399
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1194436979
Short name T829
Test name
Test status
Simulation time 34887908 ps
CPU time 0.75 seconds
Started Aug 01 06:47:15 PM PDT 24
Finished Aug 01 06:47:16 PM PDT 24
Peak memory 206952 kb
Host smart-df742888-86e0-4e6d-ad8d-5bb1b311fe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194436979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1194436979
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3414569943
Short name T169
Test name
Test status
Simulation time 84951656807 ps
CPU time 308.19 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:52:23 PM PDT 24
Peak memory 253584 kb
Host smart-9828e1d0-34e2-44d2-a4f5-6e64243f8031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414569943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3414569943
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2126465056
Short name T963
Test name
Test status
Simulation time 37286436419 ps
CPU time 107.37 seconds
Started Aug 01 06:47:23 PM PDT 24
Finished Aug 01 06:49:11 PM PDT 24
Peak memory 249596 kb
Host smart-ffcd803d-7cf3-45e3-9793-13f6b438cfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126465056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2126465056
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.202928821
Short name T526
Test name
Test status
Simulation time 5325406130 ps
CPU time 34.87 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:49 PM PDT 24
Peak memory 252112 kb
Host smart-68d88382-c72e-4e32-a2e8-13b0b6f2a7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202928821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.202928821
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3140036162
Short name T7
Test name
Test status
Simulation time 699199078 ps
CPU time 8.37 seconds
Started Aug 01 06:47:16 PM PDT 24
Finished Aug 01 06:47:24 PM PDT 24
Peak memory 252980 kb
Host smart-5c10b61e-c2a1-4491-af89-61d52cc3ffdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140036162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3140036162
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.745319649
Short name T578
Test name
Test status
Simulation time 80577202396 ps
CPU time 89.91 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:48:44 PM PDT 24
Peak memory 253416 kb
Host smart-458ddad4-213c-43df-ba09-461b78012ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745319649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.745319649
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.355100015
Short name T561
Test name
Test status
Simulation time 347570215 ps
CPU time 3.79 seconds
Started Aug 01 06:47:13 PM PDT 24
Finished Aug 01 06:47:17 PM PDT 24
Peak memory 224884 kb
Host smart-e0adf245-2658-4acc-a739-a73f2f769cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355100015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.355100015
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.158673024
Short name T678
Test name
Test status
Simulation time 823307628 ps
CPU time 9.26 seconds
Started Aug 01 06:47:18 PM PDT 24
Finished Aug 01 06:47:27 PM PDT 24
Peak memory 241028 kb
Host smart-02e1a26c-284f-4ec2-b839-669e6a4bc072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158673024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.158673024
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1049351751
Short name T760
Test name
Test status
Simulation time 762692017 ps
CPU time 11.91 seconds
Started Aug 01 06:47:16 PM PDT 24
Finished Aug 01 06:47:29 PM PDT 24
Peak memory 249924 kb
Host smart-38882786-d6be-46f0-a480-a92c8d7e52be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049351751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1049351751
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2180390228
Short name T216
Test name
Test status
Simulation time 755982552 ps
CPU time 5.12 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:19 PM PDT 24
Peak memory 233132 kb
Host smart-0c14762a-e9da-47e8-84c1-a6985b0b0119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180390228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2180390228
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3307889796
Short name T540
Test name
Test status
Simulation time 237529183 ps
CPU time 4.34 seconds
Started Aug 01 06:47:13 PM PDT 24
Finished Aug 01 06:47:18 PM PDT 24
Peak memory 220908 kb
Host smart-9cec42eb-777b-4d3b-990b-82386e9ba9b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3307889796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3307889796
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.859765683
Short name T14
Test name
Test status
Simulation time 15617097502 ps
CPU time 62.85 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:48:17 PM PDT 24
Peak memory 254912 kb
Host smart-899c146e-b8dd-4a73-98c0-e90661a16fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859765683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.859765683
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2122757813
Short name T845
Test name
Test status
Simulation time 1318579618 ps
CPU time 7.56 seconds
Started Aug 01 06:47:17 PM PDT 24
Finished Aug 01 06:47:24 PM PDT 24
Peak memory 216564 kb
Host smart-ed282d5e-8d66-43d6-8d18-3398d64f0a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122757813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2122757813
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3207258641
Short name T493
Test name
Test status
Simulation time 12249637664 ps
CPU time 7.74 seconds
Started Aug 01 06:47:13 PM PDT 24
Finished Aug 01 06:47:21 PM PDT 24
Peak memory 216756 kb
Host smart-e294aa10-dd2a-4b46-ad53-79b2a3be6eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207258641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3207258641
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.932531137
Short name T974
Test name
Test status
Simulation time 150403686 ps
CPU time 3.38 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:18 PM PDT 24
Peak memory 216564 kb
Host smart-6ba21461-4e76-4a3f-b0ed-c23e2a99942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932531137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.932531137
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3780487412
Short name T614
Test name
Test status
Simulation time 43327193 ps
CPU time 0.82 seconds
Started Aug 01 06:47:16 PM PDT 24
Finished Aug 01 06:47:17 PM PDT 24
Peak memory 206308 kb
Host smart-9e8d698c-50eb-450f-9385-e4a23105c9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780487412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3780487412
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3440904329
Short name T193
Test name
Test status
Simulation time 830709571 ps
CPU time 5.3 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:19 PM PDT 24
Peak memory 233100 kb
Host smart-ffa2907a-0658-4272-aa45-1ba6a4ec9255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440904329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3440904329
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3808597549
Short name T402
Test name
Test status
Simulation time 12985641 ps
CPU time 0.76 seconds
Started Aug 01 06:47:27 PM PDT 24
Finished Aug 01 06:47:28 PM PDT 24
Peak memory 206156 kb
Host smart-acc7530f-367b-4296-9a61-d02b98d1c251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808597549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3808597549
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4081273546
Short name T366
Test name
Test status
Simulation time 3657417149 ps
CPU time 10.9 seconds
Started Aug 01 06:47:28 PM PDT 24
Finished Aug 01 06:47:39 PM PDT 24
Peak memory 224964 kb
Host smart-0b626438-1648-4874-af36-503d57572ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081273546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4081273546
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3721579439
Short name T22
Test name
Test status
Simulation time 13448230 ps
CPU time 0.8 seconds
Started Aug 01 06:47:17 PM PDT 24
Finished Aug 01 06:47:18 PM PDT 24
Peak memory 206944 kb
Host smart-7768a725-582e-4f34-9b4f-77f8f8fff369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721579439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3721579439
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4096977311
Short name T751
Test name
Test status
Simulation time 1434184945 ps
CPU time 15.32 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:45 PM PDT 24
Peak memory 249568 kb
Host smart-c77a51db-e6d2-42e6-abf3-c0d2f19243ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096977311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4096977311
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1649487028
Short name T448
Test name
Test status
Simulation time 3270471759 ps
CPU time 36.12 seconds
Started Aug 01 06:47:25 PM PDT 24
Finished Aug 01 06:48:01 PM PDT 24
Peak memory 249624 kb
Host smart-1b5e653b-4f08-4938-8409-3db9a39b5153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649487028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1649487028
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3765444510
Short name T744
Test name
Test status
Simulation time 13651399458 ps
CPU time 138.11 seconds
Started Aug 01 06:47:26 PM PDT 24
Finished Aug 01 06:49:44 PM PDT 24
Peak memory 249624 kb
Host smart-c7994286-1911-48be-8534-b8d68b898838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765444510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3765444510
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3831173716
Short name T450
Test name
Test status
Simulation time 649801507 ps
CPU time 11.05 seconds
Started Aug 01 06:47:25 PM PDT 24
Finished Aug 01 06:47:36 PM PDT 24
Peak memory 224888 kb
Host smart-9f457a69-641f-46c6-9b7e-cd388103c7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831173716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3831173716
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1454906740
Short name T386
Test name
Test status
Simulation time 1977838626 ps
CPU time 18.28 seconds
Started Aug 01 06:47:24 PM PDT 24
Finished Aug 01 06:47:43 PM PDT 24
Peak memory 236972 kb
Host smart-911adcbc-9434-42fa-8c3d-8f1210e21062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454906740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1454906740
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2724759926
Short name T552
Test name
Test status
Simulation time 14385734587 ps
CPU time 22.68 seconds
Started Aug 01 06:47:14 PM PDT 24
Finished Aug 01 06:47:37 PM PDT 24
Peak memory 224996 kb
Host smart-fa745d70-458b-47f9-954b-6ae3dd5a2a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724759926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2724759926
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4111677767
Short name T716
Test name
Test status
Simulation time 58915964 ps
CPU time 2.12 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:32 PM PDT 24
Peak memory 224960 kb
Host smart-d27fdec1-43da-4ea8-aa84-68e392e43f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111677767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4111677767
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2545507833
Short name T547
Test name
Test status
Simulation time 303517419 ps
CPU time 2.48 seconds
Started Aug 01 06:47:19 PM PDT 24
Finished Aug 01 06:47:21 PM PDT 24
Peak memory 224760 kb
Host smart-1da454cd-abaf-40ba-a1fa-ec6df1de08d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545507833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2545507833
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1071847912
Short name T742
Test name
Test status
Simulation time 177613850 ps
CPU time 2.89 seconds
Started Aug 01 06:47:16 PM PDT 24
Finished Aug 01 06:47:19 PM PDT 24
Peak memory 233128 kb
Host smart-bc6bfc5f-1cac-490e-aab6-13669766161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071847912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1071847912
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.358752366
Short name T423
Test name
Test status
Simulation time 199382424 ps
CPU time 4.64 seconds
Started Aug 01 06:47:28 PM PDT 24
Finished Aug 01 06:47:32 PM PDT 24
Peak memory 219996 kb
Host smart-a8ce4e90-9839-486c-addf-cfcddfb1328d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=358752366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.358752366
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1886324624
Short name T340
Test name
Test status
Simulation time 6253061333 ps
CPU time 9.46 seconds
Started Aug 01 06:47:17 PM PDT 24
Finished Aug 01 06:47:27 PM PDT 24
Peak memory 216652 kb
Host smart-462c9b63-5178-4a89-8ae8-178d3442ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886324624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1886324624
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3579789522
Short name T354
Test name
Test status
Simulation time 284849096 ps
CPU time 1.85 seconds
Started Aug 01 06:47:19 PM PDT 24
Finished Aug 01 06:47:21 PM PDT 24
Peak memory 208212 kb
Host smart-4f8ce099-74fe-4f57-b8c7-a47cec140182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579789522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3579789522
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3431208905
Short name T440
Test name
Test status
Simulation time 551557250 ps
CPU time 2.17 seconds
Started Aug 01 06:47:16 PM PDT 24
Finished Aug 01 06:47:18 PM PDT 24
Peak memory 216660 kb
Host smart-7ae96d88-a603-4088-b12d-ebe1b6b894ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431208905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3431208905
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2306526544
Short name T621
Test name
Test status
Simulation time 66481634 ps
CPU time 0.86 seconds
Started Aug 01 06:47:17 PM PDT 24
Finished Aug 01 06:47:18 PM PDT 24
Peak memory 206276 kb
Host smart-b47f3de8-bb07-487a-96c1-9d31a617a43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306526544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2306526544
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.148932229
Short name T915
Test name
Test status
Simulation time 99313991 ps
CPU time 2.51 seconds
Started Aug 01 06:47:25 PM PDT 24
Finished Aug 01 06:47:28 PM PDT 24
Peak memory 232812 kb
Host smart-e0f077dc-8774-419e-9247-2dca82724fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148932229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.148932229
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2755877188
Short name T797
Test name
Test status
Simulation time 46640323 ps
CPU time 0.76 seconds
Started Aug 01 06:47:27 PM PDT 24
Finished Aug 01 06:47:28 PM PDT 24
Peak memory 205804 kb
Host smart-8e75d636-647f-4213-9da1-750d62bc96c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755877188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2755877188
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3547469568
Short name T823
Test name
Test status
Simulation time 44994291 ps
CPU time 2.22 seconds
Started Aug 01 06:47:26 PM PDT 24
Finished Aug 01 06:47:28 PM PDT 24
Peak memory 224832 kb
Host smart-2c4c0381-4109-406d-b20c-59f5b940e1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547469568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3547469568
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2290987636
Short name T697
Test name
Test status
Simulation time 57838597 ps
CPU time 0.74 seconds
Started Aug 01 06:47:27 PM PDT 24
Finished Aug 01 06:47:28 PM PDT 24
Peak memory 207228 kb
Host smart-1569b93e-a20b-4da5-bb54-9455c2db1871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290987636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2290987636
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2046562563
Short name T170
Test name
Test status
Simulation time 12053837362 ps
CPU time 72.09 seconds
Started Aug 01 06:47:25 PM PDT 24
Finished Aug 01 06:48:38 PM PDT 24
Peak memory 270716 kb
Host smart-643a03bb-40e6-4ada-a908-adab64f38d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046562563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2046562563
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3951851146
Short name T799
Test name
Test status
Simulation time 3825248271 ps
CPU time 25.27 seconds
Started Aug 01 06:47:26 PM PDT 24
Finished Aug 01 06:47:51 PM PDT 24
Peak memory 234944 kb
Host smart-fa21b0fb-a461-4680-b847-45ae822e51a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951851146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3951851146
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1886169856
Short name T34
Test name
Test status
Simulation time 419235953397 ps
CPU time 395.41 seconds
Started Aug 01 06:47:27 PM PDT 24
Finished Aug 01 06:54:03 PM PDT 24
Peak memory 271396 kb
Host smart-0ee76e61-f489-4275-bad7-1272d7dfc4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886169856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1886169856
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.162389127
Short name T467
Test name
Test status
Simulation time 647082040 ps
CPU time 5.68 seconds
Started Aug 01 06:47:28 PM PDT 24
Finished Aug 01 06:47:34 PM PDT 24
Peak memory 225164 kb
Host smart-a93a66eb-163b-455b-a9b8-1accbcfb9188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162389127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.162389127
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3133372361
Short name T644
Test name
Test status
Simulation time 6605051787 ps
CPU time 46.12 seconds
Started Aug 01 06:47:28 PM PDT 24
Finished Aug 01 06:48:14 PM PDT 24
Peak memory 256752 kb
Host smart-f1dec935-590e-46a8-a602-36762be0bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133372361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3133372361
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.154390263
Short name T961
Test name
Test status
Simulation time 1393183297 ps
CPU time 7.05 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:37 PM PDT 24
Peak memory 233136 kb
Host smart-bbdf8cbe-4813-43c2-a157-1cd5ef0fb60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154390263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.154390263
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2891315859
Short name T379
Test name
Test status
Simulation time 758459399 ps
CPU time 11.49 seconds
Started Aug 01 06:47:27 PM PDT 24
Finished Aug 01 06:47:39 PM PDT 24
Peak memory 233096 kb
Host smart-21691a2c-5d4a-4196-9ded-0abc086d2d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891315859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2891315859
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1175166543
Short name T355
Test name
Test status
Simulation time 3489419464 ps
CPU time 12.52 seconds
Started Aug 01 06:47:26 PM PDT 24
Finished Aug 01 06:47:38 PM PDT 24
Peak memory 232248 kb
Host smart-453b57d9-d1f2-407b-83e2-ffcc1a618197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175166543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1175166543
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.188924069
Short name T230
Test name
Test status
Simulation time 541788410 ps
CPU time 3.08 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:32 PM PDT 24
Peak memory 233160 kb
Host smart-89ac8171-6cfd-4f4c-ac7c-7eae308dab6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188924069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.188924069
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1981626327
Short name T732
Test name
Test status
Simulation time 1275756944 ps
CPU time 11.99 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:41 PM PDT 24
Peak memory 222088 kb
Host smart-c05f15f2-82e1-4b76-82d1-9953df1f7acc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1981626327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1981626327
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1555720652
Short name T553
Test name
Test status
Simulation time 49970746 ps
CPU time 1 seconds
Started Aug 01 06:47:28 PM PDT 24
Finished Aug 01 06:47:29 PM PDT 24
Peak memory 207028 kb
Host smart-c2d60997-0d1a-4740-8dae-bc2e59f0800f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555720652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1555720652
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3456934713
Short name T326
Test name
Test status
Simulation time 1807632605 ps
CPU time 4.24 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:34 PM PDT 24
Peak memory 216980 kb
Host smart-4452c242-1550-41d3-a89b-fbf247845572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456934713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3456934713
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3003041570
Short name T420
Test name
Test status
Simulation time 3589449658 ps
CPU time 11 seconds
Started Aug 01 06:47:28 PM PDT 24
Finished Aug 01 06:47:39 PM PDT 24
Peak memory 216628 kb
Host smart-f1d8dcb6-8372-4b39-b44d-dc58612c8b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003041570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3003041570
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2327279410
Short name T659
Test name
Test status
Simulation time 58788164 ps
CPU time 1.32 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:31 PM PDT 24
Peak memory 216620 kb
Host smart-1cdecdb6-f822-4955-bf4d-e31c7aacef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327279410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2327279410
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.920183074
Short name T769
Test name
Test status
Simulation time 28032080 ps
CPU time 0.7 seconds
Started Aug 01 06:47:28 PM PDT 24
Finished Aug 01 06:47:29 PM PDT 24
Peak memory 205952 kb
Host smart-ef052c51-23b6-46cf-844f-2a667738e976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920183074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.920183074
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3615764888
Short name T999
Test name
Test status
Simulation time 1138101977 ps
CPU time 4.08 seconds
Started Aug 01 06:47:30 PM PDT 24
Finished Aug 01 06:47:34 PM PDT 24
Peak memory 233104 kb
Host smart-835890b3-d005-4955-8638-bfda788fe7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615764888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3615764888
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.130647591
Short name T838
Test name
Test status
Simulation time 54039073 ps
CPU time 0.73 seconds
Started Aug 01 06:47:27 PM PDT 24
Finished Aug 01 06:47:28 PM PDT 24
Peak memory 205204 kb
Host smart-eb0f9c8c-d8fb-4fff-80ce-9a908c562dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130647591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.130647591
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2598858616
Short name T791
Test name
Test status
Simulation time 3030129675 ps
CPU time 6.11 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:35 PM PDT 24
Peak memory 224972 kb
Host smart-ab5df860-5429-48f7-8069-e81522586ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598858616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2598858616
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2745336341
Short name T966
Test name
Test status
Simulation time 34734305 ps
CPU time 0.81 seconds
Started Aug 01 06:47:26 PM PDT 24
Finished Aug 01 06:47:27 PM PDT 24
Peak memory 206444 kb
Host smart-11c4716a-19c7-4c8d-94c7-24e5711d404a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745336341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2745336341
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1864043241
Short name T626
Test name
Test status
Simulation time 7124943194 ps
CPU time 56.92 seconds
Started Aug 01 06:47:28 PM PDT 24
Finished Aug 01 06:48:25 PM PDT 24
Peak memory 241612 kb
Host smart-d7558acf-27af-4922-9090-466ad0d7d893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864043241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1864043241
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2963872456
Short name T180
Test name
Test status
Simulation time 4589398805 ps
CPU time 27.11 seconds
Started Aug 01 06:47:30 PM PDT 24
Finished Aug 01 06:47:58 PM PDT 24
Peak memory 250616 kb
Host smart-05ff7606-6bf8-42c9-b829-9965bffd4752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963872456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2963872456
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.62048805
Short name T41
Test name
Test status
Simulation time 69175541475 ps
CPU time 214.04 seconds
Started Aug 01 06:47:25 PM PDT 24
Finished Aug 01 06:51:00 PM PDT 24
Peak memory 267068 kb
Host smart-cffbdf7c-d0b3-4e31-ac77-cda21b132c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62048805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.62048805
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3895810645
Short name T854
Test name
Test status
Simulation time 343422976 ps
CPU time 7.11 seconds
Started Aug 01 06:47:25 PM PDT 24
Finished Aug 01 06:47:32 PM PDT 24
Peak memory 233128 kb
Host smart-fc56db6e-33a5-496f-9b66-3861d08d363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895810645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3895810645
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2855950021
Short name T81
Test name
Test status
Simulation time 27799534192 ps
CPU time 24.76 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:54 PM PDT 24
Peak memory 249572 kb
Host smart-da8d1655-962f-41be-bf42-b11be76a1cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855950021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2855950021
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1935434378
Short name T476
Test name
Test status
Simulation time 748996582 ps
CPU time 6.69 seconds
Started Aug 01 06:47:26 PM PDT 24
Finished Aug 01 06:47:32 PM PDT 24
Peak memory 224808 kb
Host smart-1e225acb-a47e-43cd-b27e-a778eb3427b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935434378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1935434378
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3976532309
Short name T485
Test name
Test status
Simulation time 3343916411 ps
CPU time 11.43 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:40 PM PDT 24
Peak memory 241172 kb
Host smart-c36a303c-7824-4828-8afe-6e22fe6a4892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976532309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3976532309
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3160407261
Short name T229
Test name
Test status
Simulation time 11737446939 ps
CPU time 6.07 seconds
Started Aug 01 06:47:25 PM PDT 24
Finished Aug 01 06:47:31 PM PDT 24
Peak memory 240568 kb
Host smart-e7d0ba50-f429-4b74-909f-2b4adb225c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160407261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3160407261
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3352864385
Short name T892
Test name
Test status
Simulation time 2421794505 ps
CPU time 9.71 seconds
Started Aug 01 06:47:27 PM PDT 24
Finished Aug 01 06:47:37 PM PDT 24
Peak memory 234100 kb
Host smart-3d3c8261-14fb-4673-89a0-00559d0b82e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352864385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3352864385
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3924769615
Short name T36
Test name
Test status
Simulation time 3039509140 ps
CPU time 8.62 seconds
Started Aug 01 06:47:26 PM PDT 24
Finished Aug 01 06:47:35 PM PDT 24
Peak memory 223136 kb
Host smart-40d85a38-4108-439b-8762-dd6c72cd0b3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3924769615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3924769615
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3163315182
Short name T20
Test name
Test status
Simulation time 10786442366 ps
CPU time 72.98 seconds
Started Aug 01 06:47:26 PM PDT 24
Finished Aug 01 06:48:39 PM PDT 24
Peak memory 249684 kb
Host smart-e5a55584-8e8a-4c5a-8241-272f18aeb5fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163315182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3163315182
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1705294713
Short name T907
Test name
Test status
Simulation time 2321661790 ps
CPU time 11.63 seconds
Started Aug 01 06:47:30 PM PDT 24
Finished Aug 01 06:47:41 PM PDT 24
Peak memory 216664 kb
Host smart-722cef71-f96a-4300-bcee-b6a937bce9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705294713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1705294713
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1230142977
Short name T24
Test name
Test status
Simulation time 11634530140 ps
CPU time 16.84 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:46 PM PDT 24
Peak memory 216620 kb
Host smart-f8db5196-67a8-4ddb-a9b7-46a32a84274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230142977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1230142977
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3000563506
Short name T341
Test name
Test status
Simulation time 1008897444 ps
CPU time 3.04 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:33 PM PDT 24
Peak memory 216652 kb
Host smart-da34de6a-245e-48c9-a4ff-b56e1f7c9618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000563506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3000563506
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2013665163
Short name T9
Test name
Test status
Simulation time 177357146 ps
CPU time 0.99 seconds
Started Aug 01 06:47:25 PM PDT 24
Finished Aug 01 06:47:27 PM PDT 24
Peak memory 207424 kb
Host smart-7b69a08b-8b76-4251-9ff2-7a069574a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013665163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2013665163
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3532305918
Short name T739
Test name
Test status
Simulation time 4686207551 ps
CPU time 11.85 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:41 PM PDT 24
Peak memory 224912 kb
Host smart-73e87d2f-691b-4b99-9315-83e4d8641333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532305918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3532305918
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1813006518
Short name T768
Test name
Test status
Simulation time 24193976 ps
CPU time 0.72 seconds
Started Aug 01 06:47:36 PM PDT 24
Finished Aug 01 06:47:37 PM PDT 24
Peak memory 206224 kb
Host smart-d5e6dbc4-73ac-4733-ad68-132620ec8af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813006518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1813006518
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2306633372
Short name T228
Test name
Test status
Simulation time 2263291323 ps
CPU time 7.73 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:47:47 PM PDT 24
Peak memory 224896 kb
Host smart-d3c6f76a-edff-4c8d-a7d3-8c4edafc1536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306633372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2306633372
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2943765725
Short name T780
Test name
Test status
Simulation time 59949664 ps
CPU time 0.76 seconds
Started Aug 01 06:47:27 PM PDT 24
Finished Aug 01 06:47:28 PM PDT 24
Peak memory 205904 kb
Host smart-62081a9d-9d97-4ebb-b696-12f79eac4de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943765725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2943765725
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3797461749
Short name T818
Test name
Test status
Simulation time 14049225254 ps
CPU time 137.41 seconds
Started Aug 01 06:47:34 PM PDT 24
Finished Aug 01 06:49:52 PM PDT 24
Peak memory 263584 kb
Host smart-749c0f55-07a9-4818-a1a5-14ae15cb9772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797461749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3797461749
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.113976390
Short name T232
Test name
Test status
Simulation time 209010041883 ps
CPU time 517.59 seconds
Started Aug 01 06:47:40 PM PDT 24
Finished Aug 01 06:56:18 PM PDT 24
Peak memory 253676 kb
Host smart-28a6d377-0270-4885-81bb-6258a25686a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113976390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.113976390
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1309222741
Short name T31
Test name
Test status
Simulation time 203448224959 ps
CPU time 366.44 seconds
Started Aug 01 06:47:35 PM PDT 24
Finished Aug 01 06:53:42 PM PDT 24
Peak memory 257744 kb
Host smart-4f8221da-652f-441e-b34a-47d5ef840187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309222741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1309222741
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1833740815
Short name T928
Test name
Test status
Simulation time 333356949 ps
CPU time 3.02 seconds
Started Aug 01 06:47:37 PM PDT 24
Finished Aug 01 06:47:40 PM PDT 24
Peak memory 233104 kb
Host smart-21b0b18c-f168-4828-8d24-8c3f12173caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833740815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1833740815
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3036127247
Short name T982
Test name
Test status
Simulation time 27055234623 ps
CPU time 41.1 seconds
Started Aug 01 06:47:37 PM PDT 24
Finished Aug 01 06:48:18 PM PDT 24
Peak memory 252152 kb
Host smart-8e4ac7c5-79d2-476c-a20b-f44ef591966c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036127247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3036127247
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.144527217
Short name T465
Test name
Test status
Simulation time 5387367750 ps
CPU time 14.21 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:43 PM PDT 24
Peak memory 233176 kb
Host smart-9db7bc05-faa5-4c2c-8ff2-aaacccc02529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144527217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.144527217
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1452556395
Short name T408
Test name
Test status
Simulation time 429064267 ps
CPU time 9.74 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:39 PM PDT 24
Peak memory 233124 kb
Host smart-e64edb30-9038-4b4f-a8b3-0047e8d46371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452556395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1452556395
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3762632934
Short name T241
Test name
Test status
Simulation time 65015716887 ps
CPU time 41.22 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:48:10 PM PDT 24
Peak memory 252164 kb
Host smart-a305084f-4843-4e19-83a5-9e14763980e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762632934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3762632934
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1696377468
Short name T820
Test name
Test status
Simulation time 5272034918 ps
CPU time 17.12 seconds
Started Aug 01 06:47:29 PM PDT 24
Finished Aug 01 06:47:46 PM PDT 24
Peak memory 240144 kb
Host smart-969ffaef-c643-4e9f-8c27-c2c0da013a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696377468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1696377468
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2945218289
Short name T122
Test name
Test status
Simulation time 671571895 ps
CPU time 6.3 seconds
Started Aug 01 06:47:40 PM PDT 24
Finished Aug 01 06:47:46 PM PDT 24
Peak memory 223604 kb
Host smart-b806f37b-fd3d-441e-a962-78332fab83d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2945218289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2945218289
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3137307282
Short name T43
Test name
Test status
Simulation time 25847288295 ps
CPU time 260.24 seconds
Started Aug 01 06:47:36 PM PDT 24
Finished Aug 01 06:51:57 PM PDT 24
Peak memory 249692 kb
Host smart-ddbeb70f-f1c0-4d5d-b6f8-57dcea8fbdb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137307282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3137307282
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3375936096
Short name T270
Test name
Test status
Simulation time 1367306906 ps
CPU time 13.58 seconds
Started Aug 01 06:47:28 PM PDT 24
Finished Aug 01 06:47:42 PM PDT 24
Peak memory 216740 kb
Host smart-9af9e33d-b177-4e8e-b25a-9841271ae6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375936096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3375936096
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1734562065
Short name T399
Test name
Test status
Simulation time 1195281417 ps
CPU time 4.03 seconds
Started Aug 01 06:47:27 PM PDT 24
Finished Aug 01 06:47:31 PM PDT 24
Peak memory 216680 kb
Host smart-1130dac0-b1d2-4a72-b8e1-7379ce4df610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734562065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1734562065
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3522077413
Short name T853
Test name
Test status
Simulation time 979025661 ps
CPU time 2.94 seconds
Started Aug 01 06:47:27 PM PDT 24
Finished Aug 01 06:47:30 PM PDT 24
Peak memory 216552 kb
Host smart-8246d73c-84a5-4f3a-89ae-cddc5465169b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522077413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3522077413
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2283655275
Short name T998
Test name
Test status
Simulation time 90952529 ps
CPU time 0.83 seconds
Started Aug 01 06:47:30 PM PDT 24
Finished Aug 01 06:47:31 PM PDT 24
Peak memory 206292 kb
Host smart-db8355f7-00d0-4501-a9d4-e9853147ec7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283655275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2283655275
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.899448535
Short name T488
Test name
Test status
Simulation time 1276551692 ps
CPU time 7.6 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:47:47 PM PDT 24
Peak memory 232964 kb
Host smart-635ae078-5a05-4d90-93ad-22dd8ee1d374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899448535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.899448535
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1365238264
Short name T292
Test name
Test status
Simulation time 14657214 ps
CPU time 0.73 seconds
Started Aug 01 06:47:38 PM PDT 24
Finished Aug 01 06:47:38 PM PDT 24
Peak memory 205808 kb
Host smart-d8f7705c-3fa1-44b8-ab37-91d497d09a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365238264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1365238264
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.719153412
Short name T646
Test name
Test status
Simulation time 207516194 ps
CPU time 4.72 seconds
Started Aug 01 06:47:35 PM PDT 24
Finished Aug 01 06:47:39 PM PDT 24
Peak memory 233072 kb
Host smart-da47abdb-89a3-453f-a78c-cdde55a2a59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719153412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.719153412
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1842782216
Short name T329
Test name
Test status
Simulation time 51403577 ps
CPU time 0.79 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:47:40 PM PDT 24
Peak memory 207296 kb
Host smart-23d53978-43cd-41ea-aa3b-ae49f6341c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842782216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1842782216
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4061888457
Short name T172
Test name
Test status
Simulation time 59272831254 ps
CPU time 40.16 seconds
Started Aug 01 06:47:36 PM PDT 24
Finished Aug 01 06:48:17 PM PDT 24
Peak memory 239140 kb
Host smart-f22d3a89-aa21-4629-a449-8afaec20509a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061888457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4061888457
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2369148600
Short name T272
Test name
Test status
Simulation time 421299414 ps
CPU time 6.89 seconds
Started Aug 01 06:47:36 PM PDT 24
Finished Aug 01 06:47:43 PM PDT 24
Peak memory 217780 kb
Host smart-c4aaaf25-a78e-4951-a6e5-7383c8467082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369148600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2369148600
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2509849791
Short name T757
Test name
Test status
Simulation time 2656168154 ps
CPU time 59.55 seconds
Started Aug 01 06:47:46 PM PDT 24
Finished Aug 01 06:48:45 PM PDT 24
Peak memory 265936 kb
Host smart-54a05ee6-bb55-4b6f-aa46-7a20d37c9b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509849791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2509849791
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3373939122
Short name T832
Test name
Test status
Simulation time 218155941 ps
CPU time 4.42 seconds
Started Aug 01 06:47:40 PM PDT 24
Finished Aug 01 06:47:45 PM PDT 24
Peak memory 224716 kb
Host smart-cdb7591a-7fd0-43bc-ba0c-bdc2502187ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373939122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3373939122
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.200490952
Short name T189
Test name
Test status
Simulation time 37162118633 ps
CPU time 59.91 seconds
Started Aug 01 06:47:36 PM PDT 24
Finished Aug 01 06:48:36 PM PDT 24
Peak memory 241356 kb
Host smart-2dc11c24-0837-4b64-84f9-a2ed6b46f6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200490952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.200490952
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2696863914
Short name T459
Test name
Test status
Simulation time 1498641323 ps
CPU time 6.68 seconds
Started Aug 01 06:47:35 PM PDT 24
Finished Aug 01 06:47:42 PM PDT 24
Peak memory 224928 kb
Host smart-4f186cd4-e32f-4545-8dd7-5170b9fcabb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696863914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2696863914
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3609485905
Short name T919
Test name
Test status
Simulation time 3133795746 ps
CPU time 50.64 seconds
Started Aug 01 06:47:35 PM PDT 24
Finished Aug 01 06:48:26 PM PDT 24
Peak memory 241412 kb
Host smart-84ad989b-8d6f-4db3-b3a6-bd9ce3bc7fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609485905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3609485905
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2093167094
Short name T895
Test name
Test status
Simulation time 5028050185 ps
CPU time 17.21 seconds
Started Aug 01 06:47:37 PM PDT 24
Finished Aug 01 06:47:54 PM PDT 24
Peak memory 240964 kb
Host smart-d74093f4-3921-401b-bcc8-c18bc5526a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093167094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2093167094
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1935893271
Short name T212
Test name
Test status
Simulation time 6519479219 ps
CPU time 11.28 seconds
Started Aug 01 06:47:40 PM PDT 24
Finished Aug 01 06:47:51 PM PDT 24
Peak memory 233164 kb
Host smart-48dcd336-4ca9-42c6-abf0-bbf6afd7f592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935893271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1935893271
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2397942582
Short name T532
Test name
Test status
Simulation time 1182985743 ps
CPU time 4.29 seconds
Started Aug 01 06:47:38 PM PDT 24
Finished Aug 01 06:47:42 PM PDT 24
Peak memory 219892 kb
Host smart-40ecb658-d4ba-4627-96a1-2ddebe5f5785
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2397942582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2397942582
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2595573171
Short name T142
Test name
Test status
Simulation time 42626100 ps
CPU time 1.01 seconds
Started Aug 01 06:47:37 PM PDT 24
Finished Aug 01 06:47:38 PM PDT 24
Peak memory 207312 kb
Host smart-e41b285e-9b19-459e-9ba0-f9548c6d15ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595573171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2595573171
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3234975914
Short name T849
Test name
Test status
Simulation time 2609084062 ps
CPU time 7.9 seconds
Started Aug 01 06:47:41 PM PDT 24
Finished Aug 01 06:47:49 PM PDT 24
Peak memory 219528 kb
Host smart-620bd191-71e9-459f-9b03-e867d90b5257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234975914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3234975914
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1349946314
Short name T356
Test name
Test status
Simulation time 7478353552 ps
CPU time 5.24 seconds
Started Aug 01 06:47:37 PM PDT 24
Finished Aug 01 06:47:42 PM PDT 24
Peak memory 216704 kb
Host smart-bf550b70-4028-4844-bcf9-1ac861cd694d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349946314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1349946314
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.402217690
Short name T995
Test name
Test status
Simulation time 27842666 ps
CPU time 0.68 seconds
Started Aug 01 06:47:34 PM PDT 24
Finished Aug 01 06:47:35 PM PDT 24
Peak memory 206012 kb
Host smart-b9990fa9-3b1b-4c26-a14d-5e765a3cc35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402217690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.402217690
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1180473859
Short name T302
Test name
Test status
Simulation time 46673995 ps
CPU time 0.74 seconds
Started Aug 01 06:47:41 PM PDT 24
Finished Aug 01 06:47:42 PM PDT 24
Peak memory 206364 kb
Host smart-7422f13e-98a0-4684-aa00-10a29b5e0f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180473859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1180473859
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2624770706
Short name T210
Test name
Test status
Simulation time 124124083 ps
CPU time 2.73 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:47:42 PM PDT 24
Peak memory 233124 kb
Host smart-7aa617df-6fef-4bbb-b2a1-0dab68604564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624770706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2624770706
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.948574488
Short name T619
Test name
Test status
Simulation time 70624349 ps
CPU time 0.71 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:47:40 PM PDT 24
Peak memory 205820 kb
Host smart-9a4c9032-5c24-4ea1-b2a4-c4de1a35a796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948574488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.948574488
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1961677370
Short name T168
Test name
Test status
Simulation time 81526801 ps
CPU time 3.48 seconds
Started Aug 01 06:47:41 PM PDT 24
Finished Aug 01 06:47:45 PM PDT 24
Peak memory 233140 kb
Host smart-f45f330a-3999-4c98-8791-b14e2534c35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961677370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1961677370
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3670892670
Short name T446
Test name
Test status
Simulation time 30152873 ps
CPU time 0.82 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:47:40 PM PDT 24
Peak memory 206980 kb
Host smart-6f3d329e-9fd3-497d-b9ed-2b6be1e23a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670892670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3670892670
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3305349981
Short name T146
Test name
Test status
Simulation time 2995492448 ps
CPU time 40.52 seconds
Started Aug 01 06:47:42 PM PDT 24
Finished Aug 01 06:48:22 PM PDT 24
Peak memory 240768 kb
Host smart-3b871373-c57f-4b05-b137-40b439bf6793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305349981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3305349981
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2450218820
Short name T512
Test name
Test status
Simulation time 32460666293 ps
CPU time 147.49 seconds
Started Aug 01 06:47:38 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 249628 kb
Host smart-c3d75cba-82fa-43df-a830-76b9c81d3efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450218820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2450218820
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4081597240
Short name T263
Test name
Test status
Simulation time 5946428257 ps
CPU time 20.95 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:48:00 PM PDT 24
Peak memory 234208 kb
Host smart-80bab982-73d3-4452-8759-b6042b3820af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081597240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4081597240
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1695673096
Short name T190
Test name
Test status
Simulation time 2289279442 ps
CPU time 19.4 seconds
Started Aug 01 06:47:41 PM PDT 24
Finished Aug 01 06:48:01 PM PDT 24
Peak memory 241356 kb
Host smart-dc2ab705-dea4-45ee-86cd-300946f35b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695673096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1695673096
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2477565114
Short name T349
Test name
Test status
Simulation time 316925287 ps
CPU time 3.26 seconds
Started Aug 01 06:47:35 PM PDT 24
Finished Aug 01 06:47:38 PM PDT 24
Peak memory 233100 kb
Host smart-2c4cccf4-61c8-40cd-b986-8499542a077d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477565114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2477565114
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3498467534
Short name T374
Test name
Test status
Simulation time 481547488 ps
CPU time 3.45 seconds
Started Aug 01 06:47:38 PM PDT 24
Finished Aug 01 06:47:42 PM PDT 24
Peak memory 233128 kb
Host smart-402ad155-a44d-4b96-94ee-c48a77d1e625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498467534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3498467534
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1130731792
Short name T452
Test name
Test status
Simulation time 3384808557 ps
CPU time 9.18 seconds
Started Aug 01 06:47:38 PM PDT 24
Finished Aug 01 06:47:48 PM PDT 24
Peak memory 234548 kb
Host smart-397dfadd-29d5-424c-a9d5-0332e4116134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130731792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1130731792
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1514878029
Short name T972
Test name
Test status
Simulation time 33718331 ps
CPU time 2.62 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:47:42 PM PDT 24
Peak memory 232776 kb
Host smart-b804767d-3b18-42cf-9d2a-a480d57aacc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514878029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1514878029
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.448074083
Short name T400
Test name
Test status
Simulation time 3673185828 ps
CPU time 11.86 seconds
Started Aug 01 06:47:41 PM PDT 24
Finished Aug 01 06:47:53 PM PDT 24
Peak memory 220460 kb
Host smart-c7e8c549-3633-4c25-848c-4c6be97307fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=448074083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.448074083
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2859924050
Short name T252
Test name
Test status
Simulation time 8926170981 ps
CPU time 178.64 seconds
Started Aug 01 06:47:43 PM PDT 24
Finished Aug 01 06:50:41 PM PDT 24
Peak memory 273156 kb
Host smart-15f76654-5336-40d9-b1f8-9787fe382790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859924050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2859924050
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3028494813
Short name T451
Test name
Test status
Simulation time 2408282514 ps
CPU time 15.84 seconds
Started Aug 01 06:47:41 PM PDT 24
Finished Aug 01 06:47:57 PM PDT 24
Peak memory 216896 kb
Host smart-c3bb03a3-b2d2-4a6a-a4d2-2dc8c3a76f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028494813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3028494813
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1386188492
Short name T479
Test name
Test status
Simulation time 873935701 ps
CPU time 3.19 seconds
Started Aug 01 06:47:35 PM PDT 24
Finished Aug 01 06:47:39 PM PDT 24
Peak memory 216664 kb
Host smart-f92a3ea1-a394-4c8e-b22c-5b6f913a1a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386188492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1386188492
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1108680479
Short name T486
Test name
Test status
Simulation time 109296280 ps
CPU time 1.59 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:47:41 PM PDT 24
Peak memory 216440 kb
Host smart-baed9dc0-7e4e-4d8e-8bc4-f3de28fa99f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108680479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1108680479
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.178416354
Short name T597
Test name
Test status
Simulation time 18528961 ps
CPU time 0.77 seconds
Started Aug 01 06:47:36 PM PDT 24
Finished Aug 01 06:47:37 PM PDT 24
Peak memory 206296 kb
Host smart-170d0e5c-21c5-4fc1-80ab-f9a2a88e9009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178416354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.178416354
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.193607481
Short name T496
Test name
Test status
Simulation time 1705119422 ps
CPU time 9.43 seconds
Started Aug 01 06:47:40 PM PDT 24
Finished Aug 01 06:47:50 PM PDT 24
Peak memory 224920 kb
Host smart-824ef916-4134-49a1-9938-eb1f9e649bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193607481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.193607481
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1607810812
Short name T51
Test name
Test status
Simulation time 42787665 ps
CPU time 0.73 seconds
Started Aug 01 06:45:15 PM PDT 24
Finished Aug 01 06:45:16 PM PDT 24
Peak memory 205752 kb
Host smart-a9aed74a-9174-44fd-a6bd-c867d04fd503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607810812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
607810812
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2953835649
Short name T213
Test name
Test status
Simulation time 366607157 ps
CPU time 3.18 seconds
Started Aug 01 06:45:04 PM PDT 24
Finished Aug 01 06:45:07 PM PDT 24
Peak memory 233068 kb
Host smart-5c40b0b0-222d-4813-9868-2a172a21a223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953835649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2953835649
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.436805937
Short name T916
Test name
Test status
Simulation time 77297443 ps
CPU time 0.88 seconds
Started Aug 01 06:45:14 PM PDT 24
Finished Aug 01 06:45:15 PM PDT 24
Peak memory 207300 kb
Host smart-8f6ed7c5-8f08-4894-a02f-722f5a2580f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436805937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.436805937
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1876974813
Short name T726
Test name
Test status
Simulation time 43200011321 ps
CPU time 321.82 seconds
Started Aug 01 06:45:13 PM PDT 24
Finished Aug 01 06:50:35 PM PDT 24
Peak memory 253312 kb
Host smart-44cdd5f8-2a68-4324-a136-40d5e03cde8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876974813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1876974813
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1035554628
Short name T922
Test name
Test status
Simulation time 66810027776 ps
CPU time 365.96 seconds
Started Aug 01 06:45:13 PM PDT 24
Finished Aug 01 06:51:19 PM PDT 24
Peak memory 251268 kb
Host smart-d9299a26-55a8-4a2f-92e0-9134556482d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035554628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1035554628
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.604367208
Short name T567
Test name
Test status
Simulation time 5808406661 ps
CPU time 82.13 seconds
Started Aug 01 06:45:14 PM PDT 24
Finished Aug 01 06:46:36 PM PDT 24
Peak memory 250624 kb
Host smart-b7b89d25-b99e-4c4e-82ce-2991c561c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604367208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
604367208
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1743203863
Short name T261
Test name
Test status
Simulation time 2697623482 ps
CPU time 25.23 seconds
Started Aug 01 06:45:15 PM PDT 24
Finished Aug 01 06:45:41 PM PDT 24
Peak memory 239928 kb
Host smart-72affd01-3390-4ff1-8cd8-43276ade13cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743203863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1743203863
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2958911398
Short name T593
Test name
Test status
Simulation time 3414024960 ps
CPU time 23.68 seconds
Started Aug 01 06:45:13 PM PDT 24
Finished Aug 01 06:45:37 PM PDT 24
Peak memory 225024 kb
Host smart-06ff6f7f-1dca-4968-ac70-564a1318bdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958911398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2958911398
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2695039888
Short name T65
Test name
Test status
Simulation time 235315875 ps
CPU time 3.43 seconds
Started Aug 01 06:45:02 PM PDT 24
Finished Aug 01 06:45:06 PM PDT 24
Peak memory 224824 kb
Host smart-9a3aefbb-ae61-4358-85f7-169d7f4360fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695039888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2695039888
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4160615381
Short name T385
Test name
Test status
Simulation time 18825458628 ps
CPU time 51.85 seconds
Started Aug 01 06:45:04 PM PDT 24
Finished Aug 01 06:45:56 PM PDT 24
Peak memory 233136 kb
Host smart-653074b7-dbb5-4e8c-9826-44e0f54c94ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160615381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4160615381
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.670636856
Short name T977
Test name
Test status
Simulation time 236930409 ps
CPU time 2.4 seconds
Started Aug 01 06:45:03 PM PDT 24
Finished Aug 01 06:45:05 PM PDT 24
Peak memory 224980 kb
Host smart-66b0c722-f12f-4ab6-9bf8-2086c6138e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670636856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
670636856
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3584674019
Short name T234
Test name
Test status
Simulation time 44267780918 ps
CPU time 25.9 seconds
Started Aug 01 06:45:01 PM PDT 24
Finished Aug 01 06:45:27 PM PDT 24
Peak memory 240188 kb
Host smart-a9dfd5d6-b3ca-4274-9a7f-99a6f0e72ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584674019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3584674019
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2378340101
Short name T628
Test name
Test status
Simulation time 214846527 ps
CPU time 3.59 seconds
Started Aug 01 06:45:15 PM PDT 24
Finished Aug 01 06:45:19 PM PDT 24
Peak memory 220980 kb
Host smart-f7ec07f3-e292-48b1-b239-474dbbe22093
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2378340101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2378340101
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1230613855
Short name T58
Test name
Test status
Simulation time 80985628 ps
CPU time 1.14 seconds
Started Aug 01 06:45:15 PM PDT 24
Finished Aug 01 06:45:16 PM PDT 24
Peak memory 236964 kb
Host smart-156b2a8b-6c86-48e0-b1a7-286b12cb6859
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230613855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1230613855
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.308312585
Short name T891
Test name
Test status
Simulation time 13969786 ps
CPU time 0.74 seconds
Started Aug 01 06:45:08 PM PDT 24
Finished Aug 01 06:45:09 PM PDT 24
Peak memory 206052 kb
Host smart-036e18a6-fba3-43c2-936b-c73b9c421d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308312585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.308312585
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.60379574
Short name T425
Test name
Test status
Simulation time 21534416515 ps
CPU time 14.89 seconds
Started Aug 01 06:45:07 PM PDT 24
Finished Aug 01 06:45:22 PM PDT 24
Peak memory 216980 kb
Host smart-6f5e1b82-ccd6-4f85-ab8a-dbc3dcefa8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60379574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.60379574
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3533893050
Short name T687
Test name
Test status
Simulation time 216740335 ps
CPU time 1.82 seconds
Started Aug 01 06:45:05 PM PDT 24
Finished Aug 01 06:45:07 PM PDT 24
Peak memory 216624 kb
Host smart-d9fcdbb2-7e9c-47c8-87c8-b94d11dd041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533893050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3533893050
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1941610000
Short name T777
Test name
Test status
Simulation time 60008908 ps
CPU time 0.92 seconds
Started Aug 01 06:45:04 PM PDT 24
Finished Aug 01 06:45:05 PM PDT 24
Peak memory 207428 kb
Host smart-8feb6012-bef4-4bf4-ab36-7b3169504070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941610000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1941610000
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3202402720
Short name T579
Test name
Test status
Simulation time 34810288262 ps
CPU time 27.52 seconds
Started Aug 01 06:45:02 PM PDT 24
Finished Aug 01 06:45:30 PM PDT 24
Peak memory 233120 kb
Host smart-23cec05f-69f9-46ad-8f9f-5fbea2070ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202402720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3202402720
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3668073206
Short name T430
Test name
Test status
Simulation time 32030953 ps
CPU time 0.7 seconds
Started Aug 01 06:47:50 PM PDT 24
Finished Aug 01 06:47:51 PM PDT 24
Peak memory 205220 kb
Host smart-acaaa72a-6e53-434a-b048-e0aeb8b93bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668073206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3668073206
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.108620303
Short name T1
Test name
Test status
Simulation time 121217356 ps
CPU time 2.62 seconds
Started Aug 01 06:47:43 PM PDT 24
Finished Aug 01 06:47:45 PM PDT 24
Peak memory 224892 kb
Host smart-98b28139-621e-47b9-b22c-fe95e6659f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108620303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.108620303
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.123348898
Short name T545
Test name
Test status
Simulation time 12585637 ps
CPU time 0.78 seconds
Started Aug 01 06:47:41 PM PDT 24
Finished Aug 01 06:47:42 PM PDT 24
Peak memory 206940 kb
Host smart-32161f94-5e9b-49af-bb0c-b9189c0a5892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123348898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.123348898
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1404251302
Short name T221
Test name
Test status
Simulation time 128565151415 ps
CPU time 198.88 seconds
Started Aug 01 06:47:47 PM PDT 24
Finished Aug 01 06:51:07 PM PDT 24
Peak memory 256776 kb
Host smart-be8bf766-9d3a-44f1-819a-0132af0d6ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404251302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1404251302
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4123150358
Short name T200
Test name
Test status
Simulation time 3283384842 ps
CPU time 76.36 seconds
Started Aug 01 06:47:50 PM PDT 24
Finished Aug 01 06:49:07 PM PDT 24
Peak memory 251172 kb
Host smart-5f37ed93-8771-48af-bab5-e2303ee1924e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123150358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4123150358
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4014550256
Short name T934
Test name
Test status
Simulation time 804506047 ps
CPU time 11.01 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:47:50 PM PDT 24
Peak memory 249464 kb
Host smart-eeb5d7ed-479d-4787-877b-ff485a9e926f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014550256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4014550256
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1208505395
Short name T993
Test name
Test status
Simulation time 5669713137 ps
CPU time 52.31 seconds
Started Aug 01 06:47:42 PM PDT 24
Finished Aug 01 06:48:35 PM PDT 24
Peak memory 257428 kb
Host smart-bd038344-4c76-41e5-89a0-b9ed2fca56d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208505395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1208505395
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.925306017
Short name T1009
Test name
Test status
Simulation time 262653967 ps
CPU time 5.48 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:47:45 PM PDT 24
Peak memory 233120 kb
Host smart-4c35a730-0965-4db5-a578-6f1121379ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925306017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.925306017
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2340655342
Short name T345
Test name
Test status
Simulation time 3523179889 ps
CPU time 22.63 seconds
Started Aug 01 06:47:39 PM PDT 24
Finished Aug 01 06:48:02 PM PDT 24
Peak memory 233176 kb
Host smart-d9fc4d65-3419-4f9c-8b6b-66ff0c20d0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340655342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2340655342
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.481562389
Short name T203
Test name
Test status
Simulation time 1416382102 ps
CPU time 7.11 seconds
Started Aug 01 06:47:42 PM PDT 24
Finished Aug 01 06:47:49 PM PDT 24
Peak memory 224920 kb
Host smart-27e264fb-fd19-46eb-9da8-c879da6d26fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481562389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.481562389
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4283032344
Short name T600
Test name
Test status
Simulation time 4522818031 ps
CPU time 16.74 seconds
Started Aug 01 06:47:37 PM PDT 24
Finished Aug 01 06:47:54 PM PDT 24
Peak memory 233060 kb
Host smart-c59d18db-5c06-43e8-8666-11ac20dbc707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283032344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4283032344
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3531973683
Short name T834
Test name
Test status
Simulation time 1553998527 ps
CPU time 17.61 seconds
Started Aug 01 06:47:47 PM PDT 24
Finished Aug 01 06:48:05 PM PDT 24
Peak memory 219192 kb
Host smart-19c3bcaa-4877-44a8-90c3-bda126d093ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3531973683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3531973683
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4160557979
Short name T143
Test name
Test status
Simulation time 66904251621 ps
CPU time 142.39 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:50:21 PM PDT 24
Peak memory 241456 kb
Host smart-63f09956-cdef-4fd0-8d27-f59fee712eb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160557979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4160557979
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.553979314
Short name T812
Test name
Test status
Simulation time 8156157963 ps
CPU time 17.51 seconds
Started Aug 01 06:47:40 PM PDT 24
Finished Aug 01 06:47:58 PM PDT 24
Peak memory 221020 kb
Host smart-fb41d74a-dc26-4ec5-b108-2bbe2a16d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553979314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.553979314
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1056229500
Short name T348
Test name
Test status
Simulation time 205231075 ps
CPU time 1.18 seconds
Started Aug 01 06:47:44 PM PDT 24
Finished Aug 01 06:47:46 PM PDT 24
Peak memory 208228 kb
Host smart-025dca75-adcd-451c-bdcb-89151fefc018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056229500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1056229500
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2071734431
Short name T874
Test name
Test status
Simulation time 104702421 ps
CPU time 1.89 seconds
Started Aug 01 06:47:37 PM PDT 24
Finished Aug 01 06:47:39 PM PDT 24
Peak memory 216588 kb
Host smart-48155e1f-50c5-47fa-840e-fc7cbfb9c8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071734431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2071734431
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3707161260
Short name T283
Test name
Test status
Simulation time 317813574 ps
CPU time 0.98 seconds
Started Aug 01 06:47:41 PM PDT 24
Finished Aug 01 06:47:42 PM PDT 24
Peak memory 206740 kb
Host smart-3807ac53-15d7-4138-9289-aa0b75983a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707161260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3707161260
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2456348008
Short name T765
Test name
Test status
Simulation time 2822170392 ps
CPU time 6.29 seconds
Started Aug 01 06:47:42 PM PDT 24
Finished Aug 01 06:47:48 PM PDT 24
Peak memory 225016 kb
Host smart-061cdaf2-b3d7-4573-a91e-afa0fdbca9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456348008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2456348008
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3504978160
Short name T685
Test name
Test status
Simulation time 42889860 ps
CPU time 0.76 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:47:50 PM PDT 24
Peak memory 205200 kb
Host smart-5eac2df0-cfb2-4af5-ba39-eea3a411574b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504978160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3504978160
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.411420795
Short name T656
Test name
Test status
Simulation time 360116584 ps
CPU time 2.24 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:47:52 PM PDT 24
Peak memory 224868 kb
Host smart-63b74d1b-9ab2-4c7d-bf4d-a26b714cf155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411420795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.411420795
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3058417221
Short name T471
Test name
Test status
Simulation time 17837904 ps
CPU time 0.75 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:47:59 PM PDT 24
Peak memory 205980 kb
Host smart-a8e286cc-6aa6-467b-aabb-dd6a5033b822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058417221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3058417221
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.132439348
Short name T186
Test name
Test status
Simulation time 23918675396 ps
CPU time 124.57 seconds
Started Aug 01 06:47:51 PM PDT 24
Finished Aug 01 06:49:56 PM PDT 24
Peak memory 241380 kb
Host smart-486f3ef2-ae16-43fd-b6b9-4a0d5e422c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132439348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.132439348
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.105832632
Short name T952
Test name
Test status
Simulation time 15694272674 ps
CPU time 72.33 seconds
Started Aug 01 06:47:47 PM PDT 24
Finished Aug 01 06:49:00 PM PDT 24
Peak memory 255788 kb
Host smart-3a6ed3f7-b1ff-456c-9a23-270b8e719381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105832632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.105832632
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2528152976
Short name T577
Test name
Test status
Simulation time 44774095550 ps
CPU time 139.25 seconds
Started Aug 01 06:47:48 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 250660 kb
Host smart-26631d4c-86b0-47ac-9b3c-a6e203f4895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528152976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2528152976
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3656115616
Short name T494
Test name
Test status
Simulation time 64347273 ps
CPU time 3.62 seconds
Started Aug 01 06:47:48 PM PDT 24
Finished Aug 01 06:47:52 PM PDT 24
Peak memory 224920 kb
Host smart-4850d92f-9985-4481-b02a-a824c70185d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656115616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3656115616
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1661268442
Short name T245
Test name
Test status
Simulation time 7872788759 ps
CPU time 55.17 seconds
Started Aug 01 06:47:46 PM PDT 24
Finished Aug 01 06:48:41 PM PDT 24
Peak memory 251588 kb
Host smart-ab5b2068-9466-457f-a96a-7cd6f07cfa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661268442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1661268442
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.90439690
Short name T516
Test name
Test status
Simulation time 6527335115 ps
CPU time 17.19 seconds
Started Aug 01 06:47:47 PM PDT 24
Finished Aug 01 06:48:05 PM PDT 24
Peak memory 225048 kb
Host smart-3a69d212-7446-47a1-989a-9b801727d12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90439690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.90439690
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1625935004
Short name T905
Test name
Test status
Simulation time 607099470 ps
CPU time 14.69 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:48:13 PM PDT 24
Peak memory 234220 kb
Host smart-a3693f22-d7f9-4b33-9858-6d56125d38d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625935004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1625935004
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1740254508
Short name T792
Test name
Test status
Simulation time 735909116 ps
CPU time 5.79 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:47:54 PM PDT 24
Peak memory 224880 kb
Host smart-49d5d018-53f2-4f01-bc52-75a0363352a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740254508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1740254508
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4034282078
Short name T320
Test name
Test status
Simulation time 5090921586 ps
CPU time 7.54 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:48:06 PM PDT 24
Peak memory 225056 kb
Host smart-e596ed4d-8bcc-4e86-874a-cc118ae35bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034282078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4034282078
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4025630689
Short name T121
Test name
Test status
Simulation time 664572688 ps
CPU time 7.35 seconds
Started Aug 01 06:47:50 PM PDT 24
Finished Aug 01 06:47:57 PM PDT 24
Peak memory 219160 kb
Host smart-39373a10-0cf2-4320-be3a-22b0e49180db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4025630689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4025630689
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.917269842
Short name T863
Test name
Test status
Simulation time 14007821165 ps
CPU time 47.53 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:48:37 PM PDT 24
Peak memory 225036 kb
Host smart-e725a5b9-1cab-4846-be1d-9f533706b1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917269842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.917269842
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1064902382
Short name T500
Test name
Test status
Simulation time 5788571841 ps
CPU time 33.34 seconds
Started Aug 01 06:47:48 PM PDT 24
Finished Aug 01 06:48:22 PM PDT 24
Peak memory 216676 kb
Host smart-4721aa6f-4768-498c-b8ea-c7589297c4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064902382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1064902382
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3896945744
Short name T542
Test name
Test status
Simulation time 8157071955 ps
CPU time 13.42 seconds
Started Aug 01 06:47:47 PM PDT 24
Finished Aug 01 06:48:01 PM PDT 24
Peak memory 216664 kb
Host smart-d6454a9c-cfcb-443b-9328-3edc100bff41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896945744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3896945744
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2330520575
Short name T300
Test name
Test status
Simulation time 79683580 ps
CPU time 1.11 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:47:51 PM PDT 24
Peak memory 208300 kb
Host smart-97f02c9a-2f44-47d4-b5e5-d301126ad1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330520575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2330520575
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.64619517
Short name T280
Test name
Test status
Simulation time 10765993 ps
CPU time 0.71 seconds
Started Aug 01 06:47:47 PM PDT 24
Finished Aug 01 06:47:48 PM PDT 24
Peak memory 205944 kb
Host smart-744d9a99-bf68-4e15-9d6a-2904cc607535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64619517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.64619517
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.408248795
Short name T865
Test name
Test status
Simulation time 111392538 ps
CPU time 2.04 seconds
Started Aug 01 06:47:50 PM PDT 24
Finished Aug 01 06:47:52 PM PDT 24
Peak memory 224484 kb
Host smart-2ada68bc-117c-4a48-bf80-5c55d5cc9099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408248795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.408248795
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3475615859
Short name T764
Test name
Test status
Simulation time 52458445 ps
CPU time 0.72 seconds
Started Aug 01 06:47:50 PM PDT 24
Finished Aug 01 06:47:51 PM PDT 24
Peak memory 205204 kb
Host smart-0d2aebe4-577c-419b-b961-3cb3063952ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475615859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3475615859
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1907458179
Short name T580
Test name
Test status
Simulation time 3599474616 ps
CPU time 29.89 seconds
Started Aug 01 06:47:50 PM PDT 24
Finished Aug 01 06:48:20 PM PDT 24
Peak memory 233112 kb
Host smart-31d64f10-21c1-4ff0-8b14-62a3b32a3f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907458179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1907458179
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3658118088
Short name T627
Test name
Test status
Simulation time 44987629 ps
CPU time 0.78 seconds
Started Aug 01 06:47:50 PM PDT 24
Finished Aug 01 06:47:51 PM PDT 24
Peak memory 207268 kb
Host smart-4dceed4c-c19f-4b41-b139-edde85399876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658118088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3658118088
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3616472484
Short name T66
Test name
Test status
Simulation time 259432413291 ps
CPU time 235.93 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:51:45 PM PDT 24
Peak memory 257716 kb
Host smart-8169ee34-cd3f-4f4c-8a98-204ecc8857b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616472484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3616472484
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2035834864
Short name T222
Test name
Test status
Simulation time 10223543665 ps
CPU time 92.9 seconds
Started Aug 01 06:47:51 PM PDT 24
Finished Aug 01 06:49:24 PM PDT 24
Peak memory 239216 kb
Host smart-b42dcc9e-90ff-48ca-aed5-7ae82ba5c2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035834864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2035834864
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1190784027
Short name T271
Test name
Test status
Simulation time 15871762650 ps
CPU time 52.49 seconds
Started Aug 01 06:47:52 PM PDT 24
Finished Aug 01 06:48:44 PM PDT 24
Peak memory 233232 kb
Host smart-73ddbbe8-6951-45af-9496-ff28a0da7b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190784027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1190784027
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2082581335
Short name T369
Test name
Test status
Simulation time 399024710 ps
CPU time 4.49 seconds
Started Aug 01 06:47:51 PM PDT 24
Finished Aug 01 06:47:56 PM PDT 24
Peak memory 233076 kb
Host smart-7618883f-bf33-4596-bf65-2151034c4d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082581335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2082581335
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2961901068
Short name T334
Test name
Test status
Simulation time 17804538 ps
CPU time 0.74 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:47:50 PM PDT 24
Peak memory 216076 kb
Host smart-89f39e52-0bf0-4c68-b5a4-ca87407aaf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961901068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2961901068
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4101447764
Short name T194
Test name
Test status
Simulation time 6886975150 ps
CPU time 37.42 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:48:26 PM PDT 24
Peak memory 225044 kb
Host smart-2849d803-37dc-43b3-803b-2a2b29901130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101447764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4101447764
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2265741466
Short name T324
Test name
Test status
Simulation time 11437895981 ps
CPU time 13.18 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:48:02 PM PDT 24
Peak memory 224896 kb
Host smart-f5d176f7-3827-4a33-b184-819e69ac19ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265741466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2265741466
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4183075099
Short name T745
Test name
Test status
Simulation time 33124918 ps
CPU time 2.35 seconds
Started Aug 01 06:47:47 PM PDT 24
Finished Aug 01 06:47:50 PM PDT 24
Peak memory 232792 kb
Host smart-1292cd51-5b96-4520-b10c-3e79ba561e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183075099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4183075099
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.583956419
Short name T482
Test name
Test status
Simulation time 11191457696 ps
CPU time 10.2 seconds
Started Aug 01 06:48:00 PM PDT 24
Finished Aug 01 06:48:10 PM PDT 24
Peak memory 233200 kb
Host smart-cc4607ef-e40f-4994-81cd-96f31c61c6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583956419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.583956419
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3053892882
Short name T806
Test name
Test status
Simulation time 816896448 ps
CPU time 4.94 seconds
Started Aug 01 06:47:48 PM PDT 24
Finished Aug 01 06:47:53 PM PDT 24
Peak memory 219664 kb
Host smart-2a8e647d-6e71-4dde-aa0e-68a83c3ae542
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3053892882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3053892882
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1509012030
Short name T136
Test name
Test status
Simulation time 3429454381 ps
CPU time 68.05 seconds
Started Aug 01 06:47:47 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 249652 kb
Host smart-936ce227-1d37-4c99-b879-42bbf4f58eed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509012030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1509012030
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3069492578
Short name T267
Test name
Test status
Simulation time 3393696066 ps
CPU time 13.22 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:48:03 PM PDT 24
Peak memory 216852 kb
Host smart-f17b79a8-8585-4f82-9193-64d7031da5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069492578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3069492578
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3275565095
Short name T707
Test name
Test status
Simulation time 11423886 ps
CPU time 0.7 seconds
Started Aug 01 06:47:51 PM PDT 24
Finished Aug 01 06:47:52 PM PDT 24
Peak memory 206072 kb
Host smart-6a52c88d-9df4-436c-afba-e1e1bfd9e377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275565095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3275565095
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2526539354
Short name T357
Test name
Test status
Simulation time 84093674 ps
CPU time 1.65 seconds
Started Aug 01 06:47:51 PM PDT 24
Finished Aug 01 06:47:52 PM PDT 24
Peak memory 216680 kb
Host smart-2aed1036-572d-45ae-92e5-060ce08de616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526539354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2526539354
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1616842081
Short name T331
Test name
Test status
Simulation time 187725687 ps
CPU time 0.98 seconds
Started Aug 01 06:47:47 PM PDT 24
Finished Aug 01 06:47:48 PM PDT 24
Peak memory 206324 kb
Host smart-cc46e006-8a4e-48bb-b678-511d74894c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616842081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1616842081
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2385148952
Short name T1008
Test name
Test status
Simulation time 5705691082 ps
CPU time 5.05 seconds
Started Aug 01 06:47:47 PM PDT 24
Finished Aug 01 06:47:52 PM PDT 24
Peak memory 224876 kb
Host smart-0096b1af-98bc-42ca-b696-6c595882c4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385148952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2385148952
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3360311971
Short name T822
Test name
Test status
Simulation time 56690128 ps
CPU time 0.76 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:47:59 PM PDT 24
Peak memory 206208 kb
Host smart-8c99912f-967a-40da-91f7-50050bea7c3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360311971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3360311971
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1059618475
Short name T632
Test name
Test status
Simulation time 114960286 ps
CPU time 2.36 seconds
Started Aug 01 06:47:57 PM PDT 24
Finished Aug 01 06:48:00 PM PDT 24
Peak memory 224868 kb
Host smart-d8a8d3cf-c57d-4d90-b8c3-000fc2701608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059618475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1059618475
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.577444250
Short name T410
Test name
Test status
Simulation time 42514030 ps
CPU time 0.77 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:48:00 PM PDT 24
Peak memory 207032 kb
Host smart-b8bfabd8-a4e6-4a21-b9cf-ff475a9780d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577444250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.577444250
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2738812372
Short name T238
Test name
Test status
Simulation time 25693256943 ps
CPU time 84.36 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:49:23 PM PDT 24
Peak memory 249732 kb
Host smart-418411d4-1002-4c09-8c39-568312b7799e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738812372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2738812372
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2593280013
Short name T30
Test name
Test status
Simulation time 12744572155 ps
CPU time 95.83 seconds
Started Aug 01 06:48:01 PM PDT 24
Finished Aug 01 06:49:37 PM PDT 24
Peak memory 256980 kb
Host smart-71950a3d-6529-45a3-afc6-c1d5318d2025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593280013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2593280013
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2624747032
Short name T548
Test name
Test status
Simulation time 25983308432 ps
CPU time 38.04 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:48:36 PM PDT 24
Peak memory 249624 kb
Host smart-9eab29d3-b7b6-4aba-a9a4-2d994d95b8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624747032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2624747032
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3624897601
Short name T871
Test name
Test status
Simulation time 2532506621 ps
CPU time 20.25 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:48:18 PM PDT 24
Peak memory 249528 kb
Host smart-69d7e248-89ff-462c-a02e-59db00c96923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624897601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3624897601
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.189130745
Short name T720
Test name
Test status
Simulation time 71906450958 ps
CPU time 99.25 seconds
Started Aug 01 06:48:04 PM PDT 24
Finished Aug 01 06:49:43 PM PDT 24
Peak memory 249996 kb
Host smart-5408addc-2087-400a-9294-8290cd609f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189130745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.189130745
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3182729675
Short name T424
Test name
Test status
Simulation time 209503673 ps
CPU time 4.13 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:48:03 PM PDT 24
Peak memory 233088 kb
Host smart-c4594385-26e2-4b60-a822-5883fc16800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182729675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3182729675
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.900654777
Short name T498
Test name
Test status
Simulation time 101072275870 ps
CPU time 53.35 seconds
Started Aug 01 06:48:01 PM PDT 24
Finished Aug 01 06:48:54 PM PDT 24
Peak memory 233144 kb
Host smart-6d125ed2-f133-48ea-b0ea-60365b5c983b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900654777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.900654777
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1182752267
Short name T421
Test name
Test status
Simulation time 199683618 ps
CPU time 3.87 seconds
Started Aug 01 06:48:00 PM PDT 24
Finished Aug 01 06:48:04 PM PDT 24
Peak memory 224884 kb
Host smart-3b88fb47-dcff-4c4e-82c0-7b3705067033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182752267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1182752267
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1785453566
Short name T64
Test name
Test status
Simulation time 3458049378 ps
CPU time 12.46 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:48:11 PM PDT 24
Peak memory 233140 kb
Host smart-db50413a-c407-4fa8-bca3-bfb31b3e3a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785453566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1785453566
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1245348968
Short name T914
Test name
Test status
Simulation time 1266785361 ps
CPU time 10.92 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:48:10 PM PDT 24
Peak memory 221084 kb
Host smart-1cf67d5b-545d-4473-9579-4f80cccd1a0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1245348968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1245348968
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.991730461
Short name T250
Test name
Test status
Simulation time 2224920552 ps
CPU time 63.58 seconds
Started Aug 01 06:48:01 PM PDT 24
Finished Aug 01 06:49:05 PM PDT 24
Peak memory 254408 kb
Host smart-2528f6ad-ad56-45eb-946a-99ce4c481b02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991730461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.991730461
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3300227060
Short name T604
Test name
Test status
Simulation time 1375514871 ps
CPU time 10.7 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:48:00 PM PDT 24
Peak memory 216672 kb
Host smart-47371e31-bbc8-4c03-a9fc-547634de0656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300227060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3300227060
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3975069052
Short name T642
Test name
Test status
Simulation time 2444784972 ps
CPU time 6.11 seconds
Started Aug 01 06:47:49 PM PDT 24
Finished Aug 01 06:47:55 PM PDT 24
Peak memory 216724 kb
Host smart-ee2ff983-759e-4ac2-83b2-d259c046e6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975069052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3975069052
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2042602628
Short name T275
Test name
Test status
Simulation time 44675946 ps
CPU time 1.28 seconds
Started Aug 01 06:48:02 PM PDT 24
Finished Aug 01 06:48:04 PM PDT 24
Peak memory 208432 kb
Host smart-c46b799c-1926-4b35-9271-9e927444ce92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042602628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2042602628
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2692650872
Short name T550
Test name
Test status
Simulation time 504147846 ps
CPU time 1.05 seconds
Started Aug 01 06:48:02 PM PDT 24
Finished Aug 01 06:48:04 PM PDT 24
Peak memory 207364 kb
Host smart-1e87ddd6-e41d-4fbf-86b9-4faecc61f4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692650872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2692650872
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2987501512
Short name T211
Test name
Test status
Simulation time 89469032429 ps
CPU time 16.04 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:48:15 PM PDT 24
Peak memory 233168 kb
Host smart-1d0831ab-a7c1-4e24-98da-42bac6ae13ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987501512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2987501512
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3197780116
Short name T296
Test name
Test status
Simulation time 13308178 ps
CPU time 0.73 seconds
Started Aug 01 06:48:01 PM PDT 24
Finished Aug 01 06:48:02 PM PDT 24
Peak memory 205796 kb
Host smart-2c6e5f5c-2488-4017-9752-5e4ccafc7655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197780116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3197780116
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4028128851
Short name T951
Test name
Test status
Simulation time 916895248 ps
CPU time 10.18 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:48:09 PM PDT 24
Peak memory 224844 kb
Host smart-6f7ab00e-9cc9-4f83-85f1-2b6c9b41918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028128851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4028128851
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.775630981
Short name T708
Test name
Test status
Simulation time 31801842 ps
CPU time 0.77 seconds
Started Aug 01 06:48:01 PM PDT 24
Finished Aug 01 06:48:02 PM PDT 24
Peak memory 207296 kb
Host smart-72398629-9499-450f-9922-3cf885a0d294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775630981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.775630981
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.973084546
Short name T798
Test name
Test status
Simulation time 14876520358 ps
CPU time 30.27 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:48:28 PM PDT 24
Peak memory 224980 kb
Host smart-dbbecab3-c2b9-4c07-bd56-6eecc99d8863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973084546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.973084546
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2299346119
Short name T533
Test name
Test status
Simulation time 10329695392 ps
CPU time 91.51 seconds
Started Aug 01 06:48:00 PM PDT 24
Finished Aug 01 06:49:31 PM PDT 24
Peak memory 240856 kb
Host smart-fae441ba-7e5c-4bc1-99a9-809f9afbdf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299346119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2299346119
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3879794344
Short name T223
Test name
Test status
Simulation time 17121209952 ps
CPU time 119.99 seconds
Started Aug 01 06:48:00 PM PDT 24
Finished Aug 01 06:50:00 PM PDT 24
Peak memory 255784 kb
Host smart-2e422494-2599-4850-912e-9f001d4b712c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879794344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3879794344
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2823348429
Short name T613
Test name
Test status
Simulation time 2803958255 ps
CPU time 20.1 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:48:19 PM PDT 24
Peak memory 233188 kb
Host smart-7f1a877c-6e62-4cc0-af3c-2437451b6456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823348429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2823348429
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1658357327
Short name T201
Test name
Test status
Simulation time 73385485348 ps
CPU time 75.82 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:49:15 PM PDT 24
Peak memory 239940 kb
Host smart-1f16f3e5-47e6-4e0e-b0ab-f5f294d5716c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658357327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1658357327
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.878222521
Short name T63
Test name
Test status
Simulation time 4289855104 ps
CPU time 16.22 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:48:15 PM PDT 24
Peak memory 224908 kb
Host smart-d132f7fe-1b36-4ad4-9b40-0a29175876b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878222521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.878222521
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1466969732
Short name T353
Test name
Test status
Simulation time 228855431 ps
CPU time 3.61 seconds
Started Aug 01 06:48:01 PM PDT 24
Finished Aug 01 06:48:05 PM PDT 24
Peak memory 224952 kb
Host smart-2ca9d7b6-2d54-4cf4-b81e-18b8dc6f7038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466969732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1466969732
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2249891783
Short name T987
Test name
Test status
Simulation time 2502322864 ps
CPU time 10.77 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:48:09 PM PDT 24
Peak memory 220744 kb
Host smart-d2a38c28-52a7-4eed-a58c-016b5c28fb81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2249891783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2249891783
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2668507928
Short name T828
Test name
Test status
Simulation time 197967047767 ps
CPU time 358.38 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:53:57 PM PDT 24
Peak memory 258364 kb
Host smart-d400cb83-c5de-4275-ad16-010541dba0c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668507928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2668507928
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2409064803
Short name T730
Test name
Test status
Simulation time 5471506966 ps
CPU time 3.76 seconds
Started Aug 01 06:48:01 PM PDT 24
Finished Aug 01 06:48:05 PM PDT 24
Peak memory 216684 kb
Host smart-4334d97d-2519-491a-afc1-f1888a6eae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409064803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2409064803
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4069251875
Short name T962
Test name
Test status
Simulation time 5645247782 ps
CPU time 5.74 seconds
Started Aug 01 06:48:02 PM PDT 24
Finished Aug 01 06:48:08 PM PDT 24
Peak memory 216664 kb
Host smart-7790a741-630e-4d4c-99a6-7a91762968a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069251875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4069251875
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1615274708
Short name T277
Test name
Test status
Simulation time 258550527 ps
CPU time 1.44 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:48:01 PM PDT 24
Peak memory 216656 kb
Host smart-317c59e8-1cef-4727-8d70-521bbb5a9eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615274708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1615274708
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3822541376
Short name T513
Test name
Test status
Simulation time 812641128 ps
CPU time 1.04 seconds
Started Aug 01 06:48:02 PM PDT 24
Finished Aug 01 06:48:03 PM PDT 24
Peak memory 207328 kb
Host smart-c97f9eaa-2fc7-4eb1-8fcb-945f11d0bf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822541376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3822541376
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1704563588
Short name T920
Test name
Test status
Simulation time 5757315276 ps
CPU time 12.55 seconds
Started Aug 01 06:48:03 PM PDT 24
Finished Aug 01 06:48:16 PM PDT 24
Peak memory 240880 kb
Host smart-d53f0114-d5dd-48bc-870c-1969ed27e4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704563588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1704563588
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3576637400
Short name T364
Test name
Test status
Simulation time 15773995 ps
CPU time 0.7 seconds
Started Aug 01 06:47:58 PM PDT 24
Finished Aug 01 06:47:59 PM PDT 24
Peak memory 205308 kb
Host smart-c46572bc-0aa1-4836-bdbd-933a2b1c7733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576637400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3576637400
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3285085975
Short name T570
Test name
Test status
Simulation time 427296648 ps
CPU time 6.47 seconds
Started Aug 01 06:48:01 PM PDT 24
Finished Aug 01 06:48:08 PM PDT 24
Peak memory 224872 kb
Host smart-56f642a8-801a-4b31-bfa5-ad5901dc7a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285085975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3285085975
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1926978625
Short name T520
Test name
Test status
Simulation time 53128862 ps
CPU time 0.9 seconds
Started Aug 01 06:48:02 PM PDT 24
Finished Aug 01 06:48:03 PM PDT 24
Peak memory 206984 kb
Host smart-615db9e6-2e1b-48af-8677-9f9240ffa3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926978625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1926978625
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.311919955
Short name T615
Test name
Test status
Simulation time 8079226877 ps
CPU time 63.34 seconds
Started Aug 01 06:48:04 PM PDT 24
Finished Aug 01 06:49:07 PM PDT 24
Peak memory 241372 kb
Host smart-76ee9c5e-93a1-4cbc-9649-673fc5246cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311919955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.311919955
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3722909608
Short name T667
Test name
Test status
Simulation time 55255143141 ps
CPU time 130.58 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:50:10 PM PDT 24
Peak memory 251668 kb
Host smart-b9532b21-e5f9-4914-81d3-1c72fa933cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722909608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3722909608
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1276693029
Short name T322
Test name
Test status
Simulation time 4092689567 ps
CPU time 7.16 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:48:06 PM PDT 24
Peak memory 224852 kb
Host smart-f529309a-d3bf-4ae2-8161-43643d00fd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276693029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1276693029
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1050467010
Short name T877
Test name
Test status
Simulation time 19704579 ps
CPU time 0.82 seconds
Started Aug 01 06:48:00 PM PDT 24
Finished Aug 01 06:48:01 PM PDT 24
Peak memory 216084 kb
Host smart-2185bcf2-42ac-403a-a39c-756f0bda74f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050467010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1050467010
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1087627787
Short name T562
Test name
Test status
Simulation time 116480156 ps
CPU time 3.74 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:48:03 PM PDT 24
Peak memory 233160 kb
Host smart-273e29c1-f4e3-4f20-acd0-1f93ec34d92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087627787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1087627787
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4093435029
Short name T699
Test name
Test status
Simulation time 4744079565 ps
CPU time 39.84 seconds
Started Aug 01 06:48:00 PM PDT 24
Finished Aug 01 06:48:40 PM PDT 24
Peak memory 224896 kb
Host smart-2f7430fd-617f-4e72-9286-b9a1bf535a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093435029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4093435029
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.159444891
Short name T490
Test name
Test status
Simulation time 88370951 ps
CPU time 2.88 seconds
Started Aug 01 06:48:07 PM PDT 24
Finished Aug 01 06:48:10 PM PDT 24
Peak memory 233088 kb
Host smart-c1475fc2-c9d0-413c-85cd-797add329ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159444891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.159444891
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.4044416101
Short name T860
Test name
Test status
Simulation time 1571830603 ps
CPU time 10.9 seconds
Started Aug 01 06:48:03 PM PDT 24
Finished Aug 01 06:48:14 PM PDT 24
Peak memory 233120 kb
Host smart-f29a2e0d-99c1-424c-bb3c-94bf7da47627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044416101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4044416101
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.508706194
Short name T715
Test name
Test status
Simulation time 1223028825 ps
CPU time 8.69 seconds
Started Aug 01 06:48:07 PM PDT 24
Finished Aug 01 06:48:16 PM PDT 24
Peak memory 223284 kb
Host smart-f3ad5c95-3e5d-4eb8-94a6-c9bd9ab660e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=508706194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.508706194
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3706242183
Short name T112
Test name
Test status
Simulation time 4325918801 ps
CPU time 44.2 seconds
Started Aug 01 06:48:07 PM PDT 24
Finished Aug 01 06:48:51 PM PDT 24
Peak memory 239404 kb
Host smart-247c24d6-c0e0-4495-a1f1-f233dcb8c3c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706242183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3706242183
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.644487405
Short name T596
Test name
Test status
Simulation time 2627602069 ps
CPU time 7.94 seconds
Started Aug 01 06:48:07 PM PDT 24
Finished Aug 01 06:48:15 PM PDT 24
Peak memory 216644 kb
Host smart-4b1921d1-bc12-4b64-b990-16506da7b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644487405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.644487405
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1024313793
Short name T462
Test name
Test status
Simulation time 40573248900 ps
CPU time 10.79 seconds
Started Aug 01 06:48:01 PM PDT 24
Finished Aug 01 06:48:12 PM PDT 24
Peak memory 216888 kb
Host smart-6c47985d-aaf6-47cb-aa50-b65a91850603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024313793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1024313793
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1402627377
Short name T396
Test name
Test status
Simulation time 20674979 ps
CPU time 0.76 seconds
Started Aug 01 06:48:00 PM PDT 24
Finished Aug 01 06:48:01 PM PDT 24
Peak memory 206328 kb
Host smart-4208863f-15bb-4e07-ad75-922b97d2c4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402627377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1402627377
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2326604730
Short name T367
Test name
Test status
Simulation time 63240022 ps
CPU time 0.71 seconds
Started Aug 01 06:47:57 PM PDT 24
Finished Aug 01 06:47:57 PM PDT 24
Peak memory 206364 kb
Host smart-d2e5c84c-13d5-47b1-b879-022f34b5f24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326604730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2326604730
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.408757087
Short name T363
Test name
Test status
Simulation time 23691586121 ps
CPU time 20.55 seconds
Started Aug 01 06:48:01 PM PDT 24
Finished Aug 01 06:48:21 PM PDT 24
Peak memory 224916 kb
Host smart-42f10e0d-cb32-4db8-8ec1-a0bf68d02797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408757087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.408757087
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1330181405
Short name T668
Test name
Test status
Simulation time 14008445 ps
CPU time 0.73 seconds
Started Aug 01 06:48:12 PM PDT 24
Finished Aug 01 06:48:12 PM PDT 24
Peak memory 205776 kb
Host smart-70cd9782-37fe-4359-aa85-7e746dbf8e0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330181405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1330181405
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1538964057
Short name T635
Test name
Test status
Simulation time 407155294 ps
CPU time 3.02 seconds
Started Aug 01 06:48:17 PM PDT 24
Finished Aug 01 06:48:20 PM PDT 24
Peak memory 233132 kb
Host smart-df83db9f-06af-4d9a-9676-fa1a0c9e4913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538964057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1538964057
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2632004502
Short name T634
Test name
Test status
Simulation time 60449258 ps
CPU time 0.81 seconds
Started Aug 01 06:48:01 PM PDT 24
Finished Aug 01 06:48:02 PM PDT 24
Peak memory 205932 kb
Host smart-aa5c90f6-2ee9-4f74-b7e4-905d537333e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632004502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2632004502
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4039233877
Short name T677
Test name
Test status
Simulation time 30825417103 ps
CPU time 218.29 seconds
Started Aug 01 06:48:06 PM PDT 24
Finished Aug 01 06:51:44 PM PDT 24
Peak memory 253764 kb
Host smart-e9ca14b5-cc9a-4a2c-951f-b5e91123adae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039233877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4039233877
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.640167518
Short name T948
Test name
Test status
Simulation time 16071486123 ps
CPU time 136.33 seconds
Started Aug 01 06:48:12 PM PDT 24
Finished Aug 01 06:50:28 PM PDT 24
Peak memory 251668 kb
Host smart-ab6a9e00-8076-425a-86fc-029de90107e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640167518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.640167518
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2974064933
Short name T594
Test name
Test status
Simulation time 32975727544 ps
CPU time 333.65 seconds
Started Aug 01 06:48:09 PM PDT 24
Finished Aug 01 06:53:43 PM PDT 24
Peak memory 265688 kb
Host smart-fc3822e7-dfb5-4389-8440-e57b86ed2343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974064933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2974064933
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1186827991
Short name T256
Test name
Test status
Simulation time 1782511354 ps
CPU time 32.76 seconds
Started Aug 01 06:48:12 PM PDT 24
Finished Aug 01 06:48:45 PM PDT 24
Peak memory 234624 kb
Host smart-3f2baae1-a5c9-4c70-9f7f-2a499a4cd040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186827991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1186827991
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1494325492
Short name T149
Test name
Test status
Simulation time 2161944382 ps
CPU time 46.62 seconds
Started Aug 01 06:48:09 PM PDT 24
Finished Aug 01 06:48:56 PM PDT 24
Peak memory 256248 kb
Host smart-8beeeba6-fbcb-40f5-aae4-433682e2f957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494325492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1494325492
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2326118869
Short name T937
Test name
Test status
Simulation time 1157773447 ps
CPU time 11.17 seconds
Started Aug 01 06:48:19 PM PDT 24
Finished Aug 01 06:48:31 PM PDT 24
Peak memory 224880 kb
Host smart-da96ee71-e702-4d54-9484-b77d2de25878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326118869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2326118869
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3827058772
Short name T813
Test name
Test status
Simulation time 135246980 ps
CPU time 5.57 seconds
Started Aug 01 06:48:09 PM PDT 24
Finished Aug 01 06:48:15 PM PDT 24
Peak memory 233128 kb
Host smart-a0c5a57f-7d39-41c6-b4ef-0b639a6e82f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827058772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3827058772
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1793410473
Short name T247
Test name
Test status
Simulation time 350933689 ps
CPU time 4.98 seconds
Started Aug 01 06:48:09 PM PDT 24
Finished Aug 01 06:48:14 PM PDT 24
Peak memory 233100 kb
Host smart-919922be-fbe8-4742-9df0-45c5eebc1ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793410473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1793410473
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3145854502
Short name T840
Test name
Test status
Simulation time 1542234905 ps
CPU time 6.03 seconds
Started Aug 01 06:48:09 PM PDT 24
Finished Aug 01 06:48:15 PM PDT 24
Peak memory 224924 kb
Host smart-c6db7417-e006-4ba8-aff2-0308f0444670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145854502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3145854502
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2053612549
Short name T978
Test name
Test status
Simulation time 1330659132 ps
CPU time 4.96 seconds
Started Aug 01 06:48:06 PM PDT 24
Finished Aug 01 06:48:11 PM PDT 24
Peak memory 222828 kb
Host smart-bb9e41bb-d3ae-432e-915b-ff3ff1eaba09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2053612549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2053612549
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.149273374
Short name T113
Test name
Test status
Simulation time 72191588632 ps
CPU time 749.74 seconds
Started Aug 01 06:48:12 PM PDT 24
Finished Aug 01 07:00:42 PM PDT 24
Peak memory 274140 kb
Host smart-f1b8f86b-54de-47a3-a2e0-a161dd2d92bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149273374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.149273374
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3788894584
Short name T802
Test name
Test status
Simulation time 7405145086 ps
CPU time 38.14 seconds
Started Aug 01 06:47:59 PM PDT 24
Finished Aug 01 06:48:38 PM PDT 24
Peak memory 216904 kb
Host smart-f5431a90-b64c-4fdc-85cc-a75695af1fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788894584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3788894584
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3646695641
Short name T140
Test name
Test status
Simulation time 764464630 ps
CPU time 4.93 seconds
Started Aug 01 06:48:03 PM PDT 24
Finished Aug 01 06:48:08 PM PDT 24
Peak memory 216584 kb
Host smart-26ecab95-08c4-444f-982e-d050fc9c6c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646695641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3646695641
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.447135404
Short name T483
Test name
Test status
Simulation time 1529318093 ps
CPU time 3.64 seconds
Started Aug 01 06:48:08 PM PDT 24
Finished Aug 01 06:48:12 PM PDT 24
Peak memory 216540 kb
Host smart-2e8b0b13-fff2-419e-aba5-92463f1a5075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447135404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.447135404
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3856470438
Short name T924
Test name
Test status
Simulation time 22878202 ps
CPU time 0.8 seconds
Started Aug 01 06:48:03 PM PDT 24
Finished Aug 01 06:48:04 PM PDT 24
Peak memory 206300 kb
Host smart-030cf9c1-c840-4851-99a9-9c321b8a4c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856470438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3856470438
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2832715177
Short name T457
Test name
Test status
Simulation time 385394641 ps
CPU time 4.46 seconds
Started Aug 01 06:48:19 PM PDT 24
Finished Aug 01 06:48:24 PM PDT 24
Peak memory 224968 kb
Host smart-db595662-2fcc-4b2d-a910-b0bba2565770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832715177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2832715177
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3744761898
Short name T781
Test name
Test status
Simulation time 14709333 ps
CPU time 0.75 seconds
Started Aug 01 06:48:13 PM PDT 24
Finished Aug 01 06:48:14 PM PDT 24
Peak memory 205288 kb
Host smart-46ad34e5-9269-474e-9f9a-01a0fa1c12db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744761898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3744761898
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2073570745
Short name T358
Test name
Test status
Simulation time 197004233 ps
CPU time 2.01 seconds
Started Aug 01 06:48:05 PM PDT 24
Finished Aug 01 06:48:08 PM PDT 24
Peak memory 224928 kb
Host smart-e5b5c554-1e74-4909-812a-7bb4e1c53b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073570745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2073570745
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1071876206
Short name T833
Test name
Test status
Simulation time 72009983 ps
CPU time 0.77 seconds
Started Aug 01 06:48:09 PM PDT 24
Finished Aug 01 06:48:10 PM PDT 24
Peak memory 205892 kb
Host smart-3d2ea3aa-9c0d-409d-9226-7052b4290719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071876206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1071876206
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2685823792
Short name T693
Test name
Test status
Simulation time 97773537773 ps
CPU time 178.32 seconds
Started Aug 01 06:48:09 PM PDT 24
Finished Aug 01 06:51:08 PM PDT 24
Peak memory 252156 kb
Host smart-5c5bfcc7-733f-4aa0-b4e0-f48a45b3037f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685823792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2685823792
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1008709690
Short name T266
Test name
Test status
Simulation time 2080187787 ps
CPU time 16.44 seconds
Started Aug 01 06:48:16 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 219572 kb
Host smart-e63b7320-98da-4cc7-bca9-b0f70b159d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008709690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1008709690
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3018577261
Short name T138
Test name
Test status
Simulation time 2112315329 ps
CPU time 44.33 seconds
Started Aug 01 06:48:16 PM PDT 24
Finished Aug 01 06:49:00 PM PDT 24
Peak memory 253424 kb
Host smart-cd710fae-b10d-4552-91ae-f4080ef3d9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018577261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3018577261
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1811228190
Short name T762
Test name
Test status
Simulation time 2223033989 ps
CPU time 18.2 seconds
Started Aug 01 06:48:10 PM PDT 24
Finished Aug 01 06:48:29 PM PDT 24
Peak memory 233288 kb
Host smart-dae8e945-5d1e-4b59-8fab-c2ac373352f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811228190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1811228190
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2434335831
Short name T164
Test name
Test status
Simulation time 51023771641 ps
CPU time 176.28 seconds
Started Aug 01 06:48:07 PM PDT 24
Finished Aug 01 06:51:03 PM PDT 24
Peak memory 249576 kb
Host smart-bb3066d8-8cf1-4839-a348-2f7f6095d7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434335831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2434335831
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1431291077
Short name T524
Test name
Test status
Simulation time 355018175 ps
CPU time 3.48 seconds
Started Aug 01 06:48:10 PM PDT 24
Finished Aug 01 06:48:14 PM PDT 24
Peak memory 233124 kb
Host smart-c2c79096-9e2a-4488-9fe5-3c9837cc7c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431291077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1431291077
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3947907036
Short name T428
Test name
Test status
Simulation time 39455292069 ps
CPU time 79.89 seconds
Started Aug 01 06:48:08 PM PDT 24
Finished Aug 01 06:49:28 PM PDT 24
Peak memory 234256 kb
Host smart-85d07fd5-5533-438e-ab8a-97d9ef1a24ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947907036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3947907036
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1265264858
Short name T674
Test name
Test status
Simulation time 518494955 ps
CPU time 3.03 seconds
Started Aug 01 06:48:08 PM PDT 24
Finished Aug 01 06:48:11 PM PDT 24
Peak memory 224848 kb
Host smart-a42aa07a-79cf-4e44-bc32-0a4695deb246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265264858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1265264858
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3464869787
Short name T695
Test name
Test status
Simulation time 577969446 ps
CPU time 3.73 seconds
Started Aug 01 06:48:08 PM PDT 24
Finished Aug 01 06:48:12 PM PDT 24
Peak memory 224896 kb
Host smart-1fc5aafe-7767-4af8-bf48-1c7f19a638f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464869787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3464869787
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3594700325
Short name T669
Test name
Test status
Simulation time 237535413 ps
CPU time 3.85 seconds
Started Aug 01 06:48:09 PM PDT 24
Finished Aug 01 06:48:13 PM PDT 24
Peak memory 220668 kb
Host smart-0e1528be-5a9c-477a-a4bb-1312689be523
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3594700325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3594700325
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.583208451
Short name T456
Test name
Test status
Simulation time 2704232204 ps
CPU time 18.02 seconds
Started Aug 01 06:48:11 PM PDT 24
Finished Aug 01 06:48:29 PM PDT 24
Peak memory 216824 kb
Host smart-065796be-1877-4ad7-9634-0e5ca59cd2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583208451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.583208451
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1650467840
Short name T530
Test name
Test status
Simulation time 1452042501 ps
CPU time 6.03 seconds
Started Aug 01 06:48:10 PM PDT 24
Finished Aug 01 06:48:16 PM PDT 24
Peak memory 216528 kb
Host smart-3d749b4a-9f38-4151-a6a0-ef34ef23129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650467840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1650467840
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1635842523
Short name T489
Test name
Test status
Simulation time 361726953 ps
CPU time 1.67 seconds
Started Aug 01 06:48:12 PM PDT 24
Finished Aug 01 06:48:14 PM PDT 24
Peak memory 216672 kb
Host smart-9fb852cd-1894-4af7-9f84-e87f576c7b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635842523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1635842523
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2954944574
Short name T807
Test name
Test status
Simulation time 17950103 ps
CPU time 0.75 seconds
Started Aug 01 06:48:11 PM PDT 24
Finished Aug 01 06:48:12 PM PDT 24
Peak memory 206364 kb
Host smart-94c4b6ed-b131-43e0-9802-d550c02a0c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954944574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2954944574
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3738124189
Short name T566
Test name
Test status
Simulation time 311475294 ps
CPU time 5.42 seconds
Started Aug 01 06:48:09 PM PDT 24
Finished Aug 01 06:48:15 PM PDT 24
Peak memory 224816 kb
Host smart-082fd5a1-588c-4a7d-a1e7-0d067876c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738124189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3738124189
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1325021598
Short name T50
Test name
Test status
Simulation time 13447675 ps
CPU time 0.76 seconds
Started Aug 01 06:48:19 PM PDT 24
Finished Aug 01 06:48:20 PM PDT 24
Peak memory 205876 kb
Host smart-e64f53f2-b54d-4761-a2f2-6373d363d23b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325021598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1325021598
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2009290392
Short name T725
Test name
Test status
Simulation time 2070416788 ps
CPU time 15.76 seconds
Started Aug 01 06:48:12 PM PDT 24
Finished Aug 01 06:48:27 PM PDT 24
Peak memory 233076 kb
Host smart-59512563-898d-443d-b91e-028708380240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009290392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2009290392
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2983515044
Short name T286
Test name
Test status
Simulation time 22681129 ps
CPU time 0.76 seconds
Started Aug 01 06:48:08 PM PDT 24
Finished Aug 01 06:48:09 PM PDT 24
Peak memory 207356 kb
Host smart-a3bee1fa-ff95-484d-b086-fe5cf63f779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983515044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2983515044
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.422418776
Short name T165
Test name
Test status
Simulation time 52539006248 ps
CPU time 56.32 seconds
Started Aug 01 06:48:17 PM PDT 24
Finished Aug 01 06:49:13 PM PDT 24
Peak memory 249644 kb
Host smart-ed2ca235-06fd-4169-910a-93f8ca66feda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422418776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.422418776
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.190615634
Short name T925
Test name
Test status
Simulation time 84950609473 ps
CPU time 733.84 seconds
Started Aug 01 06:48:22 PM PDT 24
Finished Aug 01 07:00:36 PM PDT 24
Peak memory 267812 kb
Host smart-77c57643-d195-4511-ac73-e997adcbd1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190615634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.190615634
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3994172927
Short name T883
Test name
Test status
Simulation time 4337473068 ps
CPU time 25.71 seconds
Started Aug 01 06:48:19 PM PDT 24
Finished Aug 01 06:48:45 PM PDT 24
Peak memory 253844 kb
Host smart-093b72c9-4e02-425e-95cd-f3c5c0096b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994172927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3994172927
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.553092418
Short name T443
Test name
Test status
Simulation time 8324435444 ps
CPU time 27.63 seconds
Started Aug 01 06:48:09 PM PDT 24
Finished Aug 01 06:48:37 PM PDT 24
Peak memory 241344 kb
Host smart-d848df21-9f83-46a6-80a8-fed4781ae954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553092418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.553092418
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2100762413
Short name T453
Test name
Test status
Simulation time 2108388731 ps
CPU time 37.34 seconds
Started Aug 01 06:48:11 PM PDT 24
Finished Aug 01 06:48:48 PM PDT 24
Peak memory 249524 kb
Host smart-8f495f08-5f8c-4df2-be48-555f3809d30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100762413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2100762413
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2801279111
Short name T219
Test name
Test status
Simulation time 8731035062 ps
CPU time 5.48 seconds
Started Aug 01 06:48:12 PM PDT 24
Finished Aug 01 06:48:18 PM PDT 24
Peak memory 233176 kb
Host smart-1f9e4fee-827f-4fc1-a4db-5af981fd64a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801279111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2801279111
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2646174498
Short name T323
Test name
Test status
Simulation time 5304641368 ps
CPU time 30.85 seconds
Started Aug 01 06:48:10 PM PDT 24
Finished Aug 01 06:48:41 PM PDT 24
Peak memory 249604 kb
Host smart-cc1e79a2-8918-4861-bdd8-a0cd4e3d536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646174498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2646174498
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3622297453
Short name T198
Test name
Test status
Simulation time 2944041200 ps
CPU time 10.07 seconds
Started Aug 01 06:48:08 PM PDT 24
Finished Aug 01 06:48:18 PM PDT 24
Peak memory 241148 kb
Host smart-06fce0f4-3aad-4b69-853c-761b94111978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622297453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3622297453
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.251971392
Short name T967
Test name
Test status
Simulation time 515880134 ps
CPU time 2.29 seconds
Started Aug 01 06:48:15 PM PDT 24
Finished Aug 01 06:48:18 PM PDT 24
Peak memory 224312 kb
Host smart-238c8bf8-0d39-4ea4-872b-9b6d9b0b1028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251971392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.251971392
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2707454971
Short name T691
Test name
Test status
Simulation time 702789113 ps
CPU time 6.94 seconds
Started Aug 01 06:48:07 PM PDT 24
Finished Aug 01 06:48:14 PM PDT 24
Peak memory 223424 kb
Host smart-068539f2-8f06-45ca-8031-01c8323f124d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2707454971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2707454971
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.348520502
Short name T639
Test name
Test status
Simulation time 50605460221 ps
CPU time 479.03 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:56:19 PM PDT 24
Peak memory 267004 kb
Host smart-440302c4-0f68-4209-9af5-e3cea42e7f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348520502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.348520502
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1704019862
Short name T303
Test name
Test status
Simulation time 1380256227 ps
CPU time 4.59 seconds
Started Aug 01 06:48:17 PM PDT 24
Finished Aug 01 06:48:22 PM PDT 24
Peak memory 216996 kb
Host smart-b9b7d9a8-67e6-4324-b4c6-210f357336ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704019862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1704019862
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.558603016
Short name T653
Test name
Test status
Simulation time 1286746132 ps
CPU time 4.14 seconds
Started Aug 01 06:48:10 PM PDT 24
Finished Aug 01 06:48:14 PM PDT 24
Peak memory 216680 kb
Host smart-378b94b1-ad01-4ead-b4f1-2422d73b68e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558603016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.558603016
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1318323817
Short name T950
Test name
Test status
Simulation time 66536595 ps
CPU time 1.01 seconds
Started Aug 01 06:48:16 PM PDT 24
Finished Aug 01 06:48:17 PM PDT 24
Peak memory 207316 kb
Host smart-76e1925a-300f-4d8d-8c0d-d5db2a17b8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318323817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1318323817
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2755124465
Short name T894
Test name
Test status
Simulation time 152402168 ps
CPU time 0.85 seconds
Started Aug 01 06:48:12 PM PDT 24
Finished Aug 01 06:48:13 PM PDT 24
Peak memory 206332 kb
Host smart-3d72bf2c-9473-4c62-a1f6-827a7376f9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755124465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2755124465
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.95029565
Short name T195
Test name
Test status
Simulation time 10572372759 ps
CPU time 10.46 seconds
Started Aug 01 06:48:10 PM PDT 24
Finished Aug 01 06:48:20 PM PDT 24
Peak memory 233168 kb
Host smart-785c6953-0858-4b2d-91e5-d2393c49938f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95029565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.95029565
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1141585470
Short name T289
Test name
Test status
Simulation time 44346267 ps
CPU time 0.71 seconds
Started Aug 01 06:48:21 PM PDT 24
Finished Aug 01 06:48:22 PM PDT 24
Peak memory 206148 kb
Host smart-3acc7417-c510-4d1e-bdf8-b98214cf09cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141585470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1141585470
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4271897148
Short name T842
Test name
Test status
Simulation time 1424146019 ps
CPU time 5.05 seconds
Started Aug 01 06:48:22 PM PDT 24
Finished Aug 01 06:48:27 PM PDT 24
Peak memory 233048 kb
Host smart-45b81503-3bf4-4df6-bbb3-dfd5c1853809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271897148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4271897148
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1205679663
Short name T23
Test name
Test status
Simulation time 15255067 ps
CPU time 0.74 seconds
Started Aug 01 06:48:19 PM PDT 24
Finished Aug 01 06:48:20 PM PDT 24
Peak memory 206924 kb
Host smart-ae88786a-87ef-47b5-a962-85345ee271ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205679663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1205679663
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2871014893
Short name T497
Test name
Test status
Simulation time 31409213076 ps
CPU time 52.87 seconds
Started Aug 01 06:48:17 PM PDT 24
Finished Aug 01 06:49:10 PM PDT 24
Peak memory 238476 kb
Host smart-4523dc68-55a7-4a60-9863-56205ead50cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871014893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2871014893
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4137618344
Short name T836
Test name
Test status
Simulation time 85378683124 ps
CPU time 38.82 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:59 PM PDT 24
Peak memory 225016 kb
Host smart-d69c0741-916c-4787-b253-61162bc604e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137618344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4137618344
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4139228027
Short name T38
Test name
Test status
Simulation time 215315678126 ps
CPU time 473.37 seconds
Started Aug 01 06:48:18 PM PDT 24
Finished Aug 01 06:56:12 PM PDT 24
Peak memory 255868 kb
Host smart-f1239ee3-d7bd-41d2-8fc6-dbc8295701f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139228027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4139228027
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.605965942
Short name T737
Test name
Test status
Simulation time 205330286 ps
CPU time 2.6 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:23 PM PDT 24
Peak memory 233132 kb
Host smart-d8c0dea2-16d7-465b-8673-786af902792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605965942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.605965942
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1933240342
Short name T237
Test name
Test status
Simulation time 8489522501 ps
CPU time 36.14 seconds
Started Aug 01 06:48:17 PM PDT 24
Finished Aug 01 06:48:54 PM PDT 24
Peak memory 241332 kb
Host smart-379ca0c1-dd84-49de-950f-8a39622647e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933240342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1933240342
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1208174515
Short name T571
Test name
Test status
Simulation time 8476316803 ps
CPU time 12.3 seconds
Started Aug 01 06:48:19 PM PDT 24
Finished Aug 01 06:48:32 PM PDT 24
Peak memory 225024 kb
Host smart-00f2fd66-6f59-4282-a3ae-5ff0da3ed059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208174515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1208174515
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3765361293
Short name T698
Test name
Test status
Simulation time 16721357501 ps
CPU time 37.33 seconds
Started Aug 01 06:48:19 PM PDT 24
Finished Aug 01 06:48:57 PM PDT 24
Peak memory 233188 kb
Host smart-c96cd245-dd39-42ab-8257-e817901dd9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765361293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3765361293
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1705752457
Short name T824
Test name
Test status
Simulation time 725475661 ps
CPU time 6.67 seconds
Started Aug 01 06:48:18 PM PDT 24
Finished Aug 01 06:48:25 PM PDT 24
Peak memory 233108 kb
Host smart-095ce90d-cc0c-4581-a21f-9434109d2988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705752457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1705752457
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1013314634
Short name T958
Test name
Test status
Simulation time 1228779651 ps
CPU time 7.76 seconds
Started Aug 01 06:48:19 PM PDT 24
Finished Aug 01 06:48:27 PM PDT 24
Peak memory 233108 kb
Host smart-c101b08f-bb55-477e-bec5-94f9afd57ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013314634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1013314634
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.777267919
Short name T714
Test name
Test status
Simulation time 319335963 ps
CPU time 3.8 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:24 PM PDT 24
Peak memory 219624 kb
Host smart-37d2f6be-a90a-42c2-beca-e17741fd07d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=777267919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.777267919
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3641734426
Short name T15
Test name
Test status
Simulation time 3011262654 ps
CPU time 49.55 seconds
Started Aug 01 06:48:18 PM PDT 24
Finished Aug 01 06:49:08 PM PDT 24
Peak memory 249648 kb
Host smart-25f2d389-4758-428d-9fe7-132d21351aac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641734426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3641734426
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1214487244
Short name T268
Test name
Test status
Simulation time 7090762961 ps
CPU time 3.2 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:23 PM PDT 24
Peak memory 216800 kb
Host smart-cf7644e1-0802-4319-b125-c0b2ceb63bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214487244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1214487244
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.498199482
Short name T648
Test name
Test status
Simulation time 1096545154 ps
CPU time 4.8 seconds
Started Aug 01 06:48:21 PM PDT 24
Finished Aug 01 06:48:25 PM PDT 24
Peak memory 216612 kb
Host smart-c45a5ac0-5c73-43d8-8e01-1636ed24f2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498199482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.498199482
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1530626663
Short name T888
Test name
Test status
Simulation time 24951143 ps
CPU time 0.82 seconds
Started Aug 01 06:48:20 PM PDT 24
Finished Aug 01 06:48:21 PM PDT 24
Peak memory 207340 kb
Host smart-9a4eb0f2-377d-43ba-9c33-44bad0fb2f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530626663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1530626663
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.822861788
Short name T735
Test name
Test status
Simulation time 291851187 ps
CPU time 0.88 seconds
Started Aug 01 06:48:18 PM PDT 24
Finished Aug 01 06:48:19 PM PDT 24
Peak memory 206300 kb
Host smart-9c87da8e-3a0e-443d-aef4-8fc30ef594b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822861788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.822861788
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3945654736
Short name T315
Test name
Test status
Simulation time 1915417145 ps
CPU time 7.09 seconds
Started Aug 01 06:48:17 PM PDT 24
Finished Aug 01 06:48:24 PM PDT 24
Peak memory 224908 kb
Host smart-4d0425c9-0be0-4487-abef-63bc46ed18fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945654736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3945654736
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2771333914
Short name T910
Test name
Test status
Simulation time 13466769 ps
CPU time 0.73 seconds
Started Aug 01 06:45:18 PM PDT 24
Finished Aug 01 06:45:19 PM PDT 24
Peak memory 205800 kb
Host smart-b6420d1f-8403-4934-906b-a8132c1a7e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771333914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
771333914
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.327797050
Short name T454
Test name
Test status
Simulation time 229441362 ps
CPU time 3.03 seconds
Started Aug 01 06:45:21 PM PDT 24
Finished Aug 01 06:45:24 PM PDT 24
Peak memory 233136 kb
Host smart-892b7368-e2e8-4825-a95d-c783f6a2a219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327797050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.327797050
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3530383981
Short name T464
Test name
Test status
Simulation time 14687992 ps
CPU time 0.8 seconds
Started Aug 01 06:45:14 PM PDT 24
Finished Aug 01 06:45:15 PM PDT 24
Peak memory 206976 kb
Host smart-c318af71-5cc4-4bd3-97dc-fd19257cc7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530383981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3530383981
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3948126627
Short name T196
Test name
Test status
Simulation time 606875868346 ps
CPU time 246.92 seconds
Started Aug 01 06:45:16 PM PDT 24
Finished Aug 01 06:49:23 PM PDT 24
Peak memory 252548 kb
Host smart-bbc42b85-56f4-499f-9ecc-e455c266157e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948126627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3948126627
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.661457126
Short name T868
Test name
Test status
Simulation time 7457563184 ps
CPU time 57.66 seconds
Started Aug 01 06:45:16 PM PDT 24
Finished Aug 01 06:46:14 PM PDT 24
Peak memory 255592 kb
Host smart-1cbffe56-cc35-45ea-87cb-3e1a5135b9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661457126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.661457126
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1191625970
Short name T753
Test name
Test status
Simulation time 19823699197 ps
CPU time 91.12 seconds
Started Aug 01 06:45:15 PM PDT 24
Finished Aug 01 06:46:47 PM PDT 24
Peak memory 237672 kb
Host smart-6997da8b-d179-480f-bea3-f349384c3493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191625970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1191625970
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2422792241
Short name T629
Test name
Test status
Simulation time 9571978397 ps
CPU time 33.22 seconds
Started Aug 01 06:45:21 PM PDT 24
Finished Aug 01 06:45:55 PM PDT 24
Peak memory 233224 kb
Host smart-275bad43-822f-4059-a1cb-bda258473e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422792241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2422792241
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.30319825
Short name T181
Test name
Test status
Simulation time 72341324512 ps
CPU time 486.65 seconds
Started Aug 01 06:45:15 PM PDT 24
Finished Aug 01 06:53:22 PM PDT 24
Peak memory 261652 kb
Host smart-6f322b63-ac76-401b-bc61-bc4d46032df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30319825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.30319825
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.61544304
Short name T679
Test name
Test status
Simulation time 8532647775 ps
CPU time 15.31 seconds
Started Aug 01 06:45:15 PM PDT 24
Finished Aug 01 06:45:31 PM PDT 24
Peak memory 229512 kb
Host smart-57926724-c076-47ae-bc6a-fca4506628b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61544304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.61544304
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3038754421
Short name T901
Test name
Test status
Simulation time 176261427 ps
CPU time 5.21 seconds
Started Aug 01 06:45:15 PM PDT 24
Finished Aug 01 06:45:21 PM PDT 24
Peak memory 233176 kb
Host smart-f2603917-5505-4245-9e30-3d185792ee6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038754421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3038754421
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1214258793
Short name T118
Test name
Test status
Simulation time 63533215 ps
CPU time 2.47 seconds
Started Aug 01 06:45:17 PM PDT 24
Finished Aug 01 06:45:20 PM PDT 24
Peak memory 232792 kb
Host smart-51f93c85-2eac-4de8-a870-84f7b5a9d55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214258793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1214258793
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2667147901
Short name T568
Test name
Test status
Simulation time 244680561 ps
CPU time 3.18 seconds
Started Aug 01 06:45:16 PM PDT 24
Finished Aug 01 06:45:19 PM PDT 24
Peak memory 233084 kb
Host smart-c68fa6b7-2c6c-44b9-b98c-fb52bed6168d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667147901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2667147901
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.487489030
Short name T559
Test name
Test status
Simulation time 531528515 ps
CPU time 4.91 seconds
Started Aug 01 06:45:16 PM PDT 24
Finished Aug 01 06:45:21 PM PDT 24
Peak memory 221076 kb
Host smart-d3081767-89e3-427a-b47c-867ee21566c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=487489030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.487489030
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.84731704
Short name T56
Test name
Test status
Simulation time 2882299841 ps
CPU time 35.81 seconds
Started Aug 01 06:45:19 PM PDT 24
Finished Aug 01 06:45:55 PM PDT 24
Peak memory 233268 kb
Host smart-baa4293d-8a1c-4d74-8cd9-6d23f6170d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84731704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_
all.84731704
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2787287782
Short name T717
Test name
Test status
Simulation time 349072091 ps
CPU time 5.27 seconds
Started Aug 01 06:45:15 PM PDT 24
Finished Aug 01 06:45:21 PM PDT 24
Peak memory 216828 kb
Host smart-5ac9f71e-b6ab-40f5-b020-dced18f11c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787287782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2787287782
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.166678575
Short name T313
Test name
Test status
Simulation time 29298920083 ps
CPU time 17.89 seconds
Started Aug 01 06:45:15 PM PDT 24
Finished Aug 01 06:45:33 PM PDT 24
Peak memory 219076 kb
Host smart-86913c18-a102-488d-b7fc-41b42a22e548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166678575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.166678575
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3692188997
Short name T301
Test name
Test status
Simulation time 944738713 ps
CPU time 9.19 seconds
Started Aug 01 06:45:21 PM PDT 24
Finished Aug 01 06:45:31 PM PDT 24
Peak memory 216624 kb
Host smart-72068acb-541a-4fa9-b720-ec1d7ae58f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692188997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3692188997
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2666654297
Short name T398
Test name
Test status
Simulation time 31604734 ps
CPU time 0.86 seconds
Started Aug 01 06:45:21 PM PDT 24
Finished Aug 01 06:45:22 PM PDT 24
Peak memory 206376 kb
Host smart-afe03446-8348-4013-8ed9-1743c203930e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666654297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2666654297
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.662639569
Short name T37
Test name
Test status
Simulation time 353990759 ps
CPU time 6.57 seconds
Started Aug 01 06:45:17 PM PDT 24
Finished Aug 01 06:45:23 PM PDT 24
Peak memory 233076 kb
Host smart-8fc43295-b907-4b33-992e-110471b00108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662639569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.662639569
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1299054030
Short name T449
Test name
Test status
Simulation time 39166706 ps
CPU time 0.69 seconds
Started Aug 01 06:45:20 PM PDT 24
Finished Aug 01 06:45:21 PM PDT 24
Peak memory 205212 kb
Host smart-7d18f8c4-3c0b-4196-bdae-65e1e8784b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299054030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
299054030
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3358377356
Short name T609
Test name
Test status
Simulation time 1111701281 ps
CPU time 9.7 seconds
Started Aug 01 06:45:19 PM PDT 24
Finished Aug 01 06:45:29 PM PDT 24
Peak memory 224924 kb
Host smart-bcd811e5-41bd-44f1-9a8a-4eb0977fa811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358377356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3358377356
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2127251282
Short name T297
Test name
Test status
Simulation time 60287808 ps
CPU time 0.79 seconds
Started Aug 01 06:45:15 PM PDT 24
Finished Aug 01 06:45:16 PM PDT 24
Peak memory 207256 kb
Host smart-fb26f46d-8804-4d80-ab5e-8dfd5a077e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127251282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2127251282
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3422128828
Short name T929
Test name
Test status
Simulation time 16088981108 ps
CPU time 118.32 seconds
Started Aug 01 06:45:21 PM PDT 24
Finished Aug 01 06:47:19 PM PDT 24
Peak memory 249856 kb
Host smart-cd17ddf0-28da-4103-ab58-e6a09850923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422128828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3422128828
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.609648797
Short name T415
Test name
Test status
Simulation time 35705635 ps
CPU time 0.82 seconds
Started Aug 01 06:45:20 PM PDT 24
Finished Aug 01 06:45:21 PM PDT 24
Peak memory 217644 kb
Host smart-b297f70a-37e1-4d93-9e2d-d4857f320ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609648797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.609648797
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.505950007
Short name T251
Test name
Test status
Simulation time 16159945954 ps
CPU time 114.66 seconds
Started Aug 01 06:45:20 PM PDT 24
Finished Aug 01 06:47:15 PM PDT 24
Peak memory 250596 kb
Host smart-8d340c3c-a324-42f3-864d-2c9bce0daf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505950007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
505950007
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3997068700
Short name T260
Test name
Test status
Simulation time 7850480187 ps
CPU time 59.55 seconds
Started Aug 01 06:45:18 PM PDT 24
Finished Aug 01 06:46:18 PM PDT 24
Peak memory 241400 kb
Host smart-6cbb2ab5-864b-4c50-a943-6ea01cc9c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997068700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3997068700
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3741158127
Short name T171
Test name
Test status
Simulation time 23606878461 ps
CPU time 182.07 seconds
Started Aug 01 06:45:20 PM PDT 24
Finished Aug 01 06:48:23 PM PDT 24
Peak memory 254072 kb
Host smart-8dbf6269-b856-4684-848b-3710279c7a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741158127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3741158127
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2029680152
Short name T209
Test name
Test status
Simulation time 551723171 ps
CPU time 5.71 seconds
Started Aug 01 06:45:16 PM PDT 24
Finished Aug 01 06:45:22 PM PDT 24
Peak memory 233176 kb
Host smart-3e9dc6b4-5c95-42b5-977c-907e007914ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029680152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2029680152
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1284196929
Short name T939
Test name
Test status
Simulation time 2305577757 ps
CPU time 6.65 seconds
Started Aug 01 06:45:19 PM PDT 24
Finished Aug 01 06:45:26 PM PDT 24
Peak memory 233188 kb
Host smart-89e94407-78d6-4cbc-ae49-24be4fa209d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284196929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1284196929
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2535786901
Short name T484
Test name
Test status
Simulation time 147008563 ps
CPU time 2.29 seconds
Started Aug 01 06:45:18 PM PDT 24
Finished Aug 01 06:45:21 PM PDT 24
Peak memory 224800 kb
Host smart-a4da227e-2656-4339-a908-6dff873e94a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535786901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2535786901
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1826550443
Short name T856
Test name
Test status
Simulation time 1218363233 ps
CPU time 4.87 seconds
Started Aug 01 06:45:17 PM PDT 24
Finished Aug 01 06:45:22 PM PDT 24
Peak memory 225144 kb
Host smart-43652ccb-f221-4849-866c-ca10f7c500c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826550443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1826550443
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.945139152
Short name T470
Test name
Test status
Simulation time 4880551536 ps
CPU time 7.31 seconds
Started Aug 01 06:45:19 PM PDT 24
Finished Aug 01 06:45:26 PM PDT 24
Peak memory 219756 kb
Host smart-a88afe5d-7c21-4596-8217-8decd1b54cf7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=945139152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.945139152
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1563219294
Short name T881
Test name
Test status
Simulation time 160170334569 ps
CPU time 135.96 seconds
Started Aug 01 06:45:17 PM PDT 24
Finished Aug 01 06:47:34 PM PDT 24
Peak memory 249988 kb
Host smart-78246bf3-b532-4a51-9bcb-28f3717cd8c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563219294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1563219294
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3286250579
Short name T870
Test name
Test status
Simulation time 9214394782 ps
CPU time 9.68 seconds
Started Aug 01 06:45:17 PM PDT 24
Finished Aug 01 06:45:27 PM PDT 24
Peak memory 216652 kb
Host smart-4f04007f-efba-44e0-b758-58a454c989a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286250579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3286250579
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4263228344
Short name T475
Test name
Test status
Simulation time 6998461850 ps
CPU time 7.16 seconds
Started Aug 01 06:45:19 PM PDT 24
Finished Aug 01 06:45:27 PM PDT 24
Peak memory 216708 kb
Host smart-cf58ea29-8c23-4c97-a15c-eb45ad3d15f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263228344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4263228344
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3069287843
Short name T793
Test name
Test status
Simulation time 140276272 ps
CPU time 0.97 seconds
Started Aug 01 06:45:17 PM PDT 24
Finished Aug 01 06:45:18 PM PDT 24
Peak memory 207308 kb
Host smart-02cb7c1c-7371-4862-a407-a84d038fd4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069287843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3069287843
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3353981385
Short name T281
Test name
Test status
Simulation time 18888714 ps
CPU time 0.74 seconds
Started Aug 01 06:45:21 PM PDT 24
Finished Aug 01 06:45:22 PM PDT 24
Peak memory 206368 kb
Host smart-b3d89259-d4b7-43db-bb9a-a878ec1643e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353981385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3353981385
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.4122643276
Short name T788
Test name
Test status
Simulation time 22335174837 ps
CPU time 14.98 seconds
Started Aug 01 06:45:19 PM PDT 24
Finished Aug 01 06:45:34 PM PDT 24
Peak memory 224988 kb
Host smart-a199da44-7df6-4cd7-ace0-944423ca6ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122643276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4122643276
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.708476068
Short name T284
Test name
Test status
Simulation time 35358449 ps
CPU time 0.72 seconds
Started Aug 01 06:45:30 PM PDT 24
Finished Aug 01 06:45:30 PM PDT 24
Peak memory 205212 kb
Host smart-83be444c-01be-4154-bbf9-5242ad08059b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708476068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.708476068
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2699895565
Short name T1003
Test name
Test status
Simulation time 1328271285 ps
CPU time 6.25 seconds
Started Aug 01 06:45:28 PM PDT 24
Finished Aug 01 06:45:34 PM PDT 24
Peak memory 233124 kb
Host smart-44812fdd-6d49-4625-aeca-1f1e11ec6302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699895565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2699895565
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1932717366
Short name T949
Test name
Test status
Simulation time 22698869 ps
CPU time 0.81 seconds
Started Aug 01 06:45:19 PM PDT 24
Finished Aug 01 06:45:20 PM PDT 24
Peak memory 207052 kb
Host smart-35101f65-2d5e-426b-964c-d12b3a735988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932717366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1932717366
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1248297341
Short name T557
Test name
Test status
Simulation time 4853494761 ps
CPU time 22.63 seconds
Started Aug 01 06:45:28 PM PDT 24
Finished Aug 01 06:45:51 PM PDT 24
Peak memory 225044 kb
Host smart-61fdf818-7a88-4017-888a-b7b36c730ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248297341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1248297341
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3000222195
Short name T147
Test name
Test status
Simulation time 1657185777 ps
CPU time 16.16 seconds
Started Aug 01 06:45:27 PM PDT 24
Finished Aug 01 06:45:43 PM PDT 24
Peak memory 224972 kb
Host smart-546f1cf6-981e-4bd2-8be3-2c6359ee1403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000222195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3000222195
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2738714852
Short name T1001
Test name
Test status
Simulation time 66468388705 ps
CPU time 128.47 seconds
Started Aug 01 06:45:30 PM PDT 24
Finished Aug 01 06:47:39 PM PDT 24
Peak memory 241404 kb
Host smart-90960ca5-4a4e-4d55-989b-0b2a55e279a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738714852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2738714852
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3829619649
Short name T1002
Test name
Test status
Simulation time 467574179 ps
CPU time 3.91 seconds
Started Aug 01 06:45:24 PM PDT 24
Finished Aug 01 06:45:28 PM PDT 24
Peak memory 233084 kb
Host smart-50ea7610-f50a-4e8e-b1cc-cb1583c4bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829619649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3829619649
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3114626004
Short name T983
Test name
Test status
Simulation time 6474235542 ps
CPU time 48.27 seconds
Started Aug 01 06:45:26 PM PDT 24
Finished Aug 01 06:46:15 PM PDT 24
Peak memory 255372 kb
Host smart-eba6ad84-664d-42c3-8152-83acc04eff34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114626004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3114626004
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1459774360
Short name T97
Test name
Test status
Simulation time 2646734875 ps
CPU time 10.62 seconds
Started Aug 01 06:45:24 PM PDT 24
Finished Aug 01 06:45:35 PM PDT 24
Peak memory 233136 kb
Host smart-3dd98644-e3fb-4797-8fad-f28b8c8b1839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459774360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1459774360
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2816505084
Short name T321
Test name
Test status
Simulation time 3515356270 ps
CPU time 10.22 seconds
Started Aug 01 06:45:29 PM PDT 24
Finished Aug 01 06:45:39 PM PDT 24
Peak memory 233176 kb
Host smart-031d65a0-999b-4a28-9dc4-98824432ed69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816505084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2816505084
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3537945297
Short name T789
Test name
Test status
Simulation time 7472960481 ps
CPU time 11.49 seconds
Started Aug 01 06:45:26 PM PDT 24
Finished Aug 01 06:45:38 PM PDT 24
Peak memory 233252 kb
Host smart-3deb36af-b25c-444e-ae39-79d3588d5452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537945297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3537945297
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3331224321
Short name T427
Test name
Test status
Simulation time 210508233 ps
CPU time 2.3 seconds
Started Aug 01 06:45:26 PM PDT 24
Finished Aug 01 06:45:28 PM PDT 24
Peak memory 223772 kb
Host smart-2115da35-0b9a-44ce-8cb6-9d24e8d81152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331224321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3331224321
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3130296038
Short name T976
Test name
Test status
Simulation time 2357718553 ps
CPU time 7.98 seconds
Started Aug 01 06:45:31 PM PDT 24
Finished Aug 01 06:45:39 PM PDT 24
Peak memory 223204 kb
Host smart-25f72411-b196-45eb-8bde-0fb7eb6ffac8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3130296038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3130296038
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2766201236
Short name T135
Test name
Test status
Simulation time 63560683035 ps
CPU time 149.96 seconds
Started Aug 01 06:45:30 PM PDT 24
Finished Aug 01 06:48:01 PM PDT 24
Peak memory 256340 kb
Host smart-56549557-843d-41fd-a220-cd293a11a1e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766201236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2766201236
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.787429297
Short name T771
Test name
Test status
Simulation time 7477500833 ps
CPU time 45.38 seconds
Started Aug 01 06:45:24 PM PDT 24
Finished Aug 01 06:46:09 PM PDT 24
Peak memory 216880 kb
Host smart-af653bf2-a795-4ea1-9897-3f73bf92d0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787429297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.787429297
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1017254101
Short name T380
Test name
Test status
Simulation time 5078615012 ps
CPU time 4.99 seconds
Started Aug 01 06:45:24 PM PDT 24
Finished Aug 01 06:45:29 PM PDT 24
Peak memory 216692 kb
Host smart-17ee69a9-1f6f-4f13-93cc-870fc2dcd495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017254101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1017254101
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2315776675
Short name T276
Test name
Test status
Simulation time 121269366 ps
CPU time 1.27 seconds
Started Aug 01 06:45:26 PM PDT 24
Finished Aug 01 06:45:27 PM PDT 24
Peak memory 208412 kb
Host smart-b72f03b8-f137-48aa-bd78-bfb2d4c1147a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315776675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2315776675
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1896611549
Short name T618
Test name
Test status
Simulation time 47612502 ps
CPU time 0.82 seconds
Started Aug 01 06:45:27 PM PDT 24
Finished Aug 01 06:45:28 PM PDT 24
Peak memory 206320 kb
Host smart-7f8d9f6b-28d7-49f9-a187-b228a7c5dff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896611549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1896611549
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.984659170
Short name T706
Test name
Test status
Simulation time 5612785011 ps
CPU time 21.95 seconds
Started Aug 01 06:45:25 PM PDT 24
Finished Aug 01 06:45:47 PM PDT 24
Peak memory 233100 kb
Host smart-af5cb45d-dfe0-4356-8b02-ab4658d7003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984659170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.984659170
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.4149325369
Short name T390
Test name
Test status
Simulation time 10856014 ps
CPU time 0.74 seconds
Started Aug 01 06:45:30 PM PDT 24
Finished Aug 01 06:45:31 PM PDT 24
Peak memory 205808 kb
Host smart-b659c9c0-4994-4b77-993e-c4001a0f0a89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149325369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4
149325369
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4013739277
Short name T817
Test name
Test status
Simulation time 1216623983 ps
CPU time 12.38 seconds
Started Aug 01 06:45:32 PM PDT 24
Finished Aug 01 06:45:44 PM PDT 24
Peak memory 224776 kb
Host smart-b8e87cf9-9ed6-422b-a5f9-edd2361f229d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013739277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4013739277
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.672938218
Short name T875
Test name
Test status
Simulation time 83191181 ps
CPU time 0.84 seconds
Started Aug 01 06:45:29 PM PDT 24
Finished Aug 01 06:45:30 PM PDT 24
Peak memory 206952 kb
Host smart-b9bbebf8-b0e4-4f04-ba06-953845f7520f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672938218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.672938218
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1829604678
Short name T991
Test name
Test status
Simulation time 7689134785 ps
CPU time 28.54 seconds
Started Aug 01 06:45:30 PM PDT 24
Finished Aug 01 06:45:59 PM PDT 24
Peak memory 235392 kb
Host smart-1c18a6c2-fb01-4cc0-82e0-58f8f9d3ff53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829604678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1829604678
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.74611752
Short name T244
Test name
Test status
Simulation time 21821296062 ps
CPU time 87.9 seconds
Started Aug 01 06:45:29 PM PDT 24
Finished Aug 01 06:46:57 PM PDT 24
Peak memory 255912 kb
Host smart-4d249c63-4af5-412e-96ab-e6b74e3c1a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74611752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.74611752
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3405326742
Short name T943
Test name
Test status
Simulation time 8493387676 ps
CPU time 75.2 seconds
Started Aug 01 06:45:30 PM PDT 24
Finished Aug 01 06:46:46 PM PDT 24
Peak memory 239296 kb
Host smart-cdb7ac0e-a776-42df-b2dd-293c0b4ff2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405326742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3405326742
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4213666374
Short name T339
Test name
Test status
Simulation time 268968129 ps
CPU time 8.41 seconds
Started Aug 01 06:45:34 PM PDT 24
Finished Aug 01 06:45:43 PM PDT 24
Peak memory 250016 kb
Host smart-71e88cd3-675f-4fa1-9fff-5f2bddd71255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213666374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4213666374
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1561686225
Short name T564
Test name
Test status
Simulation time 945269452 ps
CPU time 13.89 seconds
Started Aug 01 06:45:27 PM PDT 24
Finished Aug 01 06:45:41 PM PDT 24
Peak memory 224940 kb
Host smart-92a583ec-9e88-45ca-a45f-9e7536a8fcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561686225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1561686225
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2777950002
Short name T469
Test name
Test status
Simulation time 18950964094 ps
CPU time 112.02 seconds
Started Aug 01 06:45:26 PM PDT 24
Finished Aug 01 06:47:19 PM PDT 24
Peak memory 233256 kb
Host smart-76ac6f87-6d69-4b16-b951-b52894b08cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777950002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2777950002
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2383657639
Short name T612
Test name
Test status
Simulation time 3884206895 ps
CPU time 5.73 seconds
Started Aug 01 06:45:29 PM PDT 24
Finished Aug 01 06:45:35 PM PDT 24
Peak memory 233100 kb
Host smart-92c70780-6cb7-46d4-8b1e-1e328125f54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383657639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2383657639
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2775119242
Short name T661
Test name
Test status
Simulation time 1085283037 ps
CPU time 5.8 seconds
Started Aug 01 06:45:28 PM PDT 24
Finished Aug 01 06:45:34 PM PDT 24
Peak memory 224900 kb
Host smart-47baee0d-efab-4179-bd14-b93ddf32041e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775119242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2775119242
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2066675516
Short name T622
Test name
Test status
Simulation time 233189117 ps
CPU time 4.85 seconds
Started Aug 01 06:45:31 PM PDT 24
Finished Aug 01 06:45:36 PM PDT 24
Peak memory 220444 kb
Host smart-c5c65a34-cfe1-42c3-96d6-e6ba4ac0409e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2066675516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2066675516
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3153665119
Short name T971
Test name
Test status
Simulation time 84186180559 ps
CPU time 413.74 seconds
Started Aug 01 06:45:33 PM PDT 24
Finished Aug 01 06:52:27 PM PDT 24
Peak memory 286260 kb
Host smart-7bc7a536-0a8e-4a2d-ac5c-f3e5e3c87c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153665119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3153665119
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1512245133
Short name T927
Test name
Test status
Simulation time 4805558302 ps
CPU time 19.79 seconds
Started Aug 01 06:45:30 PM PDT 24
Finished Aug 01 06:45:50 PM PDT 24
Peak memory 216756 kb
Host smart-cd5396c3-2039-46c2-bdec-99a8dd52c824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512245133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1512245133
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2061755291
Short name T826
Test name
Test status
Simulation time 3608730995 ps
CPU time 5.34 seconds
Started Aug 01 06:45:26 PM PDT 24
Finished Aug 01 06:45:32 PM PDT 24
Peak memory 216704 kb
Host smart-f58a9e6d-59bf-43b1-aa78-a09f90ef59fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061755291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2061755291
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2181367025
Short name T898
Test name
Test status
Simulation time 340345540 ps
CPU time 1.55 seconds
Started Aug 01 06:45:29 PM PDT 24
Finished Aug 01 06:45:31 PM PDT 24
Peak memory 216672 kb
Host smart-ed2f010f-9763-4eee-a1f0-1bcea8b59150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181367025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2181367025
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.648759552
Short name T536
Test name
Test status
Simulation time 35101854 ps
CPU time 0.83 seconds
Started Aug 01 06:45:30 PM PDT 24
Finished Aug 01 06:45:31 PM PDT 24
Peak memory 206324 kb
Host smart-6f61e7ff-813c-4745-96b0-7bba9560204c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648759552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.648759552
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1192964854
Short name T794
Test name
Test status
Simulation time 414503387 ps
CPU time 2.84 seconds
Started Aug 01 06:45:30 PM PDT 24
Finished Aug 01 06:45:33 PM PDT 24
Peak memory 233044 kb
Host smart-e08f307e-1241-4b42-8975-48227d108948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192964854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1192964854
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3113520460
Short name T504
Test name
Test status
Simulation time 28063579 ps
CPU time 0.71 seconds
Started Aug 01 06:45:36 PM PDT 24
Finished Aug 01 06:45:37 PM PDT 24
Peak memory 206100 kb
Host smart-1381640b-5540-4cf0-a790-f2b03d436abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113520460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
113520460
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.370979202
Short name T217
Test name
Test status
Simulation time 381733256 ps
CPU time 5.09 seconds
Started Aug 01 06:45:31 PM PDT 24
Finished Aug 01 06:45:36 PM PDT 24
Peak memory 224940 kb
Host smart-1e10c5c3-b0b2-4f4b-9a80-7f2e87c0d4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370979202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.370979202
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3941389851
Short name T287
Test name
Test status
Simulation time 49228274 ps
CPU time 0.76 seconds
Started Aug 01 06:45:32 PM PDT 24
Finished Aug 01 06:45:33 PM PDT 24
Peak memory 206992 kb
Host smart-116fe562-82f0-42e0-b7ea-6f7c514f89c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941389851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3941389851
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2169466647
Short name T1000
Test name
Test status
Simulation time 3496894540 ps
CPU time 61.9 seconds
Started Aug 01 06:45:26 PM PDT 24
Finished Aug 01 06:46:28 PM PDT 24
Peak memory 251736 kb
Host smart-afb8720d-268e-4d92-8e8b-cfab79c687d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169466647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2169466647
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.77257198
Short name T11
Test name
Test status
Simulation time 113128483269 ps
CPU time 531.58 seconds
Started Aug 01 06:45:36 PM PDT 24
Finished Aug 01 06:54:28 PM PDT 24
Peak memory 272800 kb
Host smart-4a164ff5-a7d1-46f4-9efa-55b282c063c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77257198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.77257198
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2400775131
Short name T944
Test name
Test status
Simulation time 2769402145 ps
CPU time 45.35 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:46:24 PM PDT 24
Peak memory 237480 kb
Host smart-869825fc-ab1e-48eb-afb0-6ddbd8c6a464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400775131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2400775131
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4254865402
Short name T955
Test name
Test status
Simulation time 1315377855 ps
CPU time 8.5 seconds
Started Aug 01 06:45:26 PM PDT 24
Finished Aug 01 06:45:34 PM PDT 24
Peak memory 237828 kb
Host smart-4668bb0e-9725-4c20-9358-9b0ba728ecfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254865402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4254865402
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2714229005
Short name T80
Test name
Test status
Simulation time 1402430125 ps
CPU time 33.02 seconds
Started Aug 01 06:45:42 PM PDT 24
Finished Aug 01 06:46:15 PM PDT 24
Peak memory 251136 kb
Host smart-30455be4-475d-4f80-82d6-963337614c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714229005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2714229005
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.96433116
Short name T179
Test name
Test status
Simulation time 3671716073 ps
CPU time 10.92 seconds
Started Aug 01 06:45:34 PM PDT 24
Finished Aug 01 06:45:45 PM PDT 24
Peak memory 224896 kb
Host smart-53e8ee31-f3f6-4fdb-88f1-cc9670896780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96433116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.96433116
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2543268213
Short name T921
Test name
Test status
Simulation time 20765016784 ps
CPU time 75.02 seconds
Started Aug 01 06:45:34 PM PDT 24
Finished Aug 01 06:46:49 PM PDT 24
Peak memory 234168 kb
Host smart-8a54ef30-3641-4362-82e2-cbef302bec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543268213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2543268213
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1323336651
Short name T187
Test name
Test status
Simulation time 5342892954 ps
CPU time 16.44 seconds
Started Aug 01 06:45:33 PM PDT 24
Finished Aug 01 06:45:49 PM PDT 24
Peak memory 233164 kb
Host smart-dbf4df1c-6edd-4bc6-b0f4-78fb5e202dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323336651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1323336651
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3671716005
Short name T347
Test name
Test status
Simulation time 13756162013 ps
CPU time 12.47 seconds
Started Aug 01 06:45:30 PM PDT 24
Finished Aug 01 06:45:42 PM PDT 24
Peak memory 240004 kb
Host smart-29f64af5-c6ba-4d8a-93d2-7651c8904099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671716005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3671716005
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.285270414
Short name T336
Test name
Test status
Simulation time 958345886 ps
CPU time 7.8 seconds
Started Aug 01 06:45:29 PM PDT 24
Finished Aug 01 06:45:36 PM PDT 24
Peak memory 223536 kb
Host smart-0c520f2f-ae00-46ad-ba7c-cf745b22a379
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=285270414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.285270414
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1740215108
Short name T1004
Test name
Test status
Simulation time 88683378540 ps
CPU time 393.24 seconds
Started Aug 01 06:45:39 PM PDT 24
Finished Aug 01 06:52:12 PM PDT 24
Peak memory 256592 kb
Host smart-152a29d1-6879-45ef-ba00-a036a4a56ed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740215108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1740215108
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1721811930
Short name T274
Test name
Test status
Simulation time 553486808 ps
CPU time 5.43 seconds
Started Aug 01 06:45:29 PM PDT 24
Finished Aug 01 06:45:35 PM PDT 24
Peak memory 216748 kb
Host smart-4433659c-e781-4b6d-804a-c5ec53eb6540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721811930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1721811930
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3409470106
Short name T307
Test name
Test status
Simulation time 3588796206 ps
CPU time 12.17 seconds
Started Aug 01 06:45:34 PM PDT 24
Finished Aug 01 06:45:47 PM PDT 24
Peak memory 216732 kb
Host smart-1de060fb-9687-465b-9476-c3768e8052d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409470106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3409470106
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2397980457
Short name T461
Test name
Test status
Simulation time 184887492 ps
CPU time 1.01 seconds
Started Aug 01 06:45:30 PM PDT 24
Finished Aug 01 06:45:31 PM PDT 24
Peak memory 207500 kb
Host smart-0e571094-8943-4da9-a444-5244d8cd8817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397980457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2397980457
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2458991219
Short name T650
Test name
Test status
Simulation time 172248046 ps
CPU time 0.84 seconds
Started Aug 01 06:45:33 PM PDT 24
Finished Aug 01 06:45:34 PM PDT 24
Peak memory 206320 kb
Host smart-70a990af-3c87-4a82-9501-d30d5c5f236c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458991219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2458991219
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2425346332
Short name T215
Test name
Test status
Simulation time 318881773 ps
CPU time 6.39 seconds
Started Aug 01 06:45:25 PM PDT 24
Finished Aug 01 06:45:31 PM PDT 24
Peak memory 233144 kb
Host smart-a3f2aac4-ae8b-4e74-8f76-10e5e6bb1681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425346332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2425346332
Directory /workspace/9.spi_device_upload/latest
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