Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2761346	1			T1	1		T2	1		T4	1180
all_values[1]	2761346	1			T1	1		T2	1		T4	1180
all_values[2]	2761346	1			T1	1		T2	1		T4	1180
all_values[3]	2761346	1			T1	1		T2	1		T4	1180
all_values[4]	2761346	1			T1	1		T2	1		T4	1180
all_values[5]	2761346	1			T1	1		T2	1		T4	1180
all_values[6]	2761346	1			T1	1		T2	1		T4	1180
all_values[7]	2761346	1			T1	1		T2	1		T4	1180

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21643648

1

T1

8

T2

8

T4

9440

auto[1]

447120

1

T13

36

T14

45

T15

3869

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22064000

1

T1

8

T2

8

T4

9440

auto[1]

26768

1

T7

34

T10

93

T12

263

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2665129	1			T1	1		T2	1		T4	1180
all_values[0]	auto[0]	auto[1]	12108	1			T7	17		T10	44		T12	108
all_values[0]	auto[1]	auto[0]	83598	1			T13	3		T14	3		T15	4
all_values[0]	auto[1]	auto[1]	511	1			T13	4		T15	2		T16	6
all_values[1]	auto[0]	auto[0]	2632618	1			T1	1		T2	1		T4	1180
all_values[1]	auto[0]	auto[1]	8347	1			T7	17		T10	44		T12	79
all_values[1]	auto[1]	auto[0]	120075	1			T13	1		T14	6		T15	950
all_values[1]	auto[1]	auto[1]	306	1			T13	1		T14	2		T15	10
all_values[2]	auto[0]	auto[0]	2718722	1			T1	1		T2	1		T4	1180
all_values[2]	auto[0]	auto[1]	3184	1			T10	5		T12	76		T31	11
all_values[2]	auto[1]	auto[0]	39196	1			T14	3		T15	959		T16	1
all_values[2]	auto[1]	auto[1]	244	1			T13	3		T14	3		T15	3
all_values[3]	auto[0]	auto[0]	2744500	1			T1	1		T2	1		T4	1180
all_values[3]	auto[0]	auto[1]	213	1			T14	1		T15	10		T16	2
all_values[3]	auto[1]	auto[0]	16430	1			T13	4		T14	5		T15	2
all_values[3]	auto[1]	auto[1]	203	1			T13	2		T14	1		T15	2
all_values[4]	auto[0]	auto[0]	2703879	1			T1	1		T2	1		T4	1180
all_values[4]	auto[0]	auto[1]	216	1			T13	4		T14	2		T15	11
all_values[4]	auto[1]	auto[0]	57044	1			T13	2		T14	6		T15	2
all_values[4]	auto[1]	auto[1]	207	1			T14	1		T15	2		T16	8
all_values[5]	auto[0]	auto[0]	2699081	1			T1	1		T2	1		T4	1180
all_values[5]	auto[0]	auto[1]	194	1			T13	1		T14	3		T15	4
all_values[5]	auto[1]	auto[0]	61873	1			T14	5		T15	960		T16	4
all_values[5]	auto[1]	auto[1]	198	1			T13	2		T14	2		T15	3
all_values[6]	auto[0]	auto[0]	2737151	1			T1	1		T2	1		T4	1180
all_values[6]	auto[0]	auto[1]	211	1			T13	1		T14	3		T15	4
all_values[6]	auto[1]	auto[0]	23771	1			T13	4		T14	1		T15	5
all_values[6]	auto[1]	auto[1]	213	1			T13	3		T14	2		T15	6
all_values[7]	auto[0]	auto[0]	2717900	1			T1	1		T2	1		T4	1180
all_values[7]	auto[0]	auto[1]	195	1			T13	1		T15	5		T16	1
all_values[7]	auto[1]	auto[0]	43033	1			T13	6		T14	3		T15	955
all_values[7]	auto[1]	auto[1]	218	1			T13	1		T14	2		T15	4