Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33622	1			T4	4		T7	9		T10	43
auto[SpiFlashAddrCfg]	7873	1			T4	4		T5	1		T6	5
auto[SpiFlashAddr3b]	9406	1			T4	16		T5	5		T6	1
auto[SpiFlashAddr4b]	7895	1			T1	1		T4	2		T6	3

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32781

1

T1

1

T4

26

T5

6

auto[1]

26015

1

T7

8

T10

42

T12

37

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31829

1

T1

1

T4

18

T5

6

auto[1]

26967

1

T4

8

T6

3

T7

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38422	1			T4	10		T6	2		T7	13
values[1]	1160	1			T4	2		T6	1		T10	4
values[2]	1535	1			T4	4		T7	4		T10	1
values[3]	1517	1			T1	1		T4	2		T6	3
values[4]	1485	1			T8	4		T10	1		T11	2
values[5]	1452	1			T6	3		T8	2		T10	3
values[6]	1542	1			T10	2		T12	4		T30	2
values[7]	1552	1			T4	4		T10	3		T30	5
values[8]	10131	1			T4	4		T5	6		T7	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27945

1

T4

26

T7

21

T8

16

auto[1]

30851

1

T1

1

T5

6

T6

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55544

1

T1

1

T4

26

T5

6

write

3252

1

T7

2

T10

6

T11

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19802

1

T1

1

T4

14

T5

6

valids[0x1]

38994

1

T4

12

T6

3

T7

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1596	1			T7	1		T10	1		T12	1
internal_process_ops[0x5a]	1654	1			T4	4		T7	1		T10	3
internal_process_ops[0x05]	19433	1			T4	4		T7	2		T10	23
internal_process_ops[0x35]	1620	1			T7	1		T10	3		T12	1
internal_process_ops[0x15]	1570	1			T10	1		T12	2		T30	3
internal_process_ops[0x03]	1011	1			T4	2		T6	2		T7	1
internal_process_ops[0x0b]	1134	1			T6	1		T7	2		T10	3
internal_process_ops[0x3b]	1031	1			T5	1		T10	1		T30	1
internal_process_ops[0x6b]	1108	1			T5	4		T10	3		T11	2
internal_process_ops[0xbb]	1041	1			T4	4		T6	3		T7	2
internal_process_ops[0xeb]	1078	1			T1	1		T5	1		T6	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57177

1

T1

1

T4

26

T5

6

auto[1]

1619

1

T7

1

T10

4

T30

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56436

1

T1

1

T4

26

T5

6

auto[1]

2360

1

T7

1

T10

5

T12

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8463

1

T4

4

T7

7

T10

14

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5856

1

T7

2

T10

24

T47

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1904

1

T4

4

T7

2

T8

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1887

1

T10

5

T47

4

T13

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2371

1

T4

16

T7

2

T8

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2116

1

T7

3

T10

5

T47

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2104

1

T4

2

T8

4

T10

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1781

1

T7

3

T10

3

T47

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

105

1

T10

1

T13

1

T43

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T43

2

T55

1

T49

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

78

1

T10

1

T55

1

T57

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

88

1

T10

3

T13

2

T27

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

127

1

T7

1

T13

1

T23

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

82

1

T13

2

T43

3

T55

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

80

1

T51

1

T43

7

T56

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

88

1

T10

1

T51

2

T48

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

103

1

T11

4

T13

2

T48

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

68

1

T7

1

T51

3

T48

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

90

1

T13

2

T48

1

T43

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

89

1

T54

2

T17

1

T172

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

97

1

T48

3

T43

2

T56

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

89

1

T13

3

T49

4

T173

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

83

1

T55

1

T49

1

T16

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

104

1

T13

1

T51

4

T48

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10983

1

T12

18

T30

46

T31

46

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7542

1

T12

16

T30

8

T31

12

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1641

1

T5

1

T6

5

T12

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1586

1

T12

6

T30

3

T31

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2052

1

T5

5

T6

1

T12

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2066

1

T12

7

T30

18

T31

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1586

1

T1

1

T6

3

T12

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1606

1

T12

5

T30

8

T31

16

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

107

1

T33

2

T14

1

T97

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

107

1

T31

2

T33

2

T62

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

94

1

T31

1

T14

2

T62

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

107

1

T14

1

T61

5

T97

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

114

1

T12

1

T31

3

T60

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

129

1

T31

6

T33

3

T174

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

120

1

T12

3

T25

2

T14

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

115

1

T30

1

T31

2

T15

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

123

1

T33

2

T62

2

T175

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

96

1

T33

3

T14

1

T174

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

118

1

T30

1

T33

3

T14

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

114

1

T31

1

T33

3

T16

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

111

1

T31

4

T97

3

T62

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

127

1

T33

4

T14

1

T97

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

83

1

T33

2

T61

2

T62

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

124

1

T33

1

T174

1

T97

5

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3740	1			T7	4		T10	8		T50	4
auto[0]	values[0]	valids[0x1]	13249	1			T4	10		T7	9		T10	44
auto[0]	values[1]	valids[0x1]	624	1			T4	2		T10	4		T47	2
auto[0]	values[2]	valids[0x0]	550	1			T4	4		T7	2		T10	1
auto[0]	values[2]	valids[0x1]	273	1			T7	2		T13	2		T51	2
auto[0]	values[3]	valids[0x0]	522	1			T4	2		T10	1		T11	2
auto[0]	values[3]	valids[0x1]	287	1			T11	2		T47	2		T51	4
auto[0]	values[4]	valids[0x0]	497	1			T8	2		T10	1		T11	2
auto[0]	values[4]	valids[0x1]	266	1			T8	2		T13	2		T51	1
auto[0]	values[5]	valids[0x0]	508	1			T10	3		T47	4		T176	2
auto[0]	values[5]	valids[0x1]	277	1			T8	2		T13	2		T51	11
auto[0]	values[6]	valids[0x0]	522	1			T52	2		T47	2		T13	3
auto[0]	values[6]	valids[0x1]	311	1			T10	2		T52	2		T13	2
auto[0]	values[7]	valids[0x0]	536	1			T4	4		T58	4		T176	2
auto[0]	values[7]	valids[0x1]	295	1			T10	3		T13	2		T51	2
auto[0]	values[8]	valids[0x0]	3465	1			T4	4		T8	8		T10	13
auto[0]	values[8]	valids[0x1]	2023	1			T7	4		T8	2		T47	2
auto[1]	values[0]	valids[0x0]	4272	1			T12	15		T30	23		T31	28
auto[1]	values[0]	valids[0x1]	17161	1			T6	2		T12	27		T30	39
auto[1]	values[1]	valids[0x1]	536	1			T6	1		T12	3		T31	5
auto[1]	values[2]	valids[0x0]	402	1			T12	3		T30	1		T31	5
auto[1]	values[2]	valids[0x1]	310	1			T12	3		T30	3		T31	1
auto[1]	values[3]	valids[0x0]	443	1			T1	1		T6	3		T12	3
auto[1]	values[3]	valids[0x1]	265	1			T31	2		T14	1		T61	1
auto[1]	values[4]	valids[0x0]	405	1			T30	4		T31	2		T60	1
auto[1]	values[4]	valids[0x1]	317	1			T30	3		T33	4		T25	2
auto[1]	values[5]	valids[0x0]	387	1			T6	3		T30	3		T31	5
auto[1]	values[5]	valids[0x1]	280	1			T30	1		T31	1		T33	1
auto[1]	values[6]	valids[0x0]	401	1			T12	1		T30	2		T33	2
auto[1]	values[6]	valids[0x1]	308	1			T12	3		T33	4		T61	1
auto[1]	values[7]	valids[0x0]	413	1			T30	1		T31	1		T33	9
auto[1]	values[7]	valids[0x1]	308	1			T30	4		T31	1		T33	3
auto[1]	values[8]	valids[0x0]	2739	1			T5	6		T12	11		T30	7
auto[1]	values[8]	valids[0x1]	1904	1			T12	7		T30	5		T31	14