Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3381039

1

T1

9

T4

907

T5

1708

auto[1]

27855

1

T7

1

T10

20

T12

16

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

970919

1

T1

9

T4

1

T5

1708

auto[1]

2437975

1

T4

906

T7

2521

T10

3857

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	628160	1			T4	907		T5	572		T6	36
auto[524288:1048575]	434416	1			T5	38		T10	188		T30	4210
auto[1048576:1572863]	402517	1			T5	129		T6	28		T12	527
auto[1572864:2097151]	435513	1			T5	380		T10	41		T12	2212
auto[2097152:2621439]	435077	1			T1	2		T5	14		T6	43
auto[2621440:3145727]	375491	1			T5	293		T10	3634		T30	57
auto[3145728:3670015]	367751	1			T5	282		T6	310		T7	5
auto[3670016:4194303]	329969	1			T1	7		T6	1		T7	2516

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2470232

1

T1

5

T4

907

T5

23

auto[1]

938662

1

T1

4

T5

1685

T6

399

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2966509

1

T1

9

T4

907

T5

1708

auto[1]

442385

1

T7

5

T10

2879

T12

1

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	206274	1			T4	1		T5	572		T6	36
auto[0]	auto[0]	auto[0:524287]	auto[1]	354012	1			T4	906		T7	5		T12	4
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	102358	1			T5	38		T10	5		T30	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	265636	1			T10	172		T30	3439		T31	3109
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	120885	1			T5	129		T6	28		T12	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	230805	1			T12	513		T30	768		T31	8
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	116608	1			T5	380		T10	1		T12	7
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	247402	1			T10	40		T12	2201		T31	755
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	136248	1			T1	2		T5	14		T6	43
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	250592	1			T10	3		T30	1		T31	87
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	93931	1			T5	293		T30	6		T31	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	230855	1			T10	766		T30	51		T31	642
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	95883	1			T5	282		T6	310		T30	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	210663	1			T30	298		T31	256		T33	2464
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	84295	1			T1	7		T6	1		T7	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	196734	1			T7	2515		T31	4		T33	2548
auto[0]	auto[1]	auto[0:524287]	auto[0]	3258	1			T31	4		T50	196		T33	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	60690	1			T33	277		T13	272		T61	2
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	630	1			T10	2		T30	2		T31	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	60648	1			T10	1		T30	768		T31	7
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1526	1			T12	1		T30	2		T14	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	45945	1			T14	5		T48	128		T97	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	679	1			T50	1		T13	12		T14	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	67283	1			T13	5		T51	2818		T43	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1097	1			T51	10		T43	10		T49	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	43329	1			T51	3999		T49	644		T173	560
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1192	1			T10	5		T14	5		T51	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	46842	1			T10	2860		T14	610		T51	3184
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	615	1			T7	3		T30	2		T33	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	58550	1			T7	1		T30	514		T31	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1501	1			T31	1		T33	4		T13	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	44073	1			T33	512		T57	513		T44	512
auto[1]	auto[0]	auto[0:524287]	auto[0]	521	1			T12	4		T31	1		T60	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2996	1			T12	3		T31	1		T60	21
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	412	1			T33	2		T14	1		T61	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4085	1			T33	37		T61	2		T51	33
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	369	1			T12	1		T31	1		T33	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2088	1			T12	4		T33	40		T13	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	375	1			T12	3		T13	1		T51	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2705	1			T12	1		T13	4		T51	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	498	1			T10	3		T30	1		T33	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2569	1			T10	6		T33	42		T14	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	343	1			T31	2		T13	2		T14	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1728	1			T31	1		T13	16		T14	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	345	1			T30	2		T33	1		T51	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1156	1			T30	11		T51	16		T97	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	444	1			T31	3		T33	7		T13	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2694	1			T31	3		T33	28		T61	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	107	1			T33	2		T15	1		T56	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	302	1			T33	2		T15	8		T56	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	67	1			T10	1		T33	1		T56	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	580	1			T10	7		T56	1		T57	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	91	1			T97	1		T173	2		T44	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	808	1			T173	7		T44	30		T172	10
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	81	1			T13	5		T97	1		T62	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	380	1			T13	15		T62	3		T107	43
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	72	1			T51	1		T19	1		T185	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	672	1			T51	21		T19	1		T242	25
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	72	1			T10	1		T14	2		T51	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	528	1			T10	2		T14	4		T51	6
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	80	1			T7	1		T30	1		T97	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	459	1			T30	5		T97	2		T173	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	62	1			T57	1		T204	1		T227	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	166	1			T57	7		T204	3		T227	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2010685	1			T1	5		T4	907		T5	23
auto[0]	auto[0]	auto[1]	932496	1			T1	4		T5	1685		T6	399
auto[0]	auto[1]	auto[0]	432388	1			T7	4		T10	2868		T12	1
auto[0]	auto[1]	auto[1]	5470	1			T50	2		T28	2		T243	1
auto[1]	auto[0]	auto[0]	22750	1			T10	9		T12	15		T30	14
auto[1]	auto[0]	auto[1]	578	1			T12	1		T33	9		T51	6
auto[1]	auto[1]	auto[0]	4409	1			T7	1		T10	11		T30	6
auto[1]	auto[1]	auto[1]	118	1			T51	1		T43	3		T56	1