Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2761346	1			T1	1		T2	1		T4	1180
all_pins[1]	2761346	1			T1	1		T2	1		T4	1180
all_pins[2]	2761346	1			T1	1		T2	1		T4	1180
all_pins[3]	2761346	1			T1	1		T2	1		T4	1180
all_pins[4]	2761346	1			T1	1		T2	1		T4	1180
all_pins[5]	2761346	1			T1	1		T2	1		T4	1180
all_pins[6]	2761346	1			T1	1		T2	1		T4	1180
all_pins[7]	2761346	1			T1	1		T2	1		T4	1180

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22063697	1			T1	8		T2	8		T4	9440
values[0x1]	27071	1			T13	16		T14	13		T15	262
transitions[0x0=>0x1]	26047	1			T13	13		T14	13		T15	258
transitions[0x1=>0x0]	26062	1			T13	13		T14	13		T15	258

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2760750	1			T1	1		T2	1		T4	1180
all_pins[0]	values[0x1]	596	1			T13	4		T15	2		T16	6
all_pins[0]	transitions[0x0=>0x1]	461	1			T13	3		T15	2		T16	5
all_pins[0]	transitions[0x1=>0x0]	224	1			T14	2		T15	11		T16	4
all_pins[1]	values[0x0]	2760987	1			T1	1		T2	1		T4	1180
all_pins[1]	values[0x1]	359	1			T13	1		T14	2		T15	11
all_pins[1]	transitions[0x0=>0x1]	305	1			T13	1		T14	2		T15	9
all_pins[1]	transitions[0x1=>0x0]	191	1			T13	3		T14	3		T15	1
all_pins[2]	values[0x0]	2761101	1			T1	1		T2	1		T4	1180
all_pins[2]	values[0x1]	245	1			T13	3		T14	3		T15	3
all_pins[2]	transitions[0x0=>0x1]	179	1			T13	3		T14	3		T15	3
all_pins[2]	transitions[0x1=>0x0]	137	1			T13	2		T14	1		T15	2
all_pins[3]	values[0x0]	2761143	1			T1	1		T2	1		T4	1180
all_pins[3]	values[0x1]	203	1			T13	2		T14	1		T15	2
all_pins[3]	transitions[0x0=>0x1]	151	1			T13	2		T14	1		T15	1
all_pins[3]	transitions[0x1=>0x0]	155	1			T14	1		T15	1		T16	4
all_pins[4]	values[0x0]	2761139	1			T1	1		T2	1		T4	1180
all_pins[4]	values[0x1]	207	1			T14	1		T15	2		T16	8
all_pins[4]	transitions[0x0=>0x1]	162	1			T14	1		T15	2		T16	6
all_pins[4]	transitions[0x1=>0x0]	1565	1			T13	2		T14	2		T15	232
all_pins[5]	values[0x0]	2759736	1			T1	1		T2	1		T4	1180
all_pins[5]	values[0x1]	1610	1			T13	2		T14	2		T15	232
all_pins[5]	transitions[0x0=>0x1]	1051	1			T13	1		T14	2		T15	232
all_pins[5]	transitions[0x1=>0x0]	23074	1			T13	2		T14	2		T15	6
all_pins[6]	values[0x0]	2737713	1			T1	1		T2	1		T4	1180
all_pins[6]	values[0x1]	23633	1			T13	3		T14	2		T15	6
all_pins[6]	transitions[0x0=>0x1]	23583	1			T13	2		T14	2		T15	5
all_pins[6]	transitions[0x1=>0x0]	168	1			T14	2		T15	3		T16	6
all_pins[7]	values[0x0]	2761128	1			T1	1		T2	1		T4	1180
all_pins[7]	values[0x1]	218	1			T13	1		T14	2		T15	4
all_pins[7]	transitions[0x0=>0x1]	155	1			T13	1		T14	2		T15	4
all_pins[7]	transitions[0x1=>0x0]	548	1			T13	4		T15	2		T16	3