Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15605

1

T4

26

T7

13

T8

16

auto[1]

12340

1

T7

8

T10

42

T47

18

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3022	1			T8	16		T10	80		T48	20
values[1]	4205	1			T7	21		T59	2		T47	18
values[2]	3296	1			T11	14		T51	82		T48	42
values[3]	3295	1			T50	4		T58	14		T27	20
values[4]	3195	1			T13	38		T29	6		T51	20
values[5]	3830	1			T53	8		T13	24		T51	46
values[6]	3944	1			T13	22		T23	8		T51	25
values[7]	3158	1			T4	26		T52	6		T13	84

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3152	1			T10	23		T50	4		T53	8
values[1]	4094	1			T8	16		T13	64		T51	150
values[2]	3379	1			T59	2		T23	8		T51	29
values[3]	3127	1			T58	14		T13	24		T51	75
values[4]	3418	1			T10	21		T52	6		T13	38
values[5]	3981	1			T10	36		T11	14		T47	18
values[6]	3513	1			T4	26		T176	10		T74	4
values[7]	3281	1			T7	21		T13	42		T29	6

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	196	1			T10	20		T57	35		T67	14
auto[0]	values[0]	values[1]	293	1			T8	16		T244	2		T172	10
auto[0]	values[0]	values[2]	178	1			T243	24		T227	12		T245	6
auto[0]	values[0]	values[3]	249	1			T48	12		T43	9		T106	6
auto[0]	values[0]	values[4]	193	1			T10	11		T246	2		T21	10
auto[0]	values[0]	values[5]	272	1			T10	7		T56	7		T17	14
auto[0]	values[0]	values[6]	215	1			T43	16		T56	8		T44	23
auto[0]	values[0]	values[7]	120	1			T21	15		T247	12		T218	10
auto[0]	values[1]	values[0]	383	1			T51	29		T19	20		T202	12
auto[0]	values[1]	values[1]	186	1			T44	7		T225	11		T248	6
auto[0]	values[1]	values[2]	309	1			T59	2		T44	10		T249	10
auto[0]	values[1]	values[3]	226	1			T51	29		T48	20		T49	11
auto[0]	values[1]	values[4]	249	1			T51	13		T48	9		T56	14
auto[0]	values[1]	values[5]	301	1			T49	16		T44	22		T199	7
auto[0]	values[1]	values[6]	226	1			T176	10		T48	10		T55	15
auto[0]	values[1]	values[7]	332	1			T7	13		T51	13		T49	12
auto[0]	values[2]	values[0]	137	1			T48	7		T250	18		T251	11
auto[0]	values[2]	values[1]	316	1			T51	10		T44	7		T185	13
auto[0]	values[2]	values[2]	226	1			T43	11		T223	12		T44	13
auto[0]	values[2]	values[3]	149	1			T221	20		T211	26		T252	8
auto[0]	values[2]	values[4]	288	1			T17	23		T199	10		T200	10
auto[0]	values[2]	values[5]	262	1			T11	14		T173	17		T21	10
auto[0]	values[2]	values[6]	209	1			T48	15		T55	12		T17	11
auto[0]	values[2]	values[7]	122	1			T184	13		T216	8		T253	7
auto[0]	values[3]	values[0]	153	1			T50	4		T254	84		T215	11
auto[0]	values[3]	values[1]	286	1			T51	15		T173	25		T19	20
auto[0]	values[3]	values[2]	215	1			T48	15		T215	14		T227	14
auto[0]	values[3]	values[3]	236	1			T58	14		T17	13		T255	12
auto[0]	values[3]	values[4]	339	1			T28	4		T16	13		T199	13
auto[0]	values[3]	values[5]	347	1			T43	10		T173	9		T216	9
auto[0]	values[3]	values[6]	219	1			T56	17		T256	18		T190	19
auto[0]	values[3]	values[7]	146	1			T55	6		T215	18		T190	13
auto[0]	values[4]	values[0]	254	1			T69	14		T199	7		T257	4
auto[0]	values[4]	values[1]	233	1			T51	7		T258	6		T43	12
auto[0]	values[4]	values[2]	224	1			T96	43		T202	12		T259	20
auto[0]	values[4]	values[3]	212	1			T172	22		T229	10		T260	10
auto[0]	values[4]	values[4]	173	1			T13	28		T173	12		T44	12
auto[0]	values[4]	values[5]	297	1			T57	22		T184	12		T261	6
auto[0]	values[4]	values[6]	370	1			T199	22		T190	13		T262	10
auto[0]	values[4]	values[7]	208	1			T29	6		T43	13		T72	20
auto[0]	values[5]	values[0]	335	1			T53	8		T48	13		T49	10
auto[0]	values[5]	values[1]	254	1			T51	3		T57	12		T17	9
auto[0]	values[5]	values[2]	176	1			T55	11		T17	9		T165	6
auto[0]	values[5]	values[3]	304	1			T13	17		T147	18		T49	57
auto[0]	values[5]	values[4]	279	1			T51	5		T48	13		T56	17
auto[0]	values[5]	values[5]	243	1			T56	15		T49	11		T173	11
auto[0]	values[5]	values[6]	297	1			T173	21		T38	39		T263	12
auto[0]	values[5]	values[7]	292	1			T49	14		T185	14		T264	8
auto[0]	values[6]	values[0]	163	1			T202	6		T265	8		T266	10
auto[0]	values[6]	values[1]	279	1			T55	10		T17	24		T172	29
auto[0]	values[6]	values[2]	250	1			T23	8		T57	9		T49	7
auto[0]	values[6]	values[3]	297	1			T191	10		T57	13		T49	28
auto[0]	values[6]	values[4]	250	1			T208	12		T57	12		T172	20
auto[0]	values[6]	values[5]	318	1			T43	10		T56	11		T17	15
auto[0]	values[6]	values[6]	241	1			T43	21		T173	11		T232	8
auto[0]	values[6]	values[7]	247	1			T13	10		T51	16		T43	12
auto[0]	values[7]	values[0]	207	1			T207	22		T188	8		T173	13
auto[0]	values[7]	values[1]	232	1			T13	46		T226	14		T199	24
auto[0]	values[7]	values[2]	199	1			T51	6		T38	11		T267	11
auto[0]	values[7]	values[3]	128	1			T57	11		T200	12		T184	10
auto[0]	values[7]	values[4]	243	1			T52	6		T105	4		T57	44
auto[0]	values[7]	values[5]	257	1			T44	13		T172	12		T227	24
auto[0]	values[7]	values[6]	207	1			T4	26		T74	4		T49	14
auto[0]	values[7]	values[7]	358	1			T13	10		T48	13		T49	60
auto[1]	values[0]	values[0]	162	1			T10	3		T57	8		T199	15
auto[1]	values[0]	values[1]	175	1			T172	10		T19	8		T267	10
auto[1]	values[0]	values[2]	140	1			T227	10		T268	4		T234	11
auto[1]	values[0]	values[3]	166	1			T48	8		T43	11		T56	7
auto[1]	values[0]	values[4]	115	1			T10	10		T21	10		T227	8
auto[1]	values[0]	values[5]	177	1			T10	29		T56	19		T17	9
auto[1]	values[0]	values[6]	159	1			T43	24		T56	14		T44	5
auto[1]	values[0]	values[7]	212	1			T21	8		T269	10		T218	10
auto[1]	values[1]	values[0]	287	1			T51	14		T19	4		T202	46
auto[1]	values[1]	values[1]	170	1			T44	17		T225	15		T267	8
auto[1]	values[1]	values[2]	346	1			T44	10		T249	10		T38	4
auto[1]	values[1]	values[3]	169	1			T51	46		T48	23		T49	9
auto[1]	values[1]	values[4]	282	1			T51	29		T48	11		T56	13
auto[1]	values[1]	values[5]	234	1			T47	18		T49	4		T44	18
auto[1]	values[1]	values[6]	190	1			T48	10		T55	5		T220	11
auto[1]	values[1]	values[7]	315	1			T7	8		T51	29		T49	8
auto[1]	values[2]	values[0]	83	1			T48	15		T270	8		T251	9
auto[1]	values[2]	values[1]	260	1			T51	72		T44	14		T185	7
auto[1]	values[2]	values[2]	290	1			T43	9		T44	7		T227	38
auto[1]	values[2]	values[3]	211	1			T222	16		T252	71		T150	14
auto[1]	values[2]	values[4]	209	1			T17	7		T199	19		T200	12
auto[1]	values[2]	values[5]	197	1			T173	3		T21	10		T190	15
auto[1]	values[2]	values[6]	179	1			T48	5		T55	8		T17	9
auto[1]	values[2]	values[7]	158	1			T184	7		T216	24		T253	13
auto[1]	values[3]	values[0]	70	1			T215	15		T165	10		T271	4
auto[1]	values[3]	values[1]	182	1			T51	10		T173	9		T19	22
auto[1]	values[3]	values[2]	199	1			T48	5		T215	15		T227	21
auto[1]	values[3]	values[3]	82	1			T17	8		T190	5		T227	13
auto[1]	values[3]	values[4]	123	1			T16	11		T199	8		T190	14
auto[1]	values[3]	values[5]	254	1			T27	20		T43	10		T173	21
auto[1]	values[3]	values[6]	321	1			T56	3		T190	10		T38	117
auto[1]	values[3]	values[7]	123	1			T55	14		T215	4		T190	7
auto[1]	values[4]	values[0]	130	1			T199	14		T267	16		T272	9
auto[1]	values[4]	values[1]	150	1			T51	13		T43	8		T44	12
auto[1]	values[4]	values[2]	130	1			T202	8		T273	6		T193	10
auto[1]	values[4]	values[3]	196	1			T172	23		T229	10		T260	10
auto[1]	values[4]	values[4]	100	1			T13	10		T173	11		T44	8
auto[1]	values[4]	values[5]	284	1			T54	20		T57	8		T274	8
auto[1]	values[4]	values[6]	175	1			T199	6		T190	39		T197	9
auto[1]	values[4]	values[7]	59	1			T43	7		T185	5		T21	10
auto[1]	values[5]	values[0]	242	1			T48	19		T275	6		T49	93
auto[1]	values[5]	values[1]	373	1			T51	20		T57	11		T17	35
auto[1]	values[5]	values[2]	155	1			T55	9		T17	14		T165	15
auto[1]	values[5]	values[3]	141	1			T13	7		T49	9		T187	7
auto[1]	values[5]	values[4]	232	1			T51	18		T48	7		T56	4
auto[1]	values[5]	values[5]	163	1			T56	7		T49	9		T173	9
auto[1]	values[5]	values[6]	216	1			T173	2		T38	10		T276	6
auto[1]	values[5]	values[7]	128	1			T49	6		T185	6		T209	10
auto[1]	values[6]	values[0]	192	1			T202	14		T268	5		T277	98
auto[1]	values[6]	values[1]	416	1			T55	10		T17	22		T172	19
auto[1]	values[6]	values[2]	208	1			T57	11		T49	13		T200	12
auto[1]	values[6]	values[3]	249	1			T57	32		T49	12		T21	14
auto[1]	values[6]	values[4]	215	1			T57	8		T172	31		T199	15
auto[1]	values[6]	values[5]	251	1			T43	10		T56	10		T17	5
auto[1]	values[6]	values[6]	148	1			T43	19		T173	16		T218	69
auto[1]	values[6]	values[7]	220	1			T13	12		T51	9		T43	8
auto[1]	values[7]	values[0]	158	1			T173	9		T172	11		T21	10
auto[1]	values[7]	values[1]	289	1			T13	18		T199	12		T229	6
auto[1]	values[7]	values[2]	134	1			T51	23		T38	9		T267	9
auto[1]	values[7]	values[3]	112	1			T57	22		T200	8		T184	10
auto[1]	values[7]	values[4]	128	1			T57	5		T199	9		T184	14
auto[1]	values[7]	values[5]	124	1			T44	13		T172	11		T201	8
auto[1]	values[7]	values[6]	141	1			T49	38		T17	32		T185	5
auto[1]	values[7]	values[7]	241	1			T13	10		T48	7		T49	4