Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	416	1			T13	4		T51	3		T48	2
auto[ReadAddrCrossIntoMailbox]	287	1			T7	1		T10	2		T53	6
auto[ReadAddrCrossOutOfMailbox]	295	1			T7	1		T13	4		T23	2
auto[ReadAddrCrossAllMailbox]	220	1			T7	1		T13	1		T23	4
auto[ReadAddrOutsideMailbox]	3438	1			T4	6		T7	2		T8	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2366

1

T4

3

T7

2

T8

1

auto[1]

2290

1

T4

3

T7

3

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	750	1			T4	2		T7	1		T10	2
read_ops[0x0b]	824	1			T7	2		T10	3		T47	2
read_ops[0x3b]	750	1			T10	1		T58	2		T52	2
read_ops[0x6b]	809	1			T10	3		T11	2		T53	4
read_ops[0xbb]	752	1			T4	4		T7	2		T10	2
read_ops[0xeb]	771	1			T8	2		T10	2		T53	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T49	1		T44	1		T17	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T43	2		T173	1		T172	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T13	2		T223	1		T56	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T223	1		T56	1		T49	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T48	1		T173	1		T215	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T51	1		T184	2		T216	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T23	1		T44	1		T215	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T7	1		T23	1		T51	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T4	1		T13	2		T74	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	257	1			T4	1		T10	2		T13	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T13	1		T191	1		T56	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T13	1		T48	1		T191	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T10	1		T258	1		T48	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T51	1		T258	1		T48	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T51	1		T258	1		T199	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T258	1		T43	2		T56	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T56	1		T19	1		T202	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T48	1		T56	1		T172	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	322	1			T7	2		T10	1		T47	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T10	1		T47	1		T13	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T43	1		T173	1		T44	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T43	1		T49	1		T202	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T51	1		T49	1		T17	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T49	1		T44	1		T225	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T23	1		T48	2		T17	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T23	1		T202	1		T199	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T23	1		T51	2		T43	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T23	1		T56	1		T49	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T58	1		T52	1		T47	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	288	1			T10	1		T58	1		T52	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T21	1		T190	2		T266	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T173	1		T172	1		T202	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T10	1		T53	1		T13	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T53	1		T56	1		T44	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T13	1		T48	1		T57	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T43	1		T49	3		T44	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T51	1		T185	1		T200	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T199	1		T21	1		T165	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T10	1		T11	1		T53	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	292	1			T10	1		T11	1		T53	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T13	1		T51	1		T43	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T51	1		T57	1		T172	3
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T13	1		T48	1		T56	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T7	1		T185	1		T190	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T13	2		T51	1		T258	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T7	1		T258	1		T43	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T51	1		T223	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T55	1		T223	1		T185	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T4	2		T10	2		T11	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	258	1			T4	2		T11	1		T58	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T51	1		T19	1		T199	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T13	1		T48	1		T55	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T53	2		T17	1		T199	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T53	2		T51	1		T199	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T13	1		T227	1		T216	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T51	1		T48	1		T44	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T51	1		T56	2		T173	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T13	1		T44	1		T172	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T8	1		T10	1		T176	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T8	1		T10	1		T176	1