Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3935	1			T10	21		T52	6		T53	8
values[1]	3421	1			T59	2		T13	24		T74	4
values[2]	3243	1			T29	6		T51	25		T147	18
values[3]	3301	1			T11	14		T13	57		T51	29
values[4]	3595	1			T4	26		T51	23		T48	40
values[5]	2902	1			T8	16		T10	23		T47	18
values[6]	3806	1			T50	4		T58	14		T51	55
values[7]	3742	1			T7	21		T10	36		T13	27

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3123	1			T8	16		T59	2		T13	24
values[1]	4260	1			T7	21		T10	36		T29	6
values[2]	2860	1			T10	23		T13	20		T27	20
values[3]	3465	1			T58	14		T52	6		T176	10
values[4]	3881	1			T11	14		T13	27		T28	4
values[5]	3816	1			T47	18		T51	137		T191	10
values[6]	3398	1			T50	4		T13	37		T23	8
values[7]	3142	1			T4	26		T10	21		T53	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27245

1

T4

26

T7

20

T8

16

auto[1]

700

1

T7

1

T10

4

T13

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	296	1			T16	24		T199	19		T227	22
auto[0]	values[0]	values[1]	737	1			T221	20		T49	20		T44	47
auto[0]	values[0]	values[2]	555	1			T27	16		T44	25		T67	14
auto[0]	values[0]	values[3]	508	1			T52	6		T13	55		T51	65
auto[0]	values[0]	values[4]	564	1			T38	140		T278	4		T252	20
auto[0]	values[0]	values[5]	508	1			T17	23		T172	20		T21	24
auto[0]	values[0]	values[6]	203	1			T23	8		T55	20		T56	47
auto[0]	values[0]	values[7]	473	1			T10	21		T53	8		T51	45
auto[0]	values[1]	values[0]	543	1			T59	2		T13	24		T51	39
auto[0]	values[1]	values[1]	490	1			T105	4		T188	8		T172	31
auto[0]	values[1]	values[2]	441	1			T51	17		T55	19		T49	101
auto[0]	values[1]	values[3]	242	1			T55	19		T172	19		T216	20
auto[0]	values[1]	values[4]	493	1			T43	20		T172	20		T259	20
auto[0]	values[1]	values[5]	434	1			T49	17		T17	21		T184	20
auto[0]	values[1]	values[6]	456	1			T56	25		T49	61		T216	21
auto[0]	values[1]	values[7]	228	1			T74	4		T56	20		T69	14
auto[0]	values[2]	values[0]	325	1			T43	19		T246	2		T199	19
auto[0]	values[2]	values[1]	758	1			T29	6		T226	14		T44	19
auto[0]	values[2]	values[2]	155	1			T17	20		T21	38		T38	20
auto[0]	values[2]	values[3]	332	1			T17	44		T196	6		T195	40
auto[0]	values[2]	values[4]	460	1			T48	20		T208	12		T227	39
auto[0]	values[2]	values[5]	329	1			T43	20		T223	12		T49	20
auto[0]	values[2]	values[6]	436	1			T48	20		T43	17		T173	69
auto[0]	values[2]	values[7]	382	1			T51	25		T147	18		T258	6
auto[0]	values[3]	values[0]	334	1			T57	67		T199	29		T279	4
auto[0]	values[3]	values[1]	419	1			T17	24		T199	24		T21	17
auto[0]	values[3]	values[2]	293	1			T13	20		T17	26		T19	19
auto[0]	values[3]	values[3]	711	1			T51	29		T173	22		T44	20
auto[0]	values[3]	values[4]	368	1			T11	14		T211	26		T21	20
auto[0]	values[3]	values[5]	372	1			T191	10		T43	20		T56	21
auto[0]	values[3]	values[6]	475	1			T13	35		T199	36		T280	6
auto[0]	values[3]	values[7]	248	1			T54	18		T276	6		T247	12
auto[0]	values[4]	values[0]	367	1			T244	2		T57	20		T227	39
auto[0]	values[4]	values[1]	469	1			T51	22		T48	20		T49	19
auto[0]	values[4]	values[2]	239	1			T57	20		T173	21		T184	19
auto[0]	values[4]	values[3]	387	1			T48	20		T49	20		T263	12
auto[0]	values[4]	values[4]	477	1			T44	22		T227	20		T38	32
auto[0]	values[4]	values[5]	619	1			T43	19		T57	20		T173	20
auto[0]	values[4]	values[6]	525	1			T173	22		T216	52		T261	6
auto[0]	values[4]	values[7]	403	1			T4	26		T56	19		T202	16
auto[0]	values[5]	values[0]	433	1			T8	16		T57	28		T49	64
auto[0]	values[5]	values[1]	272	1			T96	43		T49	20		T281	8
auto[0]	values[5]	values[2]	269	1			T10	23		T48	29		T57	40
auto[0]	values[5]	values[3]	372	1			T176	10		T48	22		T43	20
auto[0]	values[5]	values[4]	473	1			T51	20		T48	20		T49	20
auto[0]	values[5]	values[5]	318	1			T47	18		T51	82		T282	8
auto[0]	values[5]	values[6]	374	1			T44	24		T17	19		T21	26
auto[0]	values[5]	values[7]	316	1			T227	33		T225	20		T283	18
auto[0]	values[6]	values[0]	411	1			T43	16		T185	19		T21	22
auto[0]	values[6]	values[1]	380	1			T222	16		T19	20		T21	24
auto[0]	values[6]	values[2]	347	1			T48	22		T55	20		T49	20
auto[0]	values[6]	values[3]	555	1			T58	14		T48	20		T275	6
auto[0]	values[6]	values[4]	374	1			T56	22		T68	18		T172	30
auto[0]	values[6]	values[5]	741	1			T51	52		T72	20		T225	19
auto[0]	values[6]	values[6]	520	1			T50	4		T185	38		T200	20
auto[0]	values[6]	values[7]	391	1			T43	20		T202	20		T21	19
auto[0]	values[7]	values[0]	327	1			T172	28		T200	20		T190	51
auto[0]	values[7]	values[1]	614	1			T7	20		T10	32		T51	23
auto[0]	values[7]	values[2]	487	1			T44	20		T172	115		T185	20
auto[0]	values[7]	values[3]	279	1			T256	18		T17	20		T199	21
auto[0]	values[7]	values[4]	562	1			T13	26		T28	4		T19	21
auto[0]	values[7]	values[5]	420	1			T106	6		T56	21		T44	41
auto[0]	values[7]	values[6]	336	1			T48	20		T49	51		T17	30
auto[0]	values[7]	values[7]	620	1			T57	46		T21	29		T187	20
auto[1]	values[0]	values[0]	8	1			T199	1		T227	1		T149	2
auto[1]	values[0]	values[1]	12	1			T44	3		T184	1		T165	2
auto[1]	values[0]	values[2]	16	1			T27	4		T44	1		T17	1
auto[1]	values[0]	values[3]	14	1			T13	5		T43	2		T172	1
auto[1]	values[0]	values[4]	14	1			T38	2		T272	1		T284	3
auto[1]	values[0]	values[5]	7	1			T193	2		T277	1		T285	1
auto[1]	values[0]	values[6]	6	1			T56	2		T197	1		T193	3
auto[1]	values[0]	values[7]	14	1			T173	2		T21	1		T184	1
auto[1]	values[1]	values[0]	15	1			T51	3		T173	1		T225	2
auto[1]	values[1]	values[1]	16	1			T199	3		T187	2		T193	1
auto[1]	values[1]	values[2]	14	1			T51	3		T55	1		T49	2
auto[1]	values[1]	values[3]	11	1			T55	1		T172	1		T220	1
auto[1]	values[1]	values[4]	14	1			T193	6		T253	1		T210	3
auto[1]	values[1]	values[5]	17	1			T49	3		T17	2		T272	1
auto[1]	values[1]	values[6]	6	1			T56	1		T49	3		T286	2
auto[1]	values[1]	values[7]	1	1			T287	1		-	-		-	-
auto[1]	values[2]	values[0]	10	1			T43	1		T199	2		T206	1
auto[1]	values[2]	values[1]	8	1			T44	1		T203	1		T267	2
auto[1]	values[2]	values[2]	5	1			T21	2		T218	3		-	-
auto[1]	values[2]	values[3]	7	1			T195	1		T253	1		T288	1
auto[1]	values[2]	values[4]	12	1			T227	1		T228	1		T289	2
auto[1]	values[2]	values[5]	2	1			T214	1		T290	1		-	-
auto[1]	values[2]	values[6]	10	1			T43	3		T173	1		T216	2
auto[1]	values[2]	values[7]	12	1			T172	5		T260	1		T238	1
auto[1]	values[3]	values[0]	4	1			T57	1		T291	2		T285	1
auto[1]	values[3]	values[1]	17	1			T199	4		T21	3		T197	1
auto[1]	values[3]	values[2]	8	1			T19	3		T38	3		T197	2
auto[1]	values[3]	values[3]	14	1			T173	1		T199	2		T38	1
auto[1]	values[3]	values[4]	14	1			T215	1		T165	1		T229	1
auto[1]	values[3]	values[5]	12	1			T57	1		T215	6		T292	1
auto[1]	values[3]	values[6]	8	1			T13	2		T291	2		T238	1
auto[1]	values[3]	values[7]	4	1			T54	2		T198	1		T287	1
auto[1]	values[4]	values[0]	7	1			T293	2		T205	1		T294	2
auto[1]	values[4]	values[1]	16	1			T51	1		T49	1		T202	3
auto[1]	values[4]	values[2]	6	1			T173	1		T184	1		T295	4
auto[1]	values[4]	values[3]	11	1			T273	1		T296	4		T40	1
auto[1]	values[4]	values[4]	14	1			T44	2		T267	1		T253	2
auto[1]	values[4]	values[5]	18	1			T43	1		T297	2		T206	2
auto[1]	values[4]	values[6]	17	1			T173	2		T194	3		T230	2
auto[1]	values[4]	values[7]	20	1			T56	1		T202	4		T298	2
auto[1]	values[5]	values[0]	18	1			T57	2		T49	2		T227	1
auto[1]	values[5]	values[1]	7	1			T206	5		T149	1		T299	1
auto[1]	values[5]	values[2]	11	1			T48	3		T57	3		T300	1
auto[1]	values[5]	values[3]	7	1			T48	1		T200	2		T209	2
auto[1]	values[5]	values[4]	15	1			T185	2		T87	1		T301	2
auto[1]	values[5]	values[5]	6	1			T184	1		T302	3		T303	2
auto[1]	values[5]	values[6]	6	1			T17	2		T149	2		T294	2
auto[1]	values[5]	values[7]	5	1			T227	2		T304	2		T305	1
auto[1]	values[6]	values[0]	18	1			T43	4		T185	1		T21	1
auto[1]	values[6]	values[1]	8	1			T268	2		T251	1		T65	1
auto[1]	values[6]	values[2]	7	1			T17	1		T251	1		T306	1
auto[1]	values[6]	values[3]	10	1			T187	1		T203	1		T291	2
auto[1]	values[6]	values[4]	11	1			T172	3		T206	3		T303	1
auto[1]	values[6]	values[5]	9	1			T51	3		T225	1		T294	2
auto[1]	values[6]	values[6]	10	1			T185	2		T184	2		T38	1
auto[1]	values[6]	values[7]	14	1			T21	1		T190	1		T307	4
auto[1]	values[7]	values[0]	7	1			T190	1		T300	2		T65	2
auto[1]	values[7]	values[1]	37	1			T7	1		T10	4		T43	2
auto[1]	values[7]	values[2]	7	1			T206	2		T308	1		T285	4
auto[1]	values[7]	values[3]	5	1			T215	1		T309	3		T310	1
auto[1]	values[7]	values[4]	16	1			T13	1		T19	1		T251	2
auto[1]	values[7]	values[5]	4	1			T218	1		T193	1		T311	1
auto[1]	values[7]	values[6]	10	1			T49	1		T218	4		T287	2
auto[1]	values[7]	values[7]	11	1			T57	3		T238	2		T206	1