Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	886	1			T13	7		T14	10		T15	18
all_values[1]	886	1			T13	7		T14	10		T15	18
all_values[2]	886	1			T13	7		T14	10		T15	18
all_values[3]	886	1			T13	7		T14	10		T15	18
all_values[4]	886	1			T13	7		T14	10		T15	18
all_values[5]	886	1			T13	7		T14	10		T15	18
all_values[6]	886	1			T13	7		T14	10		T15	18
all_values[7]	886	1			T13	7		T14	10		T15	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3727

1

T13

20

T14

45

T15

82

auto[1]

3361

1

T13

36

T14

35

T15

62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2886

1

T13

17

T14

39

T15

64

auto[1]

4202

1

T13

39

T14

41

T15

80

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4093

1

T13

32

T14

49

T15

89

auto[1]

2995

1

T13

24

T14

31

T15

55

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	180	1			T15	7		T16	3		T44	2
all_values[0]	auto[0]	auto[0]	auto[1]	81	1			T14	2		T15	2		T44	1
all_values[0]	auto[0]	auto[1]	auto[0]	169	1			T13	1		T14	3		T15	2
all_values[0]	auto[0]	auto[1]	auto[1]	97	1			T13	4		T15	1		T16	3
all_values[0]	auto[1]	auto[0]	auto[1]	192	1			T14	5		T15	4		T16	4
all_values[0]	auto[1]	auto[1]	auto[1]	167	1			T13	2		T15	2		T16	4
all_values[1]	auto[0]	auto[0]	auto[0]	200	1			T13	1		T15	11		T16	4
all_values[1]	auto[0]	auto[0]	auto[1]	83	1			T14	1		T16	3		T44	2
all_values[1]	auto[0]	auto[1]	auto[0]	152	1			T13	1		T14	4		T15	4
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T13	1		T14	1		T15	1
all_values[1]	auto[1]	auto[0]	auto[1]	194	1			T13	2		T14	3		T16	4
all_values[1]	auto[1]	auto[1]	auto[1]	167	1			T13	2		T14	1		T15	2
all_values[2]	auto[0]	auto[0]	auto[0]	174	1			T14	3		T15	4		T16	4
all_values[2]	auto[0]	auto[0]	auto[1]	94	1			T13	2		T16	3		T44	2
all_values[2]	auto[0]	auto[1]	auto[0]	127	1			T14	1		T15	5		T16	1
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T13	2		T14	2		T15	2
all_values[2]	auto[1]	auto[0]	auto[1]	207	1			T13	1		T14	2		T15	2
all_values[2]	auto[1]	auto[1]	auto[1]	193	1			T13	2		T14	2		T15	5
all_values[3]	auto[0]	auto[0]	auto[0]	188	1			T13	2		T14	5		T15	1
all_values[3]	auto[0]	auto[0]	auto[1]	94	1			T15	6		T16	1		T18	4
all_values[3]	auto[0]	auto[1]	auto[0]	154	1			T13	3		T14	2		T15	2
all_values[3]	auto[0]	auto[1]	auto[1]	83	1			T13	1		T14	1		T16	2
all_values[3]	auto[1]	auto[0]	auto[1]	206	1			T14	1		T15	8		T16	1
all_values[3]	auto[1]	auto[1]	auto[1]	161	1			T13	1		T14	1		T15	1
all_values[4]	auto[0]	auto[0]	auto[0]	193	1			T13	2		T14	2		T15	2
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T13	1		T14	1		T15	5
all_values[4]	auto[0]	auto[1]	auto[0]	168	1			T14	4		T15	2		T16	2
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T15	1		T16	1		T18	3
all_values[4]	auto[1]	auto[0]	auto[1]	196	1			T13	4		T14	1		T15	6
all_values[4]	auto[1]	auto[1]	auto[1]	174	1			T14	2		T15	2		T16	7
all_values[5]	auto[0]	auto[0]	auto[0]	247	1			T13	2		T14	2		T15	2
all_values[5]	auto[0]	auto[1]	auto[0]	247	1			T13	2		T14	3		T15	9
all_values[5]	auto[1]	auto[0]	auto[1]	224	1			T13	1		T14	4		T15	5
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T13	2		T14	1		T15	2
all_values[6]	auto[0]	auto[0]	auto[0]	173	1			T14	3		T15	3		T16	4
all_values[6]	auto[0]	auto[0]	auto[1]	92	1			T13	1		T14	1		T15	2
all_values[6]	auto[0]	auto[1]	auto[0]	168	1			T13	1		T14	2		T15	4
all_values[6]	auto[0]	auto[1]	auto[1]	93	1			T13	2		T14	1		T15	3
all_values[6]	auto[1]	auto[0]	auto[1]	192	1			T13	1		T14	3		T15	2
all_values[6]	auto[1]	auto[1]	auto[1]	168	1			T13	2		T15	4		T16	2
all_values[7]	auto[0]	auto[0]	auto[0]	177	1			T14	4		T15	3		T16	3
all_values[7]	auto[0]	auto[0]	auto[1]	75	1			T15	1		T18	2		T22	3
all_values[7]	auto[0]	auto[1]	auto[0]	169	1			T13	2		T14	1		T15	3
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T13	1		T15	1		T16	2
all_values[7]	auto[1]	auto[0]	auto[1]	184	1			T14	2		T15	6		T16	4
all_values[7]	auto[1]	auto[1]	auto[1]	202	1			T13	4		T14	3		T15	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal