Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1985

1

T7

1

T9

2

T10

1

auto[1]

1951

1

T7

3

T9

1

T10

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2125

1

T7

3

T9

3

T10

1

auto[1]

1811

1

T7

1

T10

1

T12

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3140

1

T7

3

T9

2

T10

1

auto[1]

796

1

T7

1

T9

1

T10

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	821	1			T9	1		T10	2		T12	1
valid[1]	731	1			T7	1		T12	2		T30	4
valid[2]	778	1			T7	1		T30	5		T31	1
valid[3]	821	1			T7	1		T12	1		T31	1
valid[4]	785	1			T7	1		T9	2		T12	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	140	1			T12	1		T30	1		T32	1
auto[0]	auto[0]	valid[0]	auto[1]	205	1			T36	2		T102	6		T37	1
auto[0]	auto[0]	valid[1]	auto[0]	124	1			T30	2		T33	1		T34	1
auto[0]	auto[0]	valid[1]	auto[1]	180	1			T36	3		T37	3		T103	5
auto[0]	auto[0]	valid[2]	auto[0]	141	1			T30	3		T32	2		T41	2
auto[0]	auto[0]	valid[2]	auto[1]	174	1			T34	1		T36	5		T102	2
auto[0]	auto[0]	valid[3]	auto[0]	141	1			T13	1		T61	1		T48	1
auto[0]	auto[0]	valid[3]	auto[1]	183	1			T36	3		T102	1		T61	1
auto[0]	auto[0]	valid[4]	auto[0]	115	1			T9	1		T12	1		T30	1
auto[0]	auto[0]	valid[4]	auto[1]	168	1			T36	6		T102	1		T37	7
auto[0]	auto[1]	valid[0]	auto[0]	126	1			T9	1		T30	1		T33	1
auto[0]	auto[1]	valid[0]	auto[1]	178	1			T10	1		T36	2		T102	2
auto[0]	auto[1]	valid[1]	auto[0]	129	1			T12	1		T30	2		T31	1
auto[0]	auto[1]	valid[1]	auto[1]	162	1			T7	1		T34	1		T36	3
auto[0]	auto[1]	valid[2]	auto[0]	141	1			T33	1		T34	1		T14	1
auto[0]	auto[1]	valid[2]	auto[1]	170	1			T36	4		T102	1		T37	6
auto[0]	auto[1]	valid[3]	auto[0]	128	1			T7	1		T12	1		T31	1
auto[0]	auto[1]	valid[3]	auto[1]	200	1			T36	5		T102	5		T37	6
auto[0]	auto[1]	valid[4]	auto[0]	144	1			T7	1		T30	1		T32	1
auto[0]	auto[1]	valid[4]	auto[1]	191	1			T12	1		T36	2		T102	3
auto[1]	auto[0]	valid[0]	auto[0]	93	1			T10	1		T31	1		T97	2
auto[1]	auto[0]	valid[1]	auto[0]	70	1			T12	1		T31	3		T61	1
auto[1]	auto[0]	valid[2]	auto[0]	74	1			T7	1		T30	1		T33	1
auto[1]	auto[0]	valid[3]	auto[0]	97	1			T34	1		T41	1		T97	1
auto[1]	auto[0]	valid[4]	auto[0]	80	1			T9	1		T33	2		T41	2
auto[1]	auto[1]	valid[0]	auto[0]	79	1			T31	1		T13	1		T48	1
auto[1]	auto[1]	valid[1]	auto[0]	66	1			T15	1		T173	1		T44	1
auto[1]	auto[1]	valid[2]	auto[0]	78	1			T30	1		T31	1		T33	2
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T41	1		T13	1		T15	1
auto[1]	auto[1]	valid[4]	auto[0]	87	1			T34	3		T41	1		T15	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal