Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53224

1

T7

99

T9

47

T10

108

auto[1]

19700

1

T7

14

T10

14

T12

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53585

1

T7

83

T9

36

T10

82

auto[1]

19339

1

T7

30

T9

11

T10

40

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	37467	1			T7	62		T9	25		T10	64
others[1]	6045	1			T7	6		T9	2		T10	9
others[2]	6282	1			T7	13		T10	11		T12	4
others[3]	7059	1			T7	9		T9	6		T10	10
interest[1]	4060	1			T7	7		T9	1		T10	5
interest[4]	24467	1			T7	45		T9	17		T10	47
interest[64]	12011	1			T7	16		T9	13		T10	23

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17277	1			T7	36		T9	17		T10	35
auto[0]	auto[0]	others[1]	2866	1			T7	5		T9	2		T10	4
auto[0]	auto[0]	others[2]	2917	1			T7	7		T10	5		T12	1
auto[0]	auto[0]	others[3]	3290	1			T7	6		T9	6		T10	7
auto[0]	auto[0]	interest[1]	1959	1			T7	5		T9	1		T10	4
auto[0]	auto[0]	interest[4]	11242	1			T7	26		T9	15		T10	28
auto[0]	auto[0]	interest[64]	5576	1			T7	10		T9	10		T10	13
auto[0]	auto[1]	others[0]	10311	1			T7	10		T10	8		T12	9
auto[0]	auto[1]	others[1]	1586	1			T10	2		T34	3		T36	45
auto[0]	auto[1]	others[2]	1665	1			T7	1		T34	8		T36	26
auto[0]	auto[1]	others[3]	1862	1			T7	1		T12	1		T34	7
auto[0]	auto[1]	interest[1]	1067	1			T10	1		T34	1		T36	26
auto[0]	auto[1]	interest[4]	6825	1			T7	9		T10	6		T12	5
auto[0]	auto[1]	interest[64]	3209	1			T7	2		T10	3		T12	1
auto[1]	auto[0]	others[0]	9879	1			T7	16		T9	8		T10	21
auto[1]	auto[0]	others[1]	1593	1			T7	1		T10	3		T12	2
auto[1]	auto[0]	others[2]	1700	1			T7	5		T10	6		T12	3
auto[1]	auto[0]	others[3]	1907	1			T7	2		T10	3		T12	3
auto[1]	auto[0]	interest[1]	1034	1			T7	2		T12	4		T30	3
auto[1]	auto[0]	interest[4]	6400	1			T7	10		T9	2		T10	13
auto[1]	auto[0]	interest[64]	3226	1			T7	4		T9	3		T10	7

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal