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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T133 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2706250536 Aug 02 05:14:26 PM PDT 24 Aug 02 05:14:28 PM PDT 24 113898456 ps
T1027 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3899530911 Aug 02 05:14:10 PM PDT 24 Aug 02 05:14:12 PM PDT 24 51382499 ps
T134 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1629750118 Aug 02 05:14:00 PM PDT 24 Aug 02 05:14:02 PM PDT 24 96167104 ps
T1028 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1873877890 Aug 02 05:14:07 PM PDT 24 Aug 02 05:14:18 PM PDT 24 101446132 ps
T114 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4136996855 Aug 02 05:14:32 PM PDT 24 Aug 02 05:14:36 PM PDT 24 136517893 ps
T136 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2007808838 Aug 02 05:14:01 PM PDT 24 Aug 02 05:14:26 PM PDT 24 1848289892 ps
T135 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1261141174 Aug 02 05:14:09 PM PDT 24 Aug 02 05:14:11 PM PDT 24 30441914 ps
T115 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.239110166 Aug 02 05:14:25 PM PDT 24 Aug 02 05:14:29 PM PDT 24 55779369 ps
T116 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3956048285 Aug 02 05:14:15 PM PDT 24 Aug 02 05:14:19 PM PDT 24 995831653 ps
T117 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1111266480 Aug 02 05:14:28 PM PDT 24 Aug 02 05:14:30 PM PDT 24 89435879 ps
T1029 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3676057086 Aug 02 05:14:02 PM PDT 24 Aug 02 05:14:05 PM PDT 24 209225928 ps
T163 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3000853369 Aug 02 05:14:49 PM PDT 24 Aug 02 05:14:52 PM PDT 24 1974810774 ps
T1030 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.308998916 Aug 02 05:14:20 PM PDT 24 Aug 02 05:14:20 PM PDT 24 48808151 ps
T1031 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.895796003 Aug 02 05:14:23 PM PDT 24 Aug 02 05:14:24 PM PDT 24 13028025 ps
T1032 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3860033917 Aug 02 05:14:31 PM PDT 24 Aug 02 05:14:33 PM PDT 24 169102374 ps
T137 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4184979109 Aug 02 05:14:27 PM PDT 24 Aug 02 05:14:29 PM PDT 24 82486892 ps
T179 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1175390628 Aug 02 05:14:20 PM PDT 24 Aug 02 05:14:39 PM PDT 24 1106585419 ps
T1033 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3673119231 Aug 02 05:14:12 PM PDT 24 Aug 02 05:14:18 PM PDT 24 50447409 ps
T1034 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1433307593 Aug 02 05:14:28 PM PDT 24 Aug 02 05:14:29 PM PDT 24 70401697 ps
T118 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1686325053 Aug 02 05:14:13 PM PDT 24 Aug 02 05:14:19 PM PDT 24 175907984 ps
T1035 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2687518143 Aug 02 05:14:40 PM PDT 24 Aug 02 05:14:42 PM PDT 24 490813842 ps
T1036 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.391643589 Aug 02 05:14:12 PM PDT 24 Aug 02 05:14:16 PM PDT 24 118183997 ps
T1037 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.637936577 Aug 02 05:14:14 PM PDT 24 Aug 02 05:14:15 PM PDT 24 24470530 ps
T164 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1699864419 Aug 02 05:14:10 PM PDT 24 Aug 02 05:14:18 PM PDT 24 1226274677 ps
T1038 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4254894280 Aug 02 05:14:13 PM PDT 24 Aug 02 05:14:19 PM PDT 24 22090630 ps
T1039 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2869619963 Aug 02 05:14:10 PM PDT 24 Aug 02 05:14:10 PM PDT 24 34852757 ps
T1040 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1175445290 Aug 02 05:14:21 PM PDT 24 Aug 02 05:14:22 PM PDT 24 16408856 ps
T138 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3249570539 Aug 02 05:14:18 PM PDT 24 Aug 02 05:14:20 PM PDT 24 242921989 ps
T1041 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3121234882 Aug 02 05:14:12 PM PDT 24 Aug 02 05:14:13 PM PDT 24 161851017 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.545288411 Aug 02 05:14:17 PM PDT 24 Aug 02 05:14:40 PM PDT 24 1619310989 ps
T101 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2248752338 Aug 02 05:14:08 PM PDT 24 Aug 02 05:14:10 PM PDT 24 75242999 ps
T1043 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2038785994 Aug 02 05:14:27 PM PDT 24 Aug 02 05:14:29 PM PDT 24 87488613 ps
T1044 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.336427416 Aug 02 05:14:12 PM PDT 24 Aug 02 05:14:13 PM PDT 24 10905975 ps
T1045 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1623430544 Aug 02 05:14:15 PM PDT 24 Aug 02 05:14:38 PM PDT 24 3527747778 ps
T1046 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4059988684 Aug 02 05:14:22 PM PDT 24 Aug 02 05:14:26 PM PDT 24 124724144 ps
T1047 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.196271592 Aug 02 05:14:20 PM PDT 24 Aug 02 05:14:20 PM PDT 24 52353564 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2208259156 Aug 02 05:14:00 PM PDT 24 Aug 02 05:14:03 PM PDT 24 126905889 ps
T1049 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2226439747 Aug 02 05:14:36 PM PDT 24 Aug 02 05:14:37 PM PDT 24 12113605 ps
T1050 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2538712353 Aug 02 05:13:59 PM PDT 24 Aug 02 05:14:01 PM PDT 24 88098905 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2295953271 Aug 02 05:14:05 PM PDT 24 Aug 02 05:14:05 PM PDT 24 21153642 ps
T1052 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3856508779 Aug 02 05:14:27 PM PDT 24 Aug 02 05:14:27 PM PDT 24 25494252 ps
T139 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3941389673 Aug 02 05:14:10 PM PDT 24 Aug 02 05:14:19 PM PDT 24 1723093591 ps
T1053 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2862957728 Aug 02 05:14:22 PM PDT 24 Aug 02 05:14:23 PM PDT 24 42057971 ps
T140 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.675842897 Aug 02 05:14:13 PM PDT 24 Aug 02 05:14:15 PM PDT 24 28279528 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1754519922 Aug 02 05:14:12 PM PDT 24 Aug 02 05:14:13 PM PDT 24 23529061 ps
T1055 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4226461141 Aug 02 05:14:21 PM PDT 24 Aug 02 05:14:24 PM PDT 24 365572518 ps
T1056 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3560971782 Aug 02 05:14:44 PM PDT 24 Aug 02 05:14:45 PM PDT 24 28770002 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3389968567 Aug 02 05:14:25 PM PDT 24 Aug 02 05:14:27 PM PDT 24 76655998 ps
T1057 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.196901923 Aug 02 05:14:35 PM PDT 24 Aug 02 05:14:38 PM PDT 24 372837199 ps
T1058 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1326118974 Aug 02 05:14:08 PM PDT 24 Aug 02 05:14:11 PM PDT 24 340774102 ps
T1059 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1504244328 Aug 02 05:14:21 PM PDT 24 Aug 02 05:14:22 PM PDT 24 13710135 ps
T1060 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.103612420 Aug 02 05:14:25 PM PDT 24 Aug 02 05:14:26 PM PDT 24 15227294 ps
T1061 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1237062797 Aug 02 05:14:43 PM PDT 24 Aug 02 05:14:44 PM PDT 24 49357821 ps
T141 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.275229638 Aug 02 05:14:30 PM PDT 24 Aug 02 05:14:32 PM PDT 24 115788650 ps
T1062 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4174604028 Aug 02 05:14:37 PM PDT 24 Aug 02 05:14:41 PM PDT 24 377789703 ps
T120 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1993104393 Aug 02 05:14:22 PM PDT 24 Aug 02 05:14:27 PM PDT 24 81948560 ps
T142 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2724787029 Aug 02 05:14:31 PM PDT 24 Aug 02 05:14:33 PM PDT 24 210178364 ps
T1063 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1471039263 Aug 02 05:14:13 PM PDT 24 Aug 02 05:14:14 PM PDT 24 25466661 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3619184520 Aug 02 05:14:27 PM PDT 24 Aug 02 05:14:30 PM PDT 24 203388677 ps
T1065 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.534667389 Aug 02 05:14:47 PM PDT 24 Aug 02 05:14:47 PM PDT 24 32253809 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2013549186 Aug 02 05:14:06 PM PDT 24 Aug 02 05:14:07 PM PDT 24 43166114 ps
T1067 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1930948067 Aug 02 05:14:18 PM PDT 24 Aug 02 05:14:20 PM PDT 24 90327079 ps
T1068 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2537260967 Aug 02 05:14:00 PM PDT 24 Aug 02 05:14:02 PM PDT 24 51361211 ps
T1069 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1554548893 Aug 02 05:14:36 PM PDT 24 Aug 02 05:14:38 PM PDT 24 38732083 ps
T178 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.516920499 Aug 02 05:14:12 PM PDT 24 Aug 02 05:14:37 PM PDT 24 796728618 ps
T1070 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2907298912 Aug 02 05:14:09 PM PDT 24 Aug 02 05:14:14 PM PDT 24 204177724 ps
T1071 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.950158198 Aug 02 05:14:18 PM PDT 24 Aug 02 05:14:21 PM PDT 24 108115906 ps
T1072 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.770173684 Aug 02 05:14:20 PM PDT 24 Aug 02 05:14:24 PM PDT 24 307211875 ps
T1073 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4100215691 Aug 02 05:13:58 PM PDT 24 Aug 02 05:14:00 PM PDT 24 75514357 ps
T1074 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1894409312 Aug 02 05:14:05 PM PDT 24 Aug 02 05:14:08 PM PDT 24 66322053 ps
T180 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3709563423 Aug 02 05:14:23 PM PDT 24 Aug 02 05:14:37 PM PDT 24 1069920547 ps
T1075 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1994698305 Aug 02 05:14:18 PM PDT 24 Aug 02 05:14:19 PM PDT 24 18588925 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3345757299 Aug 02 05:14:20 PM PDT 24 Aug 02 05:14:22 PM PDT 24 41261570 ps
T1077 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.903608613 Aug 02 05:14:22 PM PDT 24 Aug 02 05:14:24 PM PDT 24 31213683 ps
T1078 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4204287764 Aug 02 05:14:00 PM PDT 24 Aug 02 05:14:03 PM PDT 24 137968656 ps
T1079 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2792440613 Aug 02 05:14:10 PM PDT 24 Aug 02 05:14:12 PM PDT 24 217391358 ps
T1080 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2688746796 Aug 02 05:14:40 PM PDT 24 Aug 02 05:14:54 PM PDT 24 1985784511 ps
T1081 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.448974523 Aug 02 05:14:26 PM PDT 24 Aug 02 05:14:27 PM PDT 24 14762939 ps
T1082 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2538513755 Aug 02 05:14:09 PM PDT 24 Aug 02 05:14:28 PM PDT 24 1375643584 ps
T1083 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2318486167 Aug 02 05:14:16 PM PDT 24 Aug 02 05:14:17 PM PDT 24 16859940 ps
T1084 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1899024676 Aug 02 05:14:17 PM PDT 24 Aug 02 05:14:18 PM PDT 24 26812657 ps
T1085 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3859264759 Aug 02 05:14:25 PM PDT 24 Aug 02 05:14:26 PM PDT 24 30341479 ps
T1086 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2297297650 Aug 02 05:14:14 PM PDT 24 Aug 02 05:14:35 PM PDT 24 955461311 ps
T1087 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3390676754 Aug 02 05:14:34 PM PDT 24 Aug 02 05:14:35 PM PDT 24 43893905 ps
T1088 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2023907803 Aug 02 05:14:02 PM PDT 24 Aug 02 05:14:06 PM PDT 24 62392205 ps
T1089 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1889722209 Aug 02 05:14:36 PM PDT 24 Aug 02 05:14:36 PM PDT 24 29622527 ps
T1090 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.223959292 Aug 02 05:14:24 PM PDT 24 Aug 02 05:14:26 PM PDT 24 48277197 ps
T1091 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1467297636 Aug 02 05:14:29 PM PDT 24 Aug 02 05:14:32 PM PDT 24 80868902 ps
T182 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.321441842 Aug 02 05:14:03 PM PDT 24 Aug 02 05:14:22 PM PDT 24 300871494 ps
T1092 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4160068021 Aug 02 05:14:27 PM PDT 24 Aug 02 05:14:30 PM PDT 24 240958515 ps
T1093 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3802929228 Aug 02 05:14:25 PM PDT 24 Aug 02 05:14:26 PM PDT 24 19548432 ps
T1094 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2933848471 Aug 02 05:14:39 PM PDT 24 Aug 02 05:14:43 PM PDT 24 178311927 ps
T1095 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1671563563 Aug 02 05:14:07 PM PDT 24 Aug 02 05:14:09 PM PDT 24 236720706 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.320235555 Aug 02 05:14:02 PM PDT 24 Aug 02 05:14:04 PM PDT 24 93898025 ps
T1097 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1049636198 Aug 02 05:14:33 PM PDT 24 Aug 02 05:14:34 PM PDT 24 94199517 ps
T1098 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2675152856 Aug 02 05:14:29 PM PDT 24 Aug 02 05:14:32 PM PDT 24 364310512 ps
T1099 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3028636741 Aug 02 05:14:30 PM PDT 24 Aug 02 05:14:31 PM PDT 24 19788169 ps
T1100 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.443952715 Aug 02 05:14:09 PM PDT 24 Aug 02 05:14:12 PM PDT 24 176299196 ps
T1101 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3181944202 Aug 02 05:14:10 PM PDT 24 Aug 02 05:14:13 PM PDT 24 90666595 ps
T1102 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1063753574 Aug 02 05:14:19 PM PDT 24 Aug 02 05:14:19 PM PDT 24 29788613 ps
T1103 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1589823976 Aug 02 05:14:34 PM PDT 24 Aug 02 05:14:35 PM PDT 24 14405346 ps
T1104 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3501896581 Aug 02 05:14:17 PM PDT 24 Aug 02 05:14:18 PM PDT 24 55121084 ps
T1105 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1778919114 Aug 02 05:14:39 PM PDT 24 Aug 02 05:14:40 PM PDT 24 78705525 ps
T1106 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2727604694 Aug 02 05:14:28 PM PDT 24 Aug 02 05:14:30 PM PDT 24 71147784 ps
T1107 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.109727856 Aug 02 05:14:08 PM PDT 24 Aug 02 05:14:15 PM PDT 24 117237313 ps
T1108 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3537854162 Aug 02 05:14:32 PM PDT 24 Aug 02 05:14:33 PM PDT 24 54066562 ps
T1109 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3889176859 Aug 02 05:14:18 PM PDT 24 Aug 02 05:14:20 PM PDT 24 196291319 ps
T1110 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3073017506 Aug 02 05:14:05 PM PDT 24 Aug 02 05:14:07 PM PDT 24 195941090 ps
T1111 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3657157940 Aug 02 05:14:19 PM PDT 24 Aug 02 05:14:26 PM PDT 24 648641087 ps
T1112 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3401063417 Aug 02 05:14:23 PM PDT 24 Aug 02 05:14:24 PM PDT 24 16661945 ps
T1113 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.147963320 Aug 02 05:14:12 PM PDT 24 Aug 02 05:14:14 PM PDT 24 65167388 ps
T1114 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3152085686 Aug 02 05:14:09 PM PDT 24 Aug 02 05:14:11 PM PDT 24 70493776 ps
T1115 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1823113952 Aug 02 05:14:17 PM PDT 24 Aug 02 05:14:20 PM PDT 24 626242249 ps
T1116 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3441260472 Aug 02 05:14:15 PM PDT 24 Aug 02 05:14:16 PM PDT 24 83204699 ps
T1117 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.241948361 Aug 02 05:14:00 PM PDT 24 Aug 02 05:14:01 PM PDT 24 11635668 ps
T1118 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3862060025 Aug 02 05:14:27 PM PDT 24 Aug 02 05:14:28 PM PDT 24 25146791 ps
T1119 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1318197857 Aug 02 05:14:31 PM PDT 24 Aug 02 05:14:34 PM PDT 24 458700426 ps
T1120 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2138597609 Aug 02 05:14:09 PM PDT 24 Aug 02 05:14:31 PM PDT 24 6527801783 ps
T177 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3546445196 Aug 02 05:14:18 PM PDT 24 Aug 02 05:14:20 PM PDT 24 265460178 ps
T1121 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.91229142 Aug 02 05:14:13 PM PDT 24 Aug 02 05:14:15 PM PDT 24 61187488 ps
T1122 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3511556124 Aug 02 05:14:07 PM PDT 24 Aug 02 05:14:12 PM PDT 24 311040009 ps
T1123 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3839686166 Aug 02 05:14:17 PM PDT 24 Aug 02 05:14:21 PM PDT 24 132457821 ps
T181 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1422589157 Aug 02 05:14:17 PM PDT 24 Aug 02 05:14:37 PM PDT 24 2167642608 ps
T1124 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3948951244 Aug 02 05:14:25 PM PDT 24 Aug 02 05:14:26 PM PDT 24 14667163 ps
T1125 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2972263253 Aug 02 05:14:13 PM PDT 24 Aug 02 05:14:14 PM PDT 24 18071112 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.49126937 Aug 02 05:14:02 PM PDT 24 Aug 02 05:14:04 PM PDT 24 54522247 ps
T1127 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2913891452 Aug 02 05:14:23 PM PDT 24 Aug 02 05:14:38 PM PDT 24 2180808103 ps
T1128 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.63815299 Aug 02 05:13:57 PM PDT 24 Aug 02 05:13:58 PM PDT 24 42491944 ps
T1129 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.676782068 Aug 02 05:14:07 PM PDT 24 Aug 02 05:14:24 PM PDT 24 1579995878 ps
T1130 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3991660018 Aug 02 05:14:01 PM PDT 24 Aug 02 05:14:17 PM PDT 24 629181791 ps
T1131 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3026116854 Aug 02 05:14:07 PM PDT 24 Aug 02 05:14:20 PM PDT 24 614635866 ps

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.234771087
Short name T10
Test name
Test status
Simulation time 1904264424 ps
CPU time 28.14 seconds
Started Aug 02 06:45:03 PM PDT 24
Finished Aug 02 06:45:31 PM PDT 24
Peak memory 238468 kb
Host smart-96fc816b-dd85-4fc9-9e97-b6dc3b20ec76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234771087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.234771087
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.407988497
Short name T14
Test name
Test status
Simulation time 25908030807 ps
CPU time 243.75 seconds
Started Aug 02 06:44:34 PM PDT 24
Finished Aug 02 06:48:38 PM PDT 24
Peak memory 251688 kb
Host smart-998019be-372e-47e6-9f73-dc8481a67d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407988497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.407988497
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1491825468
Short name T51
Test name
Test status
Simulation time 183063602157 ps
CPU time 361.3 seconds
Started Aug 02 06:45:18 PM PDT 24
Finished Aug 02 06:51:20 PM PDT 24
Peak memory 257604 kb
Host smart-15c262d7-b492-4863-b231-fc3f0efda918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491825468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1491825468
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.88269198
Short name T111
Test name
Test status
Simulation time 780021744 ps
CPU time 8.75 seconds
Started Aug 02 05:14:24 PM PDT 24
Finished Aug 02 05:14:32 PM PDT 24
Peak memory 215100 kb
Host smart-79caad39-e5c4-4d41-89d4-a47c52ff4e68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88269198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_
tl_intg_err.88269198
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1520190504
Short name T21
Test name
Test status
Simulation time 84071253242 ps
CPU time 601.57 seconds
Started Aug 02 06:46:14 PM PDT 24
Finished Aug 02 06:56:15 PM PDT 24
Peak memory 272976 kb
Host smart-90e61005-8a89-4bbf-88dc-9fbdf7ab9a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520190504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1520190504
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.612612273
Short name T97
Test name
Test status
Simulation time 44272026981 ps
CPU time 400.82 seconds
Started Aug 02 06:45:30 PM PDT 24
Finished Aug 02 06:52:11 PM PDT 24
Peak memory 253792 kb
Host smart-8147d00f-6ef1-482e-8629-2b43eac6cefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612612273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.612612273
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.568923210
Short name T80
Test name
Test status
Simulation time 23169210 ps
CPU time 0.73 seconds
Started Aug 02 06:43:59 PM PDT 24
Finished Aug 02 06:44:00 PM PDT 24
Peak memory 216424 kb
Host smart-cffdbad0-6adf-4150-abdc-e1b60d31c88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568923210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.568923210
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2547315942
Short name T17
Test name
Test status
Simulation time 83969931258 ps
CPU time 292.26 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:51:14 PM PDT 24
Peak memory 266068 kb
Host smart-04b6694e-c8e7-4459-8568-efbd49d23eb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547315942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2547315942
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.987351200
Short name T38
Test name
Test status
Simulation time 63542141381 ps
CPU time 226.8 seconds
Started Aug 02 06:44:44 PM PDT 24
Finished Aug 02 06:48:31 PM PDT 24
Peak memory 282360 kb
Host smart-001b3947-16fc-4c8c-95b7-c5a74da72792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987351200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.987351200
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2988789083
Short name T202
Test name
Test status
Simulation time 3553774114 ps
CPU time 72.44 seconds
Started Aug 02 06:45:27 PM PDT 24
Finished Aug 02 06:46:39 PM PDT 24
Peak memory 249688 kb
Host smart-801c0a79-d7de-42ed-8bbe-b0c621bc5f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988789083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2988789083
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2702266878
Short name T113
Test name
Test status
Simulation time 309615282 ps
CPU time 4.95 seconds
Started Aug 02 05:13:56 PM PDT 24
Finished Aug 02 05:14:01 PM PDT 24
Peak memory 215344 kb
Host smart-5b562204-2784-4758-a160-46f6b8e1af04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702266878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
702266878
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2708408256
Short name T6
Test name
Test status
Simulation time 234604851 ps
CPU time 9.81 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:44:36 PM PDT 24
Peak memory 241352 kb
Host smart-ecf5a66e-7bee-4299-a11b-861487dcf661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708408256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2708408256
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3989536327
Short name T227
Test name
Test status
Simulation time 154472388196 ps
CPU time 605.36 seconds
Started Aug 02 06:45:25 PM PDT 24
Finished Aug 02 06:55:30 PM PDT 24
Peak memory 274224 kb
Host smart-87c4ff99-c1ea-4c5c-98f3-e89bdabcd01c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989536327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3989536327
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3351808744
Short name T42
Test name
Test status
Simulation time 16493786 ps
CPU time 0.74 seconds
Started Aug 02 06:45:05 PM PDT 24
Finished Aug 02 06:45:06 PM PDT 24
Peak memory 205880 kb
Host smart-0c9a2dc9-f2db-406c-bc43-e5d5e8b1182f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351808744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3351808744
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3279616110
Short name T199
Test name
Test status
Simulation time 17831593779 ps
CPU time 234.42 seconds
Started Aug 02 06:45:23 PM PDT 24
Finished Aug 02 06:49:17 PM PDT 24
Peak memory 252320 kb
Host smart-5eafb924-c686-4c69-91ec-f64df0a963c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279616110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3279616110
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2031773505
Short name T218
Test name
Test status
Simulation time 32746996837 ps
CPU time 111.28 seconds
Started Aug 02 06:46:34 PM PDT 24
Finished Aug 02 06:48:26 PM PDT 24
Peak memory 257796 kb
Host smart-61c81838-fcab-468b-91b2-48728d4e0a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031773505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2031773505
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1999925910
Short name T44
Test name
Test status
Simulation time 314425529925 ps
CPU time 714.25 seconds
Started Aug 02 06:45:24 PM PDT 24
Finished Aug 02 06:57:18 PM PDT 24
Peak memory 267496 kb
Host smart-950ec6bc-a5cd-4586-8d66-7c45f41e9c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999925910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1999925910
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2436411632
Short name T99
Test name
Test status
Simulation time 66764946 ps
CPU time 1.16 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:09 PM PDT 24
Peak memory 215064 kb
Host smart-4e920811-cf1b-4e36-b2fe-c606313eb5ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436411632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2436411632
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2715317589
Short name T33
Test name
Test status
Simulation time 80010415168 ps
CPU time 175.61 seconds
Started Aug 02 06:46:12 PM PDT 24
Finished Aug 02 06:49:08 PM PDT 24
Peak memory 257608 kb
Host smart-cfe9e67d-5b72-4b52-8789-efaf687b6d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715317589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2715317589
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1378036109
Short name T65
Test name
Test status
Simulation time 168976411662 ps
CPU time 454.3 seconds
Started Aug 02 06:45:31 PM PDT 24
Finished Aug 02 06:53:05 PM PDT 24
Peak memory 274196 kb
Host smart-d0d4dbea-33ac-40a2-a7f9-62c134497ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378036109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1378036109
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1214785421
Short name T123
Test name
Test status
Simulation time 1231426030 ps
CPU time 19.29 seconds
Started Aug 02 05:14:28 PM PDT 24
Finished Aug 02 05:14:47 PM PDT 24
Peak memory 216604 kb
Host smart-0b1b9c36-a649-4c86-8613-18667e1d3bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214785421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1214785421
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3227254795
Short name T238
Test name
Test status
Simulation time 6509754432 ps
CPU time 136.47 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:48:14 PM PDT 24
Peak memory 271796 kb
Host smart-cd2eca19-f3ff-4669-8661-135993059dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227254795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3227254795
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3827018381
Short name T81
Test name
Test status
Simulation time 151260749 ps
CPU time 0.95 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:14 PM PDT 24
Peak memory 236952 kb
Host smart-b9215234-e184-427c-acd3-6ad8617be69a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827018381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3827018381
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2388026198
Short name T15
Test name
Test status
Simulation time 5741094357 ps
CPU time 20.07 seconds
Started Aug 02 06:44:59 PM PDT 24
Finished Aug 02 06:45:19 PM PDT 24
Peak memory 225088 kb
Host smart-922d4618-cb43-4800-b5ad-a927496180e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388026198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2388026198
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2905245268
Short name T193
Test name
Test status
Simulation time 68767623502 ps
CPU time 167.08 seconds
Started Aug 02 06:45:09 PM PDT 24
Finished Aug 02 06:47:56 PM PDT 24
Peak memory 252472 kb
Host smart-8f0926ad-c28c-4025-97eb-e420574f3dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905245268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2905245268
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1684929029
Short name T288
Test name
Test status
Simulation time 7688260222 ps
CPU time 179.81 seconds
Started Aug 02 06:46:12 PM PDT 24
Finished Aug 02 06:49:12 PM PDT 24
Peak memory 282364 kb
Host smart-8b5cabb3-55b8-4f2b-98fa-15e5ff5e3f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684929029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1684929029
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2340462492
Short name T57
Test name
Test status
Simulation time 60335760841 ps
CPU time 277.59 seconds
Started Aug 02 06:45:18 PM PDT 24
Finished Aug 02 06:49:56 PM PDT 24
Peak memory 255976 kb
Host smart-b435621f-389b-4ad8-bf2e-6cc701260c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340462492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2340462492
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4688063
Short name T172
Test name
Test status
Simulation time 81207480118 ps
CPU time 548.45 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:55:43 PM PDT 24
Peak memory 257088 kb
Host smart-3ed381e0-1fc4-4a32-b800-e811e4c31019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4688063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4688063
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.342003957
Short name T149
Test name
Test status
Simulation time 227165119603 ps
CPU time 500.79 seconds
Started Aug 02 06:44:37 PM PDT 24
Finished Aug 02 06:52:58 PM PDT 24
Peak memory 260644 kb
Host smart-8b69fae9-41de-48a6-a609-3c1ff227dff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342003957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.342003957
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3328461535
Short name T184
Test name
Test status
Simulation time 88699053262 ps
CPU time 304.19 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:50:53 PM PDT 24
Peak memory 249704 kb
Host smart-619379db-df36-4314-9167-8c73377aa048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328461535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3328461535
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1686325053
Short name T118
Test name
Test status
Simulation time 175907984 ps
CPU time 5.25 seconds
Started Aug 02 05:14:13 PM PDT 24
Finished Aug 02 05:14:19 PM PDT 24
Peak memory 216392 kb
Host smart-bf277578-94e6-4b79-ab3d-cb313d8a7920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686325053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1686325053
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2906804106
Short name T43
Test name
Test status
Simulation time 54432336369 ps
CPU time 371.94 seconds
Started Aug 02 06:44:03 PM PDT 24
Finished Aug 02 06:50:15 PM PDT 24
Peak memory 272788 kb
Host smart-423ccc3c-bd32-478d-9978-e4c32604604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906804106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2906804106
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2589720109
Short name T294
Test name
Test status
Simulation time 298497213425 ps
CPU time 407.79 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:51:56 PM PDT 24
Peak memory 265428 kb
Host smart-e9978bbe-f9c1-4eed-9ce9-938b0443aef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589720109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2589720109
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1438955982
Short name T109
Test name
Test status
Simulation time 296326768 ps
CPU time 19.65 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:21 PM PDT 24
Peak memory 215256 kb
Host smart-9e534c44-a338-401d-a246-4f73e4fb5213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438955982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1438955982
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3343775307
Short name T7
Test name
Test status
Simulation time 5333272133 ps
CPU time 49.24 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:46:39 PM PDT 24
Peak memory 225116 kb
Host smart-c96ca44f-b0ee-4cfb-80d0-8f1c86971b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343775307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3343775307
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.233139320
Short name T49
Test name
Test status
Simulation time 10020248044 ps
CPU time 118.45 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:47:55 PM PDT 24
Peak memory 252260 kb
Host smart-e7ce8fd8-e88a-40f8-a084-6158b51ad32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233139320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.233139320
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.257315015
Short name T251
Test name
Test status
Simulation time 19662482814 ps
CPU time 214.19 seconds
Started Aug 02 06:46:14 PM PDT 24
Finished Aug 02 06:49:48 PM PDT 24
Peak memory 273476 kb
Host smart-dd6c6792-66e6-43f2-b7e3-7c2e83b445da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257315015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.257315015
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3877596795
Short name T214
Test name
Test status
Simulation time 7709823451 ps
CPU time 76.57 seconds
Started Aug 02 06:44:55 PM PDT 24
Finished Aug 02 06:46:11 PM PDT 24
Peak memory 255868 kb
Host smart-98342899-bbfd-4dcc-adf5-166af8854dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877596795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3877596795
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4279857798
Short name T315
Test name
Test status
Simulation time 4593191540 ps
CPU time 14.8 seconds
Started Aug 02 06:44:11 PM PDT 24
Finished Aug 02 06:44:26 PM PDT 24
Peak memory 235256 kb
Host smart-1c2cdee6-a427-4579-a10e-90511832980f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279857798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4279857798
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.73315013
Short name T287
Test name
Test status
Simulation time 44212430403 ps
CPU time 348.18 seconds
Started Aug 02 06:45:38 PM PDT 24
Finished Aug 02 06:51:27 PM PDT 24
Peak memory 257044 kb
Host smart-67c038f5-1cfa-4e28-a601-b2bb139e79f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73315013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.73315013
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3015558467
Short name T58
Test name
Test status
Simulation time 723737297 ps
CPU time 6.41 seconds
Started Aug 02 06:44:34 PM PDT 24
Finished Aug 02 06:44:40 PM PDT 24
Peak memory 233176 kb
Host smart-755ff3bc-31fc-473f-8619-3138fc9f111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015558467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3015558467
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2853854463
Short name T79
Test name
Test status
Simulation time 306932358 ps
CPU time 2.47 seconds
Started Aug 02 05:14:06 PM PDT 24
Finished Aug 02 05:14:09 PM PDT 24
Peak memory 215328 kb
Host smart-57183af7-ad2d-4909-a194-a9e662ad6666
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853854463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
853854463
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3279523616
Short name T161
Test name
Test status
Simulation time 24575106397 ps
CPU time 40.31 seconds
Started Aug 02 06:44:01 PM PDT 24
Finished Aug 02 06:44:41 PM PDT 24
Peak memory 249592 kb
Host smart-65dc8918-78c3-4f54-9773-6be66ea01ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279523616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3279523616
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2159197690
Short name T36
Test name
Test status
Simulation time 74718832340 ps
CPU time 17.9 seconds
Started Aug 02 06:44:02 PM PDT 24
Finished Aug 02 06:44:20 PM PDT 24
Peak memory 219048 kb
Host smart-05ae1b28-b3fb-4066-b474-a0cf54e5ade1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159197690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2159197690
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1926415460
Short name T930
Test name
Test status
Simulation time 11620197850 ps
CPU time 173.66 seconds
Started Aug 02 06:44:11 PM PDT 24
Finished Aug 02 06:47:05 PM PDT 24
Peak memory 270344 kb
Host smart-e3166bfd-cf75-4d26-be65-6bbf7f28e889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926415460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1926415460
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3501965910
Short name T165
Test name
Test status
Simulation time 373973323714 ps
CPU time 257.38 seconds
Started Aug 02 06:44:15 PM PDT 24
Finished Aug 02 06:48:33 PM PDT 24
Peak memory 266024 kb
Host smart-7fc19029-347e-408e-b824-28fcfee66b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501965910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3501965910
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2044987275
Short name T310
Test name
Test status
Simulation time 203421027752 ps
CPU time 261.03 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:48:34 PM PDT 24
Peak memory 249940 kb
Host smart-1c909b19-fc5f-4453-b85d-7d11d6bf0d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044987275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2044987275
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4102804792
Short name T308
Test name
Test status
Simulation time 103493727943 ps
CPU time 252.81 seconds
Started Aug 02 06:45:41 PM PDT 24
Finished Aug 02 06:49:54 PM PDT 24
Peak memory 255104 kb
Host smart-57269f15-00d2-4cd7-afd5-18e6c5c387ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102804792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4102804792
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.516060329
Short name T98
Test name
Test status
Simulation time 86657116 ps
CPU time 1.21 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:13:59 PM PDT 24
Peak memory 206928 kb
Host smart-3224478e-463f-4c05-9fe7-df6de36b8672
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516060329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.516060329
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3991660018
Short name T1130
Test name
Test status
Simulation time 629181791 ps
CPU time 16.14 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:17 PM PDT 24
Peak memory 206916 kb
Host smart-67d73e58-f921-452a-88aa-0d988fc51282
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991660018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3991660018
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2138597609
Short name T1120
Test name
Test status
Simulation time 6527801783 ps
CPU time 22.64 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:31 PM PDT 24
Peak memory 206948 kb
Host smart-3a11a1ec-a23b-4d1f-8c40-d99b9481d2ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138597609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2138597609
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.511806243
Short name T78
Test name
Test status
Simulation time 489296855 ps
CPU time 3.48 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 217768 kb
Host smart-bfce3ca9-a01c-4fb0-8b67-5c4501dd5e9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511806243 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.511806243
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.443952715
Short name T1100
Test name
Test status
Simulation time 176299196 ps
CPU time 2.26 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:12 PM PDT 24
Peak memory 215248 kb
Host smart-13fde94c-a3d8-4d88-987b-1c6b44e70b32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443952715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.443952715
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.63815299
Short name T1128
Test name
Test status
Simulation time 42491944 ps
CPU time 0.76 seconds
Started Aug 02 05:13:57 PM PDT 24
Finished Aug 02 05:13:58 PM PDT 24
Peak memory 203592 kb
Host smart-5444d562-e5a5-43a0-bb52-cb10b819b599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63815299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.63815299
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1073844683
Short name T128
Test name
Test status
Simulation time 23404864 ps
CPU time 1.45 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 215160 kb
Host smart-84a3061f-4936-4404-a52a-bd75c0ee3a53
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073844683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1073844683
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.241948361
Short name T1117
Test name
Test status
Simulation time 11635668 ps
CPU time 0.67 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:01 PM PDT 24
Peak memory 203536 kb
Host smart-1201ade9-2417-4af0-ba52-374601cf5411
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241948361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.241948361
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2023907803
Short name T1088
Test name
Test status
Simulation time 62392205 ps
CPU time 3.58 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:06 PM PDT 24
Peak memory 215060 kb
Host smart-6fedb553-8187-4418-870a-beb34466e33c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023907803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2023907803
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2538513755
Short name T1082
Test name
Test status
Simulation time 1375643584 ps
CPU time 18.8 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:28 PM PDT 24
Peak memory 215436 kb
Host smart-6725038d-12ca-48fe-bbfd-0ef7756417e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538513755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2538513755
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.676782068
Short name T1129
Test name
Test status
Simulation time 1579995878 ps
CPU time 16.38 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:24 PM PDT 24
Peak memory 206804 kb
Host smart-cb2eebb8-d045-4308-8674-175acaf6de1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676782068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.676782068
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2007808838
Short name T136
Test name
Test status
Simulation time 1848289892 ps
CPU time 25.34 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 215204 kb
Host smart-61d158bf-46a2-428d-9238-de3a30c7beb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007808838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2007808838
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2537260967
Short name T1068
Test name
Test status
Simulation time 51361211 ps
CPU time 1.71 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 215148 kb
Host smart-bf116116-14c0-4a74-907e-eddce5ef2a16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537260967 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2537260967
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4100215691
Short name T1073
Test name
Test status
Simulation time 75514357 ps
CPU time 1.25 seconds
Started Aug 02 05:13:58 PM PDT 24
Finished Aug 02 05:14:00 PM PDT 24
Peak memory 206880 kb
Host smart-82a0668d-348e-46fa-a2ca-533171ce7898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100215691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.4
100215691
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2972263253
Short name T1125
Test name
Test status
Simulation time 18071112 ps
CPU time 0.78 seconds
Started Aug 02 05:14:13 PM PDT 24
Finished Aug 02 05:14:14 PM PDT 24
Peak memory 203916 kb
Host smart-f1a10cac-a285-4df2-8072-1a6586dd31d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972263253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
972263253
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3501896581
Short name T1104
Test name
Test status
Simulation time 55121084 ps
CPU time 1.66 seconds
Started Aug 02 05:14:17 PM PDT 24
Finished Aug 02 05:14:18 PM PDT 24
Peak memory 215152 kb
Host smart-27339eed-94d9-43a4-815c-094a5b06115e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501896581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3501896581
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2061524985
Short name T1018
Test name
Test status
Simulation time 18743017 ps
CPU time 0.67 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 203672 kb
Host smart-dd5e6b91-2f91-4c6b-bd0c-55c608bc4941
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061524985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2061524985
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.804531154
Short name T1021
Test name
Test status
Simulation time 110219435 ps
CPU time 2.96 seconds
Started Aug 02 05:14:04 PM PDT 24
Finished Aug 02 05:14:07 PM PDT 24
Peak memory 215140 kb
Host smart-2acb01c2-b15d-403c-a526-9b7bf8116721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804531154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.804531154
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1422589157
Short name T181
Test name
Test status
Simulation time 2167642608 ps
CPU time 19.7 seconds
Started Aug 02 05:14:17 PM PDT 24
Finished Aug 02 05:14:37 PM PDT 24
Peak memory 215236 kb
Host smart-9636fa77-4d4f-488e-9b8f-2c9498dcd988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422589157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1422589157
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3889176859
Short name T1109
Test name
Test status
Simulation time 196291319 ps
CPU time 2.45 seconds
Started Aug 02 05:14:18 PM PDT 24
Finished Aug 02 05:14:20 PM PDT 24
Peak memory 216636 kb
Host smart-8a32553e-ae1e-4a11-924a-26567dea39c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889176859 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3889176859
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.903608613
Short name T1077
Test name
Test status
Simulation time 31213683 ps
CPU time 2 seconds
Started Aug 02 05:14:22 PM PDT 24
Finished Aug 02 05:14:24 PM PDT 24
Peak memory 215080 kb
Host smart-f5116be6-5c60-4875-b6d4-75ced3386bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903608613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.903608613
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3028636741
Short name T1099
Test name
Test status
Simulation time 19788169 ps
CPU time 0.7 seconds
Started Aug 02 05:14:30 PM PDT 24
Finished Aug 02 05:14:31 PM PDT 24
Peak memory 203708 kb
Host smart-ffce0b4d-092c-42c5-ba5f-5a57761cafba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028636741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3028636741
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.770173684
Short name T1072
Test name
Test status
Simulation time 307211875 ps
CPU time 3.84 seconds
Started Aug 02 05:14:20 PM PDT 24
Finished Aug 02 05:14:24 PM PDT 24
Peak memory 215248 kb
Host smart-2761080a-f528-4c8c-92aa-6101e3cd56bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770173684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.770173684
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3956048285
Short name T116
Test name
Test status
Simulation time 995831653 ps
CPU time 4.1 seconds
Started Aug 02 05:14:15 PM PDT 24
Finished Aug 02 05:14:19 PM PDT 24
Peak memory 215256 kb
Host smart-650cc96c-6e49-460e-a8f4-4bc91b2f18fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956048285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3956048285
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.647996892
Short name T121
Test name
Test status
Simulation time 5945411585 ps
CPU time 20.11 seconds
Started Aug 02 05:14:28 PM PDT 24
Finished Aug 02 05:14:49 PM PDT 24
Peak memory 215344 kb
Host smart-81372a8a-3e62-44cc-b5d7-b8fa74336888
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647996892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.647996892
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1529234720
Short name T125
Test name
Test status
Simulation time 798489200 ps
CPU time 3.55 seconds
Started Aug 02 05:14:33 PM PDT 24
Finished Aug 02 05:14:37 PM PDT 24
Peak memory 216928 kb
Host smart-be6fec7c-2999-484c-8317-24eb1a852aa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529234720 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1529234720
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2969192701
Short name T132
Test name
Test status
Simulation time 403930299 ps
CPU time 2.41 seconds
Started Aug 02 05:14:18 PM PDT 24
Finished Aug 02 05:14:21 PM PDT 24
Peak memory 215236 kb
Host smart-7714b344-df8c-4535-9f0d-116e5f6c34da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969192701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2969192701
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1471039263
Short name T1063
Test name
Test status
Simulation time 25466661 ps
CPU time 0.73 seconds
Started Aug 02 05:14:13 PM PDT 24
Finished Aug 02 05:14:14 PM PDT 24
Peak memory 203608 kb
Host smart-3a819a37-af6a-4d48-bed1-6445b05fc881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471039263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1471039263
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2907298912
Short name T1070
Test name
Test status
Simulation time 204177724 ps
CPU time 4.16 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:14 PM PDT 24
Peak memory 215200 kb
Host smart-5f326cb6-dc25-4234-8dfc-02b9b15305bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907298912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2907298912
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4136996855
Short name T114
Test name
Test status
Simulation time 136517893 ps
CPU time 3.69 seconds
Started Aug 02 05:14:32 PM PDT 24
Finished Aug 02 05:14:36 PM PDT 24
Peak memory 215264 kb
Host smart-3034e309-5efe-4559-9920-09669aaec40c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136996855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4136996855
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2913891452
Short name T1127
Test name
Test status
Simulation time 2180808103 ps
CPU time 14.96 seconds
Started Aug 02 05:14:23 PM PDT 24
Finished Aug 02 05:14:38 PM PDT 24
Peak memory 215752 kb
Host smart-bc14f978-48ff-4cbb-b067-c1eb72b989bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913891452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2913891452
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3261483401
Short name T77
Test name
Test status
Simulation time 132789222 ps
CPU time 3.62 seconds
Started Aug 02 05:14:45 PM PDT 24
Finished Aug 02 05:14:48 PM PDT 24
Peak memory 218384 kb
Host smart-6070c3d2-8c79-42e6-bcc8-f460794b695b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261483401 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3261483401
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2706250536
Short name T133
Test name
Test status
Simulation time 113898456 ps
CPU time 2.08 seconds
Started Aug 02 05:14:26 PM PDT 24
Finished Aug 02 05:14:28 PM PDT 24
Peak memory 207008 kb
Host smart-e1df02a2-c223-4414-9358-b25d1a367f47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706250536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2706250536
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3121234882
Short name T1041
Test name
Test status
Simulation time 161851017 ps
CPU time 0.72 seconds
Started Aug 02 05:14:12 PM PDT 24
Finished Aug 02 05:14:13 PM PDT 24
Peak memory 203968 kb
Host smart-a4f9cb56-8d52-4804-909f-45dd44966a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121234882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3121234882
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3899530911
Short name T1027
Test name
Test status
Simulation time 51382499 ps
CPU time 1.91 seconds
Started Aug 02 05:14:10 PM PDT 24
Finished Aug 02 05:14:12 PM PDT 24
Peak memory 215208 kb
Host smart-f9397211-106d-4009-8303-5da65ef43985
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899530911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3899530911
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.239110166
Short name T115
Test name
Test status
Simulation time 55779369 ps
CPU time 3.56 seconds
Started Aug 02 05:14:25 PM PDT 24
Finished Aug 02 05:14:29 PM PDT 24
Peak memory 215248 kb
Host smart-f84bfcb9-3f40-41d9-83c1-60eaca256647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239110166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.239110166
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2741172634
Short name T110
Test name
Test status
Simulation time 1116087112 ps
CPU time 14.19 seconds
Started Aug 02 05:14:17 PM PDT 24
Finished Aug 02 05:14:32 PM PDT 24
Peak memory 223336 kb
Host smart-c217df34-16fa-4f54-a675-a32b7a37cadd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741172634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2741172634
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.950158198
Short name T1071
Test name
Test status
Simulation time 108115906 ps
CPU time 2.72 seconds
Started Aug 02 05:14:18 PM PDT 24
Finished Aug 02 05:14:21 PM PDT 24
Peak memory 216316 kb
Host smart-20a566f4-cf6e-42ea-8969-ee571a95a2d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950158198 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.950158198
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1881590169
Short name T130
Test name
Test status
Simulation time 419778068 ps
CPU time 2.47 seconds
Started Aug 02 05:14:44 PM PDT 24
Finished Aug 02 05:14:47 PM PDT 24
Peak memory 206976 kb
Host smart-fe938bed-9d0c-4b88-a3f7-66932cd400b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881590169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1881590169
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1504244328
Short name T1059
Test name
Test status
Simulation time 13710135 ps
CPU time 0.73 seconds
Started Aug 02 05:14:21 PM PDT 24
Finished Aug 02 05:14:22 PM PDT 24
Peak memory 203976 kb
Host smart-b18bd5b0-38c3-4f20-8873-2b88154560c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504244328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1504244328
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1991114892
Short name T153
Test name
Test status
Simulation time 394953708 ps
CPU time 4.27 seconds
Started Aug 02 05:14:12 PM PDT 24
Finished Aug 02 05:14:16 PM PDT 24
Peak memory 215140 kb
Host smart-40e9f0fa-11ce-4db5-9952-5a70b1355514
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991114892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1991114892
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2675152856
Short name T1098
Test name
Test status
Simulation time 364310512 ps
CPU time 2.81 seconds
Started Aug 02 05:14:29 PM PDT 24
Finished Aug 02 05:14:32 PM PDT 24
Peak memory 215332 kb
Host smart-196f3e38-a371-4547-a109-99774e478df4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675152856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2675152856
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3619184520
Short name T1064
Test name
Test status
Simulation time 203388677 ps
CPU time 3.76 seconds
Started Aug 02 05:14:27 PM PDT 24
Finished Aug 02 05:14:30 PM PDT 24
Peak memory 216812 kb
Host smart-a2c28705-4563-4f88-9759-4e77fba794e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619184520 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3619184520
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1326118974
Short name T1058
Test name
Test status
Simulation time 340774102 ps
CPU time 2.72 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 206976 kb
Host smart-5d3e305b-c347-4c81-abb6-b45b05740630
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326118974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1326118974
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.637936577
Short name T1037
Test name
Test status
Simulation time 24470530 ps
CPU time 0.77 seconds
Started Aug 02 05:14:14 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 203976 kb
Host smart-147268bd-6165-4762-9bdd-94e7cc8b8baa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637936577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.637936577
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3000853369
Short name T163
Test name
Test status
Simulation time 1974810774 ps
CPU time 3.35 seconds
Started Aug 02 05:14:49 PM PDT 24
Finished Aug 02 05:14:52 PM PDT 24
Peak memory 215176 kb
Host smart-b81e0016-ef82-44ba-9b7e-6d8cc111942d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000853369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3000853369
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3657157940
Short name T1111
Test name
Test status
Simulation time 648641087 ps
CPU time 6.12 seconds
Started Aug 02 05:14:19 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 215276 kb
Host smart-1eff4149-0054-4dd5-a439-0ff136fb5b8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657157940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3657157940
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2297297650
Short name T1086
Test name
Test status
Simulation time 955461311 ps
CPU time 21.53 seconds
Started Aug 02 05:14:14 PM PDT 24
Finished Aug 02 05:14:35 PM PDT 24
Peak memory 215872 kb
Host smart-b4f1c82d-027f-40d6-ad09-b315f9156a92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297297650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2297297650
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3839686166
Short name T1123
Test name
Test status
Simulation time 132457821 ps
CPU time 3.53 seconds
Started Aug 02 05:14:17 PM PDT 24
Finished Aug 02 05:14:21 PM PDT 24
Peak memory 217676 kb
Host smart-43fb839c-9d93-4218-8d98-3fff3ff27d1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839686166 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3839686166
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2724787029
Short name T142
Test name
Test status
Simulation time 210178364 ps
CPU time 1.53 seconds
Started Aug 02 05:14:31 PM PDT 24
Finished Aug 02 05:14:33 PM PDT 24
Peak memory 206988 kb
Host smart-41338966-49df-4759-8350-343b96ea9b0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724787029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2724787029
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3441260472
Short name T1116
Test name
Test status
Simulation time 83204699 ps
CPU time 0.74 seconds
Started Aug 02 05:14:15 PM PDT 24
Finished Aug 02 05:14:16 PM PDT 24
Peak memory 203688 kb
Host smart-5ea752c3-7e36-486a-a78a-0deeb557818e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441260472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3441260472
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2933848471
Short name T1094
Test name
Test status
Simulation time 178311927 ps
CPU time 3.92 seconds
Started Aug 02 05:14:39 PM PDT 24
Finished Aug 02 05:14:43 PM PDT 24
Peak memory 215152 kb
Host smart-79a87626-ce2b-4485-a159-f71c69e23ed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933848471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2933848471
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.223959292
Short name T1090
Test name
Test status
Simulation time 48277197 ps
CPU time 1.63 seconds
Started Aug 02 05:14:24 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 215476 kb
Host smart-30f7264a-632f-4407-98ab-2e55a53c0a1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223959292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.223959292
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2892482790
Short name T162
Test name
Test status
Simulation time 794359747 ps
CPU time 12.58 seconds
Started Aug 02 05:14:29 PM PDT 24
Finished Aug 02 05:14:42 PM PDT 24
Peak memory 215872 kb
Host smart-c1218218-e422-48a7-8675-6d0ac985c665
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892482790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2892482790
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2038785994
Short name T1043
Test name
Test status
Simulation time 87488613 ps
CPU time 1.62 seconds
Started Aug 02 05:14:27 PM PDT 24
Finished Aug 02 05:14:29 PM PDT 24
Peak memory 215156 kb
Host smart-d12eee63-57de-4afa-a99a-e918ffb0f352
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038785994 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2038785994
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3249570539
Short name T138
Test name
Test status
Simulation time 242921989 ps
CPU time 1.96 seconds
Started Aug 02 05:14:18 PM PDT 24
Finished Aug 02 05:14:20 PM PDT 24
Peak memory 215296 kb
Host smart-dc67f938-fafa-485f-9614-f2aa36f67763
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249570539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3249570539
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3875634176
Short name T1013
Test name
Test status
Simulation time 49465834 ps
CPU time 0.75 seconds
Started Aug 02 05:14:31 PM PDT 24
Finished Aug 02 05:14:32 PM PDT 24
Peak memory 203688 kb
Host smart-fac8bcdc-576d-4091-b90c-e88bd164aa34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875634176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3875634176
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.196901923
Short name T1057
Test name
Test status
Simulation time 372837199 ps
CPU time 2.92 seconds
Started Aug 02 05:14:35 PM PDT 24
Finished Aug 02 05:14:38 PM PDT 24
Peak memory 215732 kb
Host smart-f5fc1431-6b82-4f0b-8c84-c5fad9f3cddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196901923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.196901923
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3709563423
Short name T180
Test name
Test status
Simulation time 1069920547 ps
CPU time 13.8 seconds
Started Aug 02 05:14:23 PM PDT 24
Finished Aug 02 05:14:37 PM PDT 24
Peak memory 215852 kb
Host smart-ccc69393-4492-4d43-8f4b-a2283351067f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709563423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3709563423
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2792440613
Short name T1079
Test name
Test status
Simulation time 217391358 ps
CPU time 1.73 seconds
Started Aug 02 05:14:10 PM PDT 24
Finished Aug 02 05:14:12 PM PDT 24
Peak memory 216188 kb
Host smart-4526adfa-ccf6-4d7b-9a66-ffb71f3c0642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792440613 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2792440613
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.275229638
Short name T141
Test name
Test status
Simulation time 115788650 ps
CPU time 1.9 seconds
Started Aug 02 05:14:30 PM PDT 24
Finished Aug 02 05:14:32 PM PDT 24
Peak memory 215284 kb
Host smart-f36d6b9f-e6d8-4697-8ba0-72c9b806ca5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275229638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.275229638
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.308998916
Short name T1030
Test name
Test status
Simulation time 48808151 ps
CPU time 0.7 seconds
Started Aug 02 05:14:20 PM PDT 24
Finished Aug 02 05:14:20 PM PDT 24
Peak memory 203980 kb
Host smart-297495ce-be59-412c-a19e-be82c5e07242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308998916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.308998916
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.267999819
Short name T155
Test name
Test status
Simulation time 64805818 ps
CPU time 1.89 seconds
Started Aug 02 05:14:38 PM PDT 24
Finished Aug 02 05:14:40 PM PDT 24
Peak memory 215128 kb
Host smart-c1077fc1-c4f0-47a9-b58b-89adb8eaf2f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267999819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.267999819
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1993104393
Short name T120
Test name
Test status
Simulation time 81948560 ps
CPU time 4.95 seconds
Started Aug 02 05:14:22 PM PDT 24
Finished Aug 02 05:14:27 PM PDT 24
Peak memory 216476 kb
Host smart-76655e29-f9ae-4e60-ac0f-820e8680536c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993104393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1993104393
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1623430544
Short name T1045
Test name
Test status
Simulation time 3527747778 ps
CPU time 22.7 seconds
Started Aug 02 05:14:15 PM PDT 24
Finished Aug 02 05:14:38 PM PDT 24
Peak memory 215344 kb
Host smart-ba8dc192-3e51-45de-913e-19d44d5f26c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623430544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1623430544
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4174604028
Short name T1062
Test name
Test status
Simulation time 377789703 ps
CPU time 3.75 seconds
Started Aug 02 05:14:37 PM PDT 24
Finished Aug 02 05:14:41 PM PDT 24
Peak memory 216804 kb
Host smart-b2e5fc20-f27b-4f32-8d71-1eee829f6f11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174604028 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4174604028
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3860033917
Short name T1032
Test name
Test status
Simulation time 169102374 ps
CPU time 1.36 seconds
Started Aug 02 05:14:31 PM PDT 24
Finished Aug 02 05:14:33 PM PDT 24
Peak memory 215188 kb
Host smart-44b7876b-5fd8-45f9-a2ac-0508723604fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860033917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3860033917
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1433307593
Short name T1034
Test name
Test status
Simulation time 70401697 ps
CPU time 0.76 seconds
Started Aug 02 05:14:28 PM PDT 24
Finished Aug 02 05:14:29 PM PDT 24
Peak memory 203624 kb
Host smart-d533a4f4-2d07-454b-9342-e02d7feef157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433307593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1433307593
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.391643589
Short name T1036
Test name
Test status
Simulation time 118183997 ps
CPU time 3.6 seconds
Started Aug 02 05:14:12 PM PDT 24
Finished Aug 02 05:14:16 PM PDT 24
Peak memory 215880 kb
Host smart-d0469434-9521-4ac2-8f37-1a76774ead39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391643589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.391643589
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.147963320
Short name T1113
Test name
Test status
Simulation time 65167388 ps
CPU time 1.75 seconds
Started Aug 02 05:14:12 PM PDT 24
Finished Aug 02 05:14:14 PM PDT 24
Peak memory 215264 kb
Host smart-b3e6a115-9577-49d5-aa71-3c4bc7e522ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147963320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.147963320
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.877329435
Short name T126
Test name
Test status
Simulation time 107075829 ps
CPU time 6.41 seconds
Started Aug 02 05:14:28 PM PDT 24
Finished Aug 02 05:14:35 PM PDT 24
Peak memory 215216 kb
Host smart-dd1eb500-d27a-4e74-b994-0b09e125c71a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877329435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.877329435
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4226461141
Short name T1055
Test name
Test status
Simulation time 365572518 ps
CPU time 2.63 seconds
Started Aug 02 05:14:21 PM PDT 24
Finished Aug 02 05:14:24 PM PDT 24
Peak memory 216908 kb
Host smart-a79fcf5a-5253-435c-b65d-525a86177f44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226461141 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4226461141
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1554548893
Short name T1069
Test name
Test status
Simulation time 38732083 ps
CPU time 2.3 seconds
Started Aug 02 05:14:36 PM PDT 24
Finished Aug 02 05:14:38 PM PDT 24
Peak memory 207076 kb
Host smart-e0d99c1d-2a5a-405d-a53a-070c29069b0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554548893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1554548893
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1063753574
Short name T1102
Test name
Test status
Simulation time 29788613 ps
CPU time 0.7 seconds
Started Aug 02 05:14:19 PM PDT 24
Finished Aug 02 05:14:19 PM PDT 24
Peak memory 203980 kb
Host smart-73ff185d-eba4-4e49-b18b-a633667c433c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063753574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1063753574
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1467297636
Short name T1091
Test name
Test status
Simulation time 80868902 ps
CPU time 2.03 seconds
Started Aug 02 05:14:29 PM PDT 24
Finished Aug 02 05:14:32 PM PDT 24
Peak memory 215104 kb
Host smart-af8e0139-7e57-40dc-b083-4c136bde307f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467297636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1467297636
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4160068021
Short name T1092
Test name
Test status
Simulation time 240958515 ps
CPU time 2.22 seconds
Started Aug 02 05:14:27 PM PDT 24
Finished Aug 02 05:14:30 PM PDT 24
Peak memory 215440 kb
Host smart-e2a5dafe-7fe1-400c-b888-8fb0b1702344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160068021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4160068021
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2688746796
Short name T1080
Test name
Test status
Simulation time 1985784511 ps
CPU time 14.75 seconds
Started Aug 02 05:14:40 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 215208 kb
Host smart-c487c61b-39db-4884-b787-bf911a7a64f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688746796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2688746796
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1177520487
Short name T1011
Test name
Test status
Simulation time 218421559 ps
CPU time 7.68 seconds
Started Aug 02 05:14:01 PM PDT 24
Finished Aug 02 05:14:09 PM PDT 24
Peak memory 206932 kb
Host smart-b7aee452-d8ad-45f9-b2f4-2b3a60609362
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177520487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1177520487
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2599482071
Short name T1023
Test name
Test status
Simulation time 2630718900 ps
CPU time 13.3 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:13 PM PDT 24
Peak memory 207004 kb
Host smart-71432d62-c1aa-42ae-854c-9b9470593648
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599482071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2599482071
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2013549186
Short name T1066
Test name
Test status
Simulation time 43166114 ps
CPU time 0.95 seconds
Started Aug 02 05:14:06 PM PDT 24
Finished Aug 02 05:14:07 PM PDT 24
Peak memory 206876 kb
Host smart-4843d210-8548-4c26-9692-e7250cb33e6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013549186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2013549186
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.320235555
Short name T1096
Test name
Test status
Simulation time 93898025 ps
CPU time 1.65 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:04 PM PDT 24
Peak memory 215172 kb
Host smart-85c98d25-01f5-46a2-9c69-66857c0ee55a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320235555 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.320235555
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.675842897
Short name T140
Test name
Test status
Simulation time 28279528 ps
CPU time 1.75 seconds
Started Aug 02 05:14:13 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 215132 kb
Host smart-224e5a33-ae37-45a0-8da6-3175d6bc13bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675842897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.675842897
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2295953271
Short name T1051
Test name
Test status
Simulation time 21153642 ps
CPU time 0.69 seconds
Started Aug 02 05:14:05 PM PDT 24
Finished Aug 02 05:14:05 PM PDT 24
Peak memory 203872 kb
Host smart-453bdaf7-4af0-4d34-9e00-145d89b0fb60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295953271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
295953271
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1629750118
Short name T134
Test name
Test status
Simulation time 96167104 ps
CPU time 1.65 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:02 PM PDT 24
Peak memory 215196 kb
Host smart-6ab54a43-868e-4dcc-8ad3-88328648d42a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629750118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1629750118
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1873877890
Short name T1028
Test name
Test status
Simulation time 101446132 ps
CPU time 0.66 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:18 PM PDT 24
Peak memory 203632 kb
Host smart-ee050ff3-600e-4adf-b4fd-60095b1b79dd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873877890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1873877890
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2538712353
Short name T1050
Test name
Test status
Simulation time 88098905 ps
CPU time 1.7 seconds
Started Aug 02 05:13:59 PM PDT 24
Finished Aug 02 05:14:01 PM PDT 24
Peak memory 215188 kb
Host smart-1cc38a99-0936-459e-b3d3-aa8616421a84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538712353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2538712353
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3511556124
Short name T1122
Test name
Test status
Simulation time 311040009 ps
CPU time 4.96 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:12 PM PDT 24
Peak memory 215372 kb
Host smart-4e32f0f5-de99-43f0-a648-a2be36706785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511556124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
511556124
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3081924658
Short name T1010
Test name
Test status
Simulation time 11768508 ps
CPU time 0.68 seconds
Started Aug 02 05:14:46 PM PDT 24
Finished Aug 02 05:14:47 PM PDT 24
Peak memory 203696 kb
Host smart-35cc1410-c042-4c8b-aed3-41077e61aa3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081924658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3081924658
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1589823976
Short name T1103
Test name
Test status
Simulation time 14405346 ps
CPU time 0.74 seconds
Started Aug 02 05:14:34 PM PDT 24
Finished Aug 02 05:14:35 PM PDT 24
Peak memory 204016 kb
Host smart-adf74024-4065-4aef-9639-42336a23dc35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589823976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1589823976
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1175445290
Short name T1040
Test name
Test status
Simulation time 16408856 ps
CPU time 0.72 seconds
Started Aug 02 05:14:21 PM PDT 24
Finished Aug 02 05:14:22 PM PDT 24
Peak memory 203712 kb
Host smart-58f669ff-3e5a-474e-9322-f261152b0dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175445290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1175445290
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4173051116
Short name T1012
Test name
Test status
Simulation time 12937785 ps
CPU time 0.75 seconds
Started Aug 02 05:14:33 PM PDT 24
Finished Aug 02 05:14:34 PM PDT 24
Peak memory 203632 kb
Host smart-fc93ea05-86c0-4e35-b961-dde373eff14d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173051116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4173051116
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1778919114
Short name T1105
Test name
Test status
Simulation time 78705525 ps
CPU time 0.75 seconds
Started Aug 02 05:14:39 PM PDT 24
Finished Aug 02 05:14:40 PM PDT 24
Peak memory 204096 kb
Host smart-5206de50-a1df-4dec-9774-77c3c584a4fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778919114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1778919114
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3859264759
Short name T1085
Test name
Test status
Simulation time 30341479 ps
CPU time 0.72 seconds
Started Aug 02 05:14:25 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 203620 kb
Host smart-07751d4a-6711-492f-b449-b3b01a65f57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859264759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3859264759
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.534667389
Short name T1065
Test name
Test status
Simulation time 32253809 ps
CPU time 0.68 seconds
Started Aug 02 05:14:47 PM PDT 24
Finished Aug 02 05:14:47 PM PDT 24
Peak memory 203704 kb
Host smart-f2465304-7cd1-41a8-8ac4-ab640c2b9952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534667389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.534667389
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3802929228
Short name T1093
Test name
Test status
Simulation time 19548432 ps
CPU time 0.71 seconds
Started Aug 02 05:14:25 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 203920 kb
Host smart-8d18b48d-6419-4aa6-b882-585b690061eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802929228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3802929228
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3673119231
Short name T1033
Test name
Test status
Simulation time 50447409 ps
CPU time 0.69 seconds
Started Aug 02 05:14:12 PM PDT 24
Finished Aug 02 05:14:18 PM PDT 24
Peak memory 203756 kb
Host smart-9ae15c9b-f136-4ba7-91e7-7caf87e7825a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673119231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3673119231
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1219547455
Short name T1016
Test name
Test status
Simulation time 42044061 ps
CPU time 0.68 seconds
Started Aug 02 05:14:21 PM PDT 24
Finished Aug 02 05:14:22 PM PDT 24
Peak memory 203696 kb
Host smart-9852fca2-2e14-4a5a-a682-db0d74ae87ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219547455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1219547455
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.109727856
Short name T1107
Test name
Test status
Simulation time 117237313 ps
CPU time 7.11 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 206904 kb
Host smart-e021a8cf-bc8b-46a1-9c98-c61a78d3a416
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109727856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.109727856
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3026116854
Short name T1131
Test name
Test status
Simulation time 614635866 ps
CPU time 13.11 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:20 PM PDT 24
Peak memory 215144 kb
Host smart-6231b4c0-6e5c-43ac-9875-59bc8a3d1d04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026116854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3026116854
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3993053779
Short name T100
Test name
Test status
Simulation time 15636060 ps
CPU time 0.96 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:10 PM PDT 24
Peak memory 206620 kb
Host smart-36d11936-45ba-4850-b8c0-9842361eb3be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993053779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3993053779
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.282411770
Short name T122
Test name
Test status
Simulation time 300323153 ps
CPU time 1.63 seconds
Started Aug 02 05:14:24 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 215168 kb
Host smart-c622e9a5-77cc-447d-b017-56f0a0c4069a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282411770 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.282411770
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.49126937
Short name T1126
Test name
Test status
Simulation time 54522247 ps
CPU time 1.92 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:04 PM PDT 24
Peak memory 215068 kb
Host smart-2d44c2cd-002a-42b4-ade2-d7cbeff386a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49126937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.49126937
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2221869454
Short name T1019
Test name
Test status
Simulation time 10979792 ps
CPU time 0.71 seconds
Started Aug 02 05:14:16 PM PDT 24
Finished Aug 02 05:14:16 PM PDT 24
Peak memory 203604 kb
Host smart-e877f6c4-b7ab-4015-8028-771f8f9c7b55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221869454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
221869454
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3073017506
Short name T1110
Test name
Test status
Simulation time 195941090 ps
CPU time 1.68 seconds
Started Aug 02 05:14:05 PM PDT 24
Finished Aug 02 05:14:07 PM PDT 24
Peak memory 215080 kb
Host smart-d713c7df-37a1-465f-9f2f-8d782a73dbbf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073017506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3073017506
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2869619963
Short name T1039
Test name
Test status
Simulation time 34852757 ps
CPU time 0.67 seconds
Started Aug 02 05:14:10 PM PDT 24
Finished Aug 02 05:14:10 PM PDT 24
Peak memory 203524 kb
Host smart-399b2708-fb62-49eb-b0a6-d7a59153904f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869619963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2869619963
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2891111191
Short name T1014
Test name
Test status
Simulation time 250183715 ps
CPU time 1.86 seconds
Started Aug 02 05:14:03 PM PDT 24
Finished Aug 02 05:14:05 PM PDT 24
Peak memory 214724 kb
Host smart-8cce240e-7e0b-4276-a1b2-f4cecac0b034
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891111191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2891111191
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2208259156
Short name T1048
Test name
Test status
Simulation time 126905889 ps
CPU time 2.84 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 215328 kb
Host smart-76227f0a-0c5a-4a17-9429-f78108cf02ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208259156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
208259156
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.321441842
Short name T182
Test name
Test status
Simulation time 300871494 ps
CPU time 18.81 seconds
Started Aug 02 05:14:03 PM PDT 24
Finished Aug 02 05:14:22 PM PDT 24
Peak memory 215180 kb
Host smart-b29d43bd-f54f-4eb9-8278-ff0db321e35e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321441842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.321441842
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3560971782
Short name T1056
Test name
Test status
Simulation time 28770002 ps
CPU time 0.75 seconds
Started Aug 02 05:14:44 PM PDT 24
Finished Aug 02 05:14:45 PM PDT 24
Peak memory 203608 kb
Host smart-415256be-a894-4c16-872e-3be23ba5bdb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560971782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3560971782
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3537854162
Short name T1108
Test name
Test status
Simulation time 54066562 ps
CPU time 0.74 seconds
Started Aug 02 05:14:32 PM PDT 24
Finished Aug 02 05:14:33 PM PDT 24
Peak memory 203660 kb
Host smart-8321bffe-483d-4c28-a99c-3c30ee915bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537854162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3537854162
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1376794977
Short name T1022
Test name
Test status
Simulation time 13982600 ps
CPU time 0.76 seconds
Started Aug 02 05:14:27 PM PDT 24
Finished Aug 02 05:14:28 PM PDT 24
Peak memory 203960 kb
Host smart-0debc3fa-45ec-4cd2-a8b2-9af7d9ca4963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376794977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1376794977
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.448974523
Short name T1081
Test name
Test status
Simulation time 14762939 ps
CPU time 0.71 seconds
Started Aug 02 05:14:26 PM PDT 24
Finished Aug 02 05:14:27 PM PDT 24
Peak memory 203920 kb
Host smart-5625f493-203c-4380-a4f8-5299aeb14961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448974523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.448974523
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1889722209
Short name T1089
Test name
Test status
Simulation time 29622527 ps
CPU time 0.73 seconds
Started Aug 02 05:14:36 PM PDT 24
Finished Aug 02 05:14:36 PM PDT 24
Peak memory 203732 kb
Host smart-b0a0c322-71f3-4edf-9088-066a6b68e9e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889722209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1889722209
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3948951244
Short name T1124
Test name
Test status
Simulation time 14667163 ps
CPU time 0.74 seconds
Started Aug 02 05:14:25 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 203604 kb
Host smart-2e6a7371-f172-4048-a19a-e3a9fec6132b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948951244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3948951244
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4254894280
Short name T1038
Test name
Test status
Simulation time 22090630 ps
CPU time 0.69 seconds
Started Aug 02 05:14:13 PM PDT 24
Finished Aug 02 05:14:19 PM PDT 24
Peak memory 203656 kb
Host smart-d7bb468d-6b53-4e90-9dd1-2f3e2576c2cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254894280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4254894280
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3401063417
Short name T1112
Test name
Test status
Simulation time 16661945 ps
CPU time 0.77 seconds
Started Aug 02 05:14:23 PM PDT 24
Finished Aug 02 05:14:24 PM PDT 24
Peak memory 203640 kb
Host smart-0be47777-fc70-43a4-883f-47e0d9c91412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401063417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3401063417
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3031707145
Short name T1025
Test name
Test status
Simulation time 17765759 ps
CPU time 0.74 seconds
Started Aug 02 05:14:16 PM PDT 24
Finished Aug 02 05:14:17 PM PDT 24
Peak memory 203660 kb
Host smart-0dcb554d-4c77-483c-8cdb-ad08a036739d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031707145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3031707145
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1013143957
Short name T1015
Test name
Test status
Simulation time 16767169 ps
CPU time 0.74 seconds
Started Aug 02 05:14:30 PM PDT 24
Finished Aug 02 05:14:31 PM PDT 24
Peak memory 203724 kb
Host smart-c3783763-93da-4303-b3f8-78f0911be219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013143957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1013143957
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3941389673
Short name T139
Test name
Test status
Simulation time 1723093591 ps
CPU time 8.29 seconds
Started Aug 02 05:14:10 PM PDT 24
Finished Aug 02 05:14:19 PM PDT 24
Peak memory 206980 kb
Host smart-4aaccd6b-4eb5-4ebd-8013-54ea58aaf28f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941389673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3941389673
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1282617306
Short name T129
Test name
Test status
Simulation time 5500382705 ps
CPU time 39.55 seconds
Started Aug 02 05:14:14 PM PDT 24
Finished Aug 02 05:14:54 PM PDT 24
Peak memory 206456 kb
Host smart-dda0dc66-a5d1-49c1-8762-67bf2252e0ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282617306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1282617306
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2248752338
Short name T101
Test name
Test status
Simulation time 75242999 ps
CPU time 1.43 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:10 PM PDT 24
Peak memory 206844 kb
Host smart-d65fd599-c363-46b0-a9a7-c76af031be60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248752338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2248752338
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3345757299
Short name T1076
Test name
Test status
Simulation time 41261570 ps
CPU time 2.27 seconds
Started Aug 02 05:14:20 PM PDT 24
Finished Aug 02 05:14:22 PM PDT 24
Peak memory 217608 kb
Host smart-a736c469-bffb-4519-ab49-661f590cadd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345757299 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3345757299
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3181944202
Short name T1101
Test name
Test status
Simulation time 90666595 ps
CPU time 2.57 seconds
Started Aug 02 05:14:10 PM PDT 24
Finished Aug 02 05:14:13 PM PDT 24
Peak memory 215192 kb
Host smart-77c32632-3a66-47d2-90b1-2489619e08a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181944202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
181944202
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1754519922
Short name T1054
Test name
Test status
Simulation time 23529061 ps
CPU time 0.71 seconds
Started Aug 02 05:14:12 PM PDT 24
Finished Aug 02 05:14:13 PM PDT 24
Peak memory 203176 kb
Host smart-34bd30bf-0fd6-4e00-b932-12a96204c067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754519922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
754519922
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1894409312
Short name T1074
Test name
Test status
Simulation time 66322053 ps
CPU time 2.18 seconds
Started Aug 02 05:14:05 PM PDT 24
Finished Aug 02 05:14:08 PM PDT 24
Peak memory 215140 kb
Host smart-e76fac23-66d1-42f1-a5e0-e1c007bcf4f5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894409312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1894409312
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1358309375
Short name T1017
Test name
Test status
Simulation time 38199663 ps
CPU time 0.63 seconds
Started Aug 02 05:14:08 PM PDT 24
Finished Aug 02 05:14:09 PM PDT 24
Peak memory 203620 kb
Host smart-3d290afc-3111-43ed-bffa-217c500e427c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358309375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1358309375
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.91229142
Short name T1121
Test name
Test status
Simulation time 61187488 ps
CPU time 1.86 seconds
Started Aug 02 05:14:13 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 207016 kb
Host smart-7077a349-5d58-427c-a52b-78d1be05af32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91229142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_same_csr_outstanding.91229142
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3389968567
Short name T119
Test name
Test status
Simulation time 76655998 ps
CPU time 2.1 seconds
Started Aug 02 05:14:25 PM PDT 24
Finished Aug 02 05:14:27 PM PDT 24
Peak memory 215364 kb
Host smart-f35be10d-cf5b-442b-8d99-81209a0d8076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389968567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
389968567
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.545288411
Short name T1042
Test name
Test status
Simulation time 1619310989 ps
CPU time 22.98 seconds
Started Aug 02 05:14:17 PM PDT 24
Finished Aug 02 05:14:40 PM PDT 24
Peak memory 223396 kb
Host smart-0bb7aaa4-ef95-4977-9ff0-17a5901e6495
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545288411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.545288411
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2226439747
Short name T1049
Test name
Test status
Simulation time 12113605 ps
CPU time 0.7 seconds
Started Aug 02 05:14:36 PM PDT 24
Finished Aug 02 05:14:37 PM PDT 24
Peak memory 203676 kb
Host smart-e350c968-8f82-4e26-8165-e594463ba994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226439747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2226439747
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.103612420
Short name T1060
Test name
Test status
Simulation time 15227294 ps
CPU time 0.76 seconds
Started Aug 02 05:14:25 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 203720 kb
Host smart-bd5bc05c-5a7e-475f-9a8f-de4abdc0267f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103612420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.103612420
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.895796003
Short name T1031
Test name
Test status
Simulation time 13028025 ps
CPU time 0.73 seconds
Started Aug 02 05:14:23 PM PDT 24
Finished Aug 02 05:14:24 PM PDT 24
Peak memory 203716 kb
Host smart-c2937ec8-c0ea-422f-9cc5-47e2d787e574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895796003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.895796003
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2862957728
Short name T1053
Test name
Test status
Simulation time 42057971 ps
CPU time 0.7 seconds
Started Aug 02 05:14:22 PM PDT 24
Finished Aug 02 05:14:23 PM PDT 24
Peak memory 203964 kb
Host smart-c43b7936-f5ac-44e2-b2f6-0dbb1195413c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862957728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2862957728
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1049636198
Short name T1097
Test name
Test status
Simulation time 94199517 ps
CPU time 0.76 seconds
Started Aug 02 05:14:33 PM PDT 24
Finished Aug 02 05:14:34 PM PDT 24
Peak memory 203696 kb
Host smart-35622234-62b2-4e1b-bdff-a9584dd368d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049636198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1049636198
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.336427416
Short name T1044
Test name
Test status
Simulation time 10905975 ps
CPU time 0.7 seconds
Started Aug 02 05:14:12 PM PDT 24
Finished Aug 02 05:14:13 PM PDT 24
Peak memory 203660 kb
Host smart-5c77bbe7-f74d-42f7-8d80-34820ee3f77c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336427416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.336427416
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3856508779
Short name T1052
Test name
Test status
Simulation time 25494252 ps
CPU time 0.69 seconds
Started Aug 02 05:14:27 PM PDT 24
Finished Aug 02 05:14:27 PM PDT 24
Peak memory 203708 kb
Host smart-2f2edcb1-e116-497c-8009-3c30e9d3b244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856508779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3856508779
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1237062797
Short name T1061
Test name
Test status
Simulation time 49357821 ps
CPU time 0.72 seconds
Started Aug 02 05:14:43 PM PDT 24
Finished Aug 02 05:14:44 PM PDT 24
Peak memory 203700 kb
Host smart-2864c3d1-cfc3-4c88-8095-a7fedee1839b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237062797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1237062797
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3390676754
Short name T1087
Test name
Test status
Simulation time 43893905 ps
CPU time 0.76 seconds
Started Aug 02 05:14:34 PM PDT 24
Finished Aug 02 05:14:35 PM PDT 24
Peak memory 203680 kb
Host smart-5692af31-23bc-42c0-bef6-9f413daa57e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390676754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3390676754
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1857916452
Short name T1024
Test name
Test status
Simulation time 19231097 ps
CPU time 0.68 seconds
Started Aug 02 05:14:17 PM PDT 24
Finished Aug 02 05:14:18 PM PDT 24
Peak memory 203992 kb
Host smart-9a796efa-b0c2-46fa-9d54-3423b7d95266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857916452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1857916452
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1671563563
Short name T1095
Test name
Test status
Simulation time 236720706 ps
CPU time 2.54 seconds
Started Aug 02 05:14:07 PM PDT 24
Finished Aug 02 05:14:09 PM PDT 24
Peak memory 216836 kb
Host smart-f752e800-7a13-4eb8-9608-29d0c58347a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671563563 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1671563563
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2856328307
Short name T127
Test name
Test status
Simulation time 154509497 ps
CPU time 2.53 seconds
Started Aug 02 05:14:12 PM PDT 24
Finished Aug 02 05:14:15 PM PDT 24
Peak memory 215276 kb
Host smart-6b8a6c85-ed3c-4841-a8a5-00c76f8eb775
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856328307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
856328307
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.196271592
Short name T1047
Test name
Test status
Simulation time 52353564 ps
CPU time 0.76 seconds
Started Aug 02 05:14:20 PM PDT 24
Finished Aug 02 05:14:20 PM PDT 24
Peak memory 203692 kb
Host smart-10ccd10d-481c-49c9-8146-88392a5f24b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196271592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.196271592
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4059988684
Short name T1046
Test name
Test status
Simulation time 124724144 ps
CPU time 3.16 seconds
Started Aug 02 05:14:22 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 215132 kb
Host smart-c092b51d-e869-48b4-8f30-3bbd5805c3e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059988684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4059988684
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4204287764
Short name T1078
Test name
Test status
Simulation time 137968656 ps
CPU time 3.58 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:03 PM PDT 24
Peak memory 215432 kb
Host smart-a9f94333-c377-4b8a-891e-031cb2fc6463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204287764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
204287764
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1699864419
Short name T164
Test name
Test status
Simulation time 1226274677 ps
CPU time 7.68 seconds
Started Aug 02 05:14:10 PM PDT 24
Finished Aug 02 05:14:18 PM PDT 24
Peak memory 215148 kb
Host smart-50f3ab5e-2a4f-48dd-9530-ec4753503021
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699864419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1699864419
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3676057086
Short name T1029
Test name
Test status
Simulation time 209225928 ps
CPU time 3.49 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:05 PM PDT 24
Peak memory 217740 kb
Host smart-d1086cc2-aec6-4f8d-a0c3-bcea1b9de8bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676057086 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3676057086
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1261141174
Short name T135
Test name
Test status
Simulation time 30441914 ps
CPU time 1.66 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 215204 kb
Host smart-bd8b8c5b-11b6-455b-bdf0-2f1f8eb44ecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261141174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
261141174
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2318486167
Short name T1083
Test name
Test status
Simulation time 16859940 ps
CPU time 0.8 seconds
Started Aug 02 05:14:16 PM PDT 24
Finished Aug 02 05:14:17 PM PDT 24
Peak memory 203608 kb
Host smart-209c5960-ed9b-4c1e-998b-7f295db7b73d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318486167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
318486167
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3117022168
Short name T1020
Test name
Test status
Simulation time 1661519661 ps
CPU time 4.16 seconds
Started Aug 02 05:14:00 PM PDT 24
Finished Aug 02 05:14:04 PM PDT 24
Peak memory 215208 kb
Host smart-cea7771c-7c05-4f9c-9e25-4c9491730c81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117022168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3117022168
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3546445196
Short name T177
Test name
Test status
Simulation time 265460178 ps
CPU time 1.82 seconds
Started Aug 02 05:14:18 PM PDT 24
Finished Aug 02 05:14:20 PM PDT 24
Peak memory 215568 kb
Host smart-c254c9a9-9418-48a5-872d-369b4ca5a361
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546445196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
546445196
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3522773201
Short name T124
Test name
Test status
Simulation time 745561329 ps
CPU time 7.94 seconds
Started Aug 02 05:14:02 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 216436 kb
Host smart-be006eec-fd4a-4fd2-839b-741a3d65689c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522773201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3522773201
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1930948067
Short name T1067
Test name
Test status
Simulation time 90327079 ps
CPU time 1.52 seconds
Started Aug 02 05:14:18 PM PDT 24
Finished Aug 02 05:14:20 PM PDT 24
Peak memory 215300 kb
Host smart-b198d578-584a-4846-9be8-284659196954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930948067 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1930948067
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4184979109
Short name T137
Test name
Test status
Simulation time 82486892 ps
CPU time 2.13 seconds
Started Aug 02 05:14:27 PM PDT 24
Finished Aug 02 05:14:29 PM PDT 24
Peak memory 206944 kb
Host smart-a18f7f7b-d98f-4ab0-8b53-a5942be49ab8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184979109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
184979109
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1437140278
Short name T1026
Test name
Test status
Simulation time 13088828 ps
CPU time 0.7 seconds
Started Aug 02 05:14:37 PM PDT 24
Finished Aug 02 05:14:38 PM PDT 24
Peak memory 203740 kb
Host smart-47d6df49-82be-4fda-bbc2-b3a5353f6333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437140278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
437140278
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1863039314
Short name T154
Test name
Test status
Simulation time 191430550 ps
CPU time 4.29 seconds
Started Aug 02 05:14:18 PM PDT 24
Finished Aug 02 05:14:23 PM PDT 24
Peak memory 215216 kb
Host smart-0291c809-81fa-4a05-aef0-d23a6408a3d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863039314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1863039314
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3152085686
Short name T1114
Test name
Test status
Simulation time 70493776 ps
CPU time 2.08 seconds
Started Aug 02 05:14:09 PM PDT 24
Finished Aug 02 05:14:11 PM PDT 24
Peak memory 215344 kb
Host smart-1fe79730-cf17-4c59-a5e1-c4f3dde31b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152085686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
152085686
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1175390628
Short name T179
Test name
Test status
Simulation time 1106585419 ps
CPU time 18.03 seconds
Started Aug 02 05:14:20 PM PDT 24
Finished Aug 02 05:14:39 PM PDT 24
Peak memory 215264 kb
Host smart-0762a11e-1d91-428e-b08a-6ccc55cd24bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175390628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1175390628
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2687518143
Short name T1035
Test name
Test status
Simulation time 490813842 ps
CPU time 1.54 seconds
Started Aug 02 05:14:40 PM PDT 24
Finished Aug 02 05:14:42 PM PDT 24
Peak memory 215280 kb
Host smart-e2af3866-106a-485e-9cfb-cc15f62ad15a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687518143 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2687518143
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2727604694
Short name T1106
Test name
Test status
Simulation time 71147784 ps
CPU time 1.84 seconds
Started Aug 02 05:14:28 PM PDT 24
Finished Aug 02 05:14:30 PM PDT 24
Peak memory 215232 kb
Host smart-b59e57d7-c898-45f0-811e-94faab8f1587
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727604694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
727604694
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1994698305
Short name T1075
Test name
Test status
Simulation time 18588925 ps
CPU time 0.7 seconds
Started Aug 02 05:14:18 PM PDT 24
Finished Aug 02 05:14:19 PM PDT 24
Peak memory 203708 kb
Host smart-bdd0063a-ca64-431d-9188-11fc45f6b419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994698305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
994698305
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1823113952
Short name T1115
Test name
Test status
Simulation time 626242249 ps
CPU time 3.07 seconds
Started Aug 02 05:14:17 PM PDT 24
Finished Aug 02 05:14:20 PM PDT 24
Peak memory 215112 kb
Host smart-87bb8f46-3066-48c0-9995-e006477b057e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823113952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1823113952
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.305257260
Short name T112
Test name
Test status
Simulation time 965837587 ps
CPU time 1.91 seconds
Started Aug 02 05:14:06 PM PDT 24
Finished Aug 02 05:14:08 PM PDT 24
Peak memory 215404 kb
Host smart-be63f330-f9b0-4d03-9fa6-5c7ddbd652da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305257260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.305257260
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3862060025
Short name T1118
Test name
Test status
Simulation time 25146791 ps
CPU time 1.71 seconds
Started Aug 02 05:14:27 PM PDT 24
Finished Aug 02 05:14:28 PM PDT 24
Peak memory 215292 kb
Host smart-a9ddd1ec-8abf-4bec-92c5-30204ff443a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862060025 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3862060025
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3044247341
Short name T131
Test name
Test status
Simulation time 106524710 ps
CPU time 2.19 seconds
Started Aug 02 05:14:23 PM PDT 24
Finished Aug 02 05:14:26 PM PDT 24
Peak memory 215252 kb
Host smart-29257689-acc5-403a-8025-4549e0237fa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044247341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
044247341
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1899024676
Short name T1084
Test name
Test status
Simulation time 26812657 ps
CPU time 0.76 seconds
Started Aug 02 05:14:17 PM PDT 24
Finished Aug 02 05:14:18 PM PDT 24
Peak memory 203624 kb
Host smart-70829938-ef0f-4d8a-b886-90a94dceef19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899024676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
899024676
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1318197857
Short name T1119
Test name
Test status
Simulation time 458700426 ps
CPU time 3.06 seconds
Started Aug 02 05:14:31 PM PDT 24
Finished Aug 02 05:14:34 PM PDT 24
Peak memory 215256 kb
Host smart-5e8411c3-60e3-4981-b90c-a8293888c7a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318197857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1318197857
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1111266480
Short name T117
Test name
Test status
Simulation time 89435879 ps
CPU time 1.5 seconds
Started Aug 02 05:14:28 PM PDT 24
Finished Aug 02 05:14:30 PM PDT 24
Peak memory 215244 kb
Host smart-e729decc-7d92-40e4-bb1c-3fa0d85f75a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111266480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
111266480
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.516920499
Short name T178
Test name
Test status
Simulation time 796728618 ps
CPU time 19.71 seconds
Started Aug 02 05:14:12 PM PDT 24
Finished Aug 02 05:14:37 PM PDT 24
Peak memory 215416 kb
Host smart-5938caa6-d4ff-4a53-a52f-da16d5763384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516920499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.516920499
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.736767032
Short name T581
Test name
Test status
Simulation time 49278936 ps
CPU time 0.73 seconds
Started Aug 02 06:44:18 PM PDT 24
Finished Aug 02 06:44:19 PM PDT 24
Peak memory 205844 kb
Host smart-6ac64f07-11a0-4323-aa2b-a673ffe2f953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736767032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.736767032
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.986785221
Short name T401
Test name
Test status
Simulation time 227335032 ps
CPU time 2.66 seconds
Started Aug 02 06:43:58 PM PDT 24
Finished Aug 02 06:44:01 PM PDT 24
Peak memory 233116 kb
Host smart-b09b1013-5e97-4783-8857-092a25ef13a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986785221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.986785221
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1388033812
Short name T384
Test name
Test status
Simulation time 29143330 ps
CPU time 0.8 seconds
Started Aug 02 06:44:00 PM PDT 24
Finished Aug 02 06:44:01 PM PDT 24
Peak memory 206988 kb
Host smart-bb4372fd-8554-44eb-b22b-eca3fd87d5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388033812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1388033812
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3367847606
Short name T213
Test name
Test status
Simulation time 149257493851 ps
CPU time 110.57 seconds
Started Aug 02 06:44:14 PM PDT 24
Finished Aug 02 06:46:05 PM PDT 24
Peak memory 257792 kb
Host smart-06e3552b-12db-4a2b-88ec-6ee04acc9ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367847606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3367847606
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2068434538
Short name T388
Test name
Test status
Simulation time 53581985314 ps
CPU time 179.31 seconds
Started Aug 02 06:44:09 PM PDT 24
Finished Aug 02 06:47:09 PM PDT 24
Peak memory 251608 kb
Host smart-9dc14296-9e92-4327-8a47-2191155aa299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068434538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2068434538
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4153044179
Short name T12
Test name
Test status
Simulation time 4205502345 ps
CPU time 53.51 seconds
Started Aug 02 06:44:15 PM PDT 24
Finished Aug 02 06:45:09 PM PDT 24
Peak memory 249684 kb
Host smart-d4923351-8f86-49e0-85e8-3220c0466ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153044179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4153044179
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.504922035
Short name T70
Test name
Test status
Simulation time 143886237 ps
CPU time 2.16 seconds
Started Aug 02 06:44:00 PM PDT 24
Finished Aug 02 06:44:03 PM PDT 24
Peak memory 223492 kb
Host smart-738b0610-55b1-43b7-89be-3ebab1ef1ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504922035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.504922035
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2742967702
Short name T366
Test name
Test status
Simulation time 30257843 ps
CPU time 2.38 seconds
Started Aug 02 06:44:03 PM PDT 24
Finished Aug 02 06:44:05 PM PDT 24
Peak memory 232884 kb
Host smart-eafc4633-3fc2-4d7d-8fd1-e44505b65cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742967702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2742967702
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.883675692
Short name T710
Test name
Test status
Simulation time 126438478 ps
CPU time 2.16 seconds
Started Aug 02 06:44:01 PM PDT 24
Finished Aug 02 06:44:03 PM PDT 24
Peak memory 224872 kb
Host smart-4a921939-84c7-4c4d-8032-24f5f0bb659c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883675692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
883675692
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1949481783
Short name T947
Test name
Test status
Simulation time 2026261753 ps
CPU time 8.31 seconds
Started Aug 02 06:44:00 PM PDT 24
Finished Aug 02 06:44:09 PM PDT 24
Peak memory 233080 kb
Host smart-eb57991f-8315-4307-96bc-39ac15d0ecfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949481783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1949481783
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3496385933
Short name T575
Test name
Test status
Simulation time 6162552800 ps
CPU time 9.8 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:22 PM PDT 24
Peak memory 223584 kb
Host smart-53520a7c-161d-44c7-98c8-0e47ee408f7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3496385933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3496385933
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3319525145
Short name T738
Test name
Test status
Simulation time 104891869863 ps
CPU time 329.13 seconds
Started Aug 02 06:44:12 PM PDT 24
Finished Aug 02 06:49:42 PM PDT 24
Peak memory 266012 kb
Host smart-f4936e1e-e5f0-4c7a-8ac0-411af7f5bf99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319525145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3319525145
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.959935182
Short name T842
Test name
Test status
Simulation time 77759045 ps
CPU time 0.72 seconds
Started Aug 02 06:43:59 PM PDT 24
Finished Aug 02 06:44:00 PM PDT 24
Peak memory 206128 kb
Host smart-ec9e9881-f305-40b1-8418-32ba745773f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959935182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.959935182
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1735982822
Short name T720
Test name
Test status
Simulation time 449676363 ps
CPU time 8.75 seconds
Started Aug 02 06:44:03 PM PDT 24
Finished Aug 02 06:44:12 PM PDT 24
Peak memory 216712 kb
Host smart-10c05e97-969d-4d93-81a0-1c3184b12e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735982822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1735982822
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.581308483
Short name T667
Test name
Test status
Simulation time 35515185 ps
CPU time 0.7 seconds
Started Aug 02 06:44:00 PM PDT 24
Finished Aug 02 06:44:01 PM PDT 24
Peak memory 206068 kb
Host smart-8235693e-7e60-4da0-81ed-01ae96eb8c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581308483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.581308483
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3659803439
Short name T492
Test name
Test status
Simulation time 126707933 ps
CPU time 2.28 seconds
Started Aug 02 06:44:00 PM PDT 24
Finished Aug 02 06:44:02 PM PDT 24
Peak memory 232852 kb
Host smart-834b6199-c873-4e1c-8869-650cb374fe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659803439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3659803439
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3028029230
Short name T994
Test name
Test status
Simulation time 37838433 ps
CPU time 0.7 seconds
Started Aug 02 06:44:12 PM PDT 24
Finished Aug 02 06:44:12 PM PDT 24
Peak memory 205260 kb
Host smart-10aec89e-c5c4-4959-8548-a175944126f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028029230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
028029230
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.569501746
Short name T870
Test name
Test status
Simulation time 75651180 ps
CPU time 2.36 seconds
Started Aug 02 06:44:10 PM PDT 24
Finished Aug 02 06:44:13 PM PDT 24
Peak memory 224884 kb
Host smart-5e7bb32b-6b05-4a49-8150-17e50e8ed1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569501746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.569501746
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2109045303
Short name T494
Test name
Test status
Simulation time 21144424 ps
CPU time 0.81 seconds
Started Aug 02 06:44:07 PM PDT 24
Finished Aug 02 06:44:08 PM PDT 24
Peak memory 207320 kb
Host smart-337312cb-dbcf-4554-bd41-b18e3404f49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109045303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2109045303
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3128106141
Short name T540
Test name
Test status
Simulation time 47729524 ps
CPU time 0.92 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:15 PM PDT 24
Peak memory 216440 kb
Host smart-9e52be98-ceac-4b8f-814a-ed41f25957a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128106141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3128106141
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1658634148
Short name T350
Test name
Test status
Simulation time 78321417 ps
CPU time 0.82 seconds
Started Aug 02 06:44:14 PM PDT 24
Finished Aug 02 06:44:15 PM PDT 24
Peak memory 217372 kb
Host smart-f1132fb1-26b0-4702-b2c3-3f1235bc812a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658634148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1658634148
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3884119870
Short name T932
Test name
Test status
Simulation time 216850028 ps
CPU time 4.4 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:18 PM PDT 24
Peak memory 233112 kb
Host smart-7231ee05-0fb2-4dcc-a372-f7e6d242cfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884119870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3884119870
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1377683987
Short name T697
Test name
Test status
Simulation time 3364807230 ps
CPU time 22.48 seconds
Started Aug 02 06:44:07 PM PDT 24
Finished Aug 02 06:44:30 PM PDT 24
Peak memory 225008 kb
Host smart-308d5bd2-fe67-4826-83c8-35d51f46af64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377683987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1377683987
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2094809186
Short name T574
Test name
Test status
Simulation time 926805115 ps
CPU time 2.65 seconds
Started Aug 02 06:44:10 PM PDT 24
Finished Aug 02 06:44:13 PM PDT 24
Peak memory 224948 kb
Host smart-4de0e1f9-2771-4b1b-b245-5117655cdba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094809186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2094809186
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2770082980
Short name T561
Test name
Test status
Simulation time 682452660 ps
CPU time 13.06 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:26 PM PDT 24
Peak memory 238904 kb
Host smart-62757206-4823-47d6-9361-7c22693b7849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770082980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2770082980
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2077538141
Short name T503
Test name
Test status
Simulation time 377274361 ps
CPU time 5.24 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:19 PM PDT 24
Peak memory 233180 kb
Host smart-c6de97de-4e46-41bc-b3ea-50cac0045c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077538141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2077538141
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2911550279
Short name T645
Test name
Test status
Simulation time 35506507 ps
CPU time 2.54 seconds
Started Aug 02 06:44:15 PM PDT 24
Finished Aug 02 06:44:18 PM PDT 24
Peak memory 232836 kb
Host smart-e7605529-e0cf-47f4-897f-11b298dcad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911550279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2911550279
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.472185995
Short name T582
Test name
Test status
Simulation time 232278446 ps
CPU time 5.12 seconds
Started Aug 02 06:44:11 PM PDT 24
Finished Aug 02 06:44:17 PM PDT 24
Peak memory 223452 kb
Host smart-7be55dd2-3186-4630-9834-38d52d5e1211
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=472185995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.472185995
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3447368008
Short name T83
Test name
Test status
Simulation time 131783484 ps
CPU time 1.05 seconds
Started Aug 02 06:44:12 PM PDT 24
Finished Aug 02 06:44:13 PM PDT 24
Peak memory 236296 kb
Host smart-2340d98e-17fd-4fb4-beb3-8fe8043cf460
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447368008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3447368008
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1253552705
Short name T900
Test name
Test status
Simulation time 2482493322 ps
CPU time 20.43 seconds
Started Aug 02 06:44:12 PM PDT 24
Finished Aug 02 06:44:32 PM PDT 24
Peak memory 217048 kb
Host smart-a08793d3-d04d-47f4-9b29-df10224da6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253552705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1253552705
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3103237217
Short name T360
Test name
Test status
Simulation time 2627231751 ps
CPU time 11.43 seconds
Started Aug 02 06:44:14 PM PDT 24
Finished Aug 02 06:44:26 PM PDT 24
Peak memory 216772 kb
Host smart-9beaaaaf-9c50-46f2-8cde-8d40b8dcac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103237217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3103237217
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1064473526
Short name T481
Test name
Test status
Simulation time 1466069548 ps
CPU time 2.71 seconds
Started Aug 02 06:44:12 PM PDT 24
Finished Aug 02 06:44:15 PM PDT 24
Peak memory 216680 kb
Host smart-8a748e91-2a0e-4532-b259-9f7d4d220694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064473526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1064473526
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.961245698
Short name T641
Test name
Test status
Simulation time 76163126 ps
CPU time 0.91 seconds
Started Aug 02 06:44:10 PM PDT 24
Finished Aug 02 06:44:11 PM PDT 24
Peak memory 206340 kb
Host smart-81179e80-31f2-4e2c-935d-18a30d147c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961245698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.961245698
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.64482282
Short name T815
Test name
Test status
Simulation time 4885641364 ps
CPU time 4.49 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:18 PM PDT 24
Peak memory 233232 kb
Host smart-13581807-4c8e-40cc-a0dd-a48795bc781f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64482282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.64482282
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4017552603
Short name T402
Test name
Test status
Simulation time 13775413 ps
CPU time 0.74 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:44:44 PM PDT 24
Peak memory 205172 kb
Host smart-e30fb8e3-6356-4cd5-9f07-f0fd3fd45bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017552603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4017552603
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3950203039
Short name T433
Test name
Test status
Simulation time 485594145 ps
CPU time 3.95 seconds
Started Aug 02 06:44:35 PM PDT 24
Finished Aug 02 06:44:39 PM PDT 24
Peak memory 233104 kb
Host smart-b2c884d1-1bc8-403d-ace7-ecb772658bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950203039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3950203039
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2611749271
Short name T759
Test name
Test status
Simulation time 27640180 ps
CPU time 0.74 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:44:41 PM PDT 24
Peak memory 205960 kb
Host smart-ebfe0873-66bc-452e-b1d2-3abead003711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611749271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2611749271
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1586435126
Short name T369
Test name
Test status
Simulation time 1208759265 ps
CPU time 12.77 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:54 PM PDT 24
Peak memory 233160 kb
Host smart-de1af26d-0b8a-44ec-b97c-05ecfcaaf33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586435126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1586435126
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2406784926
Short name T427
Test name
Test status
Simulation time 20150851541 ps
CPU time 62.47 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:45:43 PM PDT 24
Peak memory 249448 kb
Host smart-ebafeb5f-1e1c-4228-b3fc-4cfc41eefc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406784926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2406784926
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2187485121
Short name T578
Test name
Test status
Simulation time 601427140 ps
CPU time 8.85 seconds
Started Aug 02 06:44:38 PM PDT 24
Finished Aug 02 06:44:47 PM PDT 24
Peak memory 237680 kb
Host smart-ab5d8a80-8d14-407c-b091-8486fb018ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187485121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2187485121
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2369771757
Short name T867
Test name
Test status
Simulation time 7241828560 ps
CPU time 58.93 seconds
Started Aug 02 06:44:32 PM PDT 24
Finished Aug 02 06:45:31 PM PDT 24
Peak memory 254612 kb
Host smart-48be2965-b53d-4f10-91b8-97c2141d3a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369771757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2369771757
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1462541024
Short name T468
Test name
Test status
Simulation time 3016509832 ps
CPU time 11.72 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:44:52 PM PDT 24
Peak memory 233208 kb
Host smart-103c170c-b05b-4321-bd13-b01ea6361eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462541024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1462541024
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4238447314
Short name T281
Test name
Test status
Simulation time 14667152272 ps
CPU time 35.79 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:45:09 PM PDT 24
Peak memory 233212 kb
Host smart-a3f330a5-6e2c-4faf-86e1-7e4ea2c60410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238447314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4238447314
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1115358044
Short name T750
Test name
Test status
Simulation time 856023318 ps
CPU time 4.24 seconds
Started Aug 02 06:44:31 PM PDT 24
Finished Aug 02 06:44:36 PM PDT 24
Peak memory 224960 kb
Host smart-887f4e20-4bb6-4a45-a34c-7b4ae77cd89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115358044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1115358044
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3109002235
Short name T404
Test name
Test status
Simulation time 4533144725 ps
CPU time 5.61 seconds
Started Aug 02 06:44:34 PM PDT 24
Finished Aug 02 06:44:40 PM PDT 24
Peak memory 233224 kb
Host smart-87e2cffc-f45a-4fe1-8335-1944af0bad54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109002235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3109002235
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2310571598
Short name T920
Test name
Test status
Simulation time 383074905 ps
CPU time 6.11 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:47 PM PDT 24
Peak memory 220992 kb
Host smart-9c8aa52f-5247-4329-a4f0-7d129ab2b381
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2310571598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2310571598
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3202350536
Short name T806
Test name
Test status
Simulation time 16824599 ps
CPU time 0.73 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:44:34 PM PDT 24
Peak memory 206116 kb
Host smart-99872fb0-d17b-40e0-8eb9-1bec84f2564c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202350536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3202350536
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.260513530
Short name T775
Test name
Test status
Simulation time 1501541406 ps
CPU time 6.87 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:44:40 PM PDT 24
Peak memory 216736 kb
Host smart-dd209d58-3e00-44e7-928c-8d8ffa344cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260513530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.260513530
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.271739915
Short name T858
Test name
Test status
Simulation time 28137999 ps
CPU time 1.36 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:44:44 PM PDT 24
Peak memory 216600 kb
Host smart-05205568-7470-4a2d-8d8e-9fd6269bea99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271739915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.271739915
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2654900696
Short name T554
Test name
Test status
Simulation time 58468067 ps
CPU time 0.85 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:42 PM PDT 24
Peak memory 206360 kb
Host smart-2037de87-d3b6-419d-a0a6-e7de32e3838a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654900696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2654900696
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2120742436
Short name T257
Test name
Test status
Simulation time 3168950056 ps
CPU time 12.95 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:44:56 PM PDT 24
Peak memory 240196 kb
Host smart-d7fc928d-ac73-4e2d-909e-2cb4ea23f698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120742436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2120742436
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.726133142
Short name T472
Test name
Test status
Simulation time 19965928 ps
CPU time 0.75 seconds
Started Aug 02 06:44:37 PM PDT 24
Finished Aug 02 06:44:38 PM PDT 24
Peak memory 206168 kb
Host smart-9dc6fa0b-9426-448c-b5fc-c0fc5d6f0109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726133142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.726133142
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2766445291
Short name T262
Test name
Test status
Simulation time 890660140 ps
CPU time 3.89 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:44:37 PM PDT 24
Peak memory 224960 kb
Host smart-0870fa3d-1bb5-4805-b9d9-b59264a96439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766445291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2766445291
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2888664450
Short name T580
Test name
Test status
Simulation time 141281528 ps
CPU time 0.73 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:42 PM PDT 24
Peak memory 205956 kb
Host smart-0f5be72b-69b1-46b8-9773-090ce5747dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888664450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2888664450
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.587633129
Short name T933
Test name
Test status
Simulation time 35923375833 ps
CPU time 250.02 seconds
Started Aug 02 06:44:39 PM PDT 24
Finished Aug 02 06:48:49 PM PDT 24
Peak memory 254812 kb
Host smart-307265d4-d9a7-4a47-a553-f9b2da36c057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587633129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.587633129
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.725364043
Short name T416
Test name
Test status
Simulation time 16413185452 ps
CPU time 154.28 seconds
Started Aug 02 06:44:38 PM PDT 24
Finished Aug 02 06:47:12 PM PDT 24
Peak memory 264964 kb
Host smart-4fd71d80-240e-4ee8-baea-ac5a35628122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725364043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.725364043
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.97071979
Short name T937
Test name
Test status
Simulation time 71217316446 ps
CPU time 328.87 seconds
Started Aug 02 06:44:36 PM PDT 24
Finished Aug 02 06:50:05 PM PDT 24
Peak memory 257508 kb
Host smart-63c5e5e0-2eab-4eef-b046-e4c36e46b566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97071979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.97071979
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3237407588
Short name T798
Test name
Test status
Simulation time 938361797 ps
CPU time 9.09 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:44:49 PM PDT 24
Peak memory 249520 kb
Host smart-2866c6e6-fd94-443e-9a8a-b8d851fb84de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237407588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3237407588
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2896269689
Short name T622
Test name
Test status
Simulation time 11476269262 ps
CPU time 21.54 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:45:02 PM PDT 24
Peak memory 233056 kb
Host smart-1d7deef7-e202-4ed9-9e02-30bcc32880ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896269689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2896269689
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3563284813
Short name T59
Test name
Test status
Simulation time 364788526 ps
CPU time 9.19 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:44:49 PM PDT 24
Peak memory 233120 kb
Host smart-c592b359-0272-466c-88d4-25905fab5ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563284813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3563284813
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2460096584
Short name T54
Test name
Test status
Simulation time 8639496133 ps
CPU time 22.45 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:44:56 PM PDT 24
Peak memory 225040 kb
Host smart-ff0da450-688a-43b8-b177-1c8562189959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460096584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2460096584
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3438301284
Short name T176
Test name
Test status
Simulation time 2456508035 ps
CPU time 5.96 seconds
Started Aug 02 06:44:39 PM PDT 24
Finished Aug 02 06:44:45 PM PDT 24
Peak memory 225040 kb
Host smart-9e07b90f-88bb-4052-b16b-17c6733a7b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438301284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3438301284
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3668394292
Short name T93
Test name
Test status
Simulation time 3355674045 ps
CPU time 13.32 seconds
Started Aug 02 06:44:38 PM PDT 24
Finished Aug 02 06:44:52 PM PDT 24
Peak memory 220784 kb
Host smart-5694ff85-0ed4-468a-bcae-7c032b397cab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3668394292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3668394292
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4189084466
Short name T39
Test name
Test status
Simulation time 636117405480 ps
CPU time 736.42 seconds
Started Aug 02 06:44:36 PM PDT 24
Finished Aug 02 06:56:53 PM PDT 24
Peak memory 274224 kb
Host smart-a4752c07-433a-49da-81cf-86fde58f31b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189084466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4189084466
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3513121519
Short name T330
Test name
Test status
Simulation time 13802025 ps
CPU time 0.72 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:44:41 PM PDT 24
Peak memory 206084 kb
Host smart-46a49671-ec93-41cd-886c-fe350ecddfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513121519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3513121519
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1561217567
Short name T420
Test name
Test status
Simulation time 8439486043 ps
CPU time 8.99 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:50 PM PDT 24
Peak memory 216756 kb
Host smart-4364938d-f045-46f4-b094-99e2ee0885d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561217567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1561217567
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2771598940
Short name T609
Test name
Test status
Simulation time 480699396 ps
CPU time 0.92 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:44:34 PM PDT 24
Peak memory 207384 kb
Host smart-cf8f3e49-e294-47b5-8954-8d23a160df1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771598940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2771598940
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3274687152
Short name T869
Test name
Test status
Simulation time 23048667 ps
CPU time 0.7 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:42 PM PDT 24
Peak memory 206000 kb
Host smart-f070b734-7512-4afd-a136-9050631b562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274687152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3274687152
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3503306333
Short name T804
Test name
Test status
Simulation time 990934717 ps
CPU time 8.15 seconds
Started Aug 02 06:44:39 PM PDT 24
Finished Aug 02 06:44:48 PM PDT 24
Peak memory 233148 kb
Host smart-119c26c3-016d-4a3a-a768-eac126039571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503306333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3503306333
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2899962774
Short name T520
Test name
Test status
Simulation time 12019648 ps
CPU time 0.71 seconds
Started Aug 02 06:44:51 PM PDT 24
Finished Aug 02 06:44:52 PM PDT 24
Peak memory 205824 kb
Host smart-23f005a9-027b-464d-b00f-320f8cfd7182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899962774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2899962774
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2834443556
Short name T259
Test name
Test status
Simulation time 6788868332 ps
CPU time 14.54 seconds
Started Aug 02 06:44:44 PM PDT 24
Finished Aug 02 06:44:58 PM PDT 24
Peak memory 224948 kb
Host smart-c4524f34-bdf8-4bc4-b894-c3ac1fba45fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834443556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2834443556
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.538187238
Short name T752
Test name
Test status
Simulation time 20878392 ps
CPU time 0.77 seconds
Started Aug 02 06:44:34 PM PDT 24
Finished Aug 02 06:44:35 PM PDT 24
Peak memory 205972 kb
Host smart-7331a6c9-0c41-4872-bf68-7ee89170e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538187238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.538187238
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1105528289
Short name T249
Test name
Test status
Simulation time 3710983866 ps
CPU time 22.28 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:45:04 PM PDT 24
Peak memory 224940 kb
Host smart-5593951b-4ea7-435e-915d-4fd496b96fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105528289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1105528289
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3073023117
Short name T693
Test name
Test status
Simulation time 152362243438 ps
CPU time 268.27 seconds
Started Aug 02 06:44:46 PM PDT 24
Finished Aug 02 06:49:15 PM PDT 24
Peak memory 265740 kb
Host smart-2c9631b4-1237-498d-a049-a9b3fa6d5989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073023117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3073023117
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2003719743
Short name T889
Test name
Test status
Simulation time 82797958153 ps
CPU time 219.19 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:48:22 PM PDT 24
Peak memory 256744 kb
Host smart-5e6039b3-8d3c-4d3f-8b27-1aa9c9be637a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003719743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2003719743
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3719527680
Short name T349
Test name
Test status
Simulation time 1054570963 ps
CPU time 12.6 seconds
Started Aug 02 06:44:46 PM PDT 24
Finished Aug 02 06:44:58 PM PDT 24
Peak memory 233084 kb
Host smart-b97142ed-9e46-4fca-81ae-1799ad5a7302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719527680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3719527680
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.734566677
Short name T989
Test name
Test status
Simulation time 21636483224 ps
CPU time 185.97 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:47:47 PM PDT 24
Peak memory 255768 kb
Host smart-c788728f-916e-4bf6-b3ce-1d05a9f3f450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734566677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.734566677
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3992211057
Short name T648
Test name
Test status
Simulation time 259058360 ps
CPU time 3.35 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:44:47 PM PDT 24
Peak memory 233124 kb
Host smart-d73b8086-ee35-4d70-bebc-43edc9f10414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992211057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3992211057
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2064049715
Short name T820
Test name
Test status
Simulation time 8820612411 ps
CPU time 22.83 seconds
Started Aug 02 06:44:42 PM PDT 24
Finished Aug 02 06:45:05 PM PDT 24
Peak memory 233168 kb
Host smart-58ae284f-c972-43f2-81f5-16ae94ab039b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064049715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2064049715
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1725289506
Short name T676
Test name
Test status
Simulation time 4748802963 ps
CPU time 15.42 seconds
Started Aug 02 06:44:47 PM PDT 24
Finished Aug 02 06:45:02 PM PDT 24
Peak memory 233184 kb
Host smart-6e46ee55-0296-4f8f-b640-3b736cac01aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725289506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1725289506
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2407340931
Short name T998
Test name
Test status
Simulation time 1954193794 ps
CPU time 3.2 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:45 PM PDT 24
Peak memory 224884 kb
Host smart-4e39272a-841c-4e9b-921f-dc086b4ea061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407340931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2407340931
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2631235654
Short name T755
Test name
Test status
Simulation time 1254601138 ps
CPU time 17.07 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:58 PM PDT 24
Peak memory 222492 kb
Host smart-37f8de34-281a-4c1e-bcdf-1d83db7955e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2631235654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2631235654
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2471439773
Short name T999
Test name
Test status
Simulation time 102565080 ps
CPU time 1.15 seconds
Started Aug 02 06:44:45 PM PDT 24
Finished Aug 02 06:44:46 PM PDT 24
Peak memory 208140 kb
Host smart-34dbbc83-d815-4e0c-8536-93e9316fd242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471439773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2471439773
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3305892237
Short name T656
Test name
Test status
Simulation time 2257666760 ps
CPU time 12.3 seconds
Started Aug 02 06:44:38 PM PDT 24
Finished Aug 02 06:44:51 PM PDT 24
Peak memory 216732 kb
Host smart-db10b05f-df6a-42a6-9de5-b7653975d822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305892237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3305892237
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4042854047
Short name T381
Test name
Test status
Simulation time 1772350500 ps
CPU time 4.3 seconds
Started Aug 02 06:44:42 PM PDT 24
Finished Aug 02 06:44:46 PM PDT 24
Peak memory 216728 kb
Host smart-f07860fc-cc2d-4512-9305-ebd970df9b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042854047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4042854047
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.848217651
Short name T329
Test name
Test status
Simulation time 83589991 ps
CPU time 1.13 seconds
Started Aug 02 06:44:35 PM PDT 24
Finished Aug 02 06:44:36 PM PDT 24
Peak memory 208268 kb
Host smart-20aa8a84-64a9-4778-aef3-7d6c808f4ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848217651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.848217651
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2692656539
Short name T572
Test name
Test status
Simulation time 54873002 ps
CPU time 0.84 seconds
Started Aug 02 06:44:38 PM PDT 24
Finished Aug 02 06:44:39 PM PDT 24
Peak memory 206404 kb
Host smart-0ee7bbe4-8d03-4793-89f4-cac1dc2dce7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692656539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2692656539
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2962894433
Short name T261
Test name
Test status
Simulation time 5181910563 ps
CPU time 11.3 seconds
Started Aug 02 06:44:42 PM PDT 24
Finished Aug 02 06:44:53 PM PDT 24
Peak memory 248628 kb
Host smart-b9c0ac54-1aa3-4be5-814d-9c0d82a4db2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962894433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2962894433
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.160334329
Short name T518
Test name
Test status
Simulation time 45308364 ps
CPU time 0.72 seconds
Started Aug 02 06:44:42 PM PDT 24
Finished Aug 02 06:44:43 PM PDT 24
Peak memory 205928 kb
Host smart-0c22c363-1c77-430a-90d4-4ee93f52fd8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160334329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.160334329
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2147186435
Short name T473
Test name
Test status
Simulation time 1898572022 ps
CPU time 5.19 seconds
Started Aug 02 06:44:44 PM PDT 24
Finished Aug 02 06:44:49 PM PDT 24
Peak memory 224852 kb
Host smart-48e5d67f-3f69-4f02-a71f-e658b5cfe22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147186435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2147186435
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2014798468
Short name T555
Test name
Test status
Simulation time 16008333 ps
CPU time 0.74 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:42 PM PDT 24
Peak memory 206956 kb
Host smart-4b6bb48e-7b47-4ec2-b4da-5efefefb2811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014798468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2014798468
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1773947584
Short name T881
Test name
Test status
Simulation time 36731221886 ps
CPU time 56.37 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:45:38 PM PDT 24
Peak memory 257812 kb
Host smart-5e88c229-beb5-41b1-bfae-f8523ee53f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773947584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1773947584
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1346428587
Short name T375
Test name
Test status
Simulation time 1409946576 ps
CPU time 6.37 seconds
Started Aug 02 06:44:44 PM PDT 24
Finished Aug 02 06:44:50 PM PDT 24
Peak memory 218172 kb
Host smart-48249abc-b9c8-48f5-9135-34df57dcd585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346428587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1346428587
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4114052333
Short name T234
Test name
Test status
Simulation time 66280043319 ps
CPU time 632.96 seconds
Started Aug 02 06:44:39 PM PDT 24
Finished Aug 02 06:55:13 PM PDT 24
Peak memory 266444 kb
Host smart-264f4d90-ee12-43ec-bbfa-f4fb91130b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114052333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4114052333
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.993133113
Short name T505
Test name
Test status
Simulation time 61799588 ps
CPU time 4.36 seconds
Started Aug 02 06:44:45 PM PDT 24
Finished Aug 02 06:44:49 PM PDT 24
Peak memory 224968 kb
Host smart-0e5ecea8-7faa-4931-85e1-ca079c34559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993133113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.993133113
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1480889361
Short name T936
Test name
Test status
Simulation time 5131476782 ps
CPU time 14.45 seconds
Started Aug 02 06:44:42 PM PDT 24
Finished Aug 02 06:44:56 PM PDT 24
Peak memory 249576 kb
Host smart-a8897637-59f8-4de3-bfc9-8f2171f6d10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480889361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1480889361
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2923037633
Short name T86
Test name
Test status
Simulation time 4108112675 ps
CPU time 11.56 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:53 PM PDT 24
Peak memory 233168 kb
Host smart-cb8550f6-f25c-4b98-aa7f-93f20a9160db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923037633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2923037633
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2175163540
Short name T264
Test name
Test status
Simulation time 7162838728 ps
CPU time 26.8 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:45:10 PM PDT 24
Peak memory 233240 kb
Host smart-c578e184-5a07-46bf-b340-0c08f42db1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175163540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2175163540
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1401590452
Short name T614
Test name
Test status
Simulation time 954624219 ps
CPU time 4.8 seconds
Started Aug 02 06:44:48 PM PDT 24
Finished Aug 02 06:44:53 PM PDT 24
Peak memory 233156 kb
Host smart-f9885c64-4e78-4cf1-bfc5-bca155b7c536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401590452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1401590452
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2517566533
Short name T383
Test name
Test status
Simulation time 2806397352 ps
CPU time 10.21 seconds
Started Aug 02 06:44:46 PM PDT 24
Finished Aug 02 06:44:56 PM PDT 24
Peak memory 224924 kb
Host smart-42eba32e-f364-4a09-bdcc-467b6fee8b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517566533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2517566533
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3152349144
Short name T516
Test name
Test status
Simulation time 2004386264 ps
CPU time 20.15 seconds
Started Aug 02 06:44:44 PM PDT 24
Finished Aug 02 06:45:05 PM PDT 24
Peak memory 221880 kb
Host smart-e1bec13f-c85b-4c1a-972f-032a1ece17f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3152349144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3152349144
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3021383745
Short name T303
Test name
Test status
Simulation time 85319769365 ps
CPU time 773.99 seconds
Started Aug 02 06:44:46 PM PDT 24
Finished Aug 02 06:57:40 PM PDT 24
Peak memory 298392 kb
Host smart-c457a3ab-d763-473e-8555-8b04ac3ebe24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021383745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3021383745
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1301171029
Short name T32
Test name
Test status
Simulation time 878401020 ps
CPU time 5.44 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:44:49 PM PDT 24
Peak memory 219108 kb
Host smart-3eb4c49f-8fd7-407b-9b2f-2e8570462aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301171029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1301171029
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.965017136
Short name T373
Test name
Test status
Simulation time 2791108377 ps
CPU time 12.49 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:44:56 PM PDT 24
Peak memory 216748 kb
Host smart-10026540-82c3-4897-af50-99937a0547f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965017136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.965017136
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2790483779
Short name T813
Test name
Test status
Simulation time 334009908 ps
CPU time 4.13 seconds
Started Aug 02 06:44:42 PM PDT 24
Finished Aug 02 06:44:46 PM PDT 24
Peak memory 216696 kb
Host smart-b55b1438-a4fa-4041-b680-bb1a23c7b81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790483779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2790483779
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3449131491
Short name T104
Test name
Test status
Simulation time 199247807 ps
CPU time 0.87 seconds
Started Aug 02 06:44:46 PM PDT 24
Finished Aug 02 06:44:47 PM PDT 24
Peak memory 206380 kb
Host smart-13dbfe51-a8a7-4577-902d-0b86640d7e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449131491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3449131491
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.697461115
Short name T72
Test name
Test status
Simulation time 5926109326 ps
CPU time 17.39 seconds
Started Aug 02 06:44:45 PM PDT 24
Finished Aug 02 06:45:03 PM PDT 24
Peak memory 230288 kb
Host smart-2a003770-62d7-4e92-a6e3-5734d5397ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697461115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.697461115
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.273211834
Short name T840
Test name
Test status
Simulation time 38434277 ps
CPU time 0.73 seconds
Started Aug 02 06:44:48 PM PDT 24
Finished Aug 02 06:44:49 PM PDT 24
Peak memory 205788 kb
Host smart-7db47ce6-0529-4746-aee1-b010bcf994f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273211834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.273211834
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1665720387
Short name T981
Test name
Test status
Simulation time 105640428 ps
CPU time 3.77 seconds
Started Aug 02 06:44:46 PM PDT 24
Finished Aug 02 06:44:50 PM PDT 24
Peak memory 233144 kb
Host smart-bbcfd6cf-c21d-4a47-9f62-c53c33500d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665720387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1665720387
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.278711608
Short name T911
Test name
Test status
Simulation time 16444021 ps
CPU time 0.77 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:42 PM PDT 24
Peak memory 206260 kb
Host smart-3f50e2dc-10b3-4b76-94ec-751a74ade04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278711608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.278711608
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1683679869
Short name T91
Test name
Test status
Simulation time 17984922904 ps
CPU time 43.7 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:45:27 PM PDT 24
Peak memory 224992 kb
Host smart-bd92cd8c-3994-4824-b115-9a602203474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683679869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1683679869
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1603959414
Short name T620
Test name
Test status
Simulation time 12211612647 ps
CPU time 31.46 seconds
Started Aug 02 06:44:48 PM PDT 24
Finished Aug 02 06:45:20 PM PDT 24
Peak memory 225072 kb
Host smart-50cfd6be-e920-4cf3-8c76-22edac083b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603959414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1603959414
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1419884602
Short name T1004
Test name
Test status
Simulation time 7156485221 ps
CPU time 19.53 seconds
Started Aug 02 06:44:46 PM PDT 24
Finished Aug 02 06:45:05 PM PDT 24
Peak memory 218180 kb
Host smart-574d6e24-c41f-485f-aa2a-3d01bd893ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419884602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1419884602
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.377394147
Short name T837
Test name
Test status
Simulation time 1597962425 ps
CPU time 6.25 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:44:49 PM PDT 24
Peak memory 224876 kb
Host smart-09bd1067-8790-474d-affc-10ca347880e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377394147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.377394147
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3407468091
Short name T495
Test name
Test status
Simulation time 4077327313 ps
CPU time 33.74 seconds
Started Aug 02 06:44:46 PM PDT 24
Finished Aug 02 06:45:20 PM PDT 24
Peak memory 249580 kb
Host smart-219927f9-92b5-436f-bbf6-554e33b50926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407468091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3407468091
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1392330311
Short name T29
Test name
Test status
Simulation time 254456169 ps
CPU time 2.8 seconds
Started Aug 02 06:44:45 PM PDT 24
Finished Aug 02 06:44:48 PM PDT 24
Peak memory 233144 kb
Host smart-10fa5d8b-eeb6-4fb1-8a6f-0fbd94111cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392330311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1392330311
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1573687178
Short name T280
Test name
Test status
Simulation time 26926582987 ps
CPU time 68.49 seconds
Started Aug 02 06:44:49 PM PDT 24
Finished Aug 02 06:45:58 PM PDT 24
Peak memory 241368 kb
Host smart-ff7067ff-0443-43c4-995b-42e87d83f66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573687178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1573687178
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4020117189
Short name T307
Test name
Test status
Simulation time 978599209 ps
CPU time 8.56 seconds
Started Aug 02 06:44:46 PM PDT 24
Finished Aug 02 06:44:55 PM PDT 24
Peak memory 224940 kb
Host smart-62c5c251-b080-4e17-9461-a281a446dc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020117189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4020117189
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1098598184
Short name T556
Test name
Test status
Simulation time 2472609764 ps
CPU time 4.37 seconds
Started Aug 02 06:44:46 PM PDT 24
Finished Aug 02 06:44:51 PM PDT 24
Peak memory 233192 kb
Host smart-09989756-c49d-41dd-94a5-63ed1e8290c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098598184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1098598184
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.463033497
Short name T157
Test name
Test status
Simulation time 1221227819 ps
CPU time 5.65 seconds
Started Aug 02 06:44:49 PM PDT 24
Finished Aug 02 06:44:54 PM PDT 24
Peak memory 222536 kb
Host smart-668f38ad-8cbf-4243-8da0-1409cfa7aa8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=463033497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.463033497
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1266224755
Short name T421
Test name
Test status
Simulation time 5608955212 ps
CPU time 38.37 seconds
Started Aug 02 06:44:47 PM PDT 24
Finished Aug 02 06:45:25 PM PDT 24
Peak memory 216868 kb
Host smart-24a6e141-464d-4133-8da6-1e9a77a4103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266224755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1266224755
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1349398901
Short name T497
Test name
Test status
Simulation time 3266497171 ps
CPU time 4.57 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:44:48 PM PDT 24
Peak memory 216716 kb
Host smart-fa66bb5f-118e-4e8c-9fbf-223cec7f562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349398901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1349398901
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3367171680
Short name T386
Test name
Test status
Simulation time 525379102 ps
CPU time 2.59 seconds
Started Aug 02 06:44:45 PM PDT 24
Finished Aug 02 06:44:48 PM PDT 24
Peak memory 216724 kb
Host smart-77d1ced7-0280-49be-827d-a2c87735d262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367171680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3367171680
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.111280187
Short name T964
Test name
Test status
Simulation time 186025264 ps
CPU time 0.85 seconds
Started Aug 02 06:44:42 PM PDT 24
Finished Aug 02 06:44:43 PM PDT 24
Peak memory 206336 kb
Host smart-aa8dd3e3-7a8f-41fb-9f5a-ceae84447ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111280187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.111280187
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4186017296
Short name T412
Test name
Test status
Simulation time 33218156551 ps
CPU time 18.07 seconds
Started Aug 02 06:44:42 PM PDT 24
Finished Aug 02 06:45:00 PM PDT 24
Peak memory 241284 kb
Host smart-d12d9bd0-e6ef-4638-bb4f-2a1cbba9cf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186017296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4186017296
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2211142600
Short name T528
Test name
Test status
Simulation time 41485053 ps
CPU time 0.69 seconds
Started Aug 02 06:44:50 PM PDT 24
Finished Aug 02 06:44:51 PM PDT 24
Peak memory 206176 kb
Host smart-7ec2e085-c50a-4fdd-bc3a-b430d0dbd884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211142600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2211142600
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3174912760
Short name T537
Test name
Test status
Simulation time 501614925 ps
CPU time 2.48 seconds
Started Aug 02 06:44:51 PM PDT 24
Finished Aug 02 06:44:53 PM PDT 24
Peak memory 224932 kb
Host smart-464dd18b-7ace-48cf-90f4-7bc72f8c126b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174912760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3174912760
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1031827498
Short name T24
Test name
Test status
Simulation time 57478289 ps
CPU time 0.76 seconds
Started Aug 02 06:44:49 PM PDT 24
Finished Aug 02 06:44:50 PM PDT 24
Peak memory 206288 kb
Host smart-3ecd25af-115d-4cbc-9388-1cfc2ce8c2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031827498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1031827498
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.205447751
Short name T311
Test name
Test status
Simulation time 19965726608 ps
CPU time 202.26 seconds
Started Aug 02 06:44:52 PM PDT 24
Finished Aug 02 06:48:14 PM PDT 24
Peak memory 253748 kb
Host smart-265794de-7a37-401b-83d4-c04536edd16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205447751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.205447751
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1643520941
Short name T805
Test name
Test status
Simulation time 4794282527 ps
CPU time 13.57 seconds
Started Aug 02 06:44:48 PM PDT 24
Finished Aug 02 06:45:02 PM PDT 24
Peak memory 218136 kb
Host smart-6d4f308b-d812-49b0-a2c6-d15d9c86cabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643520941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1643520941
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2859470690
Short name T856
Test name
Test status
Simulation time 2885648717 ps
CPU time 53.26 seconds
Started Aug 02 06:44:55 PM PDT 24
Finished Aug 02 06:45:48 PM PDT 24
Peak memory 257832 kb
Host smart-b54ac84a-8a28-4249-b7a3-4f2d7c55a388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859470690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2859470690
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1264189869
Short name T972
Test name
Test status
Simulation time 3252277982 ps
CPU time 8.04 seconds
Started Aug 02 06:44:51 PM PDT 24
Finished Aug 02 06:44:59 PM PDT 24
Peak memory 233448 kb
Host smart-433f7cb8-4534-4d94-9c1e-a802bd50bff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264189869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1264189869
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.4050270753
Short name T467
Test name
Test status
Simulation time 8741757709 ps
CPU time 20.25 seconds
Started Aug 02 06:44:51 PM PDT 24
Finished Aug 02 06:45:11 PM PDT 24
Peak memory 233160 kb
Host smart-c0e74c4f-6c1f-4b97-aea0-e58cc58b6f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050270753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.4050270753
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.721081417
Short name T217
Test name
Test status
Simulation time 351240461 ps
CPU time 3.28 seconds
Started Aug 02 06:44:49 PM PDT 24
Finished Aug 02 06:44:53 PM PDT 24
Peak memory 224884 kb
Host smart-578c4d79-b6db-4c10-8c39-c11bdba2de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721081417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.721081417
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.447740929
Short name T943
Test name
Test status
Simulation time 5142628176 ps
CPU time 63.48 seconds
Started Aug 02 06:44:50 PM PDT 24
Finished Aug 02 06:45:53 PM PDT 24
Peak memory 233168 kb
Host smart-57f76bd4-5d70-468f-a10b-88db2f872005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447740929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.447740929
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3558192704
Short name T890
Test name
Test status
Simulation time 20753657050 ps
CPU time 19.05 seconds
Started Aug 02 06:44:44 PM PDT 24
Finished Aug 02 06:45:03 PM PDT 24
Peak memory 233256 kb
Host smart-49154574-e4cc-419b-8f91-2e7a709a0682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558192704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3558192704
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.401474424
Short name T250
Test name
Test status
Simulation time 3035606055 ps
CPU time 4.67 seconds
Started Aug 02 06:44:44 PM PDT 24
Finished Aug 02 06:44:48 PM PDT 24
Peak memory 233264 kb
Host smart-d0ffa477-3015-486b-822d-a8735e82e186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401474424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.401474424
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.181279237
Short name T769
Test name
Test status
Simulation time 365967281 ps
CPU time 5.28 seconds
Started Aug 02 06:44:50 PM PDT 24
Finished Aug 02 06:44:56 PM PDT 24
Peak memory 223120 kb
Host smart-64cc61c2-67ea-4c52-882a-e433a6b54fd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=181279237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.181279237
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1965316260
Short name T203
Test name
Test status
Simulation time 25905245087 ps
CPU time 242.3 seconds
Started Aug 02 06:44:50 PM PDT 24
Finished Aug 02 06:48:52 PM PDT 24
Peak memory 268704 kb
Host smart-7add2dd5-df18-46d8-b97f-89e32c110733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965316260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1965316260
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1365103403
Short name T429
Test name
Test status
Simulation time 4673719273 ps
CPU time 20.23 seconds
Started Aug 02 06:44:48 PM PDT 24
Finished Aug 02 06:45:08 PM PDT 24
Peak memory 216776 kb
Host smart-f6e629ac-e611-4025-a293-417638fab6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365103403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1365103403
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.14988513
Short name T573
Test name
Test status
Simulation time 1706443016 ps
CPU time 5.71 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:44:49 PM PDT 24
Peak memory 216668 kb
Host smart-aacff318-3d45-4755-8db1-f46d1ebaaf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14988513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.14988513
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3184586130
Short name T442
Test name
Test status
Simulation time 50039310 ps
CPU time 0.77 seconds
Started Aug 02 06:44:49 PM PDT 24
Finished Aug 02 06:44:50 PM PDT 24
Peak memory 207380 kb
Host smart-a99baef5-db12-40eb-a82a-d7bb680f0040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184586130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3184586130
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3566280616
Short name T544
Test name
Test status
Simulation time 66243583 ps
CPU time 0.78 seconds
Started Aug 02 06:44:50 PM PDT 24
Finished Aug 02 06:44:51 PM PDT 24
Peak memory 206352 kb
Host smart-cab5bafa-158d-4f0c-8b75-130e1613edb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566280616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3566280616
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2341456247
Short name T246
Test name
Test status
Simulation time 597941173 ps
CPU time 3.34 seconds
Started Aug 02 06:44:52 PM PDT 24
Finished Aug 02 06:44:55 PM PDT 24
Peak memory 224844 kb
Host smart-561e3fb3-1787-4048-8a81-3adbd6611b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341456247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2341456247
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3622585541
Short name T787
Test name
Test status
Simulation time 294069377 ps
CPU time 2.95 seconds
Started Aug 02 06:44:49 PM PDT 24
Finished Aug 02 06:44:52 PM PDT 24
Peak memory 224784 kb
Host smart-4eb931ce-6e68-428b-a278-2b23a6e4a7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622585541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3622585541
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.68417870
Short name T771
Test name
Test status
Simulation time 143038687 ps
CPU time 0.81 seconds
Started Aug 02 06:44:52 PM PDT 24
Finished Aug 02 06:44:52 PM PDT 24
Peak memory 207312 kb
Host smart-60084bc1-bf05-484a-908c-d2ad0cf52e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68417870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.68417870
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1369466550
Short name T268
Test name
Test status
Simulation time 2742964351 ps
CPU time 54.95 seconds
Started Aug 02 06:45:01 PM PDT 24
Finished Aug 02 06:45:56 PM PDT 24
Peak memory 252140 kb
Host smart-fc348e37-68da-4ac7-baee-68c8b2f999f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369466550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1369466550
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3955362679
Short name T962
Test name
Test status
Simulation time 8005555286 ps
CPU time 113.79 seconds
Started Aug 02 06:45:00 PM PDT 24
Finished Aug 02 06:46:54 PM PDT 24
Peak memory 246076 kb
Host smart-3132d217-8e3f-44af-82a4-e44980d96463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955362679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3955362679
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4192678838
Short name T390
Test name
Test status
Simulation time 207164280 ps
CPU time 6.33 seconds
Started Aug 02 06:44:55 PM PDT 24
Finished Aug 02 06:45:01 PM PDT 24
Peak memory 240016 kb
Host smart-9a81486d-f9be-47ef-a8a2-15071711feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192678838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4192678838
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.795381544
Short name T463
Test name
Test status
Simulation time 2421937864 ps
CPU time 11.92 seconds
Started Aug 02 06:44:52 PM PDT 24
Finished Aug 02 06:45:04 PM PDT 24
Peak memory 225036 kb
Host smart-4ca19d04-6003-4392-a317-f8dc64a56f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795381544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.795381544
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3490043518
Short name T1008
Test name
Test status
Simulation time 844101862 ps
CPU time 9.44 seconds
Started Aug 02 06:44:55 PM PDT 24
Finished Aug 02 06:45:05 PM PDT 24
Peak memory 249204 kb
Host smart-71acbc53-d9a9-4b50-82ac-6eb896217201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490043518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3490043518
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.521547425
Short name T47
Test name
Test status
Simulation time 2624384183 ps
CPU time 6.84 seconds
Started Aug 02 06:44:51 PM PDT 24
Finished Aug 02 06:44:58 PM PDT 24
Peak memory 233196 kb
Host smart-e2753abb-4658-40a3-a442-b87154aa6980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521547425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.521547425
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3851953457
Short name T419
Test name
Test status
Simulation time 4250838043 ps
CPU time 7.17 seconds
Started Aug 02 06:44:49 PM PDT 24
Finished Aug 02 06:44:57 PM PDT 24
Peak memory 233108 kb
Host smart-213c91c3-2050-4369-b3e2-eb037ff6feb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851953457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3851953457
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1332128328
Short name T466
Test name
Test status
Simulation time 1860100975 ps
CPU time 19.94 seconds
Started Aug 02 06:44:49 PM PDT 24
Finished Aug 02 06:45:10 PM PDT 24
Peak memory 221000 kb
Host smart-41f56bef-9e90-4e44-ad63-6d9cba7247cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1332128328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1332128328
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1582906424
Short name T450
Test name
Test status
Simulation time 5000226598 ps
CPU time 16.15 seconds
Started Aug 02 06:44:52 PM PDT 24
Finished Aug 02 06:45:08 PM PDT 24
Peak memory 216708 kb
Host smart-cfe00112-d2a6-4f7b-8ec0-2a7a5ac3dcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582906424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1582906424
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.845085100
Short name T844
Test name
Test status
Simulation time 3759510077 ps
CPU time 6.26 seconds
Started Aug 02 06:44:49 PM PDT 24
Finished Aug 02 06:44:56 PM PDT 24
Peak memory 216752 kb
Host smart-ca98d627-dc0a-4b4f-a80f-97ed41821588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845085100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.845085100
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4047842494
Short name T546
Test name
Test status
Simulation time 27461507 ps
CPU time 0.92 seconds
Started Aug 02 06:44:50 PM PDT 24
Finished Aug 02 06:44:51 PM PDT 24
Peak memory 207948 kb
Host smart-c024d99a-82e8-44d0-bfd5-ce2de0486b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047842494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4047842494
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2884775481
Short name T809
Test name
Test status
Simulation time 698364213 ps
CPU time 0.94 seconds
Started Aug 02 06:44:51 PM PDT 24
Finished Aug 02 06:44:52 PM PDT 24
Peak memory 206388 kb
Host smart-6f0bbdfb-a1e5-49df-9ce2-06af73522aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884775481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2884775481
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2745273834
Short name T244
Test name
Test status
Simulation time 757646420 ps
CPU time 4.01 seconds
Started Aug 02 06:44:55 PM PDT 24
Finished Aug 02 06:44:59 PM PDT 24
Peak memory 225016 kb
Host smart-d6d88459-fd58-4049-a094-84f921731baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745273834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2745273834
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3839204837
Short name T562
Test name
Test status
Simulation time 140768674 ps
CPU time 0.74 seconds
Started Aug 02 06:44:59 PM PDT 24
Finished Aug 02 06:45:00 PM PDT 24
Peak memory 205884 kb
Host smart-49e00016-898a-4905-a0ba-eec9487b4f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839204837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3839204837
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1820457485
Short name T732
Test name
Test status
Simulation time 139617186 ps
CPU time 2.37 seconds
Started Aug 02 06:44:58 PM PDT 24
Finished Aug 02 06:45:01 PM PDT 24
Peak memory 233100 kb
Host smart-2ebca091-95e6-4c7d-96fa-7a40d8296f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820457485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1820457485
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3775002385
Short name T835
Test name
Test status
Simulation time 14726579 ps
CPU time 0.82 seconds
Started Aug 02 06:44:59 PM PDT 24
Finished Aug 02 06:45:00 PM PDT 24
Peak memory 206956 kb
Host smart-974afa2c-d0e1-49bb-a5a7-3637c0da0f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775002385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3775002385
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.4256695658
Short name T228
Test name
Test status
Simulation time 19505627636 ps
CPU time 129.75 seconds
Started Aug 02 06:45:02 PM PDT 24
Finished Aug 02 06:47:12 PM PDT 24
Peak memory 249656 kb
Host smart-44e1bbb3-d565-495a-a414-5ffe1513eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256695658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.4256695658
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.347248304
Short name T272
Test name
Test status
Simulation time 44229908550 ps
CPU time 85.36 seconds
Started Aug 02 06:44:59 PM PDT 24
Finished Aug 02 06:46:24 PM PDT 24
Peak memory 257900 kb
Host smart-3aadccc1-eb07-464d-a435-12509cb66b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347248304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.347248304
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3217243974
Short name T30
Test name
Test status
Simulation time 6401622732 ps
CPU time 43.83 seconds
Started Aug 02 06:44:59 PM PDT 24
Finished Aug 02 06:45:43 PM PDT 24
Peak memory 239044 kb
Host smart-cccfaf5d-ca47-4f27-9dec-61f78a71fe1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217243974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3217243974
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1671507090
Short name T476
Test name
Test status
Simulation time 2917000332 ps
CPU time 51.93 seconds
Started Aug 02 06:45:00 PM PDT 24
Finished Aug 02 06:45:52 PM PDT 24
Peak memory 233200 kb
Host smart-02f1920f-f4b7-4ea2-ac36-554762688e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671507090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1671507090
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3849879630
Short name T454
Test name
Test status
Simulation time 52127649 ps
CPU time 0.95 seconds
Started Aug 02 06:45:00 PM PDT 24
Finished Aug 02 06:45:01 PM PDT 24
Peak memory 216416 kb
Host smart-4737c71e-d56d-4a49-ad4e-62480f765f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849879630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3849879630
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3695517055
Short name T944
Test name
Test status
Simulation time 33653343 ps
CPU time 2.4 seconds
Started Aug 02 06:45:04 PM PDT 24
Finished Aug 02 06:45:07 PM PDT 24
Peak memory 227224 kb
Host smart-460678f8-3d18-496d-9d39-18fc84c0e0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695517055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3695517055
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3427272157
Short name T357
Test name
Test status
Simulation time 206228528 ps
CPU time 5.59 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:45:14 PM PDT 24
Peak memory 224956 kb
Host smart-7d5f032a-6797-4b50-9738-73d04c889ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427272157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3427272157
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1449877396
Short name T977
Test name
Test status
Simulation time 614771802 ps
CPU time 3.33 seconds
Started Aug 02 06:45:00 PM PDT 24
Finished Aug 02 06:45:04 PM PDT 24
Peak memory 224900 kb
Host smart-363a88d9-0bc7-4583-b6fb-aaca0b8c75d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449877396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1449877396
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.48837713
Short name T995
Test name
Test status
Simulation time 5913194702 ps
CPU time 15.31 seconds
Started Aug 02 06:45:02 PM PDT 24
Finished Aug 02 06:45:18 PM PDT 24
Peak memory 224956 kb
Host smart-90400af3-f176-44a7-b33b-8bae2cc59d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48837713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.48837713
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.33585904
Short name T729
Test name
Test status
Simulation time 187649452 ps
CPU time 3.2 seconds
Started Aug 02 06:45:09 PM PDT 24
Finished Aug 02 06:45:12 PM PDT 24
Peak memory 221120 kb
Host smart-394a7625-6a97-4b3b-9e76-3eaa49bfa27f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=33585904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direc
t.33585904
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2681788466
Short name T22
Test name
Test status
Simulation time 465932828 ps
CPU time 1.19 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:45:10 PM PDT 24
Peak memory 216444 kb
Host smart-69959a38-bd4e-4045-a1c0-c7bd1c833df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681788466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2681788466
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3659254365
Short name T426
Test name
Test status
Simulation time 8966066280 ps
CPU time 48.14 seconds
Started Aug 02 06:45:09 PM PDT 24
Finished Aug 02 06:45:58 PM PDT 24
Peak memory 221340 kb
Host smart-7103fca3-9588-465a-9c57-4e87f4e46c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659254365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3659254365
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3282636147
Short name T410
Test name
Test status
Simulation time 15616676892 ps
CPU time 14.32 seconds
Started Aug 02 06:44:58 PM PDT 24
Finished Aug 02 06:45:12 PM PDT 24
Peak memory 216744 kb
Host smart-34dec247-b354-4f67-a769-d73dfbb147c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282636147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3282636147
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.430389864
Short name T335
Test name
Test status
Simulation time 115396618 ps
CPU time 1.96 seconds
Started Aug 02 06:45:00 PM PDT 24
Finished Aug 02 06:45:03 PM PDT 24
Peak memory 216756 kb
Host smart-ed0851fe-95e1-41cc-8ca5-550c6abfd664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430389864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.430389864
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3257679315
Short name T603
Test name
Test status
Simulation time 136276607 ps
CPU time 0.88 seconds
Started Aug 02 06:45:00 PM PDT 24
Finished Aug 02 06:45:01 PM PDT 24
Peak memory 207420 kb
Host smart-0b79c6fa-5698-461b-ac2a-51111667d6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257679315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3257679315
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2353007082
Short name T482
Test name
Test status
Simulation time 4036040341 ps
CPU time 13.68 seconds
Started Aug 02 06:44:58 PM PDT 24
Finished Aug 02 06:45:12 PM PDT 24
Peak memory 233192 kb
Host smart-5f8fd751-841a-4967-94bc-9cca835e9c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353007082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2353007082
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3170435793
Short name T352
Test name
Test status
Simulation time 15106142 ps
CPU time 0.73 seconds
Started Aug 02 06:45:14 PM PDT 24
Finished Aug 02 06:45:15 PM PDT 24
Peak memory 204812 kb
Host smart-a27371c0-3c23-4558-a378-1d09d637581d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170435793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3170435793
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2737102025
Short name T939
Test name
Test status
Simulation time 1220373363 ps
CPU time 9.42 seconds
Started Aug 02 06:45:06 PM PDT 24
Finished Aug 02 06:45:16 PM PDT 24
Peak memory 224972 kb
Host smart-e7c8abfb-f0b2-44cf-a269-d768f5897e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737102025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2737102025
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2715982486
Short name T658
Test name
Test status
Simulation time 77619659 ps
CPU time 0.74 seconds
Started Aug 02 06:45:01 PM PDT 24
Finished Aug 02 06:45:02 PM PDT 24
Peak memory 205852 kb
Host smart-83182fed-1f95-4199-a28f-b5386513c14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715982486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2715982486
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1248436337
Short name T197
Test name
Test status
Simulation time 80912814102 ps
CPU time 300.04 seconds
Started Aug 02 06:45:10 PM PDT 24
Finished Aug 02 06:50:10 PM PDT 24
Peak memory 257380 kb
Host smart-b16368f6-9214-4a53-98ab-6274b1942797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248436337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1248436337
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3144308866
Short name T682
Test name
Test status
Simulation time 99413877959 ps
CPU time 288.62 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:49:57 PM PDT 24
Peak memory 257788 kb
Host smart-f7cb500b-5eb7-4524-8066-9768b7e2d1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144308866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3144308866
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2882503419
Short name T431
Test name
Test status
Simulation time 8090959753 ps
CPU time 59.19 seconds
Started Aug 02 06:45:09 PM PDT 24
Finished Aug 02 06:46:08 PM PDT 24
Peak memory 241388 kb
Host smart-9d0351ae-1b11-4c91-ba27-1bbf4c106048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882503419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2882503419
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3715997305
Short name T66
Test name
Test status
Simulation time 1153054383 ps
CPU time 13.09 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:45:21 PM PDT 24
Peak memory 224952 kb
Host smart-a9e9643c-d8ad-4dfd-a3e1-a8512d1c44cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715997305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3715997305
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1172917200
Short name T638
Test name
Test status
Simulation time 2205246336 ps
CPU time 17.33 seconds
Started Aug 02 06:45:11 PM PDT 24
Finished Aug 02 06:45:28 PM PDT 24
Peak memory 225004 kb
Host smart-be6cfb9a-e8ae-42be-8a2a-3e26c8f04431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172917200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1172917200
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2179061415
Short name T212
Test name
Test status
Simulation time 1176664161 ps
CPU time 10.02 seconds
Started Aug 02 06:45:09 PM PDT 24
Finished Aug 02 06:45:19 PM PDT 24
Peak memory 233224 kb
Host smart-d1656e86-8175-4057-b6c0-4ff7a3e44b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179061415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2179061415
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1785123880
Short name T341
Test name
Test status
Simulation time 362800205 ps
CPU time 2.15 seconds
Started Aug 02 06:45:04 PM PDT 24
Finished Aug 02 06:45:06 PM PDT 24
Peak memory 224552 kb
Host smart-b1518f8e-0865-4e58-b513-b817e09e3eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785123880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1785123880
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2791709382
Short name T271
Test name
Test status
Simulation time 272386668 ps
CPU time 2.62 seconds
Started Aug 02 06:45:00 PM PDT 24
Finished Aug 02 06:45:03 PM PDT 24
Peak memory 224980 kb
Host smart-49664ac8-ed10-4658-8c5f-c63e4fe82e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791709382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2791709382
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.460786026
Short name T760
Test name
Test status
Simulation time 1065656066 ps
CPU time 2.72 seconds
Started Aug 02 06:45:01 PM PDT 24
Finished Aug 02 06:45:03 PM PDT 24
Peak memory 224828 kb
Host smart-6c140b82-afe7-4587-a455-a244fb8102e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460786026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.460786026
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3785382212
Short name T367
Test name
Test status
Simulation time 885180588 ps
CPU time 5 seconds
Started Aug 02 06:45:10 PM PDT 24
Finished Aug 02 06:45:15 PM PDT 24
Peak memory 220960 kb
Host smart-ebf94468-dd2d-4826-a994-033744d66b85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3785382212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3785382212
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.4237879151
Short name T533
Test name
Test status
Simulation time 44696718 ps
CPU time 0.9 seconds
Started Aug 02 06:45:10 PM PDT 24
Finished Aug 02 06:45:11 PM PDT 24
Peak memory 207068 kb
Host smart-8df3efc3-6fdd-49fb-9b25-c6169baf7267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237879151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.4237879151
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.176384190
Short name T893
Test name
Test status
Simulation time 1030315968 ps
CPU time 10.88 seconds
Started Aug 02 06:45:01 PM PDT 24
Finished Aug 02 06:45:12 PM PDT 24
Peak memory 216684 kb
Host smart-fe567560-913f-48e2-a87d-b04d392a9359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176384190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.176384190
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2075628962
Short name T954
Test name
Test status
Simulation time 575293901 ps
CPU time 5.43 seconds
Started Aug 02 06:45:01 PM PDT 24
Finished Aug 02 06:45:07 PM PDT 24
Peak memory 216748 kb
Host smart-4d73638a-ac32-4f55-a188-ec1fb81a904b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075628962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2075628962
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1346012269
Short name T380
Test name
Test status
Simulation time 155669480 ps
CPU time 1.24 seconds
Started Aug 02 06:45:00 PM PDT 24
Finished Aug 02 06:45:01 PM PDT 24
Peak memory 208244 kb
Host smart-2f8a52f7-22d5-4630-8f12-87b23bc85b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346012269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1346012269
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4002512566
Short name T456
Test name
Test status
Simulation time 67072074 ps
CPU time 0.87 seconds
Started Aug 02 06:45:05 PM PDT 24
Finished Aug 02 06:45:06 PM PDT 24
Peak memory 206376 kb
Host smart-31d40ba4-e015-4b43-8c40-63138c8e526c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002512566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4002512566
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1493811727
Short name T387
Test name
Test status
Simulation time 1005795665 ps
CPU time 6.12 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:45:14 PM PDT 24
Peak memory 233036 kb
Host smart-7d6cc5d5-4030-4b29-bec6-39356210aac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493811727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1493811727
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1056982597
Short name T909
Test name
Test status
Simulation time 21263233 ps
CPU time 0.7 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:45:09 PM PDT 24
Peak memory 205936 kb
Host smart-1480566d-8550-4f74-b6ab-2a31d2f1eec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056982597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1056982597
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1175042552
Short name T28
Test name
Test status
Simulation time 611675608 ps
CPU time 2.5 seconds
Started Aug 02 06:45:09 PM PDT 24
Finished Aug 02 06:45:11 PM PDT 24
Peak memory 233188 kb
Host smart-0e850c23-48b2-495b-aece-e15dba5d8e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175042552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1175042552
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2745588112
Short name T342
Test name
Test status
Simulation time 108015858 ps
CPU time 0.72 seconds
Started Aug 02 06:45:10 PM PDT 24
Finished Aug 02 06:45:11 PM PDT 24
Peak memory 205920 kb
Host smart-6c2597ad-b4f0-4d16-bf36-52ac91e68641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745588112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2745588112
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1527834527
Short name T225
Test name
Test status
Simulation time 32373211017 ps
CPU time 159.5 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:47:48 PM PDT 24
Peak memory 250432 kb
Host smart-3f83a202-f050-4fce-a7e5-95964cefab90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527834527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1527834527
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.4087982635
Short name T926
Test name
Test status
Simulation time 99723040602 ps
CPU time 250.53 seconds
Started Aug 02 06:45:10 PM PDT 24
Finished Aug 02 06:49:20 PM PDT 24
Peak memory 252848 kb
Host smart-9c3a059b-ef9c-4e6d-a7da-706c51c323f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087982635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.4087982635
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1210998154
Short name T906
Test name
Test status
Simulation time 1454600040 ps
CPU time 9.61 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:45:17 PM PDT 24
Peak memory 233116 kb
Host smart-7cdddacc-d780-46cd-a021-f3c07375217a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210998154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1210998154
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.879401974
Short name T644
Test name
Test status
Simulation time 805681517 ps
CPU time 22.25 seconds
Started Aug 02 06:45:06 PM PDT 24
Finished Aug 02 06:45:29 PM PDT 24
Peak memory 241372 kb
Host smart-7e2c5d42-c7b8-47d0-9b87-bfd494576c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879401974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds
.879401974
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2439812968
Short name T407
Test name
Test status
Simulation time 199284226 ps
CPU time 2.21 seconds
Started Aug 02 06:45:09 PM PDT 24
Finished Aug 02 06:45:11 PM PDT 24
Peak memory 224960 kb
Host smart-5d4c6563-3ff1-4790-8787-31e578b3bd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439812968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2439812968
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.4253195500
Short name T888
Test name
Test status
Simulation time 317125577 ps
CPU time 9.5 seconds
Started Aug 02 06:45:09 PM PDT 24
Finished Aug 02 06:45:18 PM PDT 24
Peak memory 234144 kb
Host smart-8c164a86-7f44-431a-8c16-1236947b5d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253195500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4253195500
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1576029228
Short name T270
Test name
Test status
Simulation time 17019177606 ps
CPU time 12.61 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:45:20 PM PDT 24
Peak memory 241236 kb
Host smart-5e04f651-8ccd-4ed9-9048-3fbcca59b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576029228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1576029228
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1343223577
Short name T11
Test name
Test status
Simulation time 11473451986 ps
CPU time 5.56 seconds
Started Aug 02 06:45:09 PM PDT 24
Finished Aug 02 06:45:15 PM PDT 24
Peak memory 225084 kb
Host smart-417b6d46-a0a0-4ca1-99f3-33e97ef70308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343223577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1343223577
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.812097243
Short name T887
Test name
Test status
Simulation time 331217346 ps
CPU time 3.44 seconds
Started Aug 02 06:45:07 PM PDT 24
Finished Aug 02 06:45:11 PM PDT 24
Peak memory 223660 kb
Host smart-36ba3700-3088-4f86-a86a-1eef21555d16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=812097243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.812097243
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1386042383
Short name T428
Test name
Test status
Simulation time 5274505038 ps
CPU time 43.61 seconds
Started Aug 02 06:45:12 PM PDT 24
Finished Aug 02 06:45:56 PM PDT 24
Peak memory 252692 kb
Host smart-4e80c4ae-07c9-43e5-983f-46ad119f3c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386042383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1386042383
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2218147564
Short name T748
Test name
Test status
Simulation time 1037084585 ps
CPU time 15.39 seconds
Started Aug 02 06:45:07 PM PDT 24
Finished Aug 02 06:45:22 PM PDT 24
Peak memory 216920 kb
Host smart-b17e5214-2aaf-434a-836f-186cbbb8b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218147564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2218147564
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2653506443
Short name T751
Test name
Test status
Simulation time 10753705374 ps
CPU time 15.99 seconds
Started Aug 02 06:45:07 PM PDT 24
Finished Aug 02 06:45:23 PM PDT 24
Peak memory 216676 kb
Host smart-f1385f98-bc53-4a13-b1cf-413d30150a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653506443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2653506443
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3848327678
Short name T691
Test name
Test status
Simulation time 73009001 ps
CPU time 0.71 seconds
Started Aug 02 06:45:10 PM PDT 24
Finished Aug 02 06:45:11 PM PDT 24
Peak memory 206072 kb
Host smart-5f3eb3ac-aedf-48f7-8825-9142df7d6acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848327678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3848327678
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3243296696
Short name T418
Test name
Test status
Simulation time 39205150 ps
CPU time 0.81 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:45:09 PM PDT 24
Peak memory 206336 kb
Host smart-8c5f5fb4-5723-45bc-934c-709d9f104179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243296696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3243296696
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1390975497
Short name T963
Test name
Test status
Simulation time 1535530008 ps
CPU time 2.74 seconds
Started Aug 02 06:45:16 PM PDT 24
Finished Aug 02 06:45:19 PM PDT 24
Peak memory 224916 kb
Host smart-5ab44c74-7717-41f6-869f-5d078353f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390975497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1390975497
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4029492430
Short name T338
Test name
Test status
Simulation time 43684450 ps
CPU time 0.72 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:14 PM PDT 24
Peak memory 205288 kb
Host smart-e8a8c7bb-0167-4ff1-ae96-6ba0871313b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029492430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
029492430
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3161865338
Short name T408
Test name
Test status
Simulation time 105037175 ps
CPU time 2.3 seconds
Started Aug 02 06:44:11 PM PDT 24
Finished Aug 02 06:44:14 PM PDT 24
Peak memory 224872 kb
Host smart-a25fd079-2b36-43bc-88a1-88ccd308e88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161865338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3161865338
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.142933433
Short name T35
Test name
Test status
Simulation time 213892377 ps
CPU time 0.76 seconds
Started Aug 02 06:44:09 PM PDT 24
Finished Aug 02 06:44:10 PM PDT 24
Peak memory 205936 kb
Host smart-66b945aa-ee73-48e2-ad08-f671305de932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142933433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.142933433
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3962098884
Short name T912
Test name
Test status
Simulation time 26404846909 ps
CPU time 216.44 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:47:50 PM PDT 24
Peak memory 257800 kb
Host smart-8e56041e-67f7-4b33-8b88-cdde40c78588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962098884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3962098884
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3308340024
Short name T610
Test name
Test status
Simulation time 20950076472 ps
CPU time 168.45 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:47:02 PM PDT 24
Peak memory 249704 kb
Host smart-202647b3-05cd-423b-bd0f-abced57c724a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308340024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3308340024
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.879803235
Short name T284
Test name
Test status
Simulation time 61344031202 ps
CPU time 207.87 seconds
Started Aug 02 06:44:12 PM PDT 24
Finished Aug 02 06:47:40 PM PDT 24
Peak memory 250264 kb
Host smart-e26f24a7-feca-4eb0-9635-c3916c81b61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879803235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
879803235
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2595755045
Short name T74
Test name
Test status
Simulation time 4254312582 ps
CPU time 9.93 seconds
Started Aug 02 06:44:12 PM PDT 24
Finished Aug 02 06:44:22 PM PDT 24
Peak memory 224952 kb
Host smart-ce2736e5-27e3-4c4c-857d-f5fdb548bb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595755045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2595755045
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2640172421
Short name T239
Test name
Test status
Simulation time 340053045 ps
CPU time 10.85 seconds
Started Aug 02 06:44:09 PM PDT 24
Finished Aug 02 06:44:20 PM PDT 24
Peak memory 239920 kb
Host smart-b22deb38-b71d-4036-b1c1-6aceb3c61d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640172421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2640172421
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2153421255
Short name T892
Test name
Test status
Simulation time 18778259455 ps
CPU time 8.55 seconds
Started Aug 02 06:44:12 PM PDT 24
Finished Aug 02 06:44:20 PM PDT 24
Peak memory 224928 kb
Host smart-e9e7f9f3-ed58-4202-ac63-e1ebd765fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153421255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2153421255
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2578568
Short name T232
Test name
Test status
Simulation time 726129393 ps
CPU time 5.36 seconds
Started Aug 02 06:44:12 PM PDT 24
Finished Aug 02 06:44:17 PM PDT 24
Peak memory 240768 kb
Host smart-693164c1-2e33-4d56-abbf-5c3960d047ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2578568
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3683402744
Short name T928
Test name
Test status
Simulation time 6788146516 ps
CPU time 13.11 seconds
Started Aug 02 06:44:11 PM PDT 24
Finished Aug 02 06:44:24 PM PDT 24
Peak memory 220676 kb
Host smart-543e195b-1173-464d-ab04-cb2e195b198e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3683402744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3683402744
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.52953802
Short name T85
Test name
Test status
Simulation time 88012713 ps
CPU time 1.25 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:15 PM PDT 24
Peak memory 237976 kb
Host smart-17482a25-3f1a-45b5-a9b6-14b4e0bc36dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52953802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.52953802
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1832269957
Short name T587
Test name
Test status
Simulation time 31286752973 ps
CPU time 87.46 seconds
Started Aug 02 06:44:12 PM PDT 24
Finished Aug 02 06:45:39 PM PDT 24
Peak memory 249612 kb
Host smart-3b82d6d4-4980-467f-bee2-38cb90d61ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832269957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1832269957
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3420264373
Short name T613
Test name
Test status
Simulation time 2354637181 ps
CPU time 7.77 seconds
Started Aug 02 06:44:14 PM PDT 24
Finished Aug 02 06:44:22 PM PDT 24
Peak memory 216784 kb
Host smart-802af640-a525-4816-b53f-d958126aacc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420264373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3420264373
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2464144311
Short name T103
Test name
Test status
Simulation time 16418225735 ps
CPU time 12.09 seconds
Started Aug 02 06:44:11 PM PDT 24
Finished Aug 02 06:44:23 PM PDT 24
Peak memory 216656 kb
Host smart-259d7c53-229f-4135-9c9b-5de78e3d80a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464144311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2464144311
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3789357377
Short name T834
Test name
Test status
Simulation time 40008844 ps
CPU time 2.4 seconds
Started Aug 02 06:44:11 PM PDT 24
Finished Aug 02 06:44:13 PM PDT 24
Peak memory 216644 kb
Host smart-8e5db465-e0df-4aa8-8cac-0a7c382178e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789357377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3789357377
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2815949184
Short name T859
Test name
Test status
Simulation time 43463605 ps
CPU time 0.82 seconds
Started Aug 02 06:44:10 PM PDT 24
Finished Aug 02 06:44:11 PM PDT 24
Peak memory 206392 kb
Host smart-352316ea-6ca4-42f1-a862-3f2a284aec61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815949184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2815949184
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.632414366
Short name T487
Test name
Test status
Simulation time 14244333961 ps
CPU time 14.01 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:27 PM PDT 24
Peak memory 241164 kb
Host smart-50d56cad-51b5-4e23-bdba-be5010e13be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632414366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.632414366
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2229220294
Short name T770
Test name
Test status
Simulation time 36552648 ps
CPU time 0.74 seconds
Started Aug 02 06:45:22 PM PDT 24
Finished Aug 02 06:45:23 PM PDT 24
Peak memory 205200 kb
Host smart-2481e565-e79c-4634-b92a-95a08322e5fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229220294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2229220294
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1514426846
Short name T483
Test name
Test status
Simulation time 1689987367 ps
CPU time 12.3 seconds
Started Aug 02 06:45:09 PM PDT 24
Finished Aug 02 06:45:22 PM PDT 24
Peak memory 233172 kb
Host smart-734456e1-694e-44f8-bc19-033aa45bbe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514426846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1514426846
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1884679519
Short name T754
Test name
Test status
Simulation time 26104400 ps
CPU time 0.8 seconds
Started Aug 02 06:45:06 PM PDT 24
Finished Aug 02 06:45:07 PM PDT 24
Peak memory 205968 kb
Host smart-2e1c1be6-659d-49f0-8418-8c95a9f34f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884679519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1884679519
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3210126488
Short name T774
Test name
Test status
Simulation time 46754033761 ps
CPU time 103.15 seconds
Started Aug 02 06:45:18 PM PDT 24
Finished Aug 02 06:47:01 PM PDT 24
Peak memory 241408 kb
Host smart-635bfef7-5d3e-48d4-8578-9876b705612f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210126488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3210126488
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1567781009
Short name T322
Test name
Test status
Simulation time 9586865543 ps
CPU time 43.12 seconds
Started Aug 02 06:45:20 PM PDT 24
Finished Aug 02 06:46:04 PM PDT 24
Peak memory 225092 kb
Host smart-4631ccdb-bddb-4fc9-a3cc-da20c564eb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567781009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1567781009
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2495341101
Short name T313
Test name
Test status
Simulation time 18340981303 ps
CPU time 32.51 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:45:41 PM PDT 24
Peak memory 234328 kb
Host smart-30661611-5c43-40b1-9aea-be1035f58f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495341101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2495341101
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2844311211
Short name T857
Test name
Test status
Simulation time 208538028 ps
CPU time 2.09 seconds
Started Aug 02 06:45:06 PM PDT 24
Finished Aug 02 06:45:08 PM PDT 24
Peak memory 224900 kb
Host smart-65a8a7da-3fe0-442c-ab55-0fa6b2aa559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844311211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2844311211
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.582307501
Short name T236
Test name
Test status
Simulation time 40181100107 ps
CPU time 100.06 seconds
Started Aug 02 06:45:10 PM PDT 24
Finished Aug 02 06:46:50 PM PDT 24
Peak memory 250524 kb
Host smart-e2124219-2806-4f60-9726-7135c077d072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582307501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.582307501
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1504670500
Short name T690
Test name
Test status
Simulation time 111192431 ps
CPU time 2.51 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:45:11 PM PDT 24
Peak memory 232792 kb
Host smart-1161c583-8a92-492d-b08c-592d186fa7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504670500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1504670500
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3573614623
Short name T507
Test name
Test status
Simulation time 1204009591 ps
CPU time 3.91 seconds
Started Aug 02 06:45:12 PM PDT 24
Finished Aug 02 06:45:16 PM PDT 24
Peak memory 233164 kb
Host smart-9a19e02f-c491-4570-8ddf-171e09fbde6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573614623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3573614623
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1051728442
Short name T807
Test name
Test status
Simulation time 2962588061 ps
CPU time 7.2 seconds
Started Aug 02 06:45:08 PM PDT 24
Finished Aug 02 06:45:15 PM PDT 24
Peak memory 220068 kb
Host smart-3e2fed9c-674b-42a5-bda2-cb45b0224850
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1051728442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1051728442
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3374003230
Short name T377
Test name
Test status
Simulation time 2078035612 ps
CPU time 29.68 seconds
Started Aug 02 06:45:10 PM PDT 24
Finished Aug 02 06:45:40 PM PDT 24
Peak memory 216872 kb
Host smart-46b33582-5abe-4982-8b6d-7b0c04a1e555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374003230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3374003230
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.34234020
Short name T37
Test name
Test status
Simulation time 795673619 ps
CPU time 6.23 seconds
Started Aug 02 06:45:11 PM PDT 24
Finished Aug 02 06:45:18 PM PDT 24
Peak memory 216636 kb
Host smart-36300dd5-8084-4599-a032-93ff442b649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34234020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.34234020
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1030098941
Short name T836
Test name
Test status
Simulation time 246175988 ps
CPU time 3.06 seconds
Started Aug 02 06:45:07 PM PDT 24
Finished Aug 02 06:45:10 PM PDT 24
Peak memory 216688 kb
Host smart-b2209c4c-3f26-4bd2-b499-4f6a6acfec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030098941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1030098941
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1733307734
Short name T519
Test name
Test status
Simulation time 45399841 ps
CPU time 0.77 seconds
Started Aug 02 06:45:16 PM PDT 24
Finished Aug 02 06:45:17 PM PDT 24
Peak memory 206368 kb
Host smart-b2fda635-e28d-485e-838a-aa8bf0bc90ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733307734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1733307734
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3561827847
Short name T702
Test name
Test status
Simulation time 46636531 ps
CPU time 2.44 seconds
Started Aug 02 06:45:14 PM PDT 24
Finished Aug 02 06:45:17 PM PDT 24
Peak memory 224200 kb
Host smart-3091c25f-4b64-4a65-9ccd-cac65e848116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561827847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3561827847
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2870414106
Short name T522
Test name
Test status
Simulation time 20993023 ps
CPU time 0.74 seconds
Started Aug 02 06:45:20 PM PDT 24
Finished Aug 02 06:45:21 PM PDT 24
Peak memory 205848 kb
Host smart-803470a0-6aad-4fad-9161-555ab271663e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870414106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2870414106
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3754296857
Short name T758
Test name
Test status
Simulation time 774327771 ps
CPU time 6.07 seconds
Started Aug 02 06:45:20 PM PDT 24
Finished Aug 02 06:45:27 PM PDT 24
Peak memory 224904 kb
Host smart-14668b03-ddf6-47f0-b39a-d3274168921d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754296857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3754296857
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3855101197
Short name T695
Test name
Test status
Simulation time 17833435 ps
CPU time 0.83 seconds
Started Aug 02 06:45:23 PM PDT 24
Finished Aug 02 06:45:25 PM PDT 24
Peak memory 207264 kb
Host smart-992a469d-00e8-4b17-8dce-b0bda3b71c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855101197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3855101197
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1210566781
Short name T396
Test name
Test status
Simulation time 4128549705 ps
CPU time 5.76 seconds
Started Aug 02 06:45:23 PM PDT 24
Finished Aug 02 06:45:29 PM PDT 24
Peak memory 217892 kb
Host smart-6f342781-ffd6-4d6f-b387-84c5e3805dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210566781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1210566781
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2630593987
Short name T5
Test name
Test status
Simulation time 3418583924 ps
CPU time 8.43 seconds
Started Aug 02 06:45:21 PM PDT 24
Finished Aug 02 06:45:29 PM PDT 24
Peak memory 235724 kb
Host smart-258f1686-8dd9-4022-bd7b-2db964abeaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630593987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2630593987
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3513976391
Short name T848
Test name
Test status
Simulation time 75981401431 ps
CPU time 42.44 seconds
Started Aug 02 06:45:18 PM PDT 24
Finished Aug 02 06:46:00 PM PDT 24
Peak memory 249520 kb
Host smart-3c7279e6-26d7-4b53-a855-fc9d1547a5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513976391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3513976391
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.156721626
Short name T992
Test name
Test status
Simulation time 827641181 ps
CPU time 4.14 seconds
Started Aug 02 06:45:18 PM PDT 24
Finished Aug 02 06:45:22 PM PDT 24
Peak memory 233168 kb
Host smart-ef287c23-5633-4f74-b9ae-1def598214a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156721626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.156721626
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1907694901
Short name T975
Test name
Test status
Simulation time 60282899 ps
CPU time 2.29 seconds
Started Aug 02 06:45:27 PM PDT 24
Finished Aug 02 06:45:29 PM PDT 24
Peak memory 232852 kb
Host smart-7760f49d-cde8-468d-b0c4-e0a9d4853230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907694901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1907694901
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3534633222
Short name T274
Test name
Test status
Simulation time 5152971918 ps
CPU time 8.14 seconds
Started Aug 02 06:45:23 PM PDT 24
Finished Aug 02 06:45:31 PM PDT 24
Peak memory 233116 kb
Host smart-8f6cadec-e1bf-4359-8f2f-097e82a86c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534633222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3534633222
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3126191920
Short name T514
Test name
Test status
Simulation time 132433298 ps
CPU time 2.81 seconds
Started Aug 02 06:45:21 PM PDT 24
Finished Aug 02 06:45:24 PM PDT 24
Peak memory 224828 kb
Host smart-fb7e0ab7-5d01-4b0f-b771-291f8fdaeec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126191920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3126191920
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.697731223
Short name T536
Test name
Test status
Simulation time 198493209 ps
CPU time 3.84 seconds
Started Aug 02 06:45:22 PM PDT 24
Finished Aug 02 06:45:26 PM PDT 24
Peak memory 220996 kb
Host smart-d3c09930-a8a0-49a6-a7f3-446df27951c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=697731223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.697731223
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.259703330
Short name T325
Test name
Test status
Simulation time 424555343 ps
CPU time 5.72 seconds
Started Aug 02 06:45:24 PM PDT 24
Finished Aug 02 06:45:30 PM PDT 24
Peak memory 216804 kb
Host smart-7c07143e-d899-4496-a351-29fb61f98f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259703330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.259703330
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3146328506
Short name T662
Test name
Test status
Simulation time 20939176421 ps
CPU time 13.21 seconds
Started Aug 02 06:45:20 PM PDT 24
Finished Aug 02 06:45:33 PM PDT 24
Peak memory 216704 kb
Host smart-fe4f129d-8eae-41f6-a6f0-7d8dd5fc239c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146328506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3146328506
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.502113805
Short name T865
Test name
Test status
Simulation time 309589469 ps
CPU time 3.78 seconds
Started Aug 02 06:45:23 PM PDT 24
Finished Aug 02 06:45:27 PM PDT 24
Peak memory 216668 kb
Host smart-8f906cdd-c21c-425c-98ed-af18f1601fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502113805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.502113805
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3586500484
Short name T700
Test name
Test status
Simulation time 51962098 ps
CPU time 0.96 seconds
Started Aug 02 06:45:22 PM PDT 24
Finished Aug 02 06:45:23 PM PDT 24
Peak memory 206412 kb
Host smart-4bc7b4f2-2d11-4e71-bcae-c7cceb9e1f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586500484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3586500484
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.861777157
Short name T192
Test name
Test status
Simulation time 1660080346 ps
CPU time 6.31 seconds
Started Aug 02 06:45:19 PM PDT 24
Finished Aug 02 06:45:25 PM PDT 24
Peak memory 234336 kb
Host smart-24b6aa23-183b-43ef-b57f-769183e8b634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861777157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.861777157
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1850250296
Short name T76
Test name
Test status
Simulation time 29980138 ps
CPU time 0.77 seconds
Started Aug 02 06:45:21 PM PDT 24
Finished Aug 02 06:45:22 PM PDT 24
Peak memory 205916 kb
Host smart-74a4caa3-e41b-422a-9a28-fdd3be2f4374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850250296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1850250296
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.302511121
Short name T455
Test name
Test status
Simulation time 3087537885 ps
CPU time 4.81 seconds
Started Aug 02 06:45:25 PM PDT 24
Finished Aug 02 06:45:30 PM PDT 24
Peak memory 233124 kb
Host smart-e3c925ff-42e7-45bd-85a5-dd40da01a567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302511121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.302511121
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3156094297
Short name T783
Test name
Test status
Simulation time 50739769 ps
CPU time 0.77 seconds
Started Aug 02 06:45:20 PM PDT 24
Finished Aug 02 06:45:21 PM PDT 24
Peak memory 207340 kb
Host smart-92d3c0ec-3f2e-40e5-90a8-2270f310f710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156094297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3156094297
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2899210574
Short name T60
Test name
Test status
Simulation time 253411043 ps
CPU time 5.62 seconds
Started Aug 02 06:45:23 PM PDT 24
Finished Aug 02 06:45:28 PM PDT 24
Peak memory 224992 kb
Host smart-9fd7a44d-1e25-4f7f-8322-92fed3b507a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899210574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2899210574
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2898857443
Short name T559
Test name
Test status
Simulation time 2985764461 ps
CPU time 73.5 seconds
Started Aug 02 06:45:24 PM PDT 24
Finished Aug 02 06:46:38 PM PDT 24
Peak memory 256256 kb
Host smart-32f45b42-bebd-4057-b2bf-b1fd64268073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898857443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2898857443
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1864149390
Short name T317
Test name
Test status
Simulation time 5799374302 ps
CPU time 20.11 seconds
Started Aug 02 06:45:20 PM PDT 24
Finished Aug 02 06:45:40 PM PDT 24
Peak memory 234568 kb
Host smart-52fe4195-0083-4152-9441-01c98e3fa7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864149390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1864149390
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1084509011
Short name T567
Test name
Test status
Simulation time 71746256910 ps
CPU time 87.57 seconds
Started Aug 02 06:45:25 PM PDT 24
Finished Aug 02 06:46:52 PM PDT 24
Peak memory 262232 kb
Host smart-14851855-96a6-484a-b94b-6e3e38a3db88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084509011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1084509011
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2814236215
Short name T617
Test name
Test status
Simulation time 4781609103 ps
CPU time 9.12 seconds
Started Aug 02 06:45:23 PM PDT 24
Finished Aug 02 06:45:32 PM PDT 24
Peak memory 225008 kb
Host smart-24c7e816-012b-4683-a01b-a3948f7e4216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814236215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2814236215
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.19398734
Short name T740
Test name
Test status
Simulation time 31331865 ps
CPU time 2.39 seconds
Started Aug 02 06:45:19 PM PDT 24
Finished Aug 02 06:45:21 PM PDT 24
Peak memory 232852 kb
Host smart-d70fcfe6-1754-4bb1-a431-25ec1c39ba08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19398734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.19398734
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3964312404
Short name T615
Test name
Test status
Simulation time 37146099555 ps
CPU time 27.55 seconds
Started Aug 02 06:45:20 PM PDT 24
Finished Aug 02 06:45:48 PM PDT 24
Peak memory 224928 kb
Host smart-a4677139-2fc3-4e5b-a342-65c5a96b9436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964312404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3964312404
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3573447346
Short name T446
Test name
Test status
Simulation time 88501628 ps
CPU time 2.13 seconds
Started Aug 02 06:45:24 PM PDT 24
Finished Aug 02 06:45:26 PM PDT 24
Peak memory 223424 kb
Host smart-f0cdbc14-6680-421f-8b11-a204f1c22838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573447346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3573447346
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1260134366
Short name T599
Test name
Test status
Simulation time 4716763754 ps
CPU time 11.8 seconds
Started Aug 02 06:45:20 PM PDT 24
Finished Aug 02 06:45:32 PM PDT 24
Peak memory 222532 kb
Host smart-090d83c4-0c83-4131-9d4a-f5dc2cd65d12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1260134366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1260134366
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3638382477
Short name T860
Test name
Test status
Simulation time 125233792953 ps
CPU time 238.86 seconds
Started Aug 02 06:45:24 PM PDT 24
Finished Aug 02 06:49:23 PM PDT 24
Peak memory 253572 kb
Host smart-5021598c-3cdf-4b47-bf8a-0058737265c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638382477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3638382477
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4077945378
Short name T779
Test name
Test status
Simulation time 1741472664 ps
CPU time 14.09 seconds
Started Aug 02 06:45:20 PM PDT 24
Finished Aug 02 06:45:35 PM PDT 24
Peak memory 216700 kb
Host smart-2ba3af52-791c-42a5-8a17-bc38f0d041b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077945378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4077945378
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.81880620
Short name T403
Test name
Test status
Simulation time 5535263001 ps
CPU time 11.73 seconds
Started Aug 02 06:45:20 PM PDT 24
Finished Aug 02 06:45:32 PM PDT 24
Peak memory 216684 kb
Host smart-f330c5e6-1b59-4f66-b8e1-4a48bb0a50a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81880620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.81880620
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3345704261
Short name T593
Test name
Test status
Simulation time 228514195 ps
CPU time 3.4 seconds
Started Aug 02 06:45:19 PM PDT 24
Finished Aug 02 06:45:23 PM PDT 24
Peak memory 216680 kb
Host smart-2bc033c8-2a43-4695-8aa4-1f5b41565708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345704261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3345704261
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.197862620
Short name T675
Test name
Test status
Simulation time 55682850 ps
CPU time 0.89 seconds
Started Aug 02 06:45:21 PM PDT 24
Finished Aug 02 06:45:22 PM PDT 24
Peak memory 206388 kb
Host smart-73a23e10-b480-49fc-89ce-d3a562b452d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197862620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.197862620
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1634472236
Short name T437
Test name
Test status
Simulation time 697490304 ps
CPU time 8.95 seconds
Started Aug 02 06:45:27 PM PDT 24
Finished Aug 02 06:45:36 PM PDT 24
Peak memory 237668 kb
Host smart-79d0e959-44c1-43ad-b447-1af378b26142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634472236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1634472236
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3773925137
Short name T344
Test name
Test status
Simulation time 12707152 ps
CPU time 0.76 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:45:35 PM PDT 24
Peak memory 205764 kb
Host smart-26b5b35d-d2b0-446f-84a1-ace592fd1006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773925137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3773925137
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4168238848
Short name T475
Test name
Test status
Simulation time 880305793 ps
CPU time 6.44 seconds
Started Aug 02 06:45:31 PM PDT 24
Finished Aug 02 06:45:38 PM PDT 24
Peak memory 224908 kb
Host smart-0ced77eb-582f-42f5-9d55-f66f358163db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168238848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4168238848
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3061319723
Short name T637
Test name
Test status
Simulation time 51706892 ps
CPU time 0.75 seconds
Started Aug 02 06:45:24 PM PDT 24
Finished Aug 02 06:45:25 PM PDT 24
Peak memory 206008 kb
Host smart-9cbc1057-a35e-4d6d-8fac-cb106ceefd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061319723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3061319723
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2816646079
Short name T90
Test name
Test status
Simulation time 28647532204 ps
CPU time 220.71 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:49:15 PM PDT 24
Peak memory 254448 kb
Host smart-373b4564-d306-41f0-b8f0-f7b356a0c253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816646079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2816646079
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2284108204
Short name T470
Test name
Test status
Simulation time 11410982519 ps
CPU time 80.04 seconds
Started Aug 02 06:45:29 PM PDT 24
Finished Aug 02 06:46:49 PM PDT 24
Peak memory 251440 kb
Host smart-d1cd070c-d65e-4b56-9a82-f78e05344917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284108204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2284108204
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2243563807
Short name T513
Test name
Test status
Simulation time 1368881618 ps
CPU time 2.79 seconds
Started Aug 02 06:45:30 PM PDT 24
Finished Aug 02 06:45:33 PM PDT 24
Peak memory 217752 kb
Host smart-7b2d8c9e-b042-46ba-be9b-7ca5a6b20a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243563807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2243563807
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3625716040
Short name T312
Test name
Test status
Simulation time 1225181465 ps
CPU time 11.37 seconds
Started Aug 02 06:45:31 PM PDT 24
Finished Aug 02 06:45:43 PM PDT 24
Peak memory 221232 kb
Host smart-620d31ea-a61a-44f1-9a29-52e80b0a3d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625716040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3625716040
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1911464067
Short name T898
Test name
Test status
Simulation time 9264421397 ps
CPU time 45.08 seconds
Started Aug 02 06:45:30 PM PDT 24
Finished Aug 02 06:46:15 PM PDT 24
Peak memory 257196 kb
Host smart-578fa7cb-71ae-490c-a724-00f3b3cae16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911464067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1911464067
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4282430020
Short name T196
Test name
Test status
Simulation time 673931150 ps
CPU time 4.65 seconds
Started Aug 02 06:45:32 PM PDT 24
Finished Aug 02 06:45:37 PM PDT 24
Peak memory 224972 kb
Host smart-65af97f2-6006-420b-a39b-ef341850f975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282430020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4282430020
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.244728977
Short name T1005
Test name
Test status
Simulation time 4649331321 ps
CPU time 53.32 seconds
Started Aug 02 06:45:32 PM PDT 24
Finished Aug 02 06:46:26 PM PDT 24
Peak memory 233236 kb
Host smart-9d8d046c-007a-4c1d-8a17-7b09e3fcac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244728977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.244728977
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3192645935
Short name T230
Test name
Test status
Simulation time 13758895339 ps
CPU time 19.95 seconds
Started Aug 02 06:45:33 PM PDT 24
Finished Aug 02 06:45:53 PM PDT 24
Peak memory 233120 kb
Host smart-0c9817b6-8237-410e-af3b-3990f0efcc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192645935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3192645935
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3179744573
Short name T211
Test name
Test status
Simulation time 13797542344 ps
CPU time 16.9 seconds
Started Aug 02 06:45:21 PM PDT 24
Finished Aug 02 06:45:38 PM PDT 24
Peak memory 219260 kb
Host smart-ef368e3a-7820-4598-8c7b-8ff928ca7803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179744573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3179744573
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3016828411
Short name T156
Test name
Test status
Simulation time 1612250801 ps
CPU time 3.83 seconds
Started Aug 02 06:45:32 PM PDT 24
Finished Aug 02 06:45:36 PM PDT 24
Peak memory 223716 kb
Host smart-0b7690da-0ec5-41e1-ac15-e331eafd2739
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3016828411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3016828411
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2261638689
Short name T302
Test name
Test status
Simulation time 36150086403 ps
CPU time 413.96 seconds
Started Aug 02 06:45:29 PM PDT 24
Finished Aug 02 06:52:24 PM PDT 24
Peak memory 282452 kb
Host smart-d2536ecd-4357-4801-9139-cad24b59af5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261638689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2261638689
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2056460988
Short name T941
Test name
Test status
Simulation time 13147839331 ps
CPU time 34.75 seconds
Started Aug 02 06:45:22 PM PDT 24
Finished Aug 02 06:45:57 PM PDT 24
Peak memory 216808 kb
Host smart-a78f44dc-6f50-4033-8ae9-08d2cb6732ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056460988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2056460988
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.218502441
Short name T531
Test name
Test status
Simulation time 12197021 ps
CPU time 0.71 seconds
Started Aug 02 06:45:27 PM PDT 24
Finished Aug 02 06:45:27 PM PDT 24
Peak memory 206112 kb
Host smart-c257b277-c412-4904-80a7-b33047d1de4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218502441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.218502441
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2170299646
Short name T457
Test name
Test status
Simulation time 220991383 ps
CPU time 3.18 seconds
Started Aug 02 06:45:21 PM PDT 24
Finished Aug 02 06:45:24 PM PDT 24
Peak memory 216676 kb
Host smart-b501cd62-3e28-4611-90f8-3f3d1fd20672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170299646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2170299646
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3429593352
Short name T829
Test name
Test status
Simulation time 77052946 ps
CPU time 0.79 seconds
Started Aug 02 06:45:23 PM PDT 24
Finished Aug 02 06:45:24 PM PDT 24
Peak memory 206424 kb
Host smart-2a9cca3a-6b0f-4e6d-bcd5-b21aa67d1e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429593352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3429593352
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2102245957
Short name T254
Test name
Test status
Simulation time 4649416228 ps
CPU time 10.54 seconds
Started Aug 02 06:45:28 PM PDT 24
Finished Aug 02 06:45:38 PM PDT 24
Peak memory 249616 kb
Host smart-258fe64a-1cfe-43f6-b20b-d0355fe1b2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102245957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2102245957
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3317385235
Short name T800
Test name
Test status
Simulation time 14072900 ps
CPU time 0.71 seconds
Started Aug 02 06:45:33 PM PDT 24
Finished Aug 02 06:45:34 PM PDT 24
Peak memory 205268 kb
Host smart-037ff555-9081-46f8-bebd-3e7961431c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317385235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3317385235
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2858317178
Short name T445
Test name
Test status
Simulation time 75730208 ps
CPU time 2.39 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:45:42 PM PDT 24
Peak memory 224592 kb
Host smart-803ceff2-122e-4296-9a42-ae21d9a9e5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858317178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2858317178
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3963866930
Short name T545
Test name
Test status
Simulation time 33652271 ps
CPU time 0.82 seconds
Started Aug 02 06:45:28 PM PDT 24
Finished Aug 02 06:45:29 PM PDT 24
Peak memory 206988 kb
Host smart-6b6621a9-07d9-4041-a4b8-fca7682f350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963866930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3963866930
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.4191162248
Short name T174
Test name
Test status
Simulation time 26276549900 ps
CPU time 90.81 seconds
Started Aug 02 06:45:29 PM PDT 24
Finished Aug 02 06:47:00 PM PDT 24
Peak memory 252832 kb
Host smart-6974df21-3ac1-471c-8a74-7160c072e6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191162248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4191162248
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2450395593
Short name T233
Test name
Test status
Simulation time 22131325545 ps
CPU time 233.63 seconds
Started Aug 02 06:45:32 PM PDT 24
Finished Aug 02 06:49:26 PM PDT 24
Peak memory 266064 kb
Host smart-d84c72d0-f8c2-4bbc-b871-0a5974b98be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450395593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2450395593
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1925101050
Short name T808
Test name
Test status
Simulation time 309295484 ps
CPU time 3.38 seconds
Started Aug 02 06:45:30 PM PDT 24
Finished Aug 02 06:45:33 PM PDT 24
Peak memory 233140 kb
Host smart-c845df8d-1472-4a36-9969-f4d876abca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925101050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1925101050
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2554335281
Short name T653
Test name
Test status
Simulation time 245582880662 ps
CPU time 91.62 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:47:06 PM PDT 24
Peak memory 252980 kb
Host smart-afcf6e40-6b9f-4a66-a5c2-bf8c3a809236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554335281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2554335281
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.380841294
Short name T188
Test name
Test status
Simulation time 241962016 ps
CPU time 4.26 seconds
Started Aug 02 06:45:29 PM PDT 24
Finished Aug 02 06:45:34 PM PDT 24
Peak memory 233124 kb
Host smart-10075235-4137-47df-b2eb-979d65dfc08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380841294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.380841294
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1796756868
Short name T550
Test name
Test status
Simulation time 155464692 ps
CPU time 6.06 seconds
Started Aug 02 06:45:31 PM PDT 24
Finished Aug 02 06:45:37 PM PDT 24
Peak memory 233156 kb
Host smart-64ffdf8c-58ff-4ee5-9dc2-2fae10b30fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796756868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1796756868
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2788720498
Short name T293
Test name
Test status
Simulation time 27101425303 ps
CPU time 12.99 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:45:47 PM PDT 24
Peak memory 224980 kb
Host smart-891db6ef-682a-4072-9684-b0d395e5bfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788720498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2788720498
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3075164847
Short name T757
Test name
Test status
Simulation time 3121874963 ps
CPU time 5.13 seconds
Started Aug 02 06:45:31 PM PDT 24
Finished Aug 02 06:45:36 PM PDT 24
Peak memory 233260 kb
Host smart-201ae1ff-74d8-421a-8fb2-2bba55c6dde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075164847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3075164847
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1018471668
Short name T993
Test name
Test status
Simulation time 3962438809 ps
CPU time 14.55 seconds
Started Aug 02 06:45:30 PM PDT 24
Finished Aug 02 06:45:45 PM PDT 24
Peak memory 223612 kb
Host smart-9398ebb0-20b9-47be-add4-8eb724ac039b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1018471668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1018471668
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1958915310
Short name T87
Test name
Test status
Simulation time 19951783625 ps
CPU time 259.2 seconds
Started Aug 02 06:45:30 PM PDT 24
Finished Aug 02 06:49:49 PM PDT 24
Peak memory 257872 kb
Host smart-320fa545-fdc5-42ce-a782-ab3ad1780e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958915310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1958915310
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3936133734
Short name T816
Test name
Test status
Simulation time 9229535941 ps
CPU time 11.03 seconds
Started Aug 02 06:45:29 PM PDT 24
Finished Aug 02 06:45:40 PM PDT 24
Peak memory 216992 kb
Host smart-6b14f0f8-17f1-487e-8e35-2f59b554ee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936133734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3936133734
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3215808995
Short name T336
Test name
Test status
Simulation time 1483644196 ps
CPU time 6.8 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:45:41 PM PDT 24
Peak memory 216628 kb
Host smart-3cfc74b1-dbba-485e-8def-716a8a30cfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215808995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3215808995
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4040832010
Short name T435
Test name
Test status
Simulation time 63281413 ps
CPU time 1.8 seconds
Started Aug 02 06:45:31 PM PDT 24
Finished Aug 02 06:45:33 PM PDT 24
Peak memory 216744 kb
Host smart-5f4e166d-9018-494d-88db-0be59c80cad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040832010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4040832010
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3299170116
Short name T339
Test name
Test status
Simulation time 325351221 ps
CPU time 0.9 seconds
Started Aug 02 06:45:29 PM PDT 24
Finished Aug 02 06:45:30 PM PDT 24
Peak memory 206372 kb
Host smart-4fd73c84-a567-485e-8a44-e57914fbf1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299170116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3299170116
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.318061344
Short name T405
Test name
Test status
Simulation time 1354015153 ps
CPU time 10.69 seconds
Started Aug 02 06:45:36 PM PDT 24
Finished Aug 02 06:45:47 PM PDT 24
Peak memory 233128 kb
Host smart-8e4f19ab-2ef5-4431-95e4-8a052b8a0ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318061344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.318061344
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.324407067
Short name T569
Test name
Test status
Simulation time 87102376 ps
CPU time 0.7 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:45:39 PM PDT 24
Peak memory 205256 kb
Host smart-95e51ee1-3f79-4c65-96e9-cd9ba2fbd47d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324407067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.324407067
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1505997809
Short name T607
Test name
Test status
Simulation time 215668424 ps
CPU time 2.57 seconds
Started Aug 02 06:45:29 PM PDT 24
Finished Aug 02 06:45:32 PM PDT 24
Peak memory 233068 kb
Host smart-0ec839f4-8127-4a89-843e-091837bfe66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505997809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1505997809
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2236328241
Short name T739
Test name
Test status
Simulation time 19925251 ps
CPU time 0.79 seconds
Started Aug 02 06:45:31 PM PDT 24
Finished Aug 02 06:45:32 PM PDT 24
Peak memory 206004 kb
Host smart-d03a6a80-5a53-409c-8e3c-b28df107f8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236328241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2236328241
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3154356878
Short name T198
Test name
Test status
Simulation time 11063529657 ps
CPU time 77.51 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:46:51 PM PDT 24
Peak memory 249572 kb
Host smart-29c66c30-2aa1-4f1a-84b0-a7cd87b07e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154356878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3154356878
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.928963959
Short name T195
Test name
Test status
Simulation time 22601807879 ps
CPU time 39.14 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:46:18 PM PDT 24
Peak memory 241380 kb
Host smart-009e59fb-ea9e-43d5-8adf-71652e0e7a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928963959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.928963959
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1741236624
Short name T985
Test name
Test status
Simulation time 3306803812 ps
CPU time 37.1 seconds
Started Aug 02 06:45:36 PM PDT 24
Finished Aug 02 06:46:14 PM PDT 24
Peak memory 225092 kb
Host smart-8fd1897a-a15f-4256-8803-95b16f5e0f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741236624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1741236624
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4238688950
Short name T902
Test name
Test status
Simulation time 8577376210 ps
CPU time 27.99 seconds
Started Aug 02 06:45:36 PM PDT 24
Finished Aug 02 06:46:04 PM PDT 24
Peak memory 225032 kb
Host smart-18b3b883-7496-43cc-a622-41af5c81f321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238688950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4238688950
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1210189467
Short name T736
Test name
Test status
Simulation time 8899599143 ps
CPU time 48.25 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:46:27 PM PDT 24
Peak memory 254724 kb
Host smart-daa671de-dc15-4538-9cbd-14f04e65029a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210189467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1210189467
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1117270159
Short name T917
Test name
Test status
Simulation time 2078620740 ps
CPU time 6.88 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:45:41 PM PDT 24
Peak memory 233124 kb
Host smart-e6db0f97-9eb4-47b1-a411-d47b47c9c77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117270159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1117270159
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3826902195
Short name T53
Test name
Test status
Simulation time 259857424 ps
CPU time 3.59 seconds
Started Aug 02 06:45:29 PM PDT 24
Finished Aug 02 06:45:33 PM PDT 24
Peak memory 233156 kb
Host smart-2e20376b-1b7a-45ab-ae2a-ed54bdfe0af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826902195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3826902195
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4273305713
Short name T997
Test name
Test status
Simulation time 744334413 ps
CPU time 7.14 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:45:42 PM PDT 24
Peak memory 248668 kb
Host smart-0c4a661e-d11b-47da-8f13-e2b9e9ec80c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273305713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4273305713
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.851242759
Short name T660
Test name
Test status
Simulation time 427724510 ps
CPU time 4.06 seconds
Started Aug 02 06:45:36 PM PDT 24
Finished Aug 02 06:45:41 PM PDT 24
Peak memory 234764 kb
Host smart-97173394-7635-4f2f-8825-0db69f3c3ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851242759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.851242759
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2263931880
Short name T742
Test name
Test status
Simulation time 202114045 ps
CPU time 3.86 seconds
Started Aug 02 06:45:33 PM PDT 24
Finished Aug 02 06:45:37 PM PDT 24
Peak memory 223088 kb
Host smart-e45af695-c0b1-4685-b999-86eaa9241abb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2263931880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2263931880
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.646140725
Short name T166
Test name
Test status
Simulation time 11540683330 ps
CPU time 96.49 seconds
Started Aug 02 06:45:35 PM PDT 24
Finished Aug 02 06:47:12 PM PDT 24
Peak memory 251748 kb
Host smart-cd5a72df-61ff-44b9-bff2-ac2694b6fa96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646140725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.646140725
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1653384306
Short name T434
Test name
Test status
Simulation time 6858636693 ps
CPU time 20.51 seconds
Started Aug 02 06:45:33 PM PDT 24
Finished Aug 02 06:45:54 PM PDT 24
Peak memory 216808 kb
Host smart-3e240ae7-d585-4c24-b7d7-d04c6a1372fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653384306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1653384306
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.4023311296
Short name T500
Test name
Test status
Simulation time 22172237 ps
CPU time 0.7 seconds
Started Aug 02 06:45:28 PM PDT 24
Finished Aug 02 06:45:29 PM PDT 24
Peak memory 206096 kb
Host smart-51733d17-a76f-4dbb-99fa-1a46b2e32e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023311296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4023311296
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.863177314
Short name T441
Test name
Test status
Simulation time 33250963 ps
CPU time 0.72 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:45:35 PM PDT 24
Peak memory 205164 kb
Host smart-22b30e18-3479-4cf4-b7f5-a44c5846200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863177314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.863177314
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3129840556
Short name T499
Test name
Test status
Simulation time 36886909 ps
CPU time 0.75 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:45:40 PM PDT 24
Peak memory 206360 kb
Host smart-8d02b3ab-158b-4335-b5e9-ce0c6e8a4e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129840556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3129840556
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.968098394
Short name T639
Test name
Test status
Simulation time 35971185908 ps
CPU time 33.64 seconds
Started Aug 02 06:45:31 PM PDT 24
Finished Aug 02 06:46:04 PM PDT 24
Peak memory 240476 kb
Host smart-d41a1ecb-6308-436f-989d-288fdf8e5242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968098394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.968098394
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.364017480
Short name T496
Test name
Test status
Simulation time 12331471 ps
CPU time 0.72 seconds
Started Aug 02 06:45:30 PM PDT 24
Finished Aug 02 06:45:31 PM PDT 24
Peak memory 205260 kb
Host smart-efdb70d7-ad10-4c30-9b90-3183938929c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364017480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.364017480
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4275747813
Short name T621
Test name
Test status
Simulation time 1014900904 ps
CPU time 2.7 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:45:37 PM PDT 24
Peak memory 224884 kb
Host smart-2d14f7af-892c-4dc4-8bfc-db1e3d765e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275747813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4275747813
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1741992679
Short name T148
Test name
Test status
Simulation time 68058442 ps
CPU time 0.82 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:45:40 PM PDT 24
Peak memory 207008 kb
Host smart-e472202c-0cfa-4562-b514-aa3f81b0d089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741992679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1741992679
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1364724462
Short name T901
Test name
Test status
Simulation time 90805616554 ps
CPU time 154.46 seconds
Started Aug 02 06:45:35 PM PDT 24
Finished Aug 02 06:48:10 PM PDT 24
Peak memory 249624 kb
Host smart-210730ba-5835-4d44-9012-214e7d30791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364724462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1364724462
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3806256818
Short name T267
Test name
Test status
Simulation time 52028547963 ps
CPU time 132.4 seconds
Started Aug 02 06:45:35 PM PDT 24
Finished Aug 02 06:47:48 PM PDT 24
Peak memory 256876 kb
Host smart-2ca9b189-3bd2-415e-8c1f-4775e3055b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806256818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3806256818
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1942737060
Short name T708
Test name
Test status
Simulation time 2324096178 ps
CPU time 17.92 seconds
Started Aug 02 06:45:35 PM PDT 24
Finished Aug 02 06:45:53 PM PDT 24
Peak memory 217752 kb
Host smart-43387415-0c36-4e6a-9739-f01606277757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942737060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1942737060
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2466797489
Short name T159
Test name
Test status
Simulation time 366385688 ps
CPU time 10.53 seconds
Started Aug 02 06:45:29 PM PDT 24
Finished Aug 02 06:45:40 PM PDT 24
Peak memory 233112 kb
Host smart-4cd79d55-0f57-451d-8eef-1d699b650010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466797489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2466797489
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.4281649396
Short name T107
Test name
Test status
Simulation time 8741914507 ps
CPU time 36.73 seconds
Started Aug 02 06:45:33 PM PDT 24
Finished Aug 02 06:46:09 PM PDT 24
Peak memory 252556 kb
Host smart-a8f151d6-ee80-466f-a86a-ba3730786ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281649396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.4281649396
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2105924256
Short name T191
Test name
Test status
Simulation time 1868049331 ps
CPU time 13.56 seconds
Started Aug 02 06:45:33 PM PDT 24
Finished Aug 02 06:45:47 PM PDT 24
Peak memory 233152 kb
Host smart-5dba0035-65eb-4dd0-8e7a-c46888c2c9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105924256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2105924256
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4063765914
Short name T207
Test name
Test status
Simulation time 15296586921 ps
CPU time 51.88 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:46:26 PM PDT 24
Peak memory 224960 kb
Host smart-b38f2fae-9361-4768-9476-2ad115d6915d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063765914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4063765914
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.886940287
Short name T440
Test name
Test status
Simulation time 1712493214 ps
CPU time 4.46 seconds
Started Aug 02 06:45:30 PM PDT 24
Finished Aug 02 06:45:34 PM PDT 24
Peak memory 233124 kb
Host smart-f85096e8-3438-43ad-8d04-73466a72845d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886940287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.886940287
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1160842727
Short name T241
Test name
Test status
Simulation time 2602824831 ps
CPU time 6.26 seconds
Started Aug 02 06:45:33 PM PDT 24
Finished Aug 02 06:45:40 PM PDT 24
Peak memory 224944 kb
Host smart-1e4c9f9f-654e-4144-964e-c890e7691be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160842727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1160842727
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.459340709
Short name T931
Test name
Test status
Simulation time 295608018 ps
CPU time 4.88 seconds
Started Aug 02 06:45:31 PM PDT 24
Finished Aug 02 06:45:36 PM PDT 24
Peak memory 220472 kb
Host smart-b753b905-91fd-4e9d-a0c3-f10742bacfea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=459340709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.459340709
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2585954133
Short name T534
Test name
Test status
Simulation time 1679406230 ps
CPU time 9.4 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:45:49 PM PDT 24
Peak memory 216700 kb
Host smart-c4562e33-5230-4f85-9d0f-c6833fa6c7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585954133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2585954133
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3947248848
Short name T762
Test name
Test status
Simulation time 23753197172 ps
CPU time 16.44 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:45:50 PM PDT 24
Peak memory 217788 kb
Host smart-fba1d85c-26f8-4211-b891-9fc48c22174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947248848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3947248848
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3527862093
Short name T523
Test name
Test status
Simulation time 44899082 ps
CPU time 1.16 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:45:40 PM PDT 24
Peak memory 208488 kb
Host smart-66c663a6-3cb3-4b5a-a1fc-fee782685973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527862093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3527862093
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3690673032
Short name T359
Test name
Test status
Simulation time 166656479 ps
CPU time 0.83 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:45:40 PM PDT 24
Peak memory 206320 kb
Host smart-0b069592-3d1f-43ec-9066-402348166860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690673032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3690673032
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3012475407
Short name T600
Test name
Test status
Simulation time 30454004055 ps
CPU time 18.07 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:45:52 PM PDT 24
Peak memory 239660 kb
Host smart-8f1d6eee-7ab5-4dd0-bfea-155f65c9c730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012475407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3012475407
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1883438186
Short name T486
Test name
Test status
Simulation time 49595409 ps
CPU time 0.73 seconds
Started Aug 02 06:45:54 PM PDT 24
Finished Aug 02 06:45:55 PM PDT 24
Peak memory 205900 kb
Host smart-46b8b8a7-ff6b-4e35-a566-e00cabe6be89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883438186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1883438186
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1028729741
Short name T186
Test name
Test status
Simulation time 3969878522 ps
CPU time 8.48 seconds
Started Aug 02 06:45:38 PM PDT 24
Finished Aug 02 06:45:46 PM PDT 24
Peak memory 224960 kb
Host smart-38a44c7f-bb97-4e44-a161-d7a710c0d41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028729741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1028729741
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2116958532
Short name T511
Test name
Test status
Simulation time 16407525 ps
CPU time 0.75 seconds
Started Aug 02 06:45:35 PM PDT 24
Finished Aug 02 06:45:36 PM PDT 24
Peak memory 206976 kb
Host smart-3ce7143c-f059-44ee-9093-d08e7e8876ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116958532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2116958532
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.586078179
Short name T894
Test name
Test status
Simulation time 37008324148 ps
CPU time 272.9 seconds
Started Aug 02 06:45:40 PM PDT 24
Finished Aug 02 06:50:13 PM PDT 24
Peak memory 264600 kb
Host smart-f2c70a59-7477-46b3-a7e8-cce4ff103546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586078179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.586078179
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1683988
Short name T205
Test name
Test status
Simulation time 4191548713 ps
CPU time 49.55 seconds
Started Aug 02 06:45:37 PM PDT 24
Finished Aug 02 06:46:26 PM PDT 24
Peak memory 249996 kb
Host smart-62e9f5ea-10c0-4e85-a42d-432cca2caa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1683988
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1926823232
Short name T286
Test name
Test status
Simulation time 34749885740 ps
CPU time 63.2 seconds
Started Aug 02 06:45:36 PM PDT 24
Finished Aug 02 06:46:40 PM PDT 24
Peak memory 257112 kb
Host smart-e3693967-e1ac-46f6-8cc1-30ba8a6b2412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926823232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1926823232
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3592020905
Short name T484
Test name
Test status
Simulation time 1076378916 ps
CPU time 7.58 seconds
Started Aug 02 06:45:37 PM PDT 24
Finished Aug 02 06:45:45 PM PDT 24
Peak memory 233108 kb
Host smart-4fcb6abe-005a-4606-ada1-4860a6cf2041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592020905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3592020905
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.366797481
Short name T208
Test name
Test status
Simulation time 5218702288 ps
CPU time 22.03 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:46:11 PM PDT 24
Peak memory 233212 kb
Host smart-da91f45a-2f31-4eec-b8d4-5c226335164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366797481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.366797481
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2787855799
Short name T255
Test name
Test status
Simulation time 4536337561 ps
CPU time 26.71 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:33 PM PDT 24
Peak memory 239184 kb
Host smart-ed1791fd-e848-4ff7-99f8-5e7270d15161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787855799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2787855799
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3236012673
Short name T535
Test name
Test status
Simulation time 9527150879 ps
CPU time 4.58 seconds
Started Aug 02 06:45:38 PM PDT 24
Finished Aug 02 06:45:43 PM PDT 24
Peak memory 224916 kb
Host smart-9eac9af8-f32b-4a49-884b-03c2e2180e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236012673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3236012673
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2045022872
Short name T247
Test name
Test status
Simulation time 733873809 ps
CPU time 5.93 seconds
Started Aug 02 06:45:40 PM PDT 24
Finished Aug 02 06:45:46 PM PDT 24
Peak memory 240840 kb
Host smart-49f91d25-f572-4bf5-a800-cff613920225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045022872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2045022872
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3500966630
Short name T158
Test name
Test status
Simulation time 316381408 ps
CPU time 4.94 seconds
Started Aug 02 06:45:45 PM PDT 24
Finished Aug 02 06:45:50 PM PDT 24
Peak memory 220608 kb
Host smart-e85c3fce-320a-4748-8880-5c6ae8db89f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3500966630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3500966630
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1760760340
Short name T604
Test name
Test status
Simulation time 95901442628 ps
CPU time 186.05 seconds
Started Aug 02 06:45:40 PM PDT 24
Finished Aug 02 06:48:47 PM PDT 24
Peak memory 249684 kb
Host smart-666dbe0c-3615-43f3-8a60-0a3d9b8f9645
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760760340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1760760340
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1828518913
Short name T861
Test name
Test status
Simulation time 3607324660 ps
CPU time 19.68 seconds
Started Aug 02 06:45:34 PM PDT 24
Finished Aug 02 06:45:54 PM PDT 24
Peak memory 216780 kb
Host smart-e5ab60b6-db29-44ae-80fc-855f511b46f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828518913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1828518913
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1286112750
Short name T776
Test name
Test status
Simulation time 1900468165 ps
CPU time 9.71 seconds
Started Aug 02 06:45:40 PM PDT 24
Finished Aug 02 06:45:50 PM PDT 24
Peak memory 216640 kb
Host smart-fb24e338-f6f6-4a8b-9e5f-68d00fe15899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286112750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1286112750
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4094058679
Short name T767
Test name
Test status
Simulation time 48797794 ps
CPU time 0.81 seconds
Started Aug 02 06:45:37 PM PDT 24
Finished Aug 02 06:45:38 PM PDT 24
Peak memory 206424 kb
Host smart-af19c210-ecd1-43be-b85f-8613e6fb08fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094058679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4094058679
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3735250702
Short name T862
Test name
Test status
Simulation time 15936020 ps
CPU time 0.75 seconds
Started Aug 02 06:45:35 PM PDT 24
Finished Aug 02 06:45:36 PM PDT 24
Peak memory 206352 kb
Host smart-81adef06-6368-44a2-8af2-d4c0b2c4d281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735250702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3735250702
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2831617322
Short name T709
Test name
Test status
Simulation time 7274421907 ps
CPU time 26.89 seconds
Started Aug 02 06:45:41 PM PDT 24
Finished Aug 02 06:46:08 PM PDT 24
Peak memory 241100 kb
Host smart-9b2de2ad-4aa1-4f78-b8c0-fe11fad84208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831617322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2831617322
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1233777097
Short name T489
Test name
Test status
Simulation time 22099636 ps
CPU time 0.78 seconds
Started Aug 02 06:45:41 PM PDT 24
Finished Aug 02 06:45:42 PM PDT 24
Peak memory 206156 kb
Host smart-ae38dcb8-9982-41ea-a8c0-2d60f1d31d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233777097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1233777097
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2686188080
Short name T626
Test name
Test status
Simulation time 555420103 ps
CPU time 4.24 seconds
Started Aug 02 06:45:37 PM PDT 24
Finished Aug 02 06:45:42 PM PDT 24
Peak memory 233056 kb
Host smart-0def8cf4-cb5e-4992-b952-e3d447bb1c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686188080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2686188080
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3042640353
Short name T791
Test name
Test status
Simulation time 19230998 ps
CPU time 0.76 seconds
Started Aug 02 06:45:38 PM PDT 24
Finished Aug 02 06:45:39 PM PDT 24
Peak memory 207316 kb
Host smart-b6518c40-ebca-4fe2-add1-7838e6127646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042640353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3042640353
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.858774564
Short name T25
Test name
Test status
Simulation time 16627180820 ps
CPU time 44.11 seconds
Started Aug 02 06:45:42 PM PDT 24
Finished Aug 02 06:46:26 PM PDT 24
Peak memory 241408 kb
Host smart-c332cb4b-87ef-418e-beb5-8b69c35ee667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858774564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.858774564
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4077866029
Short name T904
Test name
Test status
Simulation time 7418814242 ps
CPU time 118.28 seconds
Started Aug 02 06:45:36 PM PDT 24
Finished Aug 02 06:47:35 PM PDT 24
Peak memory 252744 kb
Host smart-83c587be-3f00-4beb-b17d-c59bcef3a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077866029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4077866029
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1322387461
Short name T521
Test name
Test status
Simulation time 381788649 ps
CPU time 3.2 seconds
Started Aug 02 06:45:56 PM PDT 24
Finished Aug 02 06:45:59 PM PDT 24
Peak memory 224972 kb
Host smart-9ee8bad1-88e6-4dcc-8c7f-4e7b3340b6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322387461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1322387461
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3613184247
Short name T229
Test name
Test status
Simulation time 1240664061 ps
CPU time 24.87 seconds
Started Aug 02 06:45:42 PM PDT 24
Finished Aug 02 06:46:07 PM PDT 24
Peak memory 233172 kb
Host smart-f87e0708-06b7-4afd-9d1b-7805e1644ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613184247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3613184247
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2466466725
Short name T465
Test name
Test status
Simulation time 648952611 ps
CPU time 3.42 seconds
Started Aug 02 06:45:41 PM PDT 24
Finished Aug 02 06:45:44 PM PDT 24
Peak memory 233132 kb
Host smart-722c1bbe-5957-459c-a68b-7384b660f2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466466725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2466466725
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.694421918
Short name T814
Test name
Test status
Simulation time 20274200073 ps
CPU time 55.01 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:46:44 PM PDT 24
Peak memory 233224 kb
Host smart-f250d45a-e7ce-48ad-9769-9929b371f358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694421918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.694421918
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1651566698
Short name T275
Test name
Test status
Simulation time 996601016 ps
CPU time 5.09 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:45:45 PM PDT 24
Peak memory 224952 kb
Host smart-514d88c0-6ede-4b92-9d39-997b6d80b299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651566698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1651566698
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4047200055
Short name T627
Test name
Test status
Simulation time 2900834483 ps
CPU time 5.53 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:45:54 PM PDT 24
Peak memory 224952 kb
Host smart-ce95f789-9660-4672-8b93-96304e3f381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047200055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4047200055
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.931669984
Short name T852
Test name
Test status
Simulation time 3039545029 ps
CPU time 12.12 seconds
Started Aug 02 06:45:38 PM PDT 24
Finished Aug 02 06:45:50 PM PDT 24
Peak memory 221104 kb
Host smart-d1777b46-53d9-4c47-b26b-683a1621b698
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=931669984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.931669984
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2866842230
Short name T422
Test name
Test status
Simulation time 84438680964 ps
CPU time 421.65 seconds
Started Aug 02 06:45:40 PM PDT 24
Finished Aug 02 06:52:42 PM PDT 24
Peak memory 266104 kb
Host smart-5f911b43-883f-40cc-a54f-e921b9fef558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866842230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2866842230
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.681204484
Short name T576
Test name
Test status
Simulation time 3780440057 ps
CPU time 14.21 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:46:02 PM PDT 24
Peak memory 220520 kb
Host smart-3a01ca61-5547-4559-b543-007c9ca06ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681204484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.681204484
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2364458576
Short name T102
Test name
Test status
Simulation time 5992978250 ps
CPU time 9.46 seconds
Started Aug 02 06:45:42 PM PDT 24
Finished Aug 02 06:45:51 PM PDT 24
Peak memory 216684 kb
Host smart-d14354ca-b4dc-41bb-9e01-5043963225f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364458576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2364458576
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.704703692
Short name T724
Test name
Test status
Simulation time 107407807 ps
CPU time 1.72 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:45:51 PM PDT 24
Peak memory 216720 kb
Host smart-691b3bc0-d2ac-4888-a511-eeed97ac9671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704703692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.704703692
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3990428828
Short name T597
Test name
Test status
Simulation time 276714166 ps
CPU time 0.85 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:45:49 PM PDT 24
Peak memory 206364 kb
Host smart-b7cf6835-1dc6-48fe-999b-1340b8aa9603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990428828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3990428828
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1083764128
Short name T839
Test name
Test status
Simulation time 3001259417 ps
CPU time 7.96 seconds
Started Aug 02 06:45:36 PM PDT 24
Finished Aug 02 06:45:44 PM PDT 24
Peak memory 233136 kb
Host smart-1491c863-f6f5-4c31-b061-dc7fa603b75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083764128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1083764128
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3295196479
Short name T596
Test name
Test status
Simulation time 14893193 ps
CPU time 0.75 seconds
Started Aug 02 06:45:47 PM PDT 24
Finished Aug 02 06:45:48 PM PDT 24
Peak memory 205300 kb
Host smart-7dd8694a-88f8-45a0-a6b8-b3af070b6885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295196479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3295196479
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2761967595
Short name T451
Test name
Test status
Simulation time 1420565422 ps
CPU time 10.2 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:46:00 PM PDT 24
Peak memory 225012 kb
Host smart-1859f42f-621b-4210-bdfe-62fcdbe961fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761967595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2761967595
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.243947591
Short name T630
Test name
Test status
Simulation time 17368538 ps
CPU time 0.83 seconds
Started Aug 02 06:45:40 PM PDT 24
Finished Aug 02 06:45:41 PM PDT 24
Peak memory 206968 kb
Host smart-e0ddd807-6846-4c33-82d2-22da9f37d64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243947591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.243947591
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2557484900
Short name T548
Test name
Test status
Simulation time 13339138917 ps
CPU time 121.02 seconds
Started Aug 02 06:45:50 PM PDT 24
Finished Aug 02 06:47:51 PM PDT 24
Peak memory 252600 kb
Host smart-b8eb78c0-397c-4f3c-a623-a7ef1a2719ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557484900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2557484900
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1827806786
Short name T772
Test name
Test status
Simulation time 5025645054 ps
CPU time 71.99 seconds
Started Aug 02 06:45:55 PM PDT 24
Finished Aug 02 06:47:07 PM PDT 24
Peak memory 263748 kb
Host smart-7c4597b4-af0e-41eb-829a-2506c9465052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827806786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1827806786
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3939163899
Short name T301
Test name
Test status
Simulation time 329178117 ps
CPU time 9.2 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:45:58 PM PDT 24
Peak memory 233192 kb
Host smart-fe2d647e-bbf5-45dc-a07b-b992af7ac61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939163899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3939163899
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.172423531
Short name T314
Test name
Test status
Simulation time 1701747005 ps
CPU time 19.63 seconds
Started Aug 02 06:45:46 PM PDT 24
Finished Aug 02 06:46:05 PM PDT 24
Peak memory 241396 kb
Host smart-cf2ceb7c-61c2-40f5-92a6-c70e94937c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172423531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.172423531
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2603034494
Short name T925
Test name
Test status
Simulation time 2388375421 ps
CPU time 17.95 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:46:06 PM PDT 24
Peak memory 225040 kb
Host smart-e8dec5bf-913d-4a16-a363-be7ef50cedb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603034494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2603034494
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1586733598
Short name T924
Test name
Test status
Simulation time 1664659575 ps
CPU time 8.28 seconds
Started Aug 02 06:45:38 PM PDT 24
Finished Aug 02 06:45:47 PM PDT 24
Peak memory 233148 kb
Host smart-df28f3e2-5503-483e-a95b-c727400139c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586733598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1586733598
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2774030239
Short name T376
Test name
Test status
Simulation time 8395153870 ps
CPU time 8.1 seconds
Started Aug 02 06:45:37 PM PDT 24
Finished Aug 02 06:45:45 PM PDT 24
Peak memory 233204 kb
Host smart-dd677f5d-4444-4565-8b97-05f1299e656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774030239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2774030239
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.688951986
Short name T745
Test name
Test status
Simulation time 382934877 ps
CPU time 3.42 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:45:53 PM PDT 24
Peak memory 233184 kb
Host smart-3d62c3f9-e5f7-489d-8b2a-d17ee796a2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688951986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.688951986
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3832611994
Short name T231
Test name
Test status
Simulation time 8809811709 ps
CPU time 27.81 seconds
Started Aug 02 06:45:35 PM PDT 24
Finished Aug 02 06:46:03 PM PDT 24
Peak memory 241876 kb
Host smart-5912e0b6-e0ea-44be-89ac-e84331db8308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832611994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3832611994
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4293796736
Short name T397
Test name
Test status
Simulation time 2577471412 ps
CPU time 9.6 seconds
Started Aug 02 06:45:46 PM PDT 24
Finished Aug 02 06:45:56 PM PDT 24
Peak memory 219624 kb
Host smart-5809a642-2e0f-40f1-a259-a5d53879ee72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4293796736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4293796736
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.454436858
Short name T169
Test name
Test status
Simulation time 6021470623 ps
CPU time 79.02 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:47:09 PM PDT 24
Peak memory 256936 kb
Host smart-5bc3f9f5-d061-4524-8c3c-483f8e9f278b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454436858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.454436858
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1400917095
Short name T784
Test name
Test status
Simulation time 690190085 ps
CPU time 4.94 seconds
Started Aug 02 06:45:55 PM PDT 24
Finished Aug 02 06:46:00 PM PDT 24
Peak memory 216720 kb
Host smart-84ca6967-399c-49ee-b7c6-076ac93c0da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400917095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1400917095
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.34009689
Short name T491
Test name
Test status
Simulation time 2238345040 ps
CPU time 8.29 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:45:48 PM PDT 24
Peak memory 216748 kb
Host smart-4b98b8a5-18f4-4002-b9d8-1b9137674bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34009689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.34009689
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1654955934
Short name T327
Test name
Test status
Simulation time 34268459 ps
CPU time 2.06 seconds
Started Aug 02 06:45:39 PM PDT 24
Finished Aug 02 06:45:41 PM PDT 24
Peak memory 216680 kb
Host smart-8ca27bb4-20ac-452a-893e-95456985e566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654955934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1654955934
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.848545773
Short name T618
Test name
Test status
Simulation time 40700985 ps
CPU time 0.79 seconds
Started Aug 02 06:45:37 PM PDT 24
Finished Aug 02 06:45:38 PM PDT 24
Peak memory 206300 kb
Host smart-c2c4d409-b0d9-4152-86a0-16e95d53fc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848545773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.848545773
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2562936976
Short name T395
Test name
Test status
Simulation time 3072980882 ps
CPU time 5.67 seconds
Started Aug 02 06:45:46 PM PDT 24
Finished Aug 02 06:45:52 PM PDT 24
Peak memory 225072 kb
Host smart-2b4f286e-0041-4a2c-9bfd-d34b28745096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562936976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2562936976
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4112613782
Short name T565
Test name
Test status
Simulation time 13233751 ps
CPU time 0.7 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:14 PM PDT 24
Peak memory 205280 kb
Host smart-32ec9e7a-10a1-4ef7-aed5-342436ede698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112613782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
112613782
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.503657571
Short name T827
Test name
Test status
Simulation time 1321921319 ps
CPU time 15.25 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:29 PM PDT 24
Peak memory 224904 kb
Host smart-638f1740-dba5-471b-874a-fa8f9d9486b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503657571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.503657571
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2678369014
Short name T876
Test name
Test status
Simulation time 26323205 ps
CPU time 0.78 seconds
Started Aug 02 06:44:09 PM PDT 24
Finished Aug 02 06:44:10 PM PDT 24
Peak memory 207016 kb
Host smart-1483712d-d2ed-4826-8f79-0eb9188b00c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678369014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2678369014
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.878412161
Short name T391
Test name
Test status
Simulation time 2368113270 ps
CPU time 51.56 seconds
Started Aug 02 06:44:19 PM PDT 24
Finished Aug 02 06:45:10 PM PDT 24
Peak memory 256796 kb
Host smart-7e34cecf-e087-429b-b1b2-9545f3f3e3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878412161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.878412161
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3969984886
Short name T780
Test name
Test status
Simulation time 30189953496 ps
CPU time 319.66 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:49:33 PM PDT 24
Peak memory 249704 kb
Host smart-1505fd4e-b69b-4ca8-a128-10fa55372c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969984886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3969984886
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.237518952
Short name T48
Test name
Test status
Simulation time 53273843564 ps
CPU time 276.05 seconds
Started Aug 02 06:44:16 PM PDT 24
Finished Aug 02 06:48:52 PM PDT 24
Peak memory 268672 kb
Host smart-c2f70697-0373-4cb8-ae39-5e6107538736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237518952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
237518952
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1811226378
Short name T318
Test name
Test status
Simulation time 930622600 ps
CPU time 6.59 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:20 PM PDT 24
Peak memory 241356 kb
Host smart-213f8b47-01fc-4ae9-a875-c9db2b999be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811226378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1811226378
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.955866669
Short name T185
Test name
Test status
Simulation time 323647025032 ps
CPU time 230.71 seconds
Started Aug 02 06:44:14 PM PDT 24
Finished Aug 02 06:48:05 PM PDT 24
Peak memory 255424 kb
Host smart-96269b57-065c-4f4c-b9fc-8e8fb057de2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955866669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
955866669
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3589649134
Short name T189
Test name
Test status
Simulation time 335452207 ps
CPU time 5.03 seconds
Started Aug 02 06:44:14 PM PDT 24
Finished Aug 02 06:44:19 PM PDT 24
Peak memory 224912 kb
Host smart-7c06a031-699e-4604-8b2e-8c32539f3aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589649134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3589649134
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1405539150
Short name T453
Test name
Test status
Simulation time 8930891998 ps
CPU time 39.52 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:53 PM PDT 24
Peak memory 241212 kb
Host smart-22146e58-cebb-44b1-abc2-d8a3752cfc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405539150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1405539150
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.173903091
Short name T828
Test name
Test status
Simulation time 149895724 ps
CPU time 3.81 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:44:18 PM PDT 24
Peak memory 233176 kb
Host smart-c81dad18-96ed-4b38-84ac-261dd135781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173903091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
173903091
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.523409830
Short name T245
Test name
Test status
Simulation time 911075298 ps
CPU time 3.56 seconds
Started Aug 02 06:44:11 PM PDT 24
Finished Aug 02 06:44:15 PM PDT 24
Peak memory 233148 kb
Host smart-923ecbfe-9c72-4875-bd92-26a06a14c9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523409830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.523409830
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.347750754
Short name T595
Test name
Test status
Simulation time 2792872653 ps
CPU time 9.3 seconds
Started Aug 02 06:44:18 PM PDT 24
Finished Aug 02 06:44:27 PM PDT 24
Peak memory 219856 kb
Host smart-ea37a30c-82e6-4916-b965-ec89100cc9d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=347750754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.347750754
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2308129856
Short name T82
Test name
Test status
Simulation time 81532763 ps
CPU time 1.26 seconds
Started Aug 02 06:44:14 PM PDT 24
Finished Aug 02 06:44:15 PM PDT 24
Peak memory 236896 kb
Host smart-e7139a85-029f-43cb-819b-0e2576acbde2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308129856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2308129856
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3688576878
Short name T855
Test name
Test status
Simulation time 22094660323 ps
CPU time 126.72 seconds
Started Aug 02 06:44:13 PM PDT 24
Finished Aug 02 06:46:21 PM PDT 24
Peak memory 257876 kb
Host smart-2e31a788-3fed-4e5f-8a85-174aca13a31d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688576878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3688576878
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.157990788
Short name T323
Test name
Test status
Simulation time 37299177736 ps
CPU time 51.58 seconds
Started Aug 02 06:44:10 PM PDT 24
Finished Aug 02 06:45:01 PM PDT 24
Peak memory 216748 kb
Host smart-651d0d45-a5c9-4dfa-982f-5d95e5a46490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157990788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.157990788
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.558554940
Short name T978
Test name
Test status
Simulation time 831454475 ps
CPU time 4.52 seconds
Started Aug 02 06:44:15 PM PDT 24
Finished Aug 02 06:44:19 PM PDT 24
Peak memory 216728 kb
Host smart-fcca03af-983b-4ff4-9ef2-0249801872fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558554940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.558554940
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3666483281
Short name T95
Test name
Test status
Simulation time 12979326 ps
CPU time 0.75 seconds
Started Aug 02 06:44:15 PM PDT 24
Finished Aug 02 06:44:16 PM PDT 24
Peak memory 206084 kb
Host smart-a4b1ced3-35d5-459a-90cc-01133b72700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666483281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3666483281
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.4223099873
Short name T547
Test name
Test status
Simulation time 24879695 ps
CPU time 0.69 seconds
Started Aug 02 06:44:10 PM PDT 24
Finished Aug 02 06:44:11 PM PDT 24
Peak memory 206036 kb
Host smart-007c59bd-39d6-4bfe-bfc5-7dfed7492aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223099873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.4223099873
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.726811118
Short name T965
Test name
Test status
Simulation time 795952944 ps
CPU time 7.99 seconds
Started Aug 02 06:44:14 PM PDT 24
Finished Aug 02 06:44:22 PM PDT 24
Peak memory 249776 kb
Host smart-9e69ce1d-e605-48bc-a024-f36960b08a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726811118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.726811118
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3596733008
Short name T723
Test name
Test status
Simulation time 150846248 ps
CPU time 0.69 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:45:50 PM PDT 24
Peak memory 206136 kb
Host smart-fe035f02-db1c-4f65-93d5-8e1767aa2a0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596733008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3596733008
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2429380321
Short name T921
Test name
Test status
Simulation time 133330578 ps
CPU time 2.55 seconds
Started Aug 02 06:45:50 PM PDT 24
Finished Aug 02 06:45:53 PM PDT 24
Peak memory 225008 kb
Host smart-67debfa9-4316-421c-9d4b-899ae68072c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429380321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2429380321
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2330785844
Short name T726
Test name
Test status
Simulation time 15525563 ps
CPU time 0.8 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:45:49 PM PDT 24
Peak memory 207000 kb
Host smart-d334bfff-7d5b-4abe-a568-0cc99dd496a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330785844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2330785844
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2964185917
Short name T877
Test name
Test status
Simulation time 2642586033 ps
CPU time 68.05 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:46:57 PM PDT 24
Peak memory 257788 kb
Host smart-cb039a9d-5329-49fc-b6fe-58782cc49678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964185917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2964185917
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1513291823
Short name T304
Test name
Test status
Simulation time 72112581743 ps
CPU time 717.28 seconds
Started Aug 02 06:45:55 PM PDT 24
Finished Aug 02 06:57:52 PM PDT 24
Peak memory 264224 kb
Host smart-70cfdf44-d79c-4677-aac7-89fa057ce928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513291823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1513291823
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2174744063
Short name T717
Test name
Test status
Simulation time 116755377 ps
CPU time 3.93 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:45:52 PM PDT 24
Peak memory 233164 kb
Host smart-634f5eab-ece6-4ce5-811b-491cad956610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174744063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2174744063
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3387582523
Short name T785
Test name
Test status
Simulation time 846232424 ps
CPU time 4.34 seconds
Started Aug 02 06:45:47 PM PDT 24
Finished Aug 02 06:45:51 PM PDT 24
Peak memory 233152 kb
Host smart-635168f6-a98b-4c2b-b3fa-3bcfc9ab7d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387582523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3387582523
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.557538928
Short name T474
Test name
Test status
Simulation time 1176038237 ps
CPU time 20.91 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:46:10 PM PDT 24
Peak memory 251612 kb
Host smart-49589eb4-f7c6-492b-a561-704a9b52376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557538928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.557538928
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4122793728
Short name T298
Test name
Test status
Simulation time 441718506 ps
CPU time 7 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:45:56 PM PDT 24
Peak memory 241336 kb
Host smart-ddb1cc7a-3ec8-4832-b9fa-e28c45f60544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122793728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4122793728
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1766744432
Short name T68
Test name
Test status
Simulation time 445124408 ps
CPU time 7.56 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:45:56 PM PDT 24
Peak memory 233200 kb
Host smart-b874c93b-e13f-4f2c-b934-706228ebdb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766744432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1766744432
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4006161059
Short name T371
Test name
Test status
Simulation time 1431788300 ps
CPU time 16.91 seconds
Started Aug 02 06:45:47 PM PDT 24
Finished Aug 02 06:46:04 PM PDT 24
Peak memory 223136 kb
Host smart-9362ad40-aba2-4342-963f-9aa7fb7d5ec7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4006161059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4006161059
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3667037410
Short name T20
Test name
Test status
Simulation time 67456337 ps
CPU time 0.88 seconds
Started Aug 02 06:45:47 PM PDT 24
Finished Aug 02 06:45:48 PM PDT 24
Peak memory 206304 kb
Host smart-3120f16b-78dd-4e62-a18e-60791a0aed61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667037410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3667037410
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1265221505
Short name T319
Test name
Test status
Simulation time 3981867807 ps
CPU time 16.85 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:46:06 PM PDT 24
Peak memory 216724 kb
Host smart-4100b69c-3768-479c-bf48-a54ea93ba1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265221505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1265221505
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3185570762
Short name T543
Test name
Test status
Simulation time 999455910 ps
CPU time 6.67 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:45:56 PM PDT 24
Peak memory 216644 kb
Host smart-c69127fd-d25a-4364-b3c7-7676a32488da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185570762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3185570762
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2849409506
Short name T579
Test name
Test status
Simulation time 45606065 ps
CPU time 0.77 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:45:49 PM PDT 24
Peak memory 206396 kb
Host smart-8acfe7c7-91d2-4792-a414-669e2e7b2915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849409506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2849409506
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1684268401
Short name T469
Test name
Test status
Simulation time 149234453 ps
CPU time 0.93 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:45:49 PM PDT 24
Peak memory 206376 kb
Host smart-5f8969f4-2c2c-4505-b220-c750a8947a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684268401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1684268401
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1481816000
Short name T872
Test name
Test status
Simulation time 3248454971 ps
CPU time 7.52 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:45:57 PM PDT 24
Peak memory 233224 kb
Host smart-ffd54207-acac-43d0-9a7b-6520687b45e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481816000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1481816000
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4055983135
Short name T343
Test name
Test status
Simulation time 27242490 ps
CPU time 0.74 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:45:57 PM PDT 24
Peak memory 205264 kb
Host smart-153acf3e-91b8-4549-b75a-ccf2be8f12a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055983135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4055983135
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1863145625
Short name T591
Test name
Test status
Simulation time 92048563 ps
CPU time 3.26 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:45:53 PM PDT 24
Peak memory 233188 kb
Host smart-feecfe7b-68ba-4c52-a6fb-991f4e1bd049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863145625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1863145625
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.928217133
Short name T765
Test name
Test status
Simulation time 17261391 ps
CPU time 0.81 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:45:50 PM PDT 24
Peak memory 207008 kb
Host smart-d8d4d3d0-bbbd-46ee-836f-c200088100de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928217133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.928217133
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2522896469
Short name T40
Test name
Test status
Simulation time 13884178903 ps
CPU time 171.84 seconds
Started Aug 02 06:45:56 PM PDT 24
Finished Aug 02 06:48:48 PM PDT 24
Peak memory 253860 kb
Host smart-9da1860c-85e1-426b-accf-6164e2377bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522896469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2522896469
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3955501123
Short name T488
Test name
Test status
Simulation time 9282502920 ps
CPU time 47.3 seconds
Started Aug 02 06:45:58 PM PDT 24
Finished Aug 02 06:46:46 PM PDT 24
Peak memory 249664 kb
Host smart-f98f69de-ad19-4cad-8cab-0d6fa131fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955501123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3955501123
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.807020269
Short name T749
Test name
Test status
Simulation time 35906790921 ps
CPU time 53.38 seconds
Started Aug 02 06:45:47 PM PDT 24
Finished Aug 02 06:46:41 PM PDT 24
Peak memory 240912 kb
Host smart-89d368e0-ed28-478f-b171-11a4b6b1d653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807020269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.807020269
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1304927592
Short name T612
Test name
Test status
Simulation time 11298273056 ps
CPU time 90.68 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:47:28 PM PDT 24
Peak memory 249748 kb
Host smart-02221475-f789-4ada-8904-aaf54abaec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304927592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1304927592
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2618407735
Short name T929
Test name
Test status
Simulation time 898974895 ps
CPU time 6.71 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:45:55 PM PDT 24
Peak memory 233092 kb
Host smart-a3a3db32-6c14-4e11-a072-4e23222178ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618407735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2618407735
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3032600988
Short name T629
Test name
Test status
Simulation time 75231210 ps
CPU time 3.28 seconds
Started Aug 02 06:45:47 PM PDT 24
Finished Aug 02 06:45:50 PM PDT 24
Peak memory 233148 kb
Host smart-a567cf3a-6f20-49f1-b0f8-5fc1a4f0a1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032600988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3032600988
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3841496892
Short name T843
Test name
Test status
Simulation time 112253021 ps
CPU time 2.42 seconds
Started Aug 02 06:45:49 PM PDT 24
Finished Aug 02 06:45:51 PM PDT 24
Peak memory 232836 kb
Host smart-7077d7b5-4145-4129-8b76-a2073b8da610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841496892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3841496892
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.750468760
Short name T967
Test name
Test status
Simulation time 4992137483 ps
CPU time 14.35 seconds
Started Aug 02 06:45:45 PM PDT 24
Finished Aug 02 06:46:00 PM PDT 24
Peak memory 239180 kb
Host smart-0e45bc18-b895-4c02-906e-0c7d18b7530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750468760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.750468760
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4014114410
Short name T961
Test name
Test status
Simulation time 1112512228 ps
CPU time 14.16 seconds
Started Aug 02 06:46:00 PM PDT 24
Finished Aug 02 06:46:15 PM PDT 24
Peak memory 219764 kb
Host smart-2e12223f-621d-4e07-931b-2e91d80fe296
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4014114410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4014114410
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1042397237
Short name T945
Test name
Test status
Simulation time 60695073 ps
CPU time 1.12 seconds
Started Aug 02 06:45:56 PM PDT 24
Finished Aug 02 06:45:57 PM PDT 24
Peak memory 207396 kb
Host smart-4a6562ee-e0b7-4400-b514-4641cfcfedea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042397237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1042397237
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1533481071
Short name T320
Test name
Test status
Simulation time 1683287089 ps
CPU time 16.94 seconds
Started Aug 02 06:45:47 PM PDT 24
Finished Aug 02 06:46:04 PM PDT 24
Peak memory 216964 kb
Host smart-5f940098-6fcf-4785-8772-0de46f312fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533481071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1533481071
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2301603341
Short name T508
Test name
Test status
Simulation time 1030540752 ps
CPU time 7.22 seconds
Started Aug 02 06:45:55 PM PDT 24
Finished Aug 02 06:46:02 PM PDT 24
Peak memory 216720 kb
Host smart-d2de0a96-f3f7-4fc4-92a0-5ee9f2c48138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301603341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2301603341
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3605696856
Short name T326
Test name
Test status
Simulation time 186737208 ps
CPU time 3.67 seconds
Started Aug 02 06:45:51 PM PDT 24
Finished Aug 02 06:45:55 PM PDT 24
Peak memory 216636 kb
Host smart-079fe295-1a77-44e4-9240-633e48a81b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605696856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3605696856
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1395492227
Short name T413
Test name
Test status
Simulation time 197533706 ps
CPU time 0.86 seconds
Started Aug 02 06:45:46 PM PDT 24
Finished Aug 02 06:45:48 PM PDT 24
Peak memory 206328 kb
Host smart-8b28faf6-a864-4aaf-9266-8692eeb31a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395492227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1395492227
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.587512970
Short name T478
Test name
Test status
Simulation time 6225215953 ps
CPU time 7.87 seconds
Started Aug 02 06:45:48 PM PDT 24
Finished Aug 02 06:45:56 PM PDT 24
Peak memory 241308 kb
Host smart-ac25a421-76e7-45e4-92ca-504f01267c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587512970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.587512970
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2415988935
Short name T399
Test name
Test status
Simulation time 129871018 ps
CPU time 0.73 seconds
Started Aug 02 06:46:01 PM PDT 24
Finished Aug 02 06:46:02 PM PDT 24
Peak memory 205224 kb
Host smart-c54ae4ca-de5e-4e03-8faa-83a66d118282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415988935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2415988935
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2110968862
Short name T105
Test name
Test status
Simulation time 1812326282 ps
CPU time 15.65 seconds
Started Aug 02 06:45:54 PM PDT 24
Finished Aug 02 06:46:10 PM PDT 24
Peak memory 233160 kb
Host smart-ea91e6e5-bbb7-46be-becd-90d8d576b1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110968862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2110968862
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.733449778
Short name T766
Test name
Test status
Simulation time 19529900 ps
CPU time 0.75 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:45:58 PM PDT 24
Peak memory 205924 kb
Host smart-b7d34607-d912-430c-b04a-baeb925d700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733449778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.733449778
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.520181155
Short name T588
Test name
Test status
Simulation time 6198618248 ps
CPU time 66.53 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:47:04 PM PDT 24
Peak memory 249684 kb
Host smart-982169f4-7e5c-4068-b372-a355730d3cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520181155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.520181155
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1054408882
Short name T63
Test name
Test status
Simulation time 29309179509 ps
CPU time 162.07 seconds
Started Aug 02 06:45:55 PM PDT 24
Finished Aug 02 06:48:37 PM PDT 24
Peak memory 250104 kb
Host smart-9a2c0dc5-55ff-4009-abc0-3aa9d3fab3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054408882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1054408882
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.453968077
Short name T664
Test name
Test status
Simulation time 385608292 ps
CPU time 7.03 seconds
Started Aug 02 06:45:59 PM PDT 24
Finished Aug 02 06:46:06 PM PDT 24
Peak memory 224920 kb
Host smart-6d5baf4e-c711-4450-901f-816ef9a8d5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453968077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.453968077
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.4178285924
Short name T685
Test name
Test status
Simulation time 10359682683 ps
CPU time 72.91 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:47:10 PM PDT 24
Peak memory 251052 kb
Host smart-32bee900-4e7b-4be4-a92c-0920670c1a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178285924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.4178285924
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1669536614
Short name T458
Test name
Test status
Simulation time 569917990 ps
CPU time 6.02 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:46:03 PM PDT 24
Peak memory 233104 kb
Host smart-0502e97b-3d25-4323-84e2-5b5e2e79c8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669536614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1669536614
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.845502283
Short name T406
Test name
Test status
Simulation time 418032107 ps
CPU time 2.43 seconds
Started Aug 02 06:45:59 PM PDT 24
Finished Aug 02 06:46:02 PM PDT 24
Peak memory 223588 kb
Host smart-2ba0bf11-3b77-4ad9-b3f8-e9111325b565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845502283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.845502283
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.279098794
Short name T927
Test name
Test status
Simulation time 1822971285 ps
CPU time 8.83 seconds
Started Aug 02 06:45:55 PM PDT 24
Finished Aug 02 06:46:04 PM PDT 24
Peak memory 237988 kb
Host smart-bbb7b594-bdfa-4f90-8ea4-38487255ffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279098794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.279098794
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1157747456
Short name T854
Test name
Test status
Simulation time 9086149791 ps
CPU time 10.23 seconds
Started Aug 02 06:46:06 PM PDT 24
Finished Aug 02 06:46:17 PM PDT 24
Peak memory 233180 kb
Host smart-fc35a8ba-25a3-4de1-bb95-9c8413506790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157747456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1157747456
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3258640018
Short name T652
Test name
Test status
Simulation time 2281931285 ps
CPU time 8.59 seconds
Started Aug 02 06:46:02 PM PDT 24
Finished Aug 02 06:46:10 PM PDT 24
Peak memory 220928 kb
Host smart-4145f35d-35c0-473b-b896-c186f43d8a66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3258640018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3258640018
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2392945221
Short name T210
Test name
Test status
Simulation time 41910613528 ps
CPU time 445.93 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:53:23 PM PDT 24
Peak memory 274216 kb
Host smart-c593b1eb-a6f6-49a3-aeb5-35523f719771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392945221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2392945221
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2397066847
Short name T701
Test name
Test status
Simulation time 1175143829 ps
CPU time 8.27 seconds
Started Aug 02 06:45:56 PM PDT 24
Finished Aug 02 06:46:04 PM PDT 24
Peak memory 216768 kb
Host smart-526c33b3-dad3-40e4-9a31-ce5c47e81807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397066847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2397066847
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2934559074
Short name T398
Test name
Test status
Simulation time 13732115 ps
CPU time 0.73 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:45:57 PM PDT 24
Peak memory 206096 kb
Host smart-06653246-fb04-4509-a5cf-a382d3e585c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934559074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2934559074
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3434282551
Short name T674
Test name
Test status
Simulation time 20236928 ps
CPU time 0.71 seconds
Started Aug 02 06:45:56 PM PDT 24
Finished Aug 02 06:45:57 PM PDT 24
Peak memory 205964 kb
Host smart-d3cde77a-5387-4ade-ad87-e44e8e822f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434282551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3434282551
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1090187523
Short name T725
Test name
Test status
Simulation time 74012081 ps
CPU time 0.78 seconds
Started Aug 02 06:46:06 PM PDT 24
Finished Aug 02 06:46:07 PM PDT 24
Peak memory 206324 kb
Host smart-89e547c2-7d51-44cb-a903-65b589ae09f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090187523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1090187523
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3038828933
Short name T67
Test name
Test status
Simulation time 632840833 ps
CPU time 6.71 seconds
Started Aug 02 06:45:58 PM PDT 24
Finished Aug 02 06:46:05 PM PDT 24
Peak memory 236996 kb
Host smart-88b09807-5fae-49fa-918d-af7338393434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038828933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3038828933
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2917876696
Short name T75
Test name
Test status
Simulation time 14718362 ps
CPU time 0.75 seconds
Started Aug 02 06:46:06 PM PDT 24
Finished Aug 02 06:46:06 PM PDT 24
Peak memory 205324 kb
Host smart-57b6f1a7-b21c-4833-962c-4ece219822ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917876696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2917876696
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2549860466
Short name T903
Test name
Test status
Simulation time 6445827963 ps
CPU time 10.01 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:17 PM PDT 24
Peak memory 233108 kb
Host smart-369d5dfb-4c64-4274-832d-395f78a44425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549860466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2549860466
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3165073376
Short name T879
Test name
Test status
Simulation time 60642324 ps
CPU time 0.76 seconds
Started Aug 02 06:45:59 PM PDT 24
Finished Aug 02 06:46:00 PM PDT 24
Peak memory 206020 kb
Host smart-51ade305-a8a9-4ed8-a360-a1c64b0ac73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165073376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3165073376
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3615866301
Short name T368
Test name
Test status
Simulation time 2889751985 ps
CPU time 15.45 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:23 PM PDT 24
Peak memory 237496 kb
Host smart-efe0b424-0bd0-4bde-af0b-a8ef37a4132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615866301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3615866301
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3349119971
Short name T744
Test name
Test status
Simulation time 9465875933 ps
CPU time 46.17 seconds
Started Aug 02 06:46:04 PM PDT 24
Finished Aug 02 06:46:51 PM PDT 24
Peak memory 233292 kb
Host smart-1cb29209-67ff-4fe1-aa84-21471583974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349119971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3349119971
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1648907993
Short name T592
Test name
Test status
Simulation time 6584206678 ps
CPU time 53.17 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:47:00 PM PDT 24
Peak memory 251392 kb
Host smart-3c31bff9-079b-4edd-b897-4cfe70951a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648907993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1648907993
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1574321945
Short name T996
Test name
Test status
Simulation time 235706869 ps
CPU time 5.12 seconds
Started Aug 02 06:46:06 PM PDT 24
Finished Aug 02 06:46:11 PM PDT 24
Peak memory 233468 kb
Host smart-bb661b29-923c-41bf-b0ef-5cd4af9e90bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574321945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1574321945
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1264975008
Short name T818
Test name
Test status
Simulation time 22621604804 ps
CPU time 83.08 seconds
Started Aug 02 06:46:10 PM PDT 24
Finished Aug 02 06:47:34 PM PDT 24
Peak memory 249644 kb
Host smart-d881155c-06c7-405f-97ad-dd885d91094a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264975008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1264975008
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2752801869
Short name T226
Test name
Test status
Simulation time 1351488473 ps
CPU time 16.82 seconds
Started Aug 02 06:45:58 PM PDT 24
Finished Aug 02 06:46:15 PM PDT 24
Peak memory 225024 kb
Host smart-afb6b473-66d7-44bb-981e-e25baea656ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752801869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2752801869
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3635377127
Short name T23
Test name
Test status
Simulation time 7857988734 ps
CPU time 100.74 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:47:38 PM PDT 24
Peak memory 240312 kb
Host smart-81a490df-bb6d-4588-abf8-2b1d3a440f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635377127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3635377127
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.816424037
Short name T713
Test name
Test status
Simulation time 24928391861 ps
CPU time 19.01 seconds
Started Aug 02 06:45:59 PM PDT 24
Finished Aug 02 06:46:18 PM PDT 24
Peak memory 241448 kb
Host smart-e638eccb-5dff-4861-9f5e-b4108f4c526f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816424037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.816424037
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1409737838
Short name T778
Test name
Test status
Simulation time 373220011 ps
CPU time 3.75 seconds
Started Aug 02 06:46:02 PM PDT 24
Finished Aug 02 06:46:06 PM PDT 24
Peak memory 224916 kb
Host smart-ca276e51-c5d7-4f6f-b88e-d7032ba3eb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409737838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1409737838
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.418323193
Short name T501
Test name
Test status
Simulation time 426604680 ps
CPU time 4.13 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:11 PM PDT 24
Peak memory 223528 kb
Host smart-f986664f-efac-44b8-835f-ea6ffb6c5ea1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=418323193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.418323193
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3902951618
Short name T64
Test name
Test status
Simulation time 126147699496 ps
CPU time 424.89 seconds
Started Aug 02 06:46:03 PM PDT 24
Finished Aug 02 06:53:08 PM PDT 24
Peak memory 261680 kb
Host smart-1658b9b2-49e7-4fcf-b640-ba127065135b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902951618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3902951618
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.461087456
Short name T41
Test name
Test status
Simulation time 4267047341 ps
CPU time 26.64 seconds
Started Aug 02 06:45:56 PM PDT 24
Finished Aug 02 06:46:23 PM PDT 24
Peak memory 216680 kb
Host smart-559dbea1-1d9b-48f8-9b60-f8716cf64e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461087456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.461087456
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4039012874
Short name T449
Test name
Test status
Simulation time 45904359 ps
CPU time 0.73 seconds
Started Aug 02 06:46:00 PM PDT 24
Finished Aug 02 06:46:01 PM PDT 24
Peak memory 206120 kb
Host smart-f31e00c1-3974-49f4-83c3-1c857f3e688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039012874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4039012874
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.105078957
Short name T1000
Test name
Test status
Simulation time 24864719 ps
CPU time 0.69 seconds
Started Aug 02 06:45:57 PM PDT 24
Finished Aug 02 06:45:58 PM PDT 24
Peak memory 205988 kb
Host smart-f60a8052-ded2-4d64-b655-2d97e2ae74b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105078957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.105078957
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2879983968
Short name T896
Test name
Test status
Simulation time 76582313 ps
CPU time 0.81 seconds
Started Aug 02 06:45:59 PM PDT 24
Finished Aug 02 06:46:00 PM PDT 24
Peak memory 206420 kb
Host smart-587bd1c4-51b0-4e93-890e-870244c95146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879983968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2879983968
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3481702483
Short name T696
Test name
Test status
Simulation time 2301560884 ps
CPU time 5.79 seconds
Started Aug 02 06:46:08 PM PDT 24
Finished Aug 02 06:46:14 PM PDT 24
Peak memory 233172 kb
Host smart-e0d68a00-2745-40e1-a960-df18e096ec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481702483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3481702483
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1383680354
Short name T623
Test name
Test status
Simulation time 44685203 ps
CPU time 0.74 seconds
Started Aug 02 06:46:09 PM PDT 24
Finished Aug 02 06:46:10 PM PDT 24
Peak memory 205304 kb
Host smart-ee882916-132e-4ac6-af8a-410353f415df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383680354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1383680354
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1835188392
Short name T345
Test name
Test status
Simulation time 122349669 ps
CPU time 2.08 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:10 PM PDT 24
Peak memory 224588 kb
Host smart-82e8eb38-4d98-4eb2-a0cd-252a539bd62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835188392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1835188392
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1150196549
Short name T411
Test name
Test status
Simulation time 86319619 ps
CPU time 0.76 seconds
Started Aug 02 06:46:04 PM PDT 24
Finished Aug 02 06:46:04 PM PDT 24
Peak memory 205984 kb
Host smart-e3672a08-21b8-4458-b8a8-9a04804cb90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150196549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1150196549
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2319325177
Short name T209
Test name
Test status
Simulation time 26083917551 ps
CPU time 224.74 seconds
Started Aug 02 06:46:04 PM PDT 24
Finished Aug 02 06:49:49 PM PDT 24
Peak memory 254952 kb
Host smart-afcb0ff4-3e36-4eeb-9811-85ebd714dcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319325177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2319325177
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3226203999
Short name T215
Test name
Test status
Simulation time 20677010430 ps
CPU time 202.39 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:49:30 PM PDT 24
Peak memory 249976 kb
Host smart-9b606178-c2c5-4bf5-868e-3ed2571e2940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226203999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3226203999
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2406882106
Short name T991
Test name
Test status
Simulation time 15230199388 ps
CPU time 105.77 seconds
Started Aug 02 06:46:10 PM PDT 24
Finished Aug 02 06:47:56 PM PDT 24
Peak memory 253536 kb
Host smart-a751cd92-2fba-4c0f-99f4-a31caec6647e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406882106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2406882106
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2218626046
Short name T432
Test name
Test status
Simulation time 591744600 ps
CPU time 12.69 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:20 PM PDT 24
Peak memory 224936 kb
Host smart-94a70f84-b8ef-4159-b4e6-ba0f3306abe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218626046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2218626046
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3126065259
Short name T956
Test name
Test status
Simulation time 326760504616 ps
CPU time 598.94 seconds
Started Aug 02 06:46:04 PM PDT 24
Finished Aug 02 06:56:03 PM PDT 24
Peak memory 272224 kb
Host smart-6730ead0-d2a3-44a9-b898-3adac5941456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126065259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3126065259
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1392693345
Short name T647
Test name
Test status
Simulation time 549373891 ps
CPU time 3.88 seconds
Started Aug 02 06:46:10 PM PDT 24
Finished Aug 02 06:46:14 PM PDT 24
Peak memory 224940 kb
Host smart-c5fc29a0-6b9c-470d-ba19-bf7b0fb66728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392693345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1392693345
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3907063653
Short name T564
Test name
Test status
Simulation time 1161097929 ps
CPU time 9.99 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:18 PM PDT 24
Peak memory 225008 kb
Host smart-0fb80234-ad23-4695-8852-91485e93597c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907063653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3907063653
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2300972491
Short name T222
Test name
Test status
Simulation time 18849008419 ps
CPU time 14.32 seconds
Started Aug 02 06:46:03 PM PDT 24
Finished Aug 02 06:46:18 PM PDT 24
Peak memory 225032 kb
Host smart-7905eb75-5ff1-46a1-a1cb-d5abc82c9525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300972491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2300972491
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3441455115
Short name T801
Test name
Test status
Simulation time 194789969 ps
CPU time 2.79 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:10 PM PDT 24
Peak memory 233196 kb
Host smart-6265d8a9-166c-4b5e-9e95-b16431b18d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441455115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3441455115
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2303557345
Short name T886
Test name
Test status
Simulation time 1826989948 ps
CPU time 6.55 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:14 PM PDT 24
Peak memory 221720 kb
Host smart-2be64496-8e0c-4528-9d4f-01bfa9545264
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2303557345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2303557345
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1339245342
Short name T16
Test name
Test status
Simulation time 8452855502 ps
CPU time 91.68 seconds
Started Aug 02 06:46:05 PM PDT 24
Finished Aug 02 06:47:37 PM PDT 24
Peak memory 241416 kb
Host smart-eee4e62f-3809-4c8b-83c9-c2ec8ed0fffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339245342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1339245342
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.875631370
Short name T9
Test name
Test status
Simulation time 2219683302 ps
CPU time 5 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:12 PM PDT 24
Peak memory 216680 kb
Host smart-9a978eb0-0bdb-4d39-884c-0d9ecb0b26eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875631370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.875631370
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.30163260
Short name T608
Test name
Test status
Simulation time 1529252396 ps
CPU time 6.32 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:13 PM PDT 24
Peak memory 216656 kb
Host smart-f2db1496-d706-4f52-a717-6a69b3fd7b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30163260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.30163260
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3750109656
Short name T970
Test name
Test status
Simulation time 142987829 ps
CPU time 3.86 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:11 PM PDT 24
Peak memory 216608 kb
Host smart-8f08a829-1c31-4b8c-be51-222ad3af9350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750109656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3750109656
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.935111920
Short name T625
Test name
Test status
Simulation time 33677869 ps
CPU time 0.76 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:08 PM PDT 24
Peak memory 206404 kb
Host smart-608ffdfc-6154-484d-871a-738fc36ca0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935111920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.935111920
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4172134866
Short name T566
Test name
Test status
Simulation time 1767664162 ps
CPU time 12.37 seconds
Started Aug 02 06:46:06 PM PDT 24
Finished Aug 02 06:46:18 PM PDT 24
Peak memory 249520 kb
Host smart-eeea32fc-2bd0-4888-b1ee-28a352f10340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172134866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4172134866
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1371027576
Short name T689
Test name
Test status
Simulation time 12303846 ps
CPU time 0.74 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:46:14 PM PDT 24
Peak memory 205852 kb
Host smart-3a5726a5-116c-48a8-962c-e8b05e362d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371027576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1371027576
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1142276450
Short name T584
Test name
Test status
Simulation time 433392891 ps
CPU time 4.25 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:12 PM PDT 24
Peak memory 225012 kb
Host smart-34291404-3cc2-406f-8985-2a52462ab6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142276450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1142276450
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.612907480
Short name T374
Test name
Test status
Simulation time 32211531 ps
CPU time 0.78 seconds
Started Aug 02 06:46:06 PM PDT 24
Finished Aug 02 06:46:07 PM PDT 24
Peak memory 206332 kb
Host smart-e3c5656a-5b3e-48c0-90b3-8327ef93c0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612907480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.612907480
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3318361917
Short name T583
Test name
Test status
Simulation time 18107217851 ps
CPU time 76.53 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:47:30 PM PDT 24
Peak memory 253916 kb
Host smart-be345ed3-6664-440c-ae8b-d7a7d8249c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318361917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3318361917
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3244935267
Short name T673
Test name
Test status
Simulation time 76429450203 ps
CPU time 103.63 seconds
Started Aug 02 06:46:16 PM PDT 24
Finished Aug 02 06:47:59 PM PDT 24
Peak memory 269664 kb
Host smart-a19e6657-3151-4532-b860-f03ee81060a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244935267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3244935267
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1230342852
Short name T542
Test name
Test status
Simulation time 1726069311 ps
CPU time 28.14 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:36 PM PDT 24
Peak memory 234388 kb
Host smart-ebc4659a-3066-448d-9ef5-c10a38bdac11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230342852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1230342852
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3421945922
Short name T55
Test name
Test status
Simulation time 32516021011 ps
CPU time 226.23 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:49:59 PM PDT 24
Peak memory 249548 kb
Host smart-81a107c9-5aca-418e-af2c-ebe8f3275a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421945922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3421945922
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3454241376
Short name T655
Test name
Test status
Simulation time 110106990 ps
CPU time 3.16 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:11 PM PDT 24
Peak memory 224940 kb
Host smart-24874f5b-56b6-4719-aa7c-f30f3e594c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454241376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3454241376
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.218901739
Short name T1009
Test name
Test status
Simulation time 8918982764 ps
CPU time 42.52 seconds
Started Aug 02 06:46:06 PM PDT 24
Finished Aug 02 06:46:48 PM PDT 24
Peak memory 239884 kb
Host smart-55f2be9a-8ab2-431f-9610-813544919ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218901739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.218901739
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2959690928
Short name T935
Test name
Test status
Simulation time 33426768346 ps
CPU time 20.37 seconds
Started Aug 02 06:46:11 PM PDT 24
Finished Aug 02 06:46:31 PM PDT 24
Peak memory 225064 kb
Host smart-6e551faf-cef2-42a7-a8fd-d2664708347c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959690928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2959690928
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1343514883
Short name T940
Test name
Test status
Simulation time 1429943090 ps
CPU time 7.21 seconds
Started Aug 02 06:46:06 PM PDT 24
Finished Aug 02 06:46:13 PM PDT 24
Peak memory 234124 kb
Host smart-dddfaad7-8fb0-4db2-89ff-e3beb86ff58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343514883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1343514883
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.461237571
Short name T553
Test name
Test status
Simulation time 1841972184 ps
CPU time 21.52 seconds
Started Aug 02 06:46:14 PM PDT 24
Finished Aug 02 06:46:35 PM PDT 24
Peak memory 223096 kb
Host smart-198b2c8b-dd94-4d27-8d44-6e0d269527c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=461237571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.461237571
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.782193981
Short name T722
Test name
Test status
Simulation time 3458633369 ps
CPU time 21.53 seconds
Started Aug 02 06:46:08 PM PDT 24
Finished Aug 02 06:46:30 PM PDT 24
Peak memory 216796 kb
Host smart-c51ccc66-90f9-4dbe-84e6-a178df29eff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782193981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.782193981
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1309805477
Short name T958
Test name
Test status
Simulation time 16278007721 ps
CPU time 4.13 seconds
Started Aug 02 06:46:04 PM PDT 24
Finished Aug 02 06:46:08 PM PDT 24
Peak memory 216920 kb
Host smart-81dcde04-8e75-4003-b876-37b6664a3c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309805477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1309805477
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1824640622
Short name T1007
Test name
Test status
Simulation time 145402392 ps
CPU time 3.56 seconds
Started Aug 02 06:46:11 PM PDT 24
Finished Aug 02 06:46:14 PM PDT 24
Peak memory 216724 kb
Host smart-af20a8f3-de80-4458-b49a-34f8ff88f236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824640622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1824640622
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4290643620
Short name T863
Test name
Test status
Simulation time 62569533 ps
CPU time 0.87 seconds
Started Aug 02 06:46:07 PM PDT 24
Finished Aug 02 06:46:08 PM PDT 24
Peak memory 206340 kb
Host smart-7008684f-17f9-4c40-9736-70f10478953d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290643620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4290643620
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3122558193
Short name T974
Test name
Test status
Simulation time 30653391908 ps
CPU time 18.45 seconds
Started Aug 02 06:46:04 PM PDT 24
Finished Aug 02 06:46:23 PM PDT 24
Peak memory 241392 kb
Host smart-055db3e5-3c46-4fbf-b109-e23be7caf5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122558193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3122558193
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2496774033
Short name T684
Test name
Test status
Simulation time 15834485 ps
CPU time 0.77 seconds
Started Aug 02 06:46:15 PM PDT 24
Finished Aug 02 06:46:16 PM PDT 24
Peak memory 206180 kb
Host smart-65c3f83a-fd60-40f7-96f5-4ef3c9225819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496774033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2496774033
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2266560751
Short name T885
Test name
Test status
Simulation time 326204252 ps
CPU time 3.36 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:46:16 PM PDT 24
Peak memory 224956 kb
Host smart-87019f4f-f74b-4daa-8869-64d97564b97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266560751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2266560751
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2455364927
Short name T631
Test name
Test status
Simulation time 49245885 ps
CPU time 0.71 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:46:14 PM PDT 24
Peak memory 206260 kb
Host smart-68444e16-1029-4c35-9067-22bbd081f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455364927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2455364927
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4141948634
Short name T296
Test name
Test status
Simulation time 20282019383 ps
CPU time 170.98 seconds
Started Aug 02 06:46:15 PM PDT 24
Finished Aug 02 06:49:06 PM PDT 24
Peak memory 256688 kb
Host smart-1e5d220d-0be7-4ac7-bcad-218e1fe9e04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141948634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4141948634
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2577528983
Short name T764
Test name
Test status
Simulation time 6826925056 ps
CPU time 95.03 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:47:48 PM PDT 24
Peak memory 249620 kb
Host smart-c79325ce-7819-48d5-962d-9cd69306ca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577528983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2577528983
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.382738126
Short name T794
Test name
Test status
Simulation time 681744123 ps
CPU time 7.12 seconds
Started Aug 02 06:46:12 PM PDT 24
Finished Aug 02 06:46:20 PM PDT 24
Peak memory 224976 kb
Host smart-58c34570-0428-4644-aa5b-30eba607f817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382738126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.382738126
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3146549611
Short name T299
Test name
Test status
Simulation time 87802903869 ps
CPU time 256.14 seconds
Started Aug 02 06:46:14 PM PDT 24
Finished Aug 02 06:50:31 PM PDT 24
Peak memory 265956 kb
Host smart-ff3e7fd8-c22f-4d21-b40f-592006b9f33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146549611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3146549611
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1192490051
Short name T938
Test name
Test status
Simulation time 5413861524 ps
CPU time 14.51 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:46:28 PM PDT 24
Peak memory 233260 kb
Host smart-fed44598-276d-443e-baca-a5b4122dd0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192490051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1192490051
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.170825141
Short name T687
Test name
Test status
Simulation time 792854726 ps
CPU time 9.67 seconds
Started Aug 02 06:46:14 PM PDT 24
Finished Aug 02 06:46:24 PM PDT 24
Peak memory 237536 kb
Host smart-71e14320-6cf4-46fb-b456-c7a90b42b4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170825141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.170825141
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2496267766
Short name T786
Test name
Test status
Simulation time 4870022481 ps
CPU time 8.89 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:46:22 PM PDT 24
Peak memory 233160 kb
Host smart-f66ded82-52f4-4ee1-9fcf-dbf5ed7fe44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496267766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2496267766
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1275090377
Short name T278
Test name
Test status
Simulation time 1018919761 ps
CPU time 2.63 seconds
Started Aug 02 06:46:11 PM PDT 24
Finished Aug 02 06:46:14 PM PDT 24
Peak memory 224860 kb
Host smart-43d6c0e0-a4b4-4464-a25b-f99814098f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275090377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1275090377
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1292546574
Short name T46
Test name
Test status
Simulation time 2786876742 ps
CPU time 9.44 seconds
Started Aug 02 06:46:11 PM PDT 24
Finished Aug 02 06:46:21 PM PDT 24
Peak memory 221404 kb
Host smart-c1c91700-e80c-475b-979a-cb803efebab3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1292546574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1292546574
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.299167463
Short name T447
Test name
Test status
Simulation time 16922278808 ps
CPU time 22.72 seconds
Started Aug 02 06:46:12 PM PDT 24
Finished Aug 02 06:46:35 PM PDT 24
Peak memory 216784 kb
Host smart-5c749e3c-d754-44a5-acb4-2aeec2b2766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299167463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.299167463
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.632803410
Short name T763
Test name
Test status
Simulation time 11433664 ps
CPU time 0.73 seconds
Started Aug 02 06:46:14 PM PDT 24
Finished Aug 02 06:46:15 PM PDT 24
Peak memory 206088 kb
Host smart-1305b063-f100-48c5-bba0-4b4a74e31e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632803410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.632803410
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3826384145
Short name T668
Test name
Test status
Simulation time 159818203 ps
CPU time 6.35 seconds
Started Aug 02 06:46:12 PM PDT 24
Finished Aug 02 06:46:18 PM PDT 24
Peak memory 216744 kb
Host smart-73905111-e350-4017-9ffa-0e0b984ffb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826384145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3826384145
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.418039956
Short name T512
Test name
Test status
Simulation time 105850816 ps
CPU time 0.96 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:46:14 PM PDT 24
Peak memory 207372 kb
Host smart-09d0cc3b-683f-4b07-98b7-e5781136743e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418039956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.418039956
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.487526560
Short name T568
Test name
Test status
Simulation time 815323616 ps
CPU time 8.14 seconds
Started Aug 02 06:46:14 PM PDT 24
Finished Aug 02 06:46:22 PM PDT 24
Peak memory 238744 kb
Host smart-983fd3e5-c820-4abf-b887-662fa1332b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487526560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.487526560
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1877479347
Short name T868
Test name
Test status
Simulation time 19359504 ps
CPU time 0.76 seconds
Started Aug 02 06:46:24 PM PDT 24
Finished Aug 02 06:46:25 PM PDT 24
Peak memory 205268 kb
Host smart-53e5f073-f153-4847-97df-5644e0eb4d76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877479347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1877479347
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2662429192
Short name T823
Test name
Test status
Simulation time 1737385691 ps
CPU time 5.1 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:46:18 PM PDT 24
Peak memory 233068 kb
Host smart-57f3ce3d-bcd8-4c99-8617-046a234cb43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662429192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2662429192
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3956815293
Short name T144
Test name
Test status
Simulation time 27909449 ps
CPU time 0.78 seconds
Started Aug 02 06:46:12 PM PDT 24
Finished Aug 02 06:46:13 PM PDT 24
Peak memory 207348 kb
Host smart-e211fe92-08c4-407d-ad15-e62490cf39d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956815293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3956815293
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1279513848
Short name T242
Test name
Test status
Simulation time 134661638069 ps
CPU time 165.25 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:49:08 PM PDT 24
Peak memory 257732 kb
Host smart-b8446e2e-be0f-4044-8d37-9f84b992f363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279513848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1279513848
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3211529524
Short name T605
Test name
Test status
Simulation time 116622580751 ps
CPU time 99.8 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:48:01 PM PDT 24
Peak memory 250668 kb
Host smart-ff2ef18a-518d-4aee-90f5-25e03f733d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211529524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3211529524
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1599093477
Short name T292
Test name
Test status
Simulation time 23020939494 ps
CPU time 65.09 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:47:27 PM PDT 24
Peak memory 239704 kb
Host smart-518aa279-6b95-448e-b332-1c865a3f4378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599093477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1599093477
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.791380753
Short name T392
Test name
Test status
Simulation time 728672273 ps
CPU time 3.38 seconds
Started Aug 02 06:46:23 PM PDT 24
Finished Aug 02 06:46:26 PM PDT 24
Peak memory 233088 kb
Host smart-9caacace-2f9f-4125-861c-5d3fbf09f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791380753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.791380753
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.631892324
Short name T756
Test name
Test status
Simulation time 1966007145 ps
CPU time 43.36 seconds
Started Aug 02 06:46:20 PM PDT 24
Finished Aug 02 06:47:04 PM PDT 24
Peak memory 256576 kb
Host smart-7b9ca4fa-c076-4695-939a-a6e6819a43b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631892324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.631892324
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.175513201
Short name T634
Test name
Test status
Simulation time 93292440 ps
CPU time 3.34 seconds
Started Aug 02 06:46:14 PM PDT 24
Finished Aug 02 06:46:18 PM PDT 24
Peak memory 224972 kb
Host smart-3b844f92-6d88-4076-9134-6e0ec421db3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175513201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.175513201
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3754168227
Short name T649
Test name
Test status
Simulation time 23566885366 ps
CPU time 51.39 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:47:05 PM PDT 24
Peak memory 239360 kb
Host smart-f691582c-4b97-4573-bcec-833a4d2d2837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754168227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3754168227
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4192800600
Short name T27
Test name
Test status
Simulation time 8868957356 ps
CPU time 27.92 seconds
Started Aug 02 06:46:16 PM PDT 24
Finished Aug 02 06:46:44 PM PDT 24
Peak memory 241436 kb
Host smart-51d515b5-6907-4673-9367-6d8cb423d1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192800600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4192800600
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1915692272
Short name T585
Test name
Test status
Simulation time 1692537757 ps
CPU time 6.85 seconds
Started Aug 02 06:46:16 PM PDT 24
Finished Aug 02 06:46:23 PM PDT 24
Peak memory 233172 kb
Host smart-b9159406-0464-489b-9587-1873f8a70557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915692272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1915692272
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3692293553
Short name T747
Test name
Test status
Simulation time 2961014920 ps
CPU time 10.78 seconds
Started Aug 02 06:46:25 PM PDT 24
Finished Aug 02 06:46:36 PM PDT 24
Peak memory 223584 kb
Host smart-658b904a-9203-4304-acd0-88619495b5d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3692293553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3692293553
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2623048726
Short name T851
Test name
Test status
Simulation time 14031215933 ps
CPU time 46.07 seconds
Started Aug 02 06:46:13 PM PDT 24
Finished Aug 02 06:46:59 PM PDT 24
Peak memory 216736 kb
Host smart-205bc8d7-7aed-4e36-8a50-9a9c098f78ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623048726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2623048726
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.187703959
Short name T777
Test name
Test status
Simulation time 8439038048 ps
CPU time 2.55 seconds
Started Aug 02 06:46:16 PM PDT 24
Finished Aug 02 06:46:19 PM PDT 24
Peak memory 208440 kb
Host smart-d6c5d3e3-dc97-4601-9817-d64b96dfd082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187703959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.187703959
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.398748557
Short name T650
Test name
Test status
Simulation time 1999944179 ps
CPU time 3.11 seconds
Started Aug 02 06:46:15 PM PDT 24
Finished Aug 02 06:46:18 PM PDT 24
Peak memory 216684 kb
Host smart-e8b86780-4a8a-4ec4-9048-6e260dfeabaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398748557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.398748557
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.724758837
Short name T803
Test name
Test status
Simulation time 53144336 ps
CPU time 0.74 seconds
Started Aug 02 06:46:16 PM PDT 24
Finished Aug 02 06:46:16 PM PDT 24
Peak memory 206264 kb
Host smart-cd3ec6a9-a73d-4c55-9af3-ec2d7d93cc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724758837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.724758837
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2134847015
Short name T69
Test name
Test status
Simulation time 1297072828 ps
CPU time 7.47 seconds
Started Aug 02 06:46:12 PM PDT 24
Finished Aug 02 06:46:20 PM PDT 24
Peak memory 233176 kb
Host smart-b47a1ca3-03e2-4b30-ba8f-ce86ecbf57f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134847015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2134847015
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1303966226
Short name T346
Test name
Test status
Simulation time 49238430 ps
CPU time 0.72 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:46:23 PM PDT 24
Peak memory 205364 kb
Host smart-41e36e9c-8c52-4e3b-9e69-102f5baf9cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303966226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1303966226
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1696625962
Short name T711
Test name
Test status
Simulation time 143636335 ps
CPU time 4.52 seconds
Started Aug 02 06:46:25 PM PDT 24
Finished Aug 02 06:46:30 PM PDT 24
Peak memory 233132 kb
Host smart-a57497ea-591b-4409-b7ce-7226e4bf2d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696625962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1696625962
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1126637709
Short name T502
Test name
Test status
Simulation time 50255000 ps
CPU time 0.78 seconds
Started Aug 02 06:46:19 PM PDT 24
Finished Aug 02 06:46:20 PM PDT 24
Peak memory 207008 kb
Host smart-33a0db11-5742-4307-b416-6fc2903acf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126637709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1126637709
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1866344630
Short name T462
Test name
Test status
Simulation time 10082198700 ps
CPU time 69.34 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:47:31 PM PDT 24
Peak memory 237524 kb
Host smart-167f9817-0ee6-4343-be14-27b45630764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866344630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1866344630
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1071859753
Short name T61
Test name
Test status
Simulation time 5915964257 ps
CPU time 36.58 seconds
Started Aug 02 06:46:21 PM PDT 24
Finished Aug 02 06:46:58 PM PDT 24
Peak memory 249584 kb
Host smart-9d4c0d6c-b2ba-4fef-8baf-e432d795e19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071859753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1071859753
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3965840992
Short name T151
Test name
Test status
Simulation time 45736019705 ps
CPU time 422.83 seconds
Started Aug 02 06:46:27 PM PDT 24
Finished Aug 02 06:53:30 PM PDT 24
Peak memory 257060 kb
Host smart-a048039a-2d03-492a-b666-246bd756d52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965840992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3965840992
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1874430537
Short name T946
Test name
Test status
Simulation time 591266428 ps
CPU time 7.73 seconds
Started Aug 02 06:46:31 PM PDT 24
Finished Aug 02 06:46:38 PM PDT 24
Peak memory 241272 kb
Host smart-34e94aea-8bd4-429c-befb-974e516419ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874430537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1874430537
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2017591656
Short name T636
Test name
Test status
Simulation time 2079269146 ps
CPU time 28.96 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:46:51 PM PDT 24
Peak memory 249496 kb
Host smart-2c976277-d440-48d5-b5c7-685e9f3d115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017591656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2017591656
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3495449148
Short name T949
Test name
Test status
Simulation time 3412055272 ps
CPU time 4.79 seconds
Started Aug 02 06:46:21 PM PDT 24
Finished Aug 02 06:46:26 PM PDT 24
Peak memory 224948 kb
Host smart-bbb58f23-94c8-4340-a77d-1cd42ac1174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495449148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3495449148
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3002172529
Short name T532
Test name
Test status
Simulation time 118347544 ps
CPU time 3.29 seconds
Started Aug 02 06:46:27 PM PDT 24
Finished Aug 02 06:46:31 PM PDT 24
Peak memory 233056 kb
Host smart-6a1d7d72-59e6-4319-bd55-a8d2d8dc00d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002172529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3002172529
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.525137757
Short name T201
Test name
Test status
Simulation time 639499679 ps
CPU time 2.47 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:46:25 PM PDT 24
Peak memory 224908 kb
Host smart-d1ba2780-3aed-4a32-91c9-4f5d7e527cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525137757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.525137757
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3021436558
Short name T802
Test name
Test status
Simulation time 545578361 ps
CPU time 4.18 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:46:26 PM PDT 24
Peak memory 233132 kb
Host smart-da717edc-791b-4975-8f30-df84c9ff7177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021436558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3021436558
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2087837451
Short name T606
Test name
Test status
Simulation time 1110848269 ps
CPU time 4.83 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:46:27 PM PDT 24
Peak memory 219752 kb
Host smart-5e250449-ec77-4942-805f-5957f93fe812
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087837451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2087837451
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1290245716
Short name T817
Test name
Test status
Simulation time 214318991 ps
CPU time 1.19 seconds
Started Aug 02 06:46:24 PM PDT 24
Finished Aug 02 06:46:25 PM PDT 24
Peak memory 207380 kb
Host smart-b6411d3e-27e1-4ceb-915e-b45271bab366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290245716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1290245716
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4133294464
Short name T423
Test name
Test status
Simulation time 1054671775 ps
CPU time 4.37 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:46:26 PM PDT 24
Peak memory 216920 kb
Host smart-2894748f-626f-4101-b4f6-b88872b97171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133294464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4133294464
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.644154781
Short name T721
Test name
Test status
Simulation time 21458725913 ps
CPU time 22.5 seconds
Started Aug 02 06:46:26 PM PDT 24
Finished Aug 02 06:46:48 PM PDT 24
Peak memory 216704 kb
Host smart-ca3eb9d5-1366-4103-8156-9935cdd7eaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644154781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.644154781
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1668774577
Short name T704
Test name
Test status
Simulation time 49283638 ps
CPU time 1.16 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:46:23 PM PDT 24
Peak memory 207920 kb
Host smart-25450dc4-5d28-49d9-bdf5-7c558734f0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668774577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1668774577
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.811388526
Short name T549
Test name
Test status
Simulation time 45341061 ps
CPU time 0.68 seconds
Started Aug 02 06:46:21 PM PDT 24
Finished Aug 02 06:46:22 PM PDT 24
Peak memory 206008 kb
Host smart-2a656bff-37cc-44e9-a4d9-5946d01899a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811388526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.811388526
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2783023003
Short name T256
Test name
Test status
Simulation time 453905638 ps
CPU time 7.72 seconds
Started Aug 02 06:46:27 PM PDT 24
Finished Aug 02 06:46:35 PM PDT 24
Peak memory 233088 kb
Host smart-1ae1cb32-c2f1-43a1-8dac-cbc9de98710e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783023003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2783023003
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3875282622
Short name T557
Test name
Test status
Simulation time 16263307 ps
CPU time 0.74 seconds
Started Aug 02 06:46:26 PM PDT 24
Finished Aug 02 06:46:27 PM PDT 24
Peak memory 205844 kb
Host smart-ed5bab1d-9592-4e46-940b-b27a88caf30d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875282622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3875282622
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2370155185
Short name T712
Test name
Test status
Simulation time 158840854 ps
CPU time 2.49 seconds
Started Aug 02 06:46:25 PM PDT 24
Finished Aug 02 06:46:27 PM PDT 24
Peak memory 224936 kb
Host smart-60c880e2-c89b-4f52-9654-69873895d909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370155185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2370155185
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.793829582
Short name T348
Test name
Test status
Simulation time 16698263 ps
CPU time 0.8 seconds
Started Aug 02 06:46:28 PM PDT 24
Finished Aug 02 06:46:29 PM PDT 24
Peak memory 206968 kb
Host smart-72be599a-4e52-4583-8f42-2f8c8fba4c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793829582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.793829582
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.247775381
Short name T204
Test name
Test status
Simulation time 90792626145 ps
CPU time 165.78 seconds
Started Aug 02 06:46:27 PM PDT 24
Finished Aug 02 06:49:12 PM PDT 24
Peak memory 249528 kb
Host smart-434dc631-0531-4bda-be93-58df1993d966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247775381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.247775381
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2090479749
Short name T706
Test name
Test status
Simulation time 9538580255 ps
CPU time 24.29 seconds
Started Aug 02 06:46:21 PM PDT 24
Finished Aug 02 06:46:46 PM PDT 24
Peak memory 240504 kb
Host smart-09665e8c-504d-4e53-8b0a-55e887897eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090479749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2090479749
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2964366344
Short name T194
Test name
Test status
Simulation time 62749803963 ps
CPU time 436.54 seconds
Started Aug 02 06:46:26 PM PDT 24
Finished Aug 02 06:53:42 PM PDT 24
Peak memory 265732 kb
Host smart-9cf85627-9b7b-4a40-a77f-1afcd929c5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964366344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2964366344
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3451283143
Short name T526
Test name
Test status
Simulation time 5196643169 ps
CPU time 13.49 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:46:36 PM PDT 24
Peak memory 224984 kb
Host smart-62a429b9-668c-4e8f-936e-d03d2fb9f986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451283143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3451283143
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1645690428
Short name T306
Test name
Test status
Simulation time 2869224551 ps
CPU time 55.74 seconds
Started Aug 02 06:46:21 PM PDT 24
Finished Aug 02 06:47:17 PM PDT 24
Peak memory 255916 kb
Host smart-9f566511-53d1-4013-814b-370073d858df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645690428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1645690428
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3996943686
Short name T899
Test name
Test status
Simulation time 2405968387 ps
CPU time 12.29 seconds
Started Aug 02 06:46:24 PM PDT 24
Finished Aug 02 06:46:36 PM PDT 24
Peak memory 233212 kb
Host smart-e30c675b-dff5-4058-a405-4ad73f362b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996943686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3996943686
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1901262681
Short name T223
Test name
Test status
Simulation time 220944729336 ps
CPU time 132.62 seconds
Started Aug 02 06:46:24 PM PDT 24
Finished Aug 02 06:48:36 PM PDT 24
Peak memory 249888 kb
Host smart-41999ad5-138d-4c4f-bf89-db46820e2678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901262681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1901262681
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4198830639
Short name T646
Test name
Test status
Simulation time 63153001 ps
CPU time 2.16 seconds
Started Aug 02 06:46:23 PM PDT 24
Finished Aug 02 06:46:25 PM PDT 24
Peak memory 224292 kb
Host smart-90398cbc-ecc0-4adf-8dfe-5c5e7fb637ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198830639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4198830639
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1154919781
Short name T221
Test name
Test status
Simulation time 899156694 ps
CPU time 8.09 seconds
Started Aug 02 06:46:26 PM PDT 24
Finished Aug 02 06:46:34 PM PDT 24
Peak memory 224892 kb
Host smart-bb866116-126e-4cc3-a1f7-6f157d36f8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154919781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1154919781
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.872666583
Short name T160
Test name
Test status
Simulation time 729470021 ps
CPU time 10.52 seconds
Started Aug 02 06:46:22 PM PDT 24
Finished Aug 02 06:46:32 PM PDT 24
Peak memory 219856 kb
Host smart-205749ba-a833-4e75-8468-641c0d4b05f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=872666583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.872666583
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3888654434
Short name T841
Test name
Test status
Simulation time 29559374338 ps
CPU time 286.48 seconds
Started Aug 02 06:46:24 PM PDT 24
Finished Aug 02 06:51:11 PM PDT 24
Peak memory 250676 kb
Host smart-c0ec4cdc-bb95-4881-a3f4-99a80ac124ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888654434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3888654434
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3987348043
Short name T563
Test name
Test status
Simulation time 1095220063 ps
CPU time 11.88 seconds
Started Aug 02 06:46:24 PM PDT 24
Finished Aug 02 06:46:36 PM PDT 24
Peak memory 219792 kb
Host smart-54fc9c1c-a10f-4c3d-9de8-e1dc1e9a7847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987348043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3987348043
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.686781248
Short name T986
Test name
Test status
Simulation time 27663925090 ps
CPU time 19.42 seconds
Started Aug 02 06:46:24 PM PDT 24
Finished Aug 02 06:46:43 PM PDT 24
Peak memory 219116 kb
Host smart-09e9eea5-dbc0-457d-acb1-62783d17de69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686781248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.686781248
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2281026584
Short name T715
Test name
Test status
Simulation time 21281803 ps
CPU time 1 seconds
Started Aug 02 06:46:23 PM PDT 24
Finished Aug 02 06:46:24 PM PDT 24
Peak memory 207516 kb
Host smart-eea0b3df-980c-44ae-835a-0f73138d96a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281026584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2281026584
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1880250988
Short name T590
Test name
Test status
Simulation time 57104978 ps
CPU time 0.89 seconds
Started Aug 02 06:46:24 PM PDT 24
Finished Aug 02 06:46:24 PM PDT 24
Peak memory 206352 kb
Host smart-edf46b10-b4a4-43d8-a48c-e44481174f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880250988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1880250988
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1336163536
Short name T96
Test name
Test status
Simulation time 5499504014 ps
CPU time 18.08 seconds
Started Aug 02 06:46:23 PM PDT 24
Finished Aug 02 06:46:41 PM PDT 24
Peak memory 239664 kb
Host smart-9631f8bf-8e11-493d-b117-7dc0a34bfd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336163536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1336163536
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.47470932
Short name T657
Test name
Test status
Simulation time 19496415 ps
CPU time 0.7 seconds
Started Aug 02 06:44:20 PM PDT 24
Finished Aug 02 06:44:21 PM PDT 24
Peak memory 205244 kb
Host smart-f8f7aeb1-2417-4031-848e-aaf17ba8c70e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47470932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.47470932
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3223367440
Short name T243
Test name
Test status
Simulation time 118489061 ps
CPU time 3.11 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:28 PM PDT 24
Peak memory 233124 kb
Host smart-38a74f32-40ae-420f-a070-a12154d08214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223367440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3223367440
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3059142581
Short name T679
Test name
Test status
Simulation time 61903674 ps
CPU time 0.75 seconds
Started Aug 02 06:44:27 PM PDT 24
Finished Aug 02 06:44:28 PM PDT 24
Peak memory 206012 kb
Host smart-d09e8d00-8a44-4b5f-9208-86c46fdfc8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059142581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3059142581
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1805847443
Short name T619
Test name
Test status
Simulation time 19640339795 ps
CPU time 135.89 seconds
Started Aug 02 06:44:21 PM PDT 24
Finished Aug 02 06:46:37 PM PDT 24
Peak memory 257260 kb
Host smart-555d3370-f2c4-4926-bf38-227d5739a3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805847443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1805847443
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3785350886
Short name T173
Test name
Test status
Simulation time 113898255742 ps
CPU time 258.04 seconds
Started Aug 02 06:44:30 PM PDT 24
Finished Aug 02 06:48:49 PM PDT 24
Peak memory 266752 kb
Host smart-32ea0f7d-9d82-4111-ba2c-32671e2f3bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785350886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3785350886
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1802893075
Short name T847
Test name
Test status
Simulation time 23412272563 ps
CPU time 57.81 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:45:24 PM PDT 24
Peak memory 249688 kb
Host smart-c6788eef-5692-47c8-ad50-ab948ad4b538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802893075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1802893075
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3955201995
Short name T866
Test name
Test status
Simulation time 3887465420 ps
CPU time 30.61 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:56 PM PDT 24
Peak memory 233236 kb
Host smart-46a33f01-0ccc-49d2-b629-e84c863658ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955201995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3955201995
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1386183947
Short name T108
Test name
Test status
Simulation time 5507776279 ps
CPU time 60.06 seconds
Started Aug 02 06:44:22 PM PDT 24
Finished Aug 02 06:45:23 PM PDT 24
Peak memory 250928 kb
Host smart-158c61ac-939e-4548-960d-63ca46cdb703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386183947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1386183947
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3911088311
Short name T734
Test name
Test status
Simulation time 1044436293 ps
CPU time 9.79 seconds
Started Aug 02 06:44:27 PM PDT 24
Finished Aug 02 06:44:37 PM PDT 24
Peak memory 224956 kb
Host smart-348e1c04-5305-41de-bb1a-8fe92e2d58bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911088311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3911088311
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3609972423
Short name T973
Test name
Test status
Simulation time 2076313091 ps
CPU time 14.81 seconds
Started Aug 02 06:44:23 PM PDT 24
Finished Aug 02 06:44:38 PM PDT 24
Peak memory 233052 kb
Host smart-72bd305a-5147-495b-85a7-59958eda00c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609972423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3609972423
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2270090870
Short name T980
Test name
Test status
Simulation time 16841363843 ps
CPU time 15.15 seconds
Started Aug 02 06:44:20 PM PDT 24
Finished Aug 02 06:44:36 PM PDT 24
Peak memory 233268 kb
Host smart-a5ce16a4-2f68-418f-837c-10ea3131e1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270090870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2270090870
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3848106367
Short name T477
Test name
Test status
Simulation time 2860966127 ps
CPU time 13.19 seconds
Started Aug 02 06:44:23 PM PDT 24
Finished Aug 02 06:44:37 PM PDT 24
Peak memory 233160 kb
Host smart-70e62c44-c7b0-4fe9-9f04-8c821b534367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848106367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3848106367
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3178126199
Short name T424
Test name
Test status
Simulation time 1428252088 ps
CPU time 11.16 seconds
Started Aug 02 06:44:22 PM PDT 24
Finished Aug 02 06:44:33 PM PDT 24
Peak memory 223604 kb
Host smart-20f9dafb-2eb0-42c0-a3d8-3878bfe64b06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3178126199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3178126199
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1910693775
Short name T84
Test name
Test status
Simulation time 371937022 ps
CPU time 1.19 seconds
Started Aug 02 06:44:27 PM PDT 24
Finished Aug 02 06:44:29 PM PDT 24
Peak memory 237988 kb
Host smart-26452bd7-d606-40d8-94b6-b3cdeefda643
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910693775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1910693775
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2066191160
Short name T716
Test name
Test status
Simulation time 2110478769 ps
CPU time 29.87 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:54 PM PDT 24
Peak memory 224868 kb
Host smart-99284a36-3939-4afe-9d47-7c28e56664d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066191160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2066191160
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4247350605
Short name T321
Test name
Test status
Simulation time 5835988501 ps
CPU time 38.65 seconds
Started Aug 02 06:44:22 PM PDT 24
Finished Aug 02 06:45:01 PM PDT 24
Peak memory 221340 kb
Host smart-4cafb782-530c-4aac-8840-410fd308dfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247350605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4247350605
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2495754967
Short name T882
Test name
Test status
Simulation time 976896333 ps
CPU time 6.28 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:31 PM PDT 24
Peak memory 216680 kb
Host smart-ec863582-2dfa-4fca-94df-ec78d2808407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495754967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2495754967
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1988905461
Short name T498
Test name
Test status
Simulation time 17950533 ps
CPU time 0.69 seconds
Started Aug 02 06:44:22 PM PDT 24
Finished Aug 02 06:44:23 PM PDT 24
Peak memory 206004 kb
Host smart-672eb21a-cb6e-4a14-9d93-b5e2a41d375b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988905461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1988905461
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2871018772
Short name T415
Test name
Test status
Simulation time 254303025 ps
CPU time 0.89 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:26 PM PDT 24
Peak memory 206412 kb
Host smart-325cd9af-4f27-44a4-9c60-2e71d0048a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871018772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2871018772
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3429499403
Short name T782
Test name
Test status
Simulation time 622170094 ps
CPU time 3.86 seconds
Started Aug 02 06:44:24 PM PDT 24
Finished Aug 02 06:44:27 PM PDT 24
Peak memory 233120 kb
Host smart-aaae49da-041c-4a0d-b6a3-751f56a3b009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429499403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3429499403
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3740097230
Short name T795
Test name
Test status
Simulation time 43514938 ps
CPU time 0.69 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:46:36 PM PDT 24
Peak memory 205832 kb
Host smart-38048e8a-9606-478c-bc65-edaeab18ef49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740097230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3740097230
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.252062514
Short name T624
Test name
Test status
Simulation time 643701753 ps
CPU time 4.22 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:46:40 PM PDT 24
Peak memory 224892 kb
Host smart-7c229f96-4f20-483e-bb66-0cfceb56f02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252062514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.252062514
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1579854490
Short name T480
Test name
Test status
Simulation time 68984480 ps
CPU time 0.8 seconds
Started Aug 02 06:46:27 PM PDT 24
Finished Aug 02 06:46:28 PM PDT 24
Peak memory 207200 kb
Host smart-3fa6e8be-d8f0-4363-8035-30bb605b51d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579854490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1579854490
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.617165289
Short name T799
Test name
Test status
Simulation time 12592008285 ps
CPU time 70.26 seconds
Started Aug 02 06:46:39 PM PDT 24
Finished Aug 02 06:47:49 PM PDT 24
Peak memory 253252 kb
Host smart-af2ec661-332c-4736-a500-070b9eeaab2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617165289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.617165289
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2824534823
Short name T918
Test name
Test status
Simulation time 22706248032 ps
CPU time 135.77 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:48:51 PM PDT 24
Peak memory 251740 kb
Host smart-132a9021-0f34-4f45-a0b5-bacf36218024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824534823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2824534823
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4038982965
Short name T146
Test name
Test status
Simulation time 258732767 ps
CPU time 7.22 seconds
Started Aug 02 06:46:32 PM PDT 24
Finished Aug 02 06:46:40 PM PDT 24
Peak memory 241320 kb
Host smart-4ac9f234-81a4-4c3c-83fd-7fe3c49a3e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038982965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4038982965
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3071833276
Short name T260
Test name
Test status
Simulation time 27976729780 ps
CPU time 104.31 seconds
Started Aug 02 06:46:37 PM PDT 24
Finished Aug 02 06:48:21 PM PDT 24
Peak memory 250684 kb
Host smart-3c60f0cf-9bd9-4ae0-9356-f1bb0adaf89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071833276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3071833276
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1697848438
Short name T718
Test name
Test status
Simulation time 10028313569 ps
CPU time 23.74 seconds
Started Aug 02 06:46:36 PM PDT 24
Finished Aug 02 06:47:00 PM PDT 24
Peak memory 233200 kb
Host smart-59820895-540c-4f1b-8c87-d9e0fc04f171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697848438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1697848438
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3584708814
Short name T643
Test name
Test status
Simulation time 10811164941 ps
CPU time 92.87 seconds
Started Aug 02 06:46:40 PM PDT 24
Finished Aug 02 06:48:13 PM PDT 24
Peak memory 233248 kb
Host smart-9b45dc9c-052a-42bd-a94b-74d5dbdd852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584708814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3584708814
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1611386495
Short name T908
Test name
Test status
Simulation time 1092668509 ps
CPU time 8.22 seconds
Started Aug 02 06:46:34 PM PDT 24
Finished Aug 02 06:46:42 PM PDT 24
Peak memory 241336 kb
Host smart-5b6ae7d9-bec8-432b-8042-42363701ef17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611386495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1611386495
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2890410122
Short name T8
Test name
Test status
Simulation time 1191738323 ps
CPU time 5.19 seconds
Started Aug 02 06:46:34 PM PDT 24
Finished Aug 02 06:46:40 PM PDT 24
Peak memory 224972 kb
Host smart-719f9228-ce38-4bd6-bd61-eae3d0162f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890410122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2890410122
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3198573959
Short name T727
Test name
Test status
Simulation time 1190761565 ps
CPU time 5.68 seconds
Started Aug 02 06:46:38 PM PDT 24
Finished Aug 02 06:46:43 PM PDT 24
Peak memory 223112 kb
Host smart-5113986e-203f-4ac9-84d3-207cd418868e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3198573959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3198573959
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3300200847
Short name T295
Test name
Test status
Simulation time 65335191480 ps
CPU time 267.74 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:51:03 PM PDT 24
Peak memory 254040 kb
Host smart-a402e820-a76e-4d22-824c-cc1eee5be0ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300200847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3300200847
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4214514356
Short name T654
Test name
Test status
Simulation time 1645825991 ps
CPU time 24.45 seconds
Started Aug 02 06:46:38 PM PDT 24
Finished Aug 02 06:47:02 PM PDT 24
Peak memory 219872 kb
Host smart-523ee473-6216-4a74-ae7c-3a562f7de557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214514356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4214514356
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1986039014
Short name T768
Test name
Test status
Simulation time 651398925 ps
CPU time 2.62 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:46:38 PM PDT 24
Peak memory 208184 kb
Host smart-be45b171-650c-44a9-b23e-7b953095c2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986039014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1986039014
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.243846650
Short name T960
Test name
Test status
Simulation time 38656162 ps
CPU time 0.7 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:46:36 PM PDT 24
Peak memory 206060 kb
Host smart-115701d8-c377-4d28-a38a-8aec0331f38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243846650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.243846650
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3237749860
Short name T905
Test name
Test status
Simulation time 101654557 ps
CPU time 0.83 seconds
Started Aug 02 06:46:37 PM PDT 24
Finished Aug 02 06:46:38 PM PDT 24
Peak memory 206360 kb
Host smart-149384ef-6ce6-4643-b52f-a137663914c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237749860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3237749860
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3520076873
Short name T4
Test name
Test status
Simulation time 8394441887 ps
CPU time 27.58 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:47:03 PM PDT 24
Peak memory 233208 kb
Host smart-d762d57d-f1b7-4b4f-a1fb-62c1cc6f608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520076873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3520076873
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1888841027
Short name T89
Test name
Test status
Simulation time 15788542 ps
CPU time 0.72 seconds
Started Aug 02 06:46:40 PM PDT 24
Finished Aug 02 06:46:40 PM PDT 24
Peak memory 205316 kb
Host smart-26943c6d-7c9f-4426-92cb-cd306314e67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888841027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1888841027
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2087246968
Short name T510
Test name
Test status
Simulation time 2204180840 ps
CPU time 6 seconds
Started Aug 02 06:46:36 PM PDT 24
Finished Aug 02 06:46:42 PM PDT 24
Peak memory 233208 kb
Host smart-a97d676b-5699-49bd-b797-88ada9015e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087246968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2087246968
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.619952126
Short name T819
Test name
Test status
Simulation time 150431852 ps
CPU time 0.8 seconds
Started Aug 02 06:46:37 PM PDT 24
Finished Aug 02 06:46:38 PM PDT 24
Peak memory 207044 kb
Host smart-1ba17a53-d376-4f1f-b7ba-551603e26715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619952126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.619952126
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.584197779
Short name T300
Test name
Test status
Simulation time 209199590343 ps
CPU time 299.39 seconds
Started Aug 02 06:46:36 PM PDT 24
Finished Aug 02 06:51:35 PM PDT 24
Peak memory 252728 kb
Host smart-b453cc4a-f20d-424a-9d40-f4b5b929f58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584197779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.584197779
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1055750979
Short name T845
Test name
Test status
Simulation time 63979559584 ps
CPU time 610.52 seconds
Started Aug 02 06:46:38 PM PDT 24
Finished Aug 02 06:56:49 PM PDT 24
Peak memory 264264 kb
Host smart-25c131b4-522c-45f9-8f13-eb46343e5e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055750979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1055750979
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.694730959
Short name T235
Test name
Test status
Simulation time 779370274 ps
CPU time 16.29 seconds
Started Aug 02 06:46:37 PM PDT 24
Finished Aug 02 06:46:53 PM PDT 24
Peak memory 224912 kb
Host smart-44b7036b-a2fa-415a-8023-3c106481eb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694730959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.694730959
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.319769039
Short name T291
Test name
Test status
Simulation time 34081018320 ps
CPU time 143.12 seconds
Started Aug 02 06:46:36 PM PDT 24
Finished Aug 02 06:48:59 PM PDT 24
Peak memory 251356 kb
Host smart-096b44b5-cd29-4768-9a1d-1bf6d9964106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319769039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.319769039
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1210654894
Short name T810
Test name
Test status
Simulation time 142468066 ps
CPU time 3.15 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:46:38 PM PDT 24
Peak memory 224836 kb
Host smart-3dcd6c7a-29ac-4ef7-8a78-5c094b83f57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210654894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1210654894
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2065671542
Short name T616
Test name
Test status
Simulation time 465896845 ps
CPU time 10.13 seconds
Started Aug 02 06:46:36 PM PDT 24
Finished Aug 02 06:46:46 PM PDT 24
Peak memory 240992 kb
Host smart-32822b15-b571-4d85-9f14-21968c21f671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065671542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2065671542
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.590087307
Short name T269
Test name
Test status
Simulation time 2040276809 ps
CPU time 8.63 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:46:44 PM PDT 24
Peak memory 224912 kb
Host smart-4d711163-57da-4826-9f0b-d4bc6935c0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590087307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.590087307
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1714180194
Short name T147
Test name
Test status
Simulation time 4941440234 ps
CPU time 10.72 seconds
Started Aug 02 06:46:37 PM PDT 24
Finished Aug 02 06:46:48 PM PDT 24
Peak memory 249072 kb
Host smart-720d1b83-497c-4b63-ae4e-8a6c2b47f9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714180194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1714180194
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1886755784
Short name T361
Test name
Test status
Simulation time 358106352 ps
CPU time 4.13 seconds
Started Aug 02 06:46:38 PM PDT 24
Finished Aug 02 06:46:42 PM PDT 24
Peak memory 223616 kb
Host smart-c0a61af4-4dc4-4bfa-97ff-40e34e9dc7d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1886755784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1886755784
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1130309996
Short name T13
Test name
Test status
Simulation time 6493319358 ps
CPU time 109.74 seconds
Started Aug 02 06:46:36 PM PDT 24
Finished Aug 02 06:48:26 PM PDT 24
Peak memory 266068 kb
Host smart-131beff3-9533-447f-9a43-342db16b72c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130309996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1130309996
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.820385051
Short name T913
Test name
Test status
Simulation time 4834305255 ps
CPU time 27.68 seconds
Started Aug 02 06:46:37 PM PDT 24
Finished Aug 02 06:47:05 PM PDT 24
Peak memory 216756 kb
Host smart-82c1f34e-48a0-41e7-8e10-a57fa8a2725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820385051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.820385051
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1963118882
Short name T354
Test name
Test status
Simulation time 1559205607 ps
CPU time 5.01 seconds
Started Aug 02 06:46:37 PM PDT 24
Finished Aug 02 06:46:43 PM PDT 24
Peak memory 216632 kb
Host smart-96eb21a7-aca0-46f3-85fd-bf2700082fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963118882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1963118882
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2577217838
Short name T365
Test name
Test status
Simulation time 1234411175 ps
CPU time 1.27 seconds
Started Aug 02 06:46:38 PM PDT 24
Finished Aug 02 06:46:39 PM PDT 24
Peak memory 208480 kb
Host smart-f35824e6-c333-44fd-b1c3-c6ad26cc803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577217838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2577217838
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1269110168
Short name T430
Test name
Test status
Simulation time 32924387 ps
CPU time 0.85 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:46:36 PM PDT 24
Peak memory 206328 kb
Host smart-afc9e83d-28fc-47db-b5ba-fd59331fa5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269110168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1269110168
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2930897501
Short name T743
Test name
Test status
Simulation time 24905038634 ps
CPU time 22.39 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:46:58 PM PDT 24
Peak memory 240616 kb
Host smart-763c4828-6c36-477f-a331-0cbaa2df4706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930897501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2930897501
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3512147223
Short name T558
Test name
Test status
Simulation time 33338877 ps
CPU time 0.72 seconds
Started Aug 02 06:46:41 PM PDT 24
Finished Aug 02 06:46:42 PM PDT 24
Peak memory 205164 kb
Host smart-7e1dd0f5-3369-4ba3-a1d4-a8252a689339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512147223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3512147223
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2063376964
Short name T436
Test name
Test status
Simulation time 2147125400 ps
CPU time 7.29 seconds
Started Aug 02 06:46:36 PM PDT 24
Finished Aug 02 06:46:44 PM PDT 24
Peak memory 224964 kb
Host smart-94c47e5a-bb79-4619-a736-105a1b6ce33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063376964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2063376964
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3655859042
Short name T334
Test name
Test status
Simulation time 39636350 ps
CPU time 0.78 seconds
Started Aug 02 06:46:35 PM PDT 24
Finished Aug 02 06:46:35 PM PDT 24
Peak memory 207296 kb
Host smart-b18b03a5-b767-440c-95c0-2998f109da0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655859042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3655859042
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.775989430
Short name T849
Test name
Test status
Simulation time 25104218038 ps
CPU time 89.6 seconds
Started Aug 02 06:46:40 PM PDT 24
Finished Aug 02 06:48:09 PM PDT 24
Peak memory 249592 kb
Host smart-a39d9a6c-f1c5-475d-99d2-b014efe1308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775989430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.775989430
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.62978604
Short name T31
Test name
Test status
Simulation time 22466434772 ps
CPU time 202.27 seconds
Started Aug 02 06:46:38 PM PDT 24
Finished Aug 02 06:50:00 PM PDT 24
Peak memory 250700 kb
Host smart-aa6bdac2-c227-423f-8251-2fe9b7183b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62978604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.62978604
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2066349341
Short name T830
Test name
Test status
Simulation time 11523030933 ps
CPU time 125.01 seconds
Started Aug 02 06:46:43 PM PDT 24
Finished Aug 02 06:48:48 PM PDT 24
Peak memory 265984 kb
Host smart-0ccac14d-56b8-486b-b4b2-25a10ba03e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066349341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2066349341
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3307561360
Short name T45
Test name
Test status
Simulation time 106117890 ps
CPU time 3.94 seconds
Started Aug 02 06:46:42 PM PDT 24
Finished Aug 02 06:46:46 PM PDT 24
Peak memory 224924 kb
Host smart-1012aaa7-aa2a-4a81-a861-877a697ecdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307561360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3307561360
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2111626884
Short name T94
Test name
Test status
Simulation time 12238124565 ps
CPU time 11.23 seconds
Started Aug 02 06:46:38 PM PDT 24
Finished Aug 02 06:46:49 PM PDT 24
Peak memory 233268 kb
Host smart-81f1364f-4049-430e-8c92-d3ceddd88b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111626884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2111626884
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3537287171
Short name T92
Test name
Test status
Simulation time 813964204 ps
CPU time 3.95 seconds
Started Aug 02 06:46:40 PM PDT 24
Finished Aug 02 06:46:44 PM PDT 24
Peak memory 224856 kb
Host smart-f9a58261-ae3f-4193-aaa2-687efb4aec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537287171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3537287171
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2120982934
Short name T258
Test name
Test status
Simulation time 23430535773 ps
CPU time 128.73 seconds
Started Aug 02 06:46:49 PM PDT 24
Finished Aug 02 06:48:58 PM PDT 24
Peak memory 241440 kb
Host smart-789d0681-aae2-47fa-a9ba-c9eabc4c4e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120982934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2120982934
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3516465657
Short name T297
Test name
Test status
Simulation time 8293480576 ps
CPU time 23.91 seconds
Started Aug 02 06:46:41 PM PDT 24
Finished Aug 02 06:47:05 PM PDT 24
Peak memory 233204 kb
Host smart-55fd8dd8-249c-4162-9f85-dedb1139ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516465657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3516465657
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.610496948
Short name T686
Test name
Test status
Simulation time 4812196076 ps
CPU time 8.14 seconds
Started Aug 02 06:46:41 PM PDT 24
Finished Aug 02 06:46:49 PM PDT 24
Peak memory 225064 kb
Host smart-cc4e825f-ca50-46b6-9cb6-c29f73eee746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610496948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.610496948
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.134467752
Short name T417
Test name
Test status
Simulation time 705588002 ps
CPU time 3.91 seconds
Started Aug 02 06:46:45 PM PDT 24
Finished Aug 02 06:46:49 PM PDT 24
Peak memory 220720 kb
Host smart-9dfb191f-59f5-4bf6-a1ce-d3ae854c9ab8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=134467752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.134467752
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3149036566
Short name T438
Test name
Test status
Simulation time 392652400 ps
CPU time 1 seconds
Started Aug 02 06:46:41 PM PDT 24
Finished Aug 02 06:46:42 PM PDT 24
Peak memory 207312 kb
Host smart-fe2673df-4afd-492f-bb76-87c8360188b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149036566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3149036566
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1121755865
Short name T414
Test name
Test status
Simulation time 25499280 ps
CPU time 0.75 seconds
Started Aug 02 06:46:38 PM PDT 24
Finished Aug 02 06:46:39 PM PDT 24
Peak memory 206172 kb
Host smart-224c1aaf-9085-4f72-873a-c982ae648467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121755865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1121755865
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1648447442
Short name T525
Test name
Test status
Simulation time 27753403 ps
CPU time 0.71 seconds
Started Aug 02 06:46:34 PM PDT 24
Finished Aug 02 06:46:35 PM PDT 24
Peak memory 206072 kb
Host smart-1ad84a9b-88df-48b0-9caa-47532ff2051e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648447442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1648447442
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2130539749
Short name T328
Test name
Test status
Simulation time 51490760 ps
CPU time 1.2 seconds
Started Aug 02 06:46:43 PM PDT 24
Finished Aug 02 06:46:44 PM PDT 24
Peak memory 216588 kb
Host smart-00a4c095-2e03-4349-93e5-77fc91e75674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130539749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2130539749
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2325328714
Short name T379
Test name
Test status
Simulation time 125359123 ps
CPU time 1.06 seconds
Started Aug 02 06:46:49 PM PDT 24
Finished Aug 02 06:46:50 PM PDT 24
Peak memory 207420 kb
Host smart-10b9a1d2-6117-4b7b-9d5a-56f3b31c7349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325328714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2325328714
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2569908258
Short name T789
Test name
Test status
Simulation time 194997994 ps
CPU time 3.42 seconds
Started Aug 02 06:46:49 PM PDT 24
Finished Aug 02 06:46:52 PM PDT 24
Peak memory 224916 kb
Host smart-49dd172f-d11e-4e02-ba60-3748a32cde9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569908258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2569908258
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.949970989
Short name T864
Test name
Test status
Simulation time 13236325 ps
CPU time 0.71 seconds
Started Aug 02 06:46:42 PM PDT 24
Finished Aug 02 06:46:43 PM PDT 24
Peak memory 205820 kb
Host smart-260b2a9b-69ba-4f59-b326-c3735eba4572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949970989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.949970989
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2836634052
Short name T50
Test name
Test status
Simulation time 193491963 ps
CPU time 4 seconds
Started Aug 02 06:46:49 PM PDT 24
Finished Aug 02 06:46:53 PM PDT 24
Peak memory 233176 kb
Host smart-38938898-e9a1-4399-a867-7c0c2db38634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836634052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2836634052
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4110510730
Short name T659
Test name
Test status
Simulation time 66654905 ps
CPU time 0.84 seconds
Started Aug 02 06:46:45 PM PDT 24
Finished Aug 02 06:46:45 PM PDT 24
Peak memory 207312 kb
Host smart-96dbc18e-dc36-4845-b6c6-e2572faf5b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110510730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4110510730
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.195887770
Short name T838
Test name
Test status
Simulation time 15591166839 ps
CPU time 64.31 seconds
Started Aug 02 06:46:42 PM PDT 24
Finished Aug 02 06:47:47 PM PDT 24
Peak memory 250624 kb
Host smart-52308718-b38d-430a-be06-0b71ee4b2e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195887770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.195887770
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3256017207
Short name T955
Test name
Test status
Simulation time 2458170080 ps
CPU time 50.05 seconds
Started Aug 02 06:46:49 PM PDT 24
Finished Aug 02 06:47:40 PM PDT 24
Peak memory 241476 kb
Host smart-311ef1c9-6cf1-45fc-848a-e0b102ff0c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256017207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3256017207
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4230972580
Short name T200
Test name
Test status
Simulation time 14229804081 ps
CPU time 156.37 seconds
Started Aug 02 06:46:48 PM PDT 24
Finished Aug 02 06:49:24 PM PDT 24
Peak memory 250052 kb
Host smart-e07592c0-ee03-4565-8d6e-32c6e76f25cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230972580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4230972580
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.462761681
Short name T362
Test name
Test status
Simulation time 374138647 ps
CPU time 5.96 seconds
Started Aug 02 06:46:42 PM PDT 24
Finished Aug 02 06:46:48 PM PDT 24
Peak memory 233096 kb
Host smart-1af856fc-21f9-416b-a5cc-902b5ca52264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462761681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.462761681
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3205216398
Short name T719
Test name
Test status
Simulation time 600670015 ps
CPU time 5.75 seconds
Started Aug 02 06:46:43 PM PDT 24
Finished Aug 02 06:46:49 PM PDT 24
Peak memory 235608 kb
Host smart-91541d5f-ad74-4c33-a861-edc3d47d0d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205216398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3205216398
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3125476679
Short name T240
Test name
Test status
Simulation time 2957755004 ps
CPU time 13.67 seconds
Started Aug 02 06:46:42 PM PDT 24
Finished Aug 02 06:46:56 PM PDT 24
Peak memory 233204 kb
Host smart-da7393e4-e8d6-4ee1-bd29-dcee832c8fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125476679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3125476679
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4276567634
Short name T358
Test name
Test status
Simulation time 23554368780 ps
CPU time 21 seconds
Started Aug 02 06:46:38 PM PDT 24
Finished Aug 02 06:47:00 PM PDT 24
Peak memory 224968 kb
Host smart-c0653310-c62c-42cc-8c8b-cf0637a3e68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276567634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4276567634
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2090511458
Short name T793
Test name
Test status
Simulation time 8067618717 ps
CPU time 6.55 seconds
Started Aug 02 06:46:44 PM PDT 24
Finished Aug 02 06:46:50 PM PDT 24
Peak memory 225004 kb
Host smart-7d7b5b96-cfc8-43e3-8a32-141a0a16d600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090511458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2090511458
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.163710120
Short name T551
Test name
Test status
Simulation time 9662715677 ps
CPU time 26.4 seconds
Started Aug 02 06:46:43 PM PDT 24
Finished Aug 02 06:47:10 PM PDT 24
Peak memory 233144 kb
Host smart-58504a79-5cf8-4b41-a535-b796a3031c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163710120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.163710120
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4271391840
Short name T1006
Test name
Test status
Simulation time 659556397 ps
CPU time 4.03 seconds
Started Aug 02 06:46:42 PM PDT 24
Finished Aug 02 06:46:46 PM PDT 24
Peak memory 219276 kb
Host smart-014f5794-dde3-4a97-bd12-78495ab657d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4271391840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4271391840
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1864077888
Short name T18
Test name
Test status
Simulation time 3412479864 ps
CPU time 75.15 seconds
Started Aug 02 06:46:43 PM PDT 24
Finished Aug 02 06:47:58 PM PDT 24
Peak memory 254820 kb
Host smart-eda8256e-1e06-49f2-b592-831d16687448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864077888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1864077888
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.739841842
Short name T951
Test name
Test status
Simulation time 9002592637 ps
CPU time 13.04 seconds
Started Aug 02 06:46:39 PM PDT 24
Finished Aug 02 06:46:53 PM PDT 24
Peak memory 216796 kb
Host smart-39d09741-1d32-4631-a544-e17d1224ab30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739841842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.739841842
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4200777092
Short name T351
Test name
Test status
Simulation time 28108316768 ps
CPU time 21.09 seconds
Started Aug 02 06:46:41 PM PDT 24
Finished Aug 02 06:47:03 PM PDT 24
Peak memory 216628 kb
Host smart-818e3d09-fe72-441c-8794-ddde1b7e4afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200777092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4200777092
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3232109295
Short name T324
Test name
Test status
Simulation time 73441357 ps
CPU time 0.98 seconds
Started Aug 02 06:46:38 PM PDT 24
Finished Aug 02 06:46:39 PM PDT 24
Peak memory 207416 kb
Host smart-e78b0ee4-cb3e-42dc-a16e-8331bb6e8f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232109295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3232109295
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2010991204
Short name T439
Test name
Test status
Simulation time 94935085 ps
CPU time 0.88 seconds
Started Aug 02 06:46:43 PM PDT 24
Finished Aug 02 06:46:44 PM PDT 24
Peak memory 206328 kb
Host smart-85ca4f0e-a382-4023-972f-3359350a445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010991204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2010991204
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.4145397468
Short name T485
Test name
Test status
Simulation time 19587091732 ps
CPU time 5.44 seconds
Started Aug 02 06:46:38 PM PDT 24
Finished Aug 02 06:46:44 PM PDT 24
Peak memory 233236 kb
Host smart-2093521f-5de9-484f-aef6-57348848fc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145397468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.4145397468
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3717165168
Short name T957
Test name
Test status
Simulation time 20176265 ps
CPU time 0.78 seconds
Started Aug 02 06:46:51 PM PDT 24
Finished Aug 02 06:46:52 PM PDT 24
Peak memory 205868 kb
Host smart-a0e7d6c3-749a-40b7-9510-39cb8354c629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717165168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3717165168
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.880445087
Short name T570
Test name
Test status
Simulation time 109969772 ps
CPU time 2.33 seconds
Started Aug 02 06:46:47 PM PDT 24
Finished Aug 02 06:46:51 PM PDT 24
Peak memory 232788 kb
Host smart-c335a677-f420-4462-9ca3-72ebe2363b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880445087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.880445087
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2733856267
Short name T571
Test name
Test status
Simulation time 172358090 ps
CPU time 0.85 seconds
Started Aug 02 06:46:42 PM PDT 24
Finished Aug 02 06:46:43 PM PDT 24
Peak memory 207004 kb
Host smart-ff499a1d-9d56-4671-9d46-a95e7cca4d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733856267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2733856267
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1690449694
Short name T979
Test name
Test status
Simulation time 21811448 ps
CPU time 0.77 seconds
Started Aug 02 06:46:48 PM PDT 24
Finished Aug 02 06:46:49 PM PDT 24
Peak memory 216204 kb
Host smart-b29b9dd7-8488-44ca-8d6d-6bf4b747f14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690449694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1690449694
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3969539301
Short name T1002
Test name
Test status
Simulation time 7204906568 ps
CPU time 90.31 seconds
Started Aug 02 06:46:47 PM PDT 24
Finished Aug 02 06:48:18 PM PDT 24
Peak memory 255840 kb
Host smart-5979b6b5-ee68-41f6-a383-295b70c7f774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969539301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3969539301
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4254415314
Short name T598
Test name
Test status
Simulation time 29196720581 ps
CPU time 125.41 seconds
Started Aug 02 06:46:56 PM PDT 24
Finished Aug 02 06:49:01 PM PDT 24
Peak memory 252988 kb
Host smart-71395edc-d721-424e-8d10-e9dbf568e207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254415314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4254415314
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.426637595
Short name T347
Test name
Test status
Simulation time 97285538 ps
CPU time 4.38 seconds
Started Aug 02 06:46:46 PM PDT 24
Finished Aug 02 06:46:51 PM PDT 24
Peak memory 236424 kb
Host smart-a40c4482-bb3b-474c-bb7b-1846afdda968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426637595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.426637595
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3062665930
Short name T305
Test name
Test status
Simulation time 11103778880 ps
CPU time 67.5 seconds
Started Aug 02 06:46:52 PM PDT 24
Finished Aug 02 06:48:00 PM PDT 24
Peak memory 250696 kb
Host smart-58144c87-c0d9-4e47-b3ac-7f96250ff852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062665930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3062665930
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1615615632
Short name T959
Test name
Test status
Simulation time 5647715549 ps
CPU time 24.55 seconds
Started Aug 02 06:46:43 PM PDT 24
Finished Aug 02 06:47:07 PM PDT 24
Peak memory 224928 kb
Host smart-ce6cdc80-deac-4664-a698-f1bead1448cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615615632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1615615632
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1554457435
Short name T919
Test name
Test status
Simulation time 2219510419 ps
CPU time 6.35 seconds
Started Aug 02 06:46:51 PM PDT 24
Finished Aug 02 06:46:57 PM PDT 24
Peak memory 233216 kb
Host smart-2e27dbee-85a0-44dc-80f7-93921e3fbeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554457435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1554457435
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1236579251
Short name T797
Test name
Test status
Simulation time 3404605037 ps
CPU time 8.42 seconds
Started Aug 02 06:46:43 PM PDT 24
Finished Aug 02 06:46:51 PM PDT 24
Peak memory 233192 kb
Host smart-5048528f-68bb-43b0-af80-78c3a5d76646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236579251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1236579251
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2492035019
Short name T953
Test name
Test status
Simulation time 8063289915 ps
CPU time 21.8 seconds
Started Aug 02 06:46:45 PM PDT 24
Finished Aug 02 06:47:06 PM PDT 24
Peak memory 233280 kb
Host smart-10fe602b-a204-40f4-9c75-b3b09321553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492035019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2492035019
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3504433892
Short name T452
Test name
Test status
Simulation time 1435844151 ps
CPU time 4.31 seconds
Started Aug 02 06:46:46 PM PDT 24
Finished Aug 02 06:46:50 PM PDT 24
Peak memory 224000 kb
Host smart-edc018eb-76df-421f-a394-9a56c8397be2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3504433892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3504433892
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.916350442
Short name T666
Test name
Test status
Simulation time 194599663657 ps
CPU time 312.92 seconds
Started Aug 02 06:46:47 PM PDT 24
Finished Aug 02 06:52:00 PM PDT 24
Peak memory 256592 kb
Host smart-cefff45a-6857-4c04-9d26-ebc81196bead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916350442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.916350442
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1476924507
Short name T541
Test name
Test status
Simulation time 9791595223 ps
CPU time 15.86 seconds
Started Aug 02 06:46:42 PM PDT 24
Finished Aug 02 06:46:58 PM PDT 24
Peak memory 216764 kb
Host smart-8a597449-e8dc-4d48-b6d5-92b59e688425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476924507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1476924507
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3588453420
Short name T73
Test name
Test status
Simulation time 68135321 ps
CPU time 0.73 seconds
Started Aug 02 06:46:44 PM PDT 24
Finished Aug 02 06:46:45 PM PDT 24
Peak memory 206128 kb
Host smart-f7828964-7bc3-4a45-9bd0-d9a0e8febbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588453420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3588453420
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2814586295
Short name T737
Test name
Test status
Simulation time 41973036 ps
CPU time 2.43 seconds
Started Aug 02 06:46:48 PM PDT 24
Finished Aug 02 06:46:51 PM PDT 24
Peak memory 216712 kb
Host smart-5e287812-28f7-4b33-bc64-29fc903e2f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814586295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2814586295
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.194452601
Short name T792
Test name
Test status
Simulation time 184571883 ps
CPU time 0.95 seconds
Started Aug 02 06:46:42 PM PDT 24
Finished Aug 02 06:46:43 PM PDT 24
Peak memory 207384 kb
Host smart-492df2d3-99ce-49c9-8cbd-725cac4dd620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194452601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.194452601
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.771104742
Short name T988
Test name
Test status
Simulation time 1814415476 ps
CPU time 9.49 seconds
Started Aug 02 06:46:46 PM PDT 24
Finished Aug 02 06:46:56 PM PDT 24
Peak memory 224924 kb
Host smart-4f7fa582-3af3-4704-8c6e-2ddf934273f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771104742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.771104742
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3612761159
Short name T651
Test name
Test status
Simulation time 22350285 ps
CPU time 0.7 seconds
Started Aug 02 06:46:48 PM PDT 24
Finished Aug 02 06:46:49 PM PDT 24
Peak memory 205864 kb
Host smart-8f1be1f6-6577-482e-beea-99262dfc5836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612761159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3612761159
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2506526842
Short name T669
Test name
Test status
Simulation time 1304286702 ps
CPU time 9.7 seconds
Started Aug 02 06:46:56 PM PDT 24
Finished Aug 02 06:47:06 PM PDT 24
Peak memory 233160 kb
Host smart-bdd7faf5-17d7-4d90-80e1-d2eaca56fd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506526842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2506526842
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2330026757
Short name T490
Test name
Test status
Simulation time 42322525 ps
CPU time 0.74 seconds
Started Aug 02 06:46:48 PM PDT 24
Finished Aug 02 06:46:49 PM PDT 24
Peak memory 205948 kb
Host smart-9f6ac433-2f26-42c4-a4ab-27b235e4da92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330026757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2330026757
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1731140047
Short name T698
Test name
Test status
Simulation time 26828754445 ps
CPU time 50.98 seconds
Started Aug 02 06:46:47 PM PDT 24
Finished Aug 02 06:47:38 PM PDT 24
Peak memory 252776 kb
Host smart-91ce2d82-a1a9-4d46-9401-ec96c08c3f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731140047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1731140047
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3289595368
Short name T216
Test name
Test status
Simulation time 13013781617 ps
CPU time 138.52 seconds
Started Aug 02 06:46:49 PM PDT 24
Finished Aug 02 06:49:08 PM PDT 24
Peak memory 249664 kb
Host smart-6ef7e44d-407b-497d-887c-52a684592c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289595368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3289595368
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1771418653
Short name T560
Test name
Test status
Simulation time 12502659841 ps
CPU time 64.54 seconds
Started Aug 02 06:46:51 PM PDT 24
Finished Aug 02 06:47:56 PM PDT 24
Peak memory 250708 kb
Host smart-c96923a1-e7c0-46b6-8599-ec2f6fd5ca6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771418653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1771418653
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2200834117
Short name T628
Test name
Test status
Simulation time 6067399494 ps
CPU time 7.69 seconds
Started Aug 02 06:46:51 PM PDT 24
Finished Aug 02 06:46:59 PM PDT 24
Peak memory 224976 kb
Host smart-ff7ee2c5-c56b-4a70-bcf9-c621274dc085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200834117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2200834117
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1492305822
Short name T530
Test name
Test status
Simulation time 102749075031 ps
CPU time 187.4 seconds
Started Aug 02 06:46:48 PM PDT 24
Finished Aug 02 06:49:55 PM PDT 24
Peak memory 257244 kb
Host smart-df536cf0-8c6f-447b-9919-ae10845ac8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492305822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1492305822
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3863531444
Short name T948
Test name
Test status
Simulation time 572718624 ps
CPU time 6.11 seconds
Started Aug 02 06:46:51 PM PDT 24
Finished Aug 02 06:46:57 PM PDT 24
Peak memory 224852 kb
Host smart-d58f6005-ce49-450b-a5a8-e915c6f05180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863531444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3863531444
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2676755761
Short name T910
Test name
Test status
Simulation time 34949294621 ps
CPU time 104.53 seconds
Started Aug 02 06:46:47 PM PDT 24
Finished Aug 02 06:48:32 PM PDT 24
Peak memory 231428 kb
Host smart-cc521f74-5e1c-4118-a891-fd12b4923c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676755761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2676755761
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3819288984
Short name T916
Test name
Test status
Simulation time 9444908162 ps
CPU time 18.18 seconds
Started Aug 02 06:46:46 PM PDT 24
Finished Aug 02 06:47:04 PM PDT 24
Peak memory 233240 kb
Host smart-c368ac28-3555-4518-bd05-88e2cb55e733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819288984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3819288984
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2918232862
Short name T332
Test name
Test status
Simulation time 74381933 ps
CPU time 2.5 seconds
Started Aug 02 06:46:46 PM PDT 24
Finished Aug 02 06:46:49 PM PDT 24
Peak memory 224496 kb
Host smart-36623d27-75f1-4c3f-b656-ff24a1020742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918232862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2918232862
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.112792052
Short name T448
Test name
Test status
Simulation time 505853487 ps
CPU time 6.46 seconds
Started Aug 02 06:46:52 PM PDT 24
Finished Aug 02 06:46:59 PM PDT 24
Peak memory 223632 kb
Host smart-f14b8e5d-ee10-4952-b59a-75c0cea2edfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=112792052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.112792052
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3902781847
Short name T897
Test name
Test status
Simulation time 44943054580 ps
CPU time 199.68 seconds
Started Aug 02 06:46:47 PM PDT 24
Finished Aug 02 06:50:07 PM PDT 24
Peak memory 253900 kb
Host smart-e6e04293-414d-42fd-a77f-383daddb6362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902781847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3902781847
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4159351642
Short name T34
Test name
Test status
Simulation time 5588907715 ps
CPU time 31.24 seconds
Started Aug 02 06:46:47 PM PDT 24
Finished Aug 02 06:47:18 PM PDT 24
Peak memory 216712 kb
Host smart-a1a4980b-25a9-4664-9136-c794d990d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159351642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4159351642
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.130676999
Short name T464
Test name
Test status
Simulation time 7897138684 ps
CPU time 8.04 seconds
Started Aug 02 06:46:46 PM PDT 24
Finished Aug 02 06:46:55 PM PDT 24
Peak memory 216768 kb
Host smart-afc8be24-ec54-445e-a72b-1cc4f8ec0ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130676999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.130676999
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.600336777
Short name T171
Test name
Test status
Simulation time 95843719 ps
CPU time 2.08 seconds
Started Aug 02 06:46:56 PM PDT 24
Finished Aug 02 06:46:58 PM PDT 24
Peak memory 216612 kb
Host smart-1c95f0a8-edb7-4c59-afac-3b3826e80e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600336777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.600336777
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1458582510
Short name T529
Test name
Test status
Simulation time 12537737 ps
CPU time 0.71 seconds
Started Aug 02 06:46:46 PM PDT 24
Finished Aug 02 06:46:47 PM PDT 24
Peak memory 206416 kb
Host smart-a4568451-11a2-43f8-9175-0ebba6bec504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458582510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1458582510
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.4152257424
Short name T633
Test name
Test status
Simulation time 11511509276 ps
CPU time 36.11 seconds
Started Aug 02 06:46:49 PM PDT 24
Finished Aug 02 06:47:26 PM PDT 24
Peak memory 237416 kb
Host smart-0d01f4dc-a957-452f-8d08-dba46952bcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152257424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4152257424
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3125946960
Short name T493
Test name
Test status
Simulation time 16965219 ps
CPU time 0.77 seconds
Started Aug 02 06:46:58 PM PDT 24
Finished Aug 02 06:46:59 PM PDT 24
Peak memory 205920 kb
Host smart-25738162-97f4-4e5f-bc1c-9fc85cfa31d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125946960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3125946960
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1451091395
Short name T279
Test name
Test status
Simulation time 1699036754 ps
CPU time 6.05 seconds
Started Aug 02 06:46:47 PM PDT 24
Finished Aug 02 06:46:53 PM PDT 24
Peak memory 233076 kb
Host smart-8b4edf73-603a-4f83-aef5-bafc600934c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451091395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1451091395
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.655538431
Short name T393
Test name
Test status
Simulation time 44040936 ps
CPU time 0.83 seconds
Started Aug 02 06:46:51 PM PDT 24
Finished Aug 02 06:46:52 PM PDT 24
Peak memory 206916 kb
Host smart-b8e7dd33-98f0-4946-8216-1e4b10115dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655538431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.655538431
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2041471611
Short name T826
Test name
Test status
Simulation time 79875486524 ps
CPU time 156.96 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:49:34 PM PDT 24
Peak memory 249592 kb
Host smart-378aa2fd-40bc-4217-8a53-b5a686276562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041471611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2041471611
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1658294140
Short name T950
Test name
Test status
Simulation time 5305196960 ps
CPU time 58.51 seconds
Started Aug 02 06:46:58 PM PDT 24
Finished Aug 02 06:47:57 PM PDT 24
Peak memory 254516 kb
Host smart-04b8b3cf-2bbd-4a44-8cad-9492d4b8666a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658294140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1658294140
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4202225520
Short name T88
Test name
Test status
Simulation time 5010744892 ps
CPU time 55.3 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:47:53 PM PDT 24
Peak memory 256164 kb
Host smart-4aeae5a3-ca4a-4e0e-98d5-43fd11e52fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202225520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4202225520
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3246766067
Short name T552
Test name
Test status
Simulation time 1948415693 ps
CPU time 22.29 seconds
Started Aug 02 06:46:58 PM PDT 24
Finished Aug 02 06:47:20 PM PDT 24
Peak memory 234268 kb
Host smart-f4baae0d-e1a6-47bc-ba5b-9f557058e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246766067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3246766067
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3220252258
Short name T586
Test name
Test status
Simulation time 55036723845 ps
CPU time 190.86 seconds
Started Aug 02 06:46:56 PM PDT 24
Finished Aug 02 06:50:07 PM PDT 24
Peak memory 251772 kb
Host smart-9138b193-c664-45b8-8861-473aa3b7dade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220252258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3220252258
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3023334319
Short name T106
Test name
Test status
Simulation time 926247197 ps
CPU time 12.89 seconds
Started Aug 02 06:46:56 PM PDT 24
Finished Aug 02 06:47:09 PM PDT 24
Peak memory 224704 kb
Host smart-ea07290c-1ad1-4a81-83a3-4905da4bc24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023334319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3023334319
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3866194163
Short name T671
Test name
Test status
Simulation time 2475016068 ps
CPU time 20.28 seconds
Started Aug 02 06:46:48 PM PDT 24
Finished Aug 02 06:47:08 PM PDT 24
Peak memory 250864 kb
Host smart-5bdd258c-56ff-4446-a7e0-6a873f2bdc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866194163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3866194163
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3546811529
Short name T971
Test name
Test status
Simulation time 1087795445 ps
CPU time 4.15 seconds
Started Aug 02 06:46:47 PM PDT 24
Finished Aug 02 06:46:51 PM PDT 24
Peak memory 233080 kb
Host smart-b1a2aa4f-875c-4b61-9a86-cf0fb9a4346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546811529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3546811529
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.107975047
Short name T539
Test name
Test status
Simulation time 2045421071 ps
CPU time 5.47 seconds
Started Aug 02 06:46:50 PM PDT 24
Finished Aug 02 06:46:56 PM PDT 24
Peak memory 233136 kb
Host smart-b1822053-7dda-425e-95b9-f669ec53e35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107975047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.107975047
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4101687392
Short name T681
Test name
Test status
Simulation time 4878058140 ps
CPU time 10.25 seconds
Started Aug 02 06:46:59 PM PDT 24
Finished Aug 02 06:47:09 PM PDT 24
Peak memory 220984 kb
Host smart-d02d35da-fff0-44d8-a5ac-0fd4a187564e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4101687392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4101687392
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1007206664
Short name T168
Test name
Test status
Simulation time 38540098004 ps
CPU time 83.27 seconds
Started Aug 02 06:47:01 PM PDT 24
Finished Aug 02 06:48:25 PM PDT 24
Peak memory 239152 kb
Host smart-e39b0479-4088-474d-85a7-46b4573b6261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007206664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1007206664
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3030499352
Short name T850
Test name
Test status
Simulation time 6668900229 ps
CPU time 26.36 seconds
Started Aug 02 06:46:47 PM PDT 24
Finished Aug 02 06:47:13 PM PDT 24
Peak memory 216840 kb
Host smart-40eb2f80-aaec-45ef-a210-3fe115a0bbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030499352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3030499352
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.530280835
Short name T915
Test name
Test status
Simulation time 3094886571 ps
CPU time 8.72 seconds
Started Aug 02 06:46:50 PM PDT 24
Finished Aug 02 06:46:59 PM PDT 24
Peak memory 216780 kb
Host smart-56baa7af-59d4-483d-9260-48c271b5613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530280835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.530280835
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1713185908
Short name T2
Test name
Test status
Simulation time 13860665 ps
CPU time 0.72 seconds
Started Aug 02 06:46:48 PM PDT 24
Finished Aug 02 06:46:49 PM PDT 24
Peak memory 206052 kb
Host smart-32c4cbd9-70d8-43f3-8c3d-b11a5a44807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713185908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1713185908
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2130999185
Short name T661
Test name
Test status
Simulation time 548126897 ps
CPU time 0.88 seconds
Started Aug 02 06:46:49 PM PDT 24
Finished Aug 02 06:46:50 PM PDT 24
Peak memory 206380 kb
Host smart-164cf4d8-70ad-4c4d-9f9a-a8fa90805ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130999185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2130999185
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1926743964
Short name T663
Test name
Test status
Simulation time 8912237219 ps
CPU time 14.25 seconds
Started Aug 02 06:46:47 PM PDT 24
Finished Aug 02 06:47:01 PM PDT 24
Peak memory 250592 kb
Host smart-76499e54-e7f1-4811-8500-63a826469982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926743964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1926743964
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2700505593
Short name T356
Test name
Test status
Simulation time 63744713 ps
CPU time 0.74 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:46:58 PM PDT 24
Peak memory 205324 kb
Host smart-0dc67180-f27e-43c7-8632-ce7d7c549eae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700505593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2700505593
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3600125150
Short name T942
Test name
Test status
Simulation time 161355986 ps
CPU time 2.68 seconds
Started Aug 02 06:46:58 PM PDT 24
Finished Aug 02 06:47:01 PM PDT 24
Peak memory 224928 kb
Host smart-bbe26c1d-fb34-4060-92d3-938b47ccd7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600125150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3600125150
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4153699014
Short name T515
Test name
Test status
Simulation time 63056186 ps
CPU time 0.79 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:46:58 PM PDT 24
Peak memory 207004 kb
Host smart-632d7e44-ee50-4e0e-bec1-0fda28dbe701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153699014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4153699014
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.235068416
Short name T471
Test name
Test status
Simulation time 71201308188 ps
CPU time 70.8 seconds
Started Aug 02 06:46:58 PM PDT 24
Finished Aug 02 06:48:09 PM PDT 24
Peak memory 257584 kb
Host smart-3aa88326-cec4-4cfb-b65b-1206a60e7fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235068416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.235068416
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.958917719
Short name T773
Test name
Test status
Simulation time 106569917334 ps
CPU time 288.39 seconds
Started Aug 02 06:46:58 PM PDT 24
Finished Aug 02 06:51:46 PM PDT 24
Peak memory 257884 kb
Host smart-12c675ad-c58c-4e88-8d1b-8cfeb491277f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958917719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.958917719
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4017395214
Short name T984
Test name
Test status
Simulation time 15336579306 ps
CPU time 165.86 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:49:43 PM PDT 24
Peak memory 249716 kb
Host smart-23078fa8-df69-43d9-9c90-8d68b42309ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017395214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4017395214
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.80972554
Short name T370
Test name
Test status
Simulation time 232675034 ps
CPU time 3.32 seconds
Started Aug 02 06:46:56 PM PDT 24
Finished Aug 02 06:47:00 PM PDT 24
Peak memory 219348 kb
Host smart-f4cdb24c-513c-4407-b82e-5eeb512dd18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80972554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.80972554
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1775332285
Short name T289
Test name
Test status
Simulation time 5893036668 ps
CPU time 46.13 seconds
Started Aug 02 06:46:59 PM PDT 24
Finished Aug 02 06:47:45 PM PDT 24
Peak memory 235740 kb
Host smart-20d13b96-4ab5-46ca-8f26-d1c46ba7dfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775332285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1775332285
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.554035523
Short name T812
Test name
Test status
Simulation time 71261235 ps
CPU time 3.12 seconds
Started Aug 02 06:46:56 PM PDT 24
Finished Aug 02 06:46:59 PM PDT 24
Peak memory 233164 kb
Host smart-fafc2531-04a3-47be-8e27-3445df4193ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554035523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.554035523
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2225274920
Short name T237
Test name
Test status
Simulation time 2680555042 ps
CPU time 20.92 seconds
Started Aug 02 06:46:58 PM PDT 24
Finished Aug 02 06:47:19 PM PDT 24
Peak memory 233268 kb
Host smart-77a4a22d-1a0c-4cc1-9cc9-a32c0510d982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225274920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2225274920
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2321882590
Short name T276
Test name
Test status
Simulation time 1979560672 ps
CPU time 5.99 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:47:03 PM PDT 24
Peak memory 224960 kb
Host smart-65114247-3d8c-48a9-abfd-37f923614e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321882590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2321882590
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.321953010
Short name T728
Test name
Test status
Simulation time 10997162161 ps
CPU time 12.02 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:47:10 PM PDT 24
Peak memory 233252 kb
Host smart-1adaf2e9-cca8-4c90-816d-8c9064dc9768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321953010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.321953010
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1220021802
Short name T378
Test name
Test status
Simulation time 3325989157 ps
CPU time 10.42 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:47:07 PM PDT 24
Peak memory 223776 kb
Host smart-7bf9adf0-007b-454f-ae19-8c6ff93497db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1220021802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1220021802
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3426445964
Short name T1003
Test name
Test status
Simulation time 135062408 ps
CPU time 0.99 seconds
Started Aug 02 06:46:59 PM PDT 24
Finished Aug 02 06:47:00 PM PDT 24
Peak memory 207400 kb
Host smart-0b43a931-9a38-4d53-9eb3-cb6307891b99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426445964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3426445964
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2004806671
Short name T833
Test name
Test status
Simulation time 5072639882 ps
CPU time 23.81 seconds
Started Aug 02 06:47:00 PM PDT 24
Finished Aug 02 06:47:24 PM PDT 24
Peak memory 216824 kb
Host smart-0a71a00e-5039-47e0-bba8-b761a00c3ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004806671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2004806671
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1228489804
Short name T506
Test name
Test status
Simulation time 3152776926 ps
CPU time 3.92 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:47:01 PM PDT 24
Peak memory 216748 kb
Host smart-7a5bfa9c-9f05-4d26-9603-2968dd8718df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228489804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1228489804
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.4202210663
Short name T409
Test name
Test status
Simulation time 260795323 ps
CPU time 1.63 seconds
Started Aug 02 06:46:58 PM PDT 24
Finished Aug 02 06:47:00 PM PDT 24
Peak memory 216740 kb
Host smart-6a2f2f8a-a9d3-4e74-85ef-996beafd84e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202210663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4202210663
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1504425659
Short name T746
Test name
Test status
Simulation time 139100941 ps
CPU time 0.87 seconds
Started Aug 02 06:47:01 PM PDT 24
Finished Aug 02 06:47:02 PM PDT 24
Peak memory 206368 kb
Host smart-645ecf1a-5216-436b-821a-a316f0c6e362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504425659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1504425659
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2587651652
Short name T265
Test name
Test status
Simulation time 685287366 ps
CPU time 5.1 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:47:02 PM PDT 24
Peak memory 233180 kb
Host smart-5bba56e2-d864-47bf-8c80-383b3d4d6d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587651652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2587651652
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2953060542
Short name T340
Test name
Test status
Simulation time 25737294 ps
CPU time 0.73 seconds
Started Aug 02 06:47:06 PM PDT 24
Finished Aug 02 06:47:07 PM PDT 24
Peak memory 205892 kb
Host smart-3c5fbfb2-61e6-432f-b734-d8847ea9e7d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953060542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2953060542
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1984528243
Short name T680
Test name
Test status
Simulation time 1102613602 ps
CPU time 4.82 seconds
Started Aug 02 06:47:00 PM PDT 24
Finished Aug 02 06:47:05 PM PDT 24
Peak memory 224916 kb
Host smart-31a1120b-eb54-405a-abc2-2a121c5b5beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984528243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1984528243
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.100848594
Short name T714
Test name
Test status
Simulation time 12434295 ps
CPU time 0.76 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:46:58 PM PDT 24
Peak memory 205860 kb
Host smart-74ca36b8-ecf6-413f-9583-834558c36a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100848594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.100848594
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2087684836
Short name T753
Test name
Test status
Simulation time 21213006905 ps
CPU time 174.74 seconds
Started Aug 02 06:47:08 PM PDT 24
Finished Aug 02 06:50:03 PM PDT 24
Peak memory 263124 kb
Host smart-63fa0c0b-0a08-4390-9d17-ae754c91245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087684836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2087684836
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3212289975
Short name T175
Test name
Test status
Simulation time 4258920077 ps
CPU time 102.57 seconds
Started Aug 02 06:47:06 PM PDT 24
Finished Aug 02 06:48:49 PM PDT 24
Peak memory 254212 kb
Host smart-b37f6432-8b36-4038-bcc8-e6da5cba7bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212289975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3212289975
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3046339535
Short name T389
Test name
Test status
Simulation time 12345909270 ps
CPU time 42.83 seconds
Started Aug 02 06:47:08 PM PDT 24
Finished Aug 02 06:47:51 PM PDT 24
Peak memory 249600 kb
Host smart-b21bbbbd-a12b-4837-93fd-3757b2b2a617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046339535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3046339535
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2501640609
Short name T683
Test name
Test status
Simulation time 205840842 ps
CPU time 3.31 seconds
Started Aug 02 06:46:58 PM PDT 24
Finished Aug 02 06:47:02 PM PDT 24
Peak memory 233104 kb
Host smart-1468a314-769b-4caf-94f0-d9625e600cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501640609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2501640609
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2927786558
Short name T224
Test name
Test status
Simulation time 17566967393 ps
CPU time 80.61 seconds
Started Aug 02 06:47:00 PM PDT 24
Finished Aug 02 06:48:21 PM PDT 24
Peak memory 253820 kb
Host smart-6a936758-9c2c-42c6-9cdb-37f452b7c8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927786558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2927786558
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.9169648
Short name T602
Test name
Test status
Simulation time 68030913 ps
CPU time 3.32 seconds
Started Aug 02 06:47:00 PM PDT 24
Finished Aug 02 06:47:03 PM PDT 24
Peak memory 233148 kb
Host smart-51742152-72ad-4ace-9b71-b9aa6aa67666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9169648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.9169648
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.539036774
Short name T824
Test name
Test status
Simulation time 4302926018 ps
CPU time 6 seconds
Started Aug 02 06:46:59 PM PDT 24
Finished Aug 02 06:47:05 PM PDT 24
Peak memory 233120 kb
Host smart-c974e995-9590-41c7-a1e0-afc75768912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539036774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.539036774
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2914502557
Short name T611
Test name
Test status
Simulation time 2494103617 ps
CPU time 8.21 seconds
Started Aug 02 06:46:59 PM PDT 24
Finished Aug 02 06:47:08 PM PDT 24
Peak memory 224948 kb
Host smart-b3ebed4c-b1d2-4ec1-b13e-7afa115c2295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914502557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2914502557
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1432749504
Short name T966
Test name
Test status
Simulation time 6502883126 ps
CPU time 19.79 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:47:17 PM PDT 24
Peak memory 233188 kb
Host smart-eff4bf25-e3ad-47a1-b261-edda3a57ad8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432749504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1432749504
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1831939711
Short name T527
Test name
Test status
Simulation time 8494025326 ps
CPU time 12.38 seconds
Started Aug 02 06:47:09 PM PDT 24
Finished Aug 02 06:47:21 PM PDT 24
Peak memory 219848 kb
Host smart-e49e5840-f5ef-4f0a-b6a7-b9001359a6b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1831939711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1831939711
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1315911260
Short name T976
Test name
Test status
Simulation time 129284828510 ps
CPU time 244.48 seconds
Started Aug 02 06:47:06 PM PDT 24
Finished Aug 02 06:51:10 PM PDT 24
Peak memory 257828 kb
Host smart-28485325-1da1-4e32-ae27-672211cb0b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315911260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1315911260
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1033466769
Short name T968
Test name
Test status
Simulation time 2179190071 ps
CPU time 17.78 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:47:15 PM PDT 24
Peak memory 216736 kb
Host smart-88ed5abe-2777-408a-90ca-08b4215824f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033466769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1033466769
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3801521724
Short name T741
Test name
Test status
Simulation time 3027109032 ps
CPU time 5.88 seconds
Started Aug 02 06:46:57 PM PDT 24
Finished Aug 02 06:47:03 PM PDT 24
Peak memory 216620 kb
Host smart-548eec40-3cb1-4015-bd38-e348daea43a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801521724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3801521724
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3223564917
Short name T990
Test name
Test status
Simulation time 109698800 ps
CPU time 0.98 seconds
Started Aug 02 06:46:56 PM PDT 24
Finished Aug 02 06:46:57 PM PDT 24
Peak memory 207296 kb
Host smart-e397cb2e-dcd8-460b-881c-ff5df53924d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223564917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3223564917
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1617582512
Short name T372
Test name
Test status
Simulation time 196701941 ps
CPU time 0.79 seconds
Started Aug 02 06:47:02 PM PDT 24
Finished Aug 02 06:47:03 PM PDT 24
Peak memory 206380 kb
Host smart-d417a98e-58e9-4d7e-b255-59bca2a27bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617582512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1617582512
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3160543498
Short name T670
Test name
Test status
Simulation time 9614450459 ps
CPU time 10.72 seconds
Started Aug 02 06:47:00 PM PDT 24
Finished Aug 02 06:47:11 PM PDT 24
Peak memory 237876 kb
Host smart-390833a4-422c-4517-8b9e-894b7be3d719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160543498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3160543498
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3026270771
Short name T143
Test name
Test status
Simulation time 41038171 ps
CPU time 0.7 seconds
Started Aug 02 06:47:05 PM PDT 24
Finished Aug 02 06:47:06 PM PDT 24
Peak memory 205268 kb
Host smart-8a959931-9c26-4d22-9176-6c43d7fbaad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026270771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3026270771
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2896293010
Short name T282
Test name
Test status
Simulation time 456553336 ps
CPU time 6.82 seconds
Started Aug 02 06:47:08 PM PDT 24
Finished Aug 02 06:47:15 PM PDT 24
Peak memory 233188 kb
Host smart-dd6ada02-3042-4cbf-9bca-f62f20b6edbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896293010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2896293010
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3119428795
Short name T460
Test name
Test status
Simulation time 22582089 ps
CPU time 0.82 seconds
Started Aug 02 06:47:05 PM PDT 24
Finished Aug 02 06:47:06 PM PDT 24
Peak memory 207036 kb
Host smart-217c8557-8e70-4956-a43b-ef3b62b4c294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119428795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3119428795
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3937504105
Short name T982
Test name
Test status
Simulation time 99556545320 ps
CPU time 128.6 seconds
Started Aug 02 06:47:07 PM PDT 24
Finished Aug 02 06:49:16 PM PDT 24
Peak memory 262468 kb
Host smart-7a70e08e-7d5b-4aa3-b122-dfbcc9416104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937504105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3937504105
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2951927492
Short name T821
Test name
Test status
Simulation time 22366695427 ps
CPU time 192.41 seconds
Started Aug 02 06:47:05 PM PDT 24
Finished Aug 02 06:50:17 PM PDT 24
Peak memory 254204 kb
Host smart-8ab39d00-b166-47c9-8c2c-331a6db9985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951927492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2951927492
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.95648862
Short name T152
Test name
Test status
Simulation time 41469037099 ps
CPU time 398.25 seconds
Started Aug 02 06:47:12 PM PDT 24
Finished Aug 02 06:53:50 PM PDT 24
Peak memory 262680 kb
Host smart-a50fe740-7aa0-489c-82d5-e557038f3a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95648862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.95648862
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2053836548
Short name T878
Test name
Test status
Simulation time 137190135 ps
CPU time 4.27 seconds
Started Aug 02 06:47:06 PM PDT 24
Finished Aug 02 06:47:10 PM PDT 24
Peak memory 224940 kb
Host smart-12616432-335f-4481-b60f-a45c0b56b189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053836548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2053836548
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2780950147
Short name T273
Test name
Test status
Simulation time 794992972 ps
CPU time 14.14 seconds
Started Aug 02 06:47:09 PM PDT 24
Finished Aug 02 06:47:23 PM PDT 24
Peak memory 236604 kb
Host smart-9fe296c0-fc20-4efb-b38f-fc4b768c5fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780950147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2780950147
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2792037831
Short name T987
Test name
Test status
Simulation time 1357956363 ps
CPU time 15.98 seconds
Started Aug 02 06:47:08 PM PDT 24
Finished Aug 02 06:47:24 PM PDT 24
Peak memory 224928 kb
Host smart-cf442af1-c21e-4eee-91bf-26ef7f0bc762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792037831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2792037831
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1224092671
Short name T952
Test name
Test status
Simulation time 7178841223 ps
CPU time 64.38 seconds
Started Aug 02 06:47:06 PM PDT 24
Finished Aug 02 06:48:10 PM PDT 24
Peak memory 225028 kb
Host smart-8c5a48f1-2f02-44c3-a61f-c86f31294080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224092671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1224092671
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1050853942
Short name T880
Test name
Test status
Simulation time 1403797870 ps
CPU time 6.54 seconds
Started Aug 02 06:47:07 PM PDT 24
Finished Aug 02 06:47:14 PM PDT 24
Peak memory 237064 kb
Host smart-5b28aff2-4095-4206-b91d-bf5402365470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050853942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1050853942
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.360782196
Short name T730
Test name
Test status
Simulation time 234384388 ps
CPU time 4.27 seconds
Started Aug 02 06:47:06 PM PDT 24
Finished Aug 02 06:47:10 PM PDT 24
Peak memory 224772 kb
Host smart-2ead7e37-906b-4c50-bdc6-33b0df8b9de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360782196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.360782196
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1489714411
Short name T444
Test name
Test status
Simulation time 912834073 ps
CPU time 5.21 seconds
Started Aug 02 06:47:06 PM PDT 24
Finished Aug 02 06:47:11 PM PDT 24
Peak memory 220936 kb
Host smart-857e495f-b297-4480-9178-67199931acfb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1489714411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1489714411
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.262214470
Short name T19
Test name
Test status
Simulation time 146139926774 ps
CPU time 365.56 seconds
Started Aug 02 06:47:20 PM PDT 24
Finished Aug 02 06:53:26 PM PDT 24
Peak memory 249760 kb
Host smart-580f4a25-1d70-4e7d-b4bb-ebece24131d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262214470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.262214470
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3571263202
Short name T443
Test name
Test status
Simulation time 23141235727 ps
CPU time 45.2 seconds
Started Aug 02 06:47:08 PM PDT 24
Finished Aug 02 06:47:54 PM PDT 24
Peak memory 220984 kb
Host smart-a2d19dc7-5cfb-4508-a7df-b45539cecc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571263202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3571263202
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2483217503
Short name T459
Test name
Test status
Simulation time 946256953 ps
CPU time 4.06 seconds
Started Aug 02 06:47:08 PM PDT 24
Finished Aug 02 06:47:12 PM PDT 24
Peak memory 216736 kb
Host smart-1a76b287-36b6-4813-9b8f-8e0ec9fd4539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483217503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2483217503
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1376539416
Short name T363
Test name
Test status
Simulation time 145108712 ps
CPU time 1.96 seconds
Started Aug 02 06:47:06 PM PDT 24
Finished Aug 02 06:47:09 PM PDT 24
Peak memory 216584 kb
Host smart-d8a1fc9c-aa53-4b6a-8f76-2141d56e588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376539416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1376539416
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4139162829
Short name T594
Test name
Test status
Simulation time 30692580 ps
CPU time 0.8 seconds
Started Aug 02 06:47:05 PM PDT 24
Finished Aug 02 06:47:06 PM PDT 24
Peak memory 206368 kb
Host smart-553a430e-4565-461a-a420-ac18b52a82db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139162829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4139162829
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.556995607
Short name T907
Test name
Test status
Simulation time 367679585 ps
CPU time 3.68 seconds
Started Aug 02 06:47:05 PM PDT 24
Finished Aug 02 06:47:09 PM PDT 24
Peak memory 233136 kb
Host smart-3ba1d309-f738-42b0-9379-a6442444af5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556995607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.556995607
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1252377732
Short name T385
Test name
Test status
Simulation time 52526970 ps
CPU time 0.79 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:44:27 PM PDT 24
Peak memory 205904 kb
Host smart-3a9eb0b4-7c94-44f2-936a-b5e05d7488b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252377732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
252377732
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4076663089
Short name T248
Test name
Test status
Simulation time 556963701 ps
CPU time 4.38 seconds
Started Aug 02 06:44:23 PM PDT 24
Finished Aug 02 06:44:27 PM PDT 24
Peak memory 224924 kb
Host smart-eb54a9d4-735a-4fd1-8a92-c57abd0d2909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076663089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4076663089
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2242552767
Short name T355
Test name
Test status
Simulation time 125378986 ps
CPU time 0.76 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:26 PM PDT 24
Peak memory 205984 kb
Host smart-a33938e7-b296-4b06-b976-13af4f8db4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242552767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2242552767
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2072796804
Short name T285
Test name
Test status
Simulation time 72332495264 ps
CPU time 139.38 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:46:45 PM PDT 24
Peak memory 266064 kb
Host smart-a810f479-255b-4c41-9ad1-d1c1d9d69373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072796804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2072796804
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.990698417
Short name T219
Test name
Test status
Simulation time 60690051678 ps
CPU time 147.79 seconds
Started Aug 02 06:44:28 PM PDT 24
Finished Aug 02 06:46:56 PM PDT 24
Peak memory 250784 kb
Host smart-d8b8f573-c32b-4f25-a648-eacb7c0a4079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990698417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.990698417
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.885014775
Short name T672
Test name
Test status
Simulation time 512115046441 ps
CPU time 252.39 seconds
Started Aug 02 06:44:20 PM PDT 24
Finished Aug 02 06:48:32 PM PDT 24
Peak memory 249640 kb
Host smart-40e8db20-576c-46a6-a438-0bcd560fd6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885014775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
885014775
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2201858883
Short name T331
Test name
Test status
Simulation time 370159072 ps
CPU time 4.35 seconds
Started Aug 02 06:44:30 PM PDT 24
Finished Aug 02 06:44:35 PM PDT 24
Peak memory 224996 kb
Host smart-ecdb3735-6c48-42a2-b6f7-52502243e9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201858883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2201858883
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.746208820
Short name T183
Test name
Test status
Simulation time 1543447839 ps
CPU time 36.45 seconds
Started Aug 02 06:44:22 PM PDT 24
Finished Aug 02 06:44:59 PM PDT 24
Peak memory 253000 kb
Host smart-e22312f5-8d94-4b89-b493-52cd8ed3d8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746208820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
746208820
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1302949172
Short name T1001
Test name
Test status
Simulation time 257003228 ps
CPU time 4.44 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:30 PM PDT 24
Peak memory 224868 kb
Host smart-93dc0199-b647-487e-9c07-e90e994b5af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302949172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1302949172
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4272166089
Short name T761
Test name
Test status
Simulation time 1643407682 ps
CPU time 5.18 seconds
Started Aug 02 06:44:24 PM PDT 24
Finished Aug 02 06:44:29 PM PDT 24
Peak memory 233160 kb
Host smart-f612e31a-bda5-4146-b5e5-f1564c2b0e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272166089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4272166089
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3844666481
Short name T891
Test name
Test status
Simulation time 185310930 ps
CPU time 3.2 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:44:29 PM PDT 24
Peak memory 233076 kb
Host smart-9de3e614-848b-40e5-97bc-e7bf972dcf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844666481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3844666481
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3787030225
Short name T884
Test name
Test status
Simulation time 9290320494 ps
CPU time 6.09 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:44:33 PM PDT 24
Peak memory 224912 kb
Host smart-3808919a-1280-4d04-8c16-d97c16071051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787030225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3787030225
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.974565018
Short name T538
Test name
Test status
Simulation time 1517258953 ps
CPU time 15.58 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:41 PM PDT 24
Peak memory 222068 kb
Host smart-c10c1727-b4f1-4cdc-a68e-9ef0b2626b68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=974565018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.974565018
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1120232714
Short name T309
Test name
Test status
Simulation time 8488402410 ps
CPU time 170.42 seconds
Started Aug 02 06:44:30 PM PDT 24
Finished Aug 02 06:47:21 PM PDT 24
Peak memory 266032 kb
Host smart-5f417391-ac62-4c2f-a74c-50ee1279c516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120232714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1120232714
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3014757633
Short name T382
Test name
Test status
Simulation time 12994400498 ps
CPU time 50.69 seconds
Started Aug 02 06:44:23 PM PDT 24
Finished Aug 02 06:45:14 PM PDT 24
Peak memory 216744 kb
Host smart-d5271a10-ad5d-410a-b635-8eb054e4f664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014757633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3014757633
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2538565757
Short name T517
Test name
Test status
Simulation time 671869858 ps
CPU time 5.03 seconds
Started Aug 02 06:44:19 PM PDT 24
Finished Aug 02 06:44:25 PM PDT 24
Peak memory 216680 kb
Host smart-3e8015f7-95c1-45fa-9707-0fb8278608a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538565757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2538565757
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3884456345
Short name T883
Test name
Test status
Simulation time 48281462 ps
CPU time 2.2 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:27 PM PDT 24
Peak memory 216684 kb
Host smart-6a63f940-4e8f-4a0f-beb0-c1fa45c4cbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884456345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3884456345
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2951696330
Short name T831
Test name
Test status
Simulation time 38567445 ps
CPU time 0.73 seconds
Started Aug 02 06:44:27 PM PDT 24
Finished Aug 02 06:44:28 PM PDT 24
Peak memory 206404 kb
Host smart-20d9b146-a419-4674-b394-9dd82595c13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951696330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2951696330
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.764088234
Short name T731
Test name
Test status
Simulation time 94475315 ps
CPU time 2.55 seconds
Started Aug 02 06:44:24 PM PDT 24
Finished Aug 02 06:44:26 PM PDT 24
Peak memory 224960 kb
Host smart-4b801814-6e1f-45a6-80b0-4401ef0dfb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764088234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.764088234
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.583344911
Short name T788
Test name
Test status
Simulation time 12079846 ps
CPU time 0.78 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:44:27 PM PDT 24
Peak memory 205872 kb
Host smart-a0dcb449-0e82-48f2-9a20-d54ea07f54e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583344911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.583344911
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2600533703
Short name T601
Test name
Test status
Simulation time 360332285 ps
CPU time 6.3 seconds
Started Aug 02 06:44:28 PM PDT 24
Finished Aug 02 06:44:34 PM PDT 24
Peak memory 233112 kb
Host smart-aa18feb9-a9f5-4a6d-8a70-990bf37e9895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600533703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2600533703
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1622274915
Short name T26
Test name
Test status
Simulation time 17425357 ps
CPU time 0.78 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:26 PM PDT 24
Peak memory 207356 kb
Host smart-65fad6d1-368b-4bca-b2e7-107cf00fdc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622274915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1622274915
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2137153859
Short name T220
Test name
Test status
Simulation time 103080006853 ps
CPU time 185.62 seconds
Started Aug 02 06:44:28 PM PDT 24
Finished Aug 02 06:47:34 PM PDT 24
Peak memory 249612 kb
Host smart-a06b4e39-5795-497a-ace2-fed143a707a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137153859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2137153859
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3913435615
Short name T62
Test name
Test status
Simulation time 314045666141 ps
CPU time 208.86 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:47:55 PM PDT 24
Peak memory 256044 kb
Host smart-9ad3f121-67da-4122-8e1d-85d32ea3ecdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913435615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3913435615
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4174352988
Short name T190
Test name
Test status
Simulation time 58596661736 ps
CPU time 252.41 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:48:38 PM PDT 24
Peak memory 254036 kb
Host smart-010ccc7b-a2dd-4d42-9f9f-26fd5ffd1ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174352988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4174352988
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.16770341
Short name T316
Test name
Test status
Simulation time 1687937809 ps
CPU time 14.72 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:40 PM PDT 24
Peak memory 241312 kb
Host smart-2e502682-7888-43d6-a342-199daf69402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16770341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.16770341
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.845670636
Short name T187
Test name
Test status
Simulation time 21539496042 ps
CPU time 72.53 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:45:39 PM PDT 24
Peak memory 249632 kb
Host smart-45467637-8665-4c2e-92ea-c710eb365802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845670636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
845670636
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1723619463
Short name T461
Test name
Test status
Simulation time 95117773 ps
CPU time 3.21 seconds
Started Aug 02 06:44:27 PM PDT 24
Finished Aug 02 06:44:31 PM PDT 24
Peak memory 233224 kb
Host smart-96c8430d-3870-40fe-9e0f-88d452abe656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723619463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1723619463
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2485808841
Short name T922
Test name
Test status
Simulation time 502931531 ps
CPU time 3.9 seconds
Started Aug 02 06:44:27 PM PDT 24
Finished Aug 02 06:44:32 PM PDT 24
Peak memory 233140 kb
Host smart-d03332f2-8521-484b-b160-f2b944deb277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485808841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2485808841
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.122438686
Short name T479
Test name
Test status
Simulation time 4859741554 ps
CPU time 8.63 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:44:35 PM PDT 24
Peak memory 233232 kb
Host smart-d0b82472-7a91-44e1-ba57-07624183f467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122438686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
122438686
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2277765664
Short name T283
Test name
Test status
Simulation time 2690388142 ps
CPU time 13.48 seconds
Started Aug 02 06:44:24 PM PDT 24
Finished Aug 02 06:44:37 PM PDT 24
Peak memory 233180 kb
Host smart-d193642a-1408-4a39-b679-f38ec8c974dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277765664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2277765664
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3907730219
Short name T3
Test name
Test status
Simulation time 15940584642 ps
CPU time 11.18 seconds
Started Aug 02 06:44:28 PM PDT 24
Finished Aug 02 06:44:39 PM PDT 24
Peak memory 219468 kb
Host smart-feee0f45-a298-4cc7-ae5b-0f109274d669
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3907730219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3907730219
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2211682678
Short name T206
Test name
Test status
Simulation time 27086867767 ps
CPU time 301.01 seconds
Started Aug 02 06:44:28 PM PDT 24
Finished Aug 02 06:49:30 PM PDT 24
Peak memory 271100 kb
Host smart-b29d30d9-30ed-47aa-8813-e46735df5d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211682678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2211682678
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.726894176
Short name T796
Test name
Test status
Simulation time 557560875 ps
CPU time 9.06 seconds
Started Aug 02 06:44:22 PM PDT 24
Finished Aug 02 06:44:31 PM PDT 24
Peak memory 216832 kb
Host smart-261b71ef-3630-4919-8e2a-1e9f02a51560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726894176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.726894176
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4157362270
Short name T875
Test name
Test status
Simulation time 4585989685 ps
CPU time 7.96 seconds
Started Aug 02 06:44:24 PM PDT 24
Finished Aug 02 06:44:33 PM PDT 24
Peak memory 216768 kb
Host smart-831a13a7-6aaf-4a42-b11c-72d4323596cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157362270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4157362270
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.484360710
Short name T692
Test name
Test status
Simulation time 127522919 ps
CPU time 0.94 seconds
Started Aug 02 06:44:23 PM PDT 24
Finished Aug 02 06:44:25 PM PDT 24
Peak memory 208220 kb
Host smart-f5ebac71-8501-4792-8fc5-38a1f2f3eedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484360710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.484360710
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.184298402
Short name T790
Test name
Test status
Simulation time 292489015 ps
CPU time 0.83 seconds
Started Aug 02 06:44:24 PM PDT 24
Finished Aug 02 06:44:25 PM PDT 24
Peak memory 206340 kb
Host smart-af06f63c-af47-4c93-a8ad-0767b32dcbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184298402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.184298402
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2476387691
Short name T263
Test name
Test status
Simulation time 3785297141 ps
CPU time 9.53 seconds
Started Aug 02 06:44:27 PM PDT 24
Finished Aug 02 06:44:37 PM PDT 24
Peak memory 233172 kb
Host smart-74d89592-5328-4417-9790-9114a431a6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476387691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2476387691
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.86759419
Short name T873
Test name
Test status
Simulation time 31340227 ps
CPU time 0.74 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:44:34 PM PDT 24
Peak memory 206080 kb
Host smart-5bb197ac-4e03-481b-8d61-c552a034094b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86759419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.86759419
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.56893371
Short name T589
Test name
Test status
Simulation time 64342418 ps
CPU time 2.25 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:44:28 PM PDT 24
Peak memory 232752 kb
Host smart-160f663b-4ca2-4469-aee7-f0591aefcfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56893371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.56893371
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.9478747
Short name T364
Test name
Test status
Simulation time 149054765 ps
CPU time 0.79 seconds
Started Aug 02 06:44:30 PM PDT 24
Finished Aug 02 06:44:31 PM PDT 24
Peak memory 207008 kb
Host smart-9f0f710f-1dea-4891-93ca-71a8f559b18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9478747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.9478747
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3771137182
Short name T504
Test name
Test status
Simulation time 8025305711 ps
CPU time 54.19 seconds
Started Aug 02 06:44:29 PM PDT 24
Finished Aug 02 06:45:24 PM PDT 24
Peak memory 266028 kb
Host smart-f0455bce-4c18-4553-850b-18ae111fe162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771137182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3771137182
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3211213392
Short name T150
Test name
Test status
Simulation time 51467565401 ps
CPU time 462.1 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:52:08 PM PDT 24
Peak memory 265688 kb
Host smart-71fada07-0233-47c5-83af-b1c07e6fd18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211213392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3211213392
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2956112960
Short name T853
Test name
Test status
Simulation time 14146788286 ps
CPU time 144.33 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:46:51 PM PDT 24
Peak memory 249636 kb
Host smart-3f62427e-b572-4248-94a3-b0b8a37a0113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956112960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2956112960
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1549431621
Short name T353
Test name
Test status
Simulation time 36134447 ps
CPU time 0.78 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:44:34 PM PDT 24
Peak memory 215408 kb
Host smart-a9985e8d-fe14-40f1-8e98-f9e951833b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549431621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1549431621
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2485074646
Short name T524
Test name
Test status
Simulation time 6132261191 ps
CPU time 24.43 seconds
Started Aug 02 06:44:31 PM PDT 24
Finished Aug 02 06:44:55 PM PDT 24
Peak memory 233196 kb
Host smart-acc699d5-9ff0-4faa-8e6c-1936d222bd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485074646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2485074646
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1839955565
Short name T266
Test name
Test status
Simulation time 9822962773 ps
CPU time 21.85 seconds
Started Aug 02 06:44:37 PM PDT 24
Finished Aug 02 06:44:59 PM PDT 24
Peak memory 224976 kb
Host smart-53536553-4ccf-4c83-9528-3cd8b57a2324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839955565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1839955565
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.644826217
Short name T707
Test name
Test status
Simulation time 1921147342 ps
CPU time 3.07 seconds
Started Aug 02 06:44:30 PM PDT 24
Finished Aug 02 06:44:33 PM PDT 24
Peak memory 233156 kb
Host smart-94d1b51a-643c-410c-a260-5082470fe644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644826217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
644826217
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1378175802
Short name T52
Test name
Test status
Simulation time 3138174453 ps
CPU time 5.08 seconds
Started Aug 02 06:44:29 PM PDT 24
Finished Aug 02 06:44:34 PM PDT 24
Peak memory 225016 kb
Host smart-fbc59d23-1895-4fb8-98ee-628aaf506020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378175802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1378175802
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.884475150
Short name T71
Test name
Test status
Simulation time 110386509 ps
CPU time 3.82 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:44:37 PM PDT 24
Peak memory 223364 kb
Host smart-8a80f3a1-85fe-4489-8d81-d5e5862ce097
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=884475150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.884475150
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1861689817
Short name T170
Test name
Test status
Simulation time 12829596670 ps
CPU time 81.07 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:45:54 PM PDT 24
Peak memory 249584 kb
Host smart-20767f28-101c-40b1-b63d-81da365466d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861689817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1861689817
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.819212826
Short name T425
Test name
Test status
Simulation time 40264571141 ps
CPU time 49.61 seconds
Started Aug 02 06:44:29 PM PDT 24
Finished Aug 02 06:45:19 PM PDT 24
Peak memory 216720 kb
Host smart-c3199acb-734f-4fdc-a990-aab3276e0d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819212826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.819212826
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2412409893
Short name T705
Test name
Test status
Simulation time 4043857061 ps
CPU time 12.85 seconds
Started Aug 02 06:44:29 PM PDT 24
Finished Aug 02 06:44:42 PM PDT 24
Peak memory 216740 kb
Host smart-37a752b7-6713-494b-a545-87a9e2c8fc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412409893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2412409893
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.165979617
Short name T400
Test name
Test status
Simulation time 120556678 ps
CPU time 2.02 seconds
Started Aug 02 06:44:30 PM PDT 24
Finished Aug 02 06:44:32 PM PDT 24
Peak memory 216644 kb
Host smart-aa5fc2cc-99bb-4318-8617-8a65d31f06aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165979617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.165979617
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1094284042
Short name T632
Test name
Test status
Simulation time 72034894 ps
CPU time 0.92 seconds
Started Aug 02 06:44:30 PM PDT 24
Finished Aug 02 06:44:32 PM PDT 24
Peak memory 207788 kb
Host smart-853e8210-b4ed-46d5-9abd-034d11e7721a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094284042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1094284042
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2421587263
Short name T640
Test name
Test status
Simulation time 4749007764 ps
CPU time 8.99 seconds
Started Aug 02 06:44:28 PM PDT 24
Finished Aug 02 06:44:37 PM PDT 24
Peak memory 227332 kb
Host smart-7a825e52-9384-45ca-9bee-c39e35c7ff8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421587263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2421587263
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.652800408
Short name T635
Test name
Test status
Simulation time 38001084 ps
CPU time 0.72 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:44:41 PM PDT 24
Peak memory 205844 kb
Host smart-9cab2901-8fde-4def-8b31-6c86347d312f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652800408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.652800408
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3222298519
Short name T822
Test name
Test status
Simulation time 1306795473 ps
CPU time 4.31 seconds
Started Aug 02 06:44:30 PM PDT 24
Finished Aug 02 06:44:35 PM PDT 24
Peak memory 224932 kb
Host smart-32852730-7ff6-4cc6-b6dc-f9ff7a8a4d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222298519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3222298519
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.388054878
Short name T923
Test name
Test status
Simulation time 16252638 ps
CPU time 0.77 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:26 PM PDT 24
Peak memory 207020 kb
Host smart-b3e4ce27-2135-4cbd-86d4-c967180d2eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388054878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.388054878
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3687368035
Short name T252
Test name
Test status
Simulation time 477777964 ps
CPU time 13.14 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:54 PM PDT 24
Peak memory 236164 kb
Host smart-efd3bcf5-e437-4790-a0d5-a098dfc28ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687368035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3687368035
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3744940110
Short name T781
Test name
Test status
Simulation time 3273971163 ps
CPU time 48.38 seconds
Started Aug 02 06:44:31 PM PDT 24
Finished Aug 02 06:45:20 PM PDT 24
Peak memory 241276 kb
Host smart-ca9380fa-aa27-4651-b532-72dcbb554385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744940110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3744940110
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1344706138
Short name T253
Test name
Test status
Simulation time 4238588101 ps
CPU time 92.35 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:46:06 PM PDT 24
Peak memory 249644 kb
Host smart-bb6fc139-d721-4dce-9364-db90d0f3f406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344706138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1344706138
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1678428442
Short name T1
Test name
Test status
Simulation time 640776535 ps
CPU time 4.28 seconds
Started Aug 02 06:44:32 PM PDT 24
Finished Aug 02 06:44:37 PM PDT 24
Peak memory 237788 kb
Host smart-f7d5e3f0-4ba6-4a23-9837-10bf617fc420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678428442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1678428442
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.4287604412
Short name T290
Test name
Test status
Simulation time 782860226607 ps
CPU time 362.57 seconds
Started Aug 02 06:44:32 PM PDT 24
Finished Aug 02 06:50:35 PM PDT 24
Peak memory 267444 kb
Host smart-9e9f0203-8e13-4db9-a607-bc6c29f25997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287604412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.4287604412
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2831789886
Short name T688
Test name
Test status
Simulation time 891190489 ps
CPU time 7.73 seconds
Started Aug 02 06:44:25 PM PDT 24
Finished Aug 02 06:44:33 PM PDT 24
Peak memory 230800 kb
Host smart-96a35778-ef36-4f53-a2fc-31e85abe7c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831789886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2831789886
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2467708875
Short name T914
Test name
Test status
Simulation time 39823623516 ps
CPU time 29.09 seconds
Started Aug 02 06:44:24 PM PDT 24
Finished Aug 02 06:44:53 PM PDT 24
Peak memory 233204 kb
Host smart-f0c6aa29-7975-4749-afd9-46ca82ec5644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467708875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2467708875
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2697633356
Short name T871
Test name
Test status
Simulation time 2272840199 ps
CPU time 9.04 seconds
Started Aug 02 06:44:23 PM PDT 24
Finished Aug 02 06:44:32 PM PDT 24
Peak memory 233188 kb
Host smart-ef219870-c9e9-45f5-8085-89f0082fde63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697633356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2697633356
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3280769984
Short name T832
Test name
Test status
Simulation time 38898090568 ps
CPU time 16.93 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:44:43 PM PDT 24
Peak memory 233184 kb
Host smart-a436a1c7-e227-40cd-b547-d354101f29fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280769984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3280769984
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1584463618
Short name T733
Test name
Test status
Simulation time 449994564 ps
CPU time 4.07 seconds
Started Aug 02 06:44:44 PM PDT 24
Finished Aug 02 06:44:48 PM PDT 24
Peak memory 222956 kb
Host smart-19d28ca7-115d-4066-b5ad-da6db6a6d93f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1584463618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1584463618
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1098681666
Short name T277
Test name
Test status
Simulation time 5790500046 ps
CPU time 61 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:45:41 PM PDT 24
Peak memory 265580 kb
Host smart-fa10362a-e363-4e5b-b8de-48c9aee6cabe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098681666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1098681666
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.310622285
Short name T694
Test name
Test status
Simulation time 16521113133 ps
CPU time 40.96 seconds
Started Aug 02 06:44:30 PM PDT 24
Finished Aug 02 06:45:11 PM PDT 24
Peak memory 216672 kb
Host smart-4e78a8db-b0a7-4b8c-a972-e74ef42950db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310622285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.310622285
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3005868524
Short name T337
Test name
Test status
Simulation time 431998659 ps
CPU time 2.95 seconds
Started Aug 02 06:44:29 PM PDT 24
Finished Aug 02 06:44:32 PM PDT 24
Peak memory 216636 kb
Host smart-b2b9a5af-4510-4a5d-993d-7f6bbf2ee8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005868524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3005868524
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.478702051
Short name T699
Test name
Test status
Simulation time 119264804 ps
CPU time 1.42 seconds
Started Aug 02 06:44:26 PM PDT 24
Finished Aug 02 06:44:28 PM PDT 24
Peak memory 216668 kb
Host smart-4fcd657b-8276-4349-a592-9bf7e72a9b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478702051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.478702051
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1359377924
Short name T895
Test name
Test status
Simulation time 196502350 ps
CPU time 0.76 seconds
Started Aug 02 06:44:29 PM PDT 24
Finished Aug 02 06:44:30 PM PDT 24
Peak memory 206396 kb
Host smart-669ee3d5-1189-41a6-a278-da25fc439369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359377924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1359377924
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.799128660
Short name T577
Test name
Test status
Simulation time 20469842455 ps
CPU time 12.74 seconds
Started Aug 02 06:44:30 PM PDT 24
Finished Aug 02 06:44:43 PM PDT 24
Peak memory 224996 kb
Host smart-65553416-4b78-4567-a9db-d10bc07373b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799128660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.799128660
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4034945128
Short name T677
Test name
Test status
Simulation time 53138441 ps
CPU time 0.69 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:44:41 PM PDT 24
Peak memory 205792 kb
Host smart-cf9560ea-3a8f-4990-aee5-0cd0cb4fbf56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034945128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
034945128
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.185864634
Short name T969
Test name
Test status
Simulation time 566910117 ps
CPU time 2.5 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:44 PM PDT 24
Peak memory 224908 kb
Host smart-5c8e6560-f367-4c6a-b356-20d64710e059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185864634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.185864634
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3737497059
Short name T333
Test name
Test status
Simulation time 61845630 ps
CPU time 0.82 seconds
Started Aug 02 06:44:34 PM PDT 24
Finished Aug 02 06:44:35 PM PDT 24
Peak memory 207048 kb
Host smart-e8b683be-98a9-4f86-a02e-e81b35cb2101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737497059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3737497059
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2791680851
Short name T703
Test name
Test status
Simulation time 29055002 ps
CPU time 0.75 seconds
Started Aug 02 06:44:34 PM PDT 24
Finished Aug 02 06:44:34 PM PDT 24
Peak memory 216160 kb
Host smart-54e3258c-7af5-40e5-a90d-f49eae9f8193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791680851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2791680851
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4131194285
Short name T811
Test name
Test status
Simulation time 8186176707 ps
CPU time 59.77 seconds
Started Aug 02 06:44:31 PM PDT 24
Finished Aug 02 06:45:31 PM PDT 24
Peak memory 249636 kb
Host smart-42b4ccb9-94d3-4bae-ae7a-bda9af5385af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131194285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4131194285
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2885946135
Short name T56
Test name
Test status
Simulation time 268239906523 ps
CPU time 447.39 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:52:01 PM PDT 24
Peak memory 256620 kb
Host smart-0073b982-6bf3-4f7b-9a8a-85156c26875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885946135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2885946135
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1297226422
Short name T983
Test name
Test status
Simulation time 1508215811 ps
CPU time 17.09 seconds
Started Aug 02 06:44:32 PM PDT 24
Finished Aug 02 06:44:50 PM PDT 24
Peak memory 224964 kb
Host smart-c9ed15f8-9349-4cfd-8425-fbf92897f7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297226422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1297226422
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2599241263
Short name T846
Test name
Test status
Simulation time 10380594373 ps
CPU time 42.41 seconds
Started Aug 02 06:44:40 PM PDT 24
Finished Aug 02 06:45:22 PM PDT 24
Peak memory 249576 kb
Host smart-655b6b43-9f8c-4f08-a597-e06ec0563eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599241263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2599241263
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3071797403
Short name T874
Test name
Test status
Simulation time 298437311 ps
CPU time 3.03 seconds
Started Aug 02 06:44:41 PM PDT 24
Finished Aug 02 06:44:44 PM PDT 24
Peak memory 233160 kb
Host smart-63e3b67e-097f-4c5a-874a-16059c2b3e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071797403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3071797403
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1553954119
Short name T825
Test name
Test status
Simulation time 1983526817 ps
CPU time 18.92 seconds
Started Aug 02 06:44:32 PM PDT 24
Finished Aug 02 06:44:51 PM PDT 24
Peak memory 224912 kb
Host smart-71307377-3813-41a6-8c88-76e4015050dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553954119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1553954119
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2660256982
Short name T678
Test name
Test status
Simulation time 376650050 ps
CPU time 2.36 seconds
Started Aug 02 06:44:43 PM PDT 24
Finished Aug 02 06:44:46 PM PDT 24
Peak memory 224528 kb
Host smart-41aff7e9-06f6-491e-8152-2e41416a0f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660256982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2660256982
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2402967746
Short name T934
Test name
Test status
Simulation time 400802504 ps
CPU time 2.76 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:44:36 PM PDT 24
Peak memory 224912 kb
Host smart-acfa8327-d058-47a1-abd1-730af5b45ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402967746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2402967746
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3337285628
Short name T642
Test name
Test status
Simulation time 182048389 ps
CPU time 3.99 seconds
Started Aug 02 06:44:44 PM PDT 24
Finished Aug 02 06:44:48 PM PDT 24
Peak memory 223512 kb
Host smart-3f303e80-c3f6-4c5f-865b-9659ad44d5f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3337285628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3337285628
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.214784409
Short name T167
Test name
Test status
Simulation time 1616174162 ps
CPU time 22.71 seconds
Started Aug 02 06:44:34 PM PDT 24
Finished Aug 02 06:44:57 PM PDT 24
Peak memory 219864 kb
Host smart-0552d965-593c-40e8-955f-d3848f185d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214784409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.214784409
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1557229500
Short name T394
Test name
Test status
Simulation time 39604236626 ps
CPU time 47.84 seconds
Started Aug 02 06:44:37 PM PDT 24
Finished Aug 02 06:45:25 PM PDT 24
Peak memory 216676 kb
Host smart-0e0ed311-3a3a-4ebf-86e3-2ff0c43ced4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557229500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1557229500
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.999900251
Short name T735
Test name
Test status
Simulation time 3538867404 ps
CPU time 10.41 seconds
Started Aug 02 06:44:31 PM PDT 24
Finished Aug 02 06:44:42 PM PDT 24
Peak memory 216812 kb
Host smart-8410003b-6e48-4d5e-8875-9693be39a96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999900251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.999900251
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2731148468
Short name T145
Test name
Test status
Simulation time 42608470 ps
CPU time 0.86 seconds
Started Aug 02 06:44:42 PM PDT 24
Finished Aug 02 06:44:43 PM PDT 24
Peak memory 206844 kb
Host smart-e4463827-3ba3-4d97-97a9-f7e6bdc84f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731148468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2731148468
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4186748152
Short name T665
Test name
Test status
Simulation time 114003435 ps
CPU time 1.01 seconds
Started Aug 02 06:44:34 PM PDT 24
Finished Aug 02 06:44:35 PM PDT 24
Peak memory 207408 kb
Host smart-bc54dcf5-c4e3-4e45-aece-3344111513b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186748152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4186748152
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1420733340
Short name T509
Test name
Test status
Simulation time 8583219892 ps
CPU time 10.19 seconds
Started Aug 02 06:44:33 PM PDT 24
Finished Aug 02 06:44:43 PM PDT 24
Peak memory 224932 kb
Host smart-fb908ff1-9db0-4580-880b-684626a7c98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420733340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1420733340
Directory /workspace/9.spi_device_upload/latest
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