Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2685766	1			T1	1		T2	1		T3	1
all_values[1]	2685766	1			T1	1		T2	1		T3	1
all_values[2]	2685766	1			T1	1		T2	1		T3	1
all_values[3]	2685766	1			T1	1		T2	1		T3	1
all_values[4]	2685766	1			T1	1		T2	1		T3	1
all_values[5]	2685766	1			T1	1		T2	1		T3	1
all_values[6]	2685766	1			T1	1		T2	1		T3	1
all_values[7]	2685766	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20739381

1

T1

8

T2

8

T3

8

auto[1]

746747

1

T4

69

T17

119

T19

2259

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21459401

1

T1

8

T2

8

T3

8

auto[1]

26727

1

T4

132

T8

144

T29

170

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2593294	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	13093	1			T4	40		T8	68		T29	70
all_values[0]	auto[1]	auto[0]	79025	1			T4	6		T17	4		T19	5
all_values[0]	auto[1]	auto[1]	354	1			T17	8		T19	4		T21	1
all_values[1]	auto[0]	auto[0]	2555242	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7885	1			T4	38		T8	68		T29	70
all_values[1]	auto[1]	auto[0]	122286	1			T4	7		T17	7		T19	7
all_values[1]	auto[1]	auto[1]	353	1			T4	5		T17	5		T19	7
all_values[2]	auto[0]	auto[0]	2603433	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2976	1			T4	6		T8	8		T29	30
all_values[2]	auto[1]	auto[0]	79179	1			T4	2		T17	16		T19	9
all_values[2]	auto[1]	auto[1]	178	1			T4	2		T17	6		T19	6
all_values[3]	auto[0]	auto[0]	2636440	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	207	1			T4	4		T17	6		T142	3
all_values[3]	auto[1]	auto[0]	48901	1			T4	2		T17	8		T19	5
all_values[3]	auto[1]	auto[1]	218	1			T4	4		T17	7		T19	13
all_values[4]	auto[0]	auto[0]	2603488	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	156	1			T4	2		T17	4		T70	2
all_values[4]	auto[1]	auto[0]	81928	1			T4	7		T17	13		T19	725
all_values[4]	auto[1]	auto[1]	194	1			T4	5		T17	4		T19	7
all_values[5]	auto[0]	auto[0]	2606354	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	168	1			T4	3		T17	4		T19	5
all_values[5]	auto[1]	auto[0]	79077	1			T4	2		T17	15		T19	6
all_values[5]	auto[1]	auto[1]	167	1			T4	5		T17	4		T19	5
all_values[6]	auto[0]	auto[0]	2499033	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	176	1			T4	3		T17	11		T19	6
all_values[6]	auto[1]	auto[0]	186374	1			T4	6		T17	10		T19	726
all_values[6]	auto[1]	auto[1]	183	1			T4	3		T17	1		T19	4
all_values[7]	auto[0]	auto[0]	2617220	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	216	1			T4	3		T17	13		T19	5
all_values[7]	auto[1]	auto[0]	68127	1			T4	4		T17	11		T19	724
all_values[7]	auto[1]	auto[1]	203	1			T4	9		T19	6		T21	5