Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36101	1			T1	8		T4	57		T5	179
auto[SpiFlashAddrCfg]	8009	1			T4	21		T5	29		T7	29
auto[SpiFlashAddr3b]	9646	1			T4	22		T5	31		T7	51
auto[SpiFlashAddr4b]	7810	1			T4	5		T5	21		T7	25

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35273

1

T1

8

T4

81

T5

148

auto[1]

26293

1

T4

24

T5

112

T7

155

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32275

1

T1

8

T4

54

T5

110

auto[1]

29291

1

T4

51

T5

150

T7

267

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40910	1			T1	8		T4	60		T5	186
values[1]	1134	1			T4	4		T5	6		T7	3
values[2]	1569	1			T4	6		T5	4		T7	4
values[3]	1538	1			T5	10		T7	4		T8	1
values[4]	1459	1			T4	4		T5	5		T7	5
values[5]	1467	1			T4	1		T5	9		T7	13
values[6]	1553	1			T4	4		T5	7		T7	8
values[7]	1506	1			T4	4		T5	7		T7	5
values[8]	10430	1			T4	22		T5	26		T7	37

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31253

1

T1

8

T4

105

T5

260

auto[1]

30313

1

T8

72

T14

20

T30

351

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58219

1

T1

8

T4

101

T5

252

write

3347

1

T4

4

T5

8

T7

10

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20282

1

T1

8

T4

41

T5

61

valids[0x1]

41284

1

T4

64

T5

199

T7

440

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1610	1			T4	2		T5	1		T7	5
internal_process_ops[0x5a]	1696	1			T4	2		T5	4		T7	8
internal_process_ops[0x05]	21418	1			T4	28		T5	128		T7	362
internal_process_ops[0x35]	1738	1			T4	2		T5	5		T7	5
internal_process_ops[0x15]	1658	1			T4	2		T5	7		T7	6
internal_process_ops[0x03]	1010	1			T4	2		T5	7		T7	3
internal_process_ops[0x0b]	1051	1			T4	3		T5	1		T7	12
internal_process_ops[0x3b]	1111	1			T4	2		T5	5		T7	5
internal_process_ops[0x6b]	1100	1			T4	5		T5	4		T7	2
internal_process_ops[0xbb]	1110	1			T4	3		T5	3		T7	6
internal_process_ops[0xeb]	1066	1			T4	2		T5	3		T7	11

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59921

1

T1

8

T4

102

T5

256

auto[1]

1645

1

T4

3

T5

4

T7

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59149

1

T1

8

T4

101

T5

254

auto[1]

2417

1

T4

4

T5

6

T7

12

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10887

1

T1

8

T4

49

T5

110

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6295

1

T4

7

T5

68

T7

104

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2161

1

T4

15

T5

10

T7

11

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1790

1

T4

6

T5

14

T7

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2534

1

T4

13

T5

14

T7

21

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2231

1

T4

7

T5

16

T7

28

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1927

1

T4

2

T5

8

T7

15

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1846

1

T4

2

T5

12

T7

9

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

113

1

T28

2

T29

1

T16

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

87

1

T42

1

T44

1

T34

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

93

1

T5

1

T7

1

T16

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

89

1

T4

1

T39

3

T29

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

123

1

T5

3

T7

4

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

100

1

T5

2

T7

2

T39

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

74

1

T41

1

T43

2

T44

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T40

2

T41

2

T42

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

117

1

T4

1

T7

1

T39

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T7

1

T29

1

T40

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

90

1

T39

2

T41

1

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

108

1

T4

1

T5

1

T40

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

100

1

T40

2

T16

2

T41

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

86

1

T4

1

T5

1

T54

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

103

1

T7

1

T40

2

T41

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T29

2

T40

1

T41

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10703

1

T8

30

T14

9

T30

137

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7396

1

T8

7

T30

47

T16

207

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1681

1

T8

2

T14

4

T30

26

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1516

1

T8

2

T30

15

T16

22

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2022

1

T8

2

T14

3

T30

24

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2013

1

T8

7

T14

3

T30

39

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1656

1

T8

8

T14

1

T30

28

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1561

1

T8

3

T30

16

T16

26

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

95

1

T16

1

T77

1

T157

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

98

1

T8

2

T158

2

T159

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

112

1

T8

2

T77

1

T157

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

133

1

T16

3

T77

1

T78

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

128

1

T8

2

T16

3

T77

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

116

1

T157

1

T78

3

T160

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

123

1

T30

2

T157

2

T158

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

94

1

T8

1

T30

5

T157

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

108

1

T8

1

T30

2

T16

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T30

1

T16

3

T157

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

115

1

T30

2

T77

5

T78

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

118

1

T77

2

T157

1

T78

8

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

120

1

T8

2

T30

2

T16

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

121

1

T30

4

T157

3

T78

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

88

1

T8

1

T77

2

T157

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T30

1

T77

5

T159

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4007	1			T1	8		T4	17		T5	26
auto[0]	values[0]	valids[0x1]	15983	1			T4	43		T5	160		T7	408
auto[0]	values[1]	valids[0x1]	584	1			T4	4		T5	6		T7	3
auto[0]	values[2]	valids[0x0]	567	1			T5	2		T7	2		T15	2
auto[0]	values[2]	valids[0x1]	300	1			T4	6		T5	2		T7	2
auto[0]	values[3]	valids[0x0]	582	1			T5	4		T7	3		T39	5
auto[0]	values[3]	valids[0x1]	290	1			T5	6		T7	1		T39	2
auto[0]	values[4]	valids[0x0]	512	1			T4	4		T5	5		T7	3
auto[0]	values[4]	valids[0x1]	275	1			T7	2		T39	2		T29	2
auto[0]	values[5]	valids[0x0]	545	1			T5	4		T7	10		T15	4
auto[0]	values[5]	valids[0x1]	260	1			T4	1		T5	5		T7	3
auto[0]	values[6]	valids[0x0]	500	1			T4	4		T5	1		T7	4
auto[0]	values[6]	valids[0x1]	334	1			T5	6		T7	4		T28	4
auto[0]	values[7]	valids[0x0]	509	1			T4	1		T5	4		T7	3
auto[0]	values[7]	valids[0x1]	311	1			T4	3		T5	3		T7	2
auto[0]	values[8]	valids[0x0]	3591	1			T4	15		T5	15		T7	22
auto[0]	values[8]	valids[0x1]	2103	1			T4	7		T5	11		T7	15
auto[1]	values[0]	valids[0x0]	4219	1			T8	14		T14	6		T30	43
auto[1]	values[0]	valids[0x1]	16701	1			T8	40		T14	4		T30	175
auto[1]	values[1]	valids[0x1]	550	1			T14	1		T30	5		T16	3
auto[1]	values[2]	valids[0x0]	454	1			T8	1		T14	3		T30	4
auto[1]	values[2]	valids[0x1]	248	1			T30	2		T16	2		T77	5
auto[1]	values[3]	valids[0x0]	375	1			T30	9		T16	2		T77	1
auto[1]	values[3]	valids[0x1]	291	1			T8	1		T14	1		T30	9
auto[1]	values[4]	valids[0x0]	399	1			T30	4		T16	11		T77	8
auto[1]	values[4]	valids[0x1]	273	1			T30	9		T16	4		T77	4
auto[1]	values[5]	valids[0x0]	399	1			T8	1		T30	2		T16	2
auto[1]	values[5]	valids[0x1]	263	1			T30	3		T16	7		T77	1
auto[1]	values[6]	valids[0x0]	431	1			T8	2		T14	1		T30	10
auto[1]	values[6]	valids[0x1]	288	1			T8	4		T30	6		T16	1
auto[1]	values[7]	valids[0x0]	436	1			T30	8		T16	8		T77	6
auto[1]	values[7]	valids[0x1]	250	1			T8	1		T30	5		T16	5
auto[1]	values[8]	valids[0x0]	2756	1			T8	5		T14	3		T30	39
auto[1]	values[8]	valids[0x1]	1980	1			T8	3		T14	1		T30	18