Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3292507

1

T1

302

T3

2096

T4

5021

auto[1]

33235

1

T4

25

T5

120

T7

357

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

881876

1

T1

302

T3

2096

T4

31

auto[1]

2443866

1

T4

5015

T5

10704

T7

4409

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	606327	1			T1	94		T3	1666		T4	5
auto[524288:1048575]	391792	1			T1	2		T3	148		T5	548
auto[1048576:1572863]	368720	1			T4	2895		T5	1325		T7	1
auto[1572864:2097151]	447505	1			T1	28		T4	1226		T5	3032
auto[2097152:2621439]	379130	1			T1	73		T4	516		T5	104
auto[2621440:3145727]	406319	1			T1	21		T4	1		T5	1529
auto[3145728:3670015]	337504	1			T1	61		T3	2		T4	143
auto[3670016:4194303]	388445	1			T1	23		T3	280		T4	260

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2477293

1

T1

153

T3

9

T4

5046

auto[1]

848449

1

T1

149

T3

2087

T5

7

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2874220

1

T1

302

T3

2096

T4

1642

auto[1]

451522

1

T4

3404

T5

2828

T7

311

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	202278	1			T1	94		T3	1666		T4	3
auto[0]	auto[0]	auto[0:524287]	auto[1]	332312	1			T4	1		T5	1024		T7	258
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	103777	1			T1	2		T3	148		T5	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	221122	1			T5	512		T7	4		T39	512
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	68314	1			T4	4		T5	9		T7	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	252132	1			T5	1281		T14	384		T39	256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	119272	1			T1	28		T4	1		T5	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	269583	1			T4	1220		T5	256		T8	398
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	82445	1			T1	73		T4	3		T7	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	223805	1			T5	102		T7	92		T39	2821
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	92071	1			T1	21		T4	1		T5	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	265399	1			T5	1525		T7	513		T8	775
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	102408	1			T1	61		T3	2		T4	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	178101	1			T4	129		T7	2115		T39	2951
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	94924	1			T1	23		T3	280		T4	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	238600	1			T4	256		T5	3102		T7	775
auto[0]	auto[1]	auto[0:524287]	auto[0]	3074	1			T14	3		T39	12		T29	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	64814	1			T14	128		T29	2139		T41	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	884	1			T5	4		T40	2		T30	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	61220	1			T5	15		T40	2968		T16	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2074	1			T4	6		T14	1		T39	46
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	41749	1			T4	2876		T39	3213		T40	770
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2260	1			T5	1		T30	2		T41	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51320	1			T5	2772		T30	257		T77	1912
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2138	1			T4	1		T5	2		T7	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	66525	1			T4	512		T7	307		T39	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	658	1			T5	2		T8	2		T39	8
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	44022	1			T40	2		T16	359		T77	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	752	1			T7	1		T8	2		T40	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	52771	1			T8	1		T40	257		T16	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	700	1			T5	6		T7	1		T8	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	51003	1			T5	1		T8	68		T39	782
auto[1]	auto[0]	auto[0:524287]	auto[0]	448	1			T4	1		T7	2		T39	5
auto[1]	auto[0]	auto[0:524287]	auto[1]	2515	1			T7	67		T29	3		T40	34
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	453	1			T7	1		T16	1		T41	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3589	1			T7	53		T16	18		T41	41
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	439	1			T5	1		T30	2		T16	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3584	1			T5	34		T16	19		T41	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	409	1			T4	1		T8	1		T39	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3913	1			T4	4		T8	1		T29	13
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	427	1			T7	1		T40	1		T30	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2865	1			T7	2		T40	16		T30	42
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	405	1			T7	1		T8	3		T39	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3130	1			T7	38		T8	4		T40	70
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	334	1			T4	1		T7	4		T39	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2565	1			T4	9		T7	68		T29	12
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	325	1			T5	2		T7	3		T8	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2276	1			T5	58		T7	117		T30	18
auto[1]	auto[1]	auto[0:524287]	auto[0]	77	1			T78	1		T42	1		T20	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	809	1			T78	3		T42	1		T20	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	110	1			T5	1		T16	1		T42	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	637	1			T5	13		T16	8		T42	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	64	1			T4	1		T39	5		T42	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	364	1			T4	8		T42	2		T20	8
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	59	1			T5	1		T42	1		T43	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	689	1			T5	1		T44	8		T209	11
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	92	1			T78	2		T42	1		T198	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	833	1			T78	22		T42	1		T198	42
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	57	1			T40	2		T77	1		T157	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	577	1			T40	63		T77	4		T157	15
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	56	1			T8	1		T40	1		T16	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	517	1			T8	1		T40	30		T16	9
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	92	1			T5	1		T42	1		T34	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	525	1			T5	8		T42	2		T26	6

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2006621	1			T1	153		T3	9		T4	1626
auto[0]	auto[0]	auto[1]	839922	1			T1	149		T3	2087		T5	1
auto[0]	auto[1]	auto[0]	438094	1			T4	3395		T5	2801		T7	311
auto[0]	auto[1]	auto[1]	7870	1			T5	2		T55	4		T77	1
auto[1]	auto[0]	auto[0]	27116	1			T4	16		T5	93		T7	356
auto[1]	auto[0]	auto[1]	561	1			T5	2		T7	1		T39	5
auto[1]	auto[1]	auto[0]	5462	1			T4	9		T5	23		T8	2
auto[1]	auto[1]	auto[1]	96	1			T5	2		T39	1		T40	1