Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2685766	1			T1	1		T2	1		T3	1
all_pins[1]	2685766	1			T1	1		T2	1		T3	1
all_pins[2]	2685766	1			T1	1		T2	1		T3	1
all_pins[3]	2685766	1			T1	1		T2	1		T3	1
all_pins[4]	2685766	1			T1	1		T2	1		T3	1
all_pins[5]	2685766	1			T1	1		T2	1		T3	1
all_pins[6]	2685766	1			T1	1		T2	1		T3	1
all_pins[7]	2685766	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21298565	1			T1	8		T2	8		T3	8
values[0x1]	187563	1			T4	33		T17	35		T19	764
transitions[0x0=>0x1]	186524	1			T4	23		T17	32		T19	745
transitions[0x1=>0x0]	186534	1			T4	24		T17	32		T19	745

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2685400	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	366	1			T17	8		T19	4		T21	1
all_pins[0]	transitions[0x0=>0x1]	318	1			T17	8		T19	3		T21	1
all_pins[0]	transitions[0x1=>0x0]	329	1			T4	5		T17	5		T19	6
all_pins[1]	values[0x0]	2685389	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	377	1			T4	5		T17	5		T19	7
all_pins[1]	transitions[0x0=>0x1]	341	1			T4	3		T17	5		T19	3
all_pins[1]	transitions[0x1=>0x0]	144	1			T17	6		T19	2		T21	4
all_pins[2]	values[0x0]	2685586	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	180	1			T4	2		T17	6		T19	6
all_pins[2]	transitions[0x0=>0x1]	128	1			T4	1		T17	5		T19	2
all_pins[2]	transitions[0x1=>0x0]	166	1			T4	3		T17	6		T19	9
all_pins[3]	values[0x0]	2685548	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	218	1			T4	4		T17	7		T19	13
all_pins[3]	transitions[0x0=>0x1]	169	1			T4	3		T17	6		T19	9
all_pins[3]	transitions[0x1=>0x0]	145	1			T4	4		T17	3		T19	3
all_pins[4]	values[0x0]	2685572	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	194	1			T4	5		T17	4		T19	7
all_pins[4]	transitions[0x0=>0x1]	157	1			T4	3		T17	3		T19	5
all_pins[4]	transitions[0x1=>0x0]	1131	1			T4	3		T17	3		T19	3
all_pins[5]	values[0x0]	2684598	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1168	1			T4	5		T17	4		T19	5
all_pins[5]	transitions[0x0=>0x1]	452	1			T4	4		T17	4		T19	3
all_pins[5]	transitions[0x1=>0x0]	184141	1			T4	2		T17	1		T19	714
all_pins[6]	values[0x0]	2500909	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	184857	1			T4	3		T17	1		T19	716
all_pins[6]	transitions[0x0=>0x1]	184807	1			T4	1		T17	1		T19	714
all_pins[6]	transitions[0x1=>0x0]	153	1			T4	7		T19	4		T21	5
all_pins[7]	values[0x0]	2685563	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	203	1			T4	9		T19	6		T21	5
all_pins[7]	transitions[0x0=>0x1]	152	1			T4	8		T19	6		T21	5
all_pins[7]	transitions[0x1=>0x0]	325	1			T17	8		T19	4		T21	1