Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18330

1

T1

8

T4

81

T5

148

auto[1]

12923

1

T4

24

T5

112

T7

155

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4084	1			T4	20		T7	20		T40	82
values[1]	4044	1			T5	94		T37	10		T39	40
values[2]	3369	1			T4	21		T7	55		T39	20
values[3]	3772	1			T5	34		T7	239		T15	20
values[4]	4430	1			T4	29		T5	37		T97	6
values[5]	4258	1			T4	35		T5	20		T7	203
values[6]	3651	1			T1	8		T39	40		T40	157
values[7]	3645	1			T5	75		T38	8		T40	67

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3781	1			T5	20		T7	239		T39	20
values[1]	3929	1			T5	55		T37	10		T38	8
values[2]	4112	1			T5	65		T7	20		T28	24
values[3]	3412	1			T4	21		T7	35		T39	40
values[4]	4793	1			T4	29		T5	54		T97	6
values[5]	4183	1			T1	8		T4	20		T5	66
values[6]	3276	1			T4	35		T39	40		T16	20
values[7]	3767	1			T7	40		T40	157		T55	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	258	1			T190	9		T222	4		T209	27
auto[0]	values[0]	values[1]	139	1			T223	2		T180	14		T224	12
auto[0]	values[0]	values[2]	309	1			T40	6		T41	38		T209	10
auto[0]	values[0]	values[3]	452	1			T43	11		T20	11		T186	6
auto[0]	values[0]	values[4]	256	1			T41	5		T180	14		T181	24
auto[0]	values[0]	values[5]	305	1			T4	17		T43	11		T44	11
auto[0]	values[0]	values[6]	183	1			T44	4		T26	10		T133	18
auto[0]	values[0]	values[7]	246	1			T7	13		T40	14		T185	8
auto[0]	values[1]	values[0]	257	1			T39	17		T21	16		T27	16
auto[0]	values[1]	values[1]	345	1			T37	10		T42	17		T43	11
auto[0]	values[1]	values[2]	334	1			T5	57		T42	13		T20	23
auto[0]	values[1]	values[3]	189	1			T69	24		T19	10		T168	11
auto[0]	values[1]	values[4]	579	1			T39	16		T41	14		T19	11
auto[0]	values[1]	values[5]	439	1			T5	21		T21	25		T168	11
auto[0]	values[1]	values[6]	278	1			T34	16		T168	10		T180	13
auto[0]	values[1]	values[7]	191	1			T26	13		T213	8		T225	4
auto[0]	values[2]	values[0]	291	1			T41	39		T44	47		T187	9
auto[0]	values[2]	values[1]	231	1			T226	8		T227	14		T169	12
auto[0]	values[2]	values[2]	240	1			T7	10		T42	13		T209	12
auto[0]	values[2]	values[3]	160	1			T4	10		T7	25		T43	12
auto[0]	values[2]	values[4]	362	1			T41	13		T43	11		T84	12
auto[0]	values[2]	values[5]	231	1			T40	14		T21	13		T26	13
auto[0]	values[2]	values[6]	151	1			T39	14		T44	7		T181	12
auto[0]	values[2]	values[7]	381	1			T41	7		T76	15		T44	50
auto[0]	values[3]	values[0]	547	1			T7	222		T34	15		T27	13
auto[0]	values[3]	values[1]	242	1			T39	11		T44	12		T180	26
auto[0]	values[3]	values[2]	256	1			T187	8		T181	24		T124	71
auto[0]	values[3]	values[3]	253	1			T39	25		T40	38		T42	11
auto[0]	values[3]	values[4]	158	1			T5	27		T16	11		T168	6
auto[0]	values[3]	values[5]	261	1			T15	20		T42	10		T184	16
auto[0]	values[3]	values[6]	288	1			T39	7		T42	17		T43	21
auto[0]	values[3]	values[7]	392	1			T34	15		T190	12		T228	12
auto[0]	values[4]	values[0]	310	1			T44	75		T26	10		T27	10
auto[0]	values[4]	values[1]	359	1			T40	27		T168	21		T209	8
auto[0]	values[4]	values[2]	342	1			T34	11		T229	32		T209	12
auto[0]	values[4]	values[3]	239	1			T43	13		T216	10		T230	16
auto[0]	values[4]	values[4]	639	1			T4	23		T97	6		T39	18
auto[0]	values[4]	values[5]	193	1			T5	7		T168	9		T130	10
auto[0]	values[4]	values[6]	248	1			T16	13		T42	9		T34	10
auto[0]	values[4]	values[7]	342	1			T231	2		T232	14		T151	29
auto[0]	values[5]	values[0]	226	1			T5	15		T44	12		T20	14
auto[0]	values[5]	values[1]	292	1			T54	12		T43	16		T34	17
auto[0]	values[5]	values[2]	332	1			T28	24		T29	8		T123	10
auto[0]	values[5]	values[3]	261	1			T44	21		T34	9		T210	4
auto[0]	values[5]	values[4]	248	1			T233	8		T168	11		T234	2
auto[0]	values[5]	values[5]	561	1			T7	81		T29	14		T41	18
auto[0]	values[5]	values[6]	251	1			T4	31		T235	10		T27	15
auto[0]	values[5]	values[7]	70	1			T7	11		T169	8		T236	10
auto[0]	values[6]	values[0]	330	1			T19	73		T20	10		T124	7
auto[0]	values[6]	values[1]	146	1			T39	27		T40	8		T41	7
auto[0]	values[6]	values[2]	153	1			T168	10		T180	10		T169	8
auto[0]	values[6]	values[3]	217	1			T209	83		T237	2		T123	15
auto[0]	values[6]	values[4]	419	1			T238	10		T27	10		T239	8
auto[0]	values[6]	values[5]	286	1			T1	8		T26	9		T123	12
auto[0]	values[6]	values[6]	343	1			T44	7		T190	7		T168	14
auto[0]	values[6]	values[7]	276	1			T40	26		T55	20		T124	12
auto[0]	values[7]	values[0]	266	1			T40	59		T21	22		T204	12
auto[0]	values[7]	values[1]	357	1			T5	9		T38	8		T43	12
auto[0]	values[7]	values[2]	231	1			T240	16		T34	11		T26	12
auto[0]	values[7]	values[3]	212	1			T41	22		T34	13		T130	27
auto[0]	values[7]	values[4]	250	1			T5	12		T19	9		T21	17
auto[0]	values[7]	values[5]	221	1			T33	4		T75	20		T43	16
auto[0]	values[7]	values[6]	222	1			T44	11		T20	15		T168	13
auto[0]	values[7]	values[7]	284	1			T124	65		T151	56		T241	12
auto[1]	values[0]	values[0]	148	1			T190	11		T209	6		T26	5
auto[1]	values[0]	values[1]	178	1			T180	8		T242	3		T243	10
auto[1]	values[0]	values[2]	355	1			T40	56		T41	43		T209	10
auto[1]	values[0]	values[3]	294	1			T43	9		T20	9		T186	14
auto[1]	values[0]	values[4]	253	1			T41	15		T180	6		T181	21
auto[1]	values[0]	values[5]	287	1			T4	3		T43	9		T44	32
auto[1]	values[0]	values[6]	134	1			T44	32		T26	10		T133	24
auto[1]	values[0]	values[7]	287	1			T7	7		T40	6		T196	20
auto[1]	values[1]	values[0]	212	1			T39	3		T21	4		T27	9
auto[1]	values[1]	values[1]	193	1			T42	9		T43	9		T44	7
auto[1]	values[1]	values[2]	291	1			T5	8		T42	13		T20	7
auto[1]	values[1]	values[3]	139	1			T19	10		T168	9		T188	8
auto[1]	values[1]	values[4]	161	1			T39	4		T41	22		T19	9
auto[1]	values[1]	values[5]	144	1			T5	8		T21	7		T168	9
auto[1]	values[1]	values[6]	170	1			T34	4		T168	10		T180	8
auto[1]	values[1]	values[7]	122	1			T26	7		T213	12		T244	5
auto[1]	values[2]	values[0]	156	1			T41	13		T44	22		T187	11
auto[1]	values[2]	values[1]	113	1			T169	8		T195	22		T213	10
auto[1]	values[2]	values[2]	153	1			T7	10		T42	12		T209	10
auto[1]	values[2]	values[3]	141	1			T4	11		T7	10		T43	8
auto[1]	values[2]	values[4]	228	1			T89	10		T41	7		T43	9
auto[1]	values[2]	values[5]	218	1			T40	67		T21	12		T26	7
auto[1]	values[2]	values[6]	84	1			T39	6		T44	13		T181	8
auto[1]	values[2]	values[7]	229	1			T41	13		T76	15		T44	8
auto[1]	values[3]	values[0]	129	1			T7	17		T34	5		T27	7
auto[1]	values[3]	values[1]	154	1			T39	9		T44	8		T180	7
auto[1]	values[3]	values[2]	113	1			T187	12		T181	3		T124	11
auto[1]	values[3]	values[3]	264	1			T39	15		T40	8		T42	11
auto[1]	values[3]	values[4]	191	1			T5	7		T179	8		T16	18
auto[1]	values[3]	values[5]	156	1			T42	10		T245	7		T213	7
auto[1]	values[3]	values[6]	189	1			T39	13		T42	6		T43	19
auto[1]	values[3]	values[7]	179	1			T34	5		T190	8		T21	4
auto[1]	values[4]	values[0]	160	1			T44	6		T26	11		T27	26
auto[1]	values[4]	values[1]	413	1			T40	3		T168	19		T209	21
auto[1]	values[4]	values[2]	295	1			T34	9		T209	33		T187	9
auto[1]	values[4]	values[3]	88	1			T43	7		T246	10		T247	8
auto[1]	values[4]	values[4]	318	1			T4	6		T39	2		T40	9
auto[1]	values[4]	values[5]	98	1			T5	30		T168	11		T130	10
auto[1]	values[4]	values[6]	160	1			T16	7		T42	14		T34	10
auto[1]	values[4]	values[7]	226	1			T248	16		T151	9		T245	16
auto[1]	values[5]	values[0]	211	1			T5	5		T44	8		T20	8
auto[1]	values[5]	values[1]	275	1			T54	8		T43	4		T34	23
auto[1]	values[5]	values[2]	268	1			T29	31		T123	57		T124	13
auto[1]	values[5]	values[3]	222	1			T44	27		T34	11		T249	20
auto[1]	values[5]	values[4]	360	1			T168	9		T124	9		T46	6
auto[1]	values[5]	values[5]	424	1			T7	102		T29	19		T41	9
auto[1]	values[5]	values[6]	181	1			T4	4		T27	6		T133	12
auto[1]	values[5]	values[7]	76	1			T7	9		T250	18		T169	12
auto[1]	values[6]	values[0]	178	1			T19	8		T20	10		T124	13
auto[1]	values[6]	values[1]	249	1			T39	13		T40	12		T41	16
auto[1]	values[6]	values[2]	238	1			T168	10		T180	10		T169	16
auto[1]	values[6]	values[3]	82	1			T209	11		T123	7		T169	12
auto[1]	values[6]	values[4]	87	1			T27	10		T199	9		T172	13
auto[1]	values[6]	values[5]	179	1			T251	12		T26	11		T123	8
auto[1]	values[6]	values[6]	194	1			T44	13		T190	13		T168	6
auto[1]	values[6]	values[7]	274	1			T40	111		T124	15		T252	12
auto[1]	values[7]	values[0]	102	1			T40	8		T21	9		T245	4
auto[1]	values[7]	values[1]	243	1			T5	46		T43	8		T27	10
auto[1]	values[7]	values[2]	202	1			T34	9		T26	10		T46	21
auto[1]	values[7]	values[3]	199	1			T41	7		T34	7		T130	7
auto[1]	values[7]	values[4]	284	1			T5	8		T19	24		T21	6
auto[1]	values[7]	values[5]	180	1			T43	4		T253	10		T168	9
auto[1]	values[7]	values[6]	200	1			T44	18		T20	5		T168	7
auto[1]	values[7]	values[7]	192	1			T124	6		T151	9		T241	8