Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	393	1			T5	2		T7	5		T38	4
auto[ReadAddrCrossIntoMailbox]	312	1			T7	2		T39	2		T40	10
auto[ReadAddrCrossOutOfMailbox]	308	1			T39	3		T40	5		T41	2
auto[ReadAddrCrossAllMailbox]	189	1			T4	1		T7	1		T39	4
auto[ReadAddrOutsideMailbox]	3505	1			T4	16		T5	21		T7	31

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2340

1

T4

8

T5

17

T7

21

auto[1]

2367

1

T4

9

T5

6

T7

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	739	1			T4	2		T5	7		T7	3
read_ops[0x0b]	757	1			T4	3		T5	1		T7	12
read_ops[0x3b]	811	1			T4	2		T5	5		T7	5
read_ops[0x6b]	817	1			T4	5		T5	4		T7	2
read_ops[0xbb]	806	1			T4	3		T5	3		T7	6
read_ops[0xeb]	777	1			T4	2		T5	3		T7	11

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T168	1		T132	1		T227	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T19	2		T44	1		T180	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T44	1		T180	1		T254	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T40	1		T42	1		T19	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T39	1		T168	1		T27	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T42	1		T43	1		T180	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T7	1		T21	2		T187	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T34	1		T26	1		T132	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T4	2		T5	7		T7	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T7	1		T39	2		T40	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T7	1		T40	1		T42	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T41	1		T186	1		T34	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T7	1		T39	1		T40	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T44	1		T168	1		T26	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T41	1		T44	1		T209	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T44	1		T210	1		T180	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T40	2		T44	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T44	1		T133	1		T255	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	272	1			T5	1		T7	6		T28	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T4	3		T7	4		T28	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T5	1		T40	1		T33	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T7	2		T40	3		T33	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T40	2		T44	1		T168	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T44	1		T168	1		T26	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T40	1		T20	1		T168	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T40	1		T43	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T40	1		T33	1		T168	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T4	1		T39	1		T33	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	301	1			T5	1		T7	2		T15	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T4	1		T5	3		T7	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T38	2		T39	1		T43	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T5	1		T38	2		T40	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T39	1		T40	2		T43	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T40	2		T43	1		T44	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T168	1		T187	1		T27	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T43	1		T34	3		T132	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T39	1		T44	2		T20	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T44	1		T168	4		T26	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T4	3		T5	3		T7	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T4	2		T7	1		T15	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T7	1		T40	1		T228	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T39	1		T40	1		T41	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T41	1		T42	1		T209	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T40	1		T43	1		T44	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T40	1		T42	1		T43	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T40	2		T41	1		T43	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T34	1		T133	1		T242	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T41	1		T44	1		T20	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	313	1			T4	2		T5	1		T7	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T4	1		T5	2		T7	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	18	1			T40	1		T41	1		T42	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T7	1		T41	1		T43	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T209	1		T26	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T7	1		T40	1		T41	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T44	1		T168	1		T209	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T39	2		T34	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T39	1		T124	1		T189	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T39	1		T40	1		T43	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T4	1		T5	3		T7	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T4	1		T7	4		T15	1