Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3844	1			T5	34		T39	40		T29	72
values[1]	4291	1			T7	109		T16	20		T41	56
values[2]	4237	1			T5	65		T7	289		T55	20
values[3]	3236	1			T5	29		T38	8		T39	40
values[4]	4551	1			T1	8		T4	21		T5	20
values[5]	3878	1			T4	20		T37	10		T39	20
values[6]	3545	1			T5	75		T39	20		T179	8
values[7]	3671	1			T4	64		T5	37		T7	119

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3979	1			T1	8		T5	20		T39	60
values[1]	3437	1			T29	33		T40	40		T54	20
values[2]	3963	1			T7	35		T97	6		T179	8
values[3]	3631	1			T4	20		T7	20		T15	20
values[4]	4074	1			T4	64		T5	84		T37	10
values[5]	4190	1			T5	34		T7	129		T38	8
values[6]	4247	1			T5	20		T7	94		T39	40
values[7]	3732	1			T4	21		T5	102		T7	239

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30484

1

T1

8

T4

102

T5

256

auto[1]

769

1

T4

3

T5

4

T7

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	308	1			T39	39		T190	20		T26	22
auto[0]	values[0]	values[1]	317	1			T29	30		T41	36		T231	2
auto[0]	values[0]	values[2]	459	1			T251	12		T20	19		T256	6
auto[0]	values[0]	values[3]	373	1			T27	24		T189	84		T195	19
auto[0]	values[0]	values[4]	653	1			T40	29		T19	32		T257	10
auto[0]	values[0]	values[5]	632	1			T5	34		T168	19		T221	12
auto[0]	values[0]	values[6]	760	1			T44	71		T168	19		T209	31
auto[0]	values[0]	values[7]	254	1			T29	37		T253	10		T168	20
auto[0]	values[1]	values[0]	550	1			T27	26		T130	34		T151	43
auto[0]	values[1]	values[1]	522	1			T41	36		T42	20		T34	20
auto[0]	values[1]	values[2]	516	1			T7	35		T16	20		T42	23
auto[0]	values[1]	values[3]	489	1			T41	20		T19	18		T43	20
auto[0]	values[1]	values[4]	561	1			T168	20		T187	28		T249	30
auto[0]	values[1]	values[5]	461	1			T44	58		T223	2		T21	29
auto[0]	values[1]	values[6]	730	1			T7	73		T44	20		T168	19
auto[0]	values[1]	values[7]	366	1			T26	21		T234	2		T181	19
auto[0]	values[2]	values[0]	194	1			T20	21		T26	25		T258	2
auto[0]	values[2]	values[1]	513	1			T197	18		T181	20		T123	20
auto[0]	values[2]	values[2]	615	1			T41	61		T43	19		T44	20
auto[0]	values[2]	values[3]	393	1			T33	4		T41	20		T168	39
auto[0]	values[2]	values[4]	320	1			T55	20		T43	20		T34	19
auto[0]	values[2]	values[5]	848	1			T7	129		T168	19		T180	20
auto[0]	values[2]	values[6]	521	1			T7	20		T250	14		T187	20
auto[0]	values[2]	values[7]	752	1			T5	64		T7	140		T34	19
auto[0]	values[3]	values[0]	402	1			T40	20		T185	8		T181	24
auto[0]	values[3]	values[1]	460	1			T40	20		T43	58		T130	31
auto[0]	values[3]	values[2]	364	1			T27	21		T86	16		T259	16
auto[0]	values[3]	values[3]	344	1			T39	18		T186	20		T27	20
auto[0]	values[3]	values[4]	411	1			T5	29		T42	24		T260	18
auto[0]	values[3]	values[5]	378	1			T38	8		T39	20		T43	19
auto[0]	values[3]	values[6]	409	1			T69	24		T42	23		T21	23
auto[0]	values[3]	values[7]	370	1			T181	20		T123	19		T151	20
auto[0]	values[4]	values[0]	632	1			T1	8		T5	19		T40	81
auto[0]	values[4]	values[1]	383	1			T26	19		T27	29		T261	16
auto[0]	values[4]	values[2]	592	1			T190	20		T262	16		T181	27
auto[0]	values[4]	values[3]	538	1			T39	40		T42	22		T44	80
auto[0]	values[4]	values[4]	517	1			T240	16		T186	19		T21	22
auto[0]	values[4]	values[5]	742	1			T43	19		T180	20		T263	4
auto[0]	values[4]	values[6]	545	1			T39	20		T40	66		T210	4
auto[0]	values[4]	values[7]	487	1			T4	21		T28	24		T40	20
auto[0]	values[5]	values[0]	634	1			T40	60		T20	29		T190	17
auto[0]	values[5]	values[1]	514	1			T43	20		T44	20		T264	2
auto[0]	values[5]	values[2]	441	1			T16	29		T41	50		T44	27
auto[0]	values[5]	values[3]	528	1			T4	20		T20	20		T27	18
auto[0]	values[5]	values[4]	450	1			T37	10		T40	26		T43	19
auto[0]	values[5]	values[5]	378	1			T89	10		T151	23		T265	4
auto[0]	values[5]	values[6]	412	1			T34	20		T46	20		T169	57
auto[0]	values[5]	values[7]	420	1			T39	20		T34	18		T169	22
auto[0]	values[6]	values[0]	384	1			T34	38		T180	20		T130	20
auto[0]	values[6]	values[1]	326	1			T54	18		T75	20		T209	93
auto[0]	values[6]	values[2]	483	1			T179	8		T186	17		T229	32
auto[0]	values[6]	values[3]	466	1			T41	23		T206	8		T180	42
auto[0]	values[6]	values[4]	617	1			T5	54		T42	23		T187	20
auto[0]	values[6]	values[5]	313	1			T40	113		T41	29		T152	20
auto[0]	values[6]	values[6]	434	1			T5	19		T39	19		T42	23
auto[0]	values[6]	values[7]	425	1			T43	20		T44	20		T266	2
auto[0]	values[7]	values[0]	775	1			T39	18		T20	22		T34	20
auto[0]	values[7]	values[1]	301	1			T40	20		T44	20		T34	20
auto[0]	values[7]	values[2]	407	1			T97	6		T40	20		T43	19
auto[0]	values[7]	values[3]	416	1			T7	20		T15	20		T267	12
auto[0]	values[7]	values[4]	434	1			T4	61		T19	79		T268	8
auto[0]	values[7]	values[5]	359	1			T76	30		T19	20		T34	20
auto[0]	values[7]	values[6]	327	1			T169	23		T269	16		T270	4
auto[0]	values[7]	values[7]	559	1			T5	37		T7	97		T44	23
auto[1]	values[0]	values[0]	9	1			T39	1		T213	2		T271	4
auto[1]	values[0]	values[1]	5	1			T29	3		T272	2		-	-
auto[1]	values[0]	values[2]	11	1			T20	1		T273	3		T246	1
auto[1]	values[0]	values[3]	10	1			T189	1		T195	1		T213	1
auto[1]	values[0]	values[4]	15	1			T40	1		T19	1		T151	3
auto[1]	values[0]	values[5]	10	1			T168	1		T169	3		T255	1
auto[1]	values[0]	values[6]	22	1			T44	10		T168	1		T209	2
auto[1]	values[0]	values[7]	6	1			T29	2		T199	3		T274	1
auto[1]	values[1]	values[0]	13	1			T169	4		T245	1		T213	1
auto[1]	values[1]	values[1]	14	1			T46	1		T169	1		T195	1
auto[1]	values[1]	values[2]	14	1			T42	3		T213	2		T152	2
auto[1]	values[1]	values[3]	11	1			T19	2		T275	2		T276	2
auto[1]	values[1]	values[4]	14	1			T187	1		T249	4		T133	1
auto[1]	values[1]	values[5]	8	1			T180	2		T124	2		T213	2
auto[1]	values[1]	values[6]	16	1			T7	1		T168	1		T181	3
auto[1]	values[1]	values[7]	6	1			T181	1		T277	3		T278	2
auto[1]	values[2]	values[0]	2	1			T279	2		-	-		-	-
auto[1]	values[2]	values[1]	15	1			T130	2		T133	3		T201	3
auto[1]	values[2]	values[2]	13	1			T41	4		T43	1		T169	3
auto[1]	values[2]	values[3]	8	1			T168	1		T187	1		T130	2
auto[1]	values[2]	values[4]	5	1			T34	1		T280	1		T281	2
auto[1]	values[2]	values[5]	14	1			T168	1		T169	4		T282	1
auto[1]	values[2]	values[6]	6	1			T250	4		T283	2		-	-
auto[1]	values[2]	values[7]	18	1			T5	1		T34	1		T284	5
auto[1]	values[3]	values[0]	7	1			T181	1		T169	1		T193	2
auto[1]	values[3]	values[1]	14	1			T43	2		T130	4		T201	3
auto[1]	values[3]	values[2]	9	1			T27	1		T123	5		T241	1
auto[1]	values[3]	values[3]	17	1			T39	2		T27	3		T180	1
auto[1]	values[3]	values[4]	9	1			T42	1		T199	1		T172	1
auto[1]	values[3]	values[5]	7	1			T43	1		T285	1		T243	3
auto[1]	values[3]	values[6]	12	1			T168	3		T286	1		T52	3
auto[1]	values[3]	values[7]	23	1			T123	1		T199	5		T241	1
auto[1]	values[4]	values[0]	27	1			T5	1		T123	3		T189	1
auto[1]	values[4]	values[1]	15	1			T26	1		T27	1		T242	3
auto[1]	values[4]	values[2]	9	1			T149	3		T189	1		T213	3
auto[1]	values[4]	values[3]	8	1			T44	1		T287	1		T288	1
auto[1]	values[4]	values[4]	19	1			T186	1		T21	1		T187	1
auto[1]	values[4]	values[5]	17	1			T43	1		T189	1		T151	3
auto[1]	values[4]	values[6]	16	1			T40	1		T26	2		T191	1
auto[1]	values[4]	values[7]	4	1			T213	1		T279	1		T289	1
auto[1]	values[5]	values[0]	9	1			T40	2		T190	3		T26	2
auto[1]	values[5]	values[1]	17	1			T124	3		T130	2		T285	3
auto[1]	values[5]	values[2]	11	1			T41	2		T44	1		T290	2
auto[1]	values[5]	values[3]	19	1			T27	2		T217	2		T46	2
auto[1]	values[5]	values[4]	6	1			T43	1		T44	2		T20	1
auto[1]	values[5]	values[5]	10	1			T151	1		T279	4		T291	2
auto[1]	values[5]	values[6]	7	1			T169	1		T282	1		T292	2
auto[1]	values[5]	values[7]	22	1			T34	2		T169	1		T172	1
auto[1]	values[6]	values[0]	18	1			T34	2		T46	1		T246	3
auto[1]	values[6]	values[1]	16	1			T54	2		T209	1		T27	1
auto[1]	values[6]	values[2]	7	1			T186	3		T293	3		T294	1
auto[1]	values[6]	values[3]	6	1			T180	3		T273	1		T295	1
auto[1]	values[6]	values[4]	21	1			T5	1		T42	3		T187	2
auto[1]	values[6]	values[5]	6	1			T40	4		T294	2		-	-
auto[1]	values[6]	values[6]	14	1			T5	1		T39	1		T123	1
auto[1]	values[6]	values[7]	9	1			T34	1		T169	1		T296	1
auto[1]	values[7]	values[0]	15	1			T39	2		T26	3		T180	2
auto[1]	values[7]	values[1]	5	1			T286	1		T293	1		T297	2
auto[1]	values[7]	values[2]	12	1			T43	1		T123	1		T191	2
auto[1]	values[7]	values[3]	5	1			T151	2		T208	1		T298	2
auto[1]	values[7]	values[4]	22	1			T4	3		T19	2		T268	2
auto[1]	values[7]	values[5]	7	1			T296	4		T287	2		T299	1
auto[1]	values[7]	values[6]	16	1			T169	3		T243	2		T173	5
auto[1]	values[7]	values[7]	11	1			T7	2		T44	1		T168	2