Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	819	1			T4	14		T17	28		T19	24
all_values[1]	819	1			T4	14		T17	28		T19	24
all_values[2]	819	1			T4	14		T17	28		T19	24
all_values[3]	819	1			T4	14		T17	28		T19	24
all_values[4]	819	1			T4	14		T17	28		T19	24
all_values[5]	819	1			T4	14		T17	28		T19	24
all_values[6]	819	1			T4	14		T17	28		T19	24
all_values[7]	819	1			T4	14		T17	28		T19	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3473

1

T4

60

T17

134

T19

97

auto[1]

3079

1

T4

52

T17

90

T19

95

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2683

1

T4

36

T17

101

T19

78

auto[1]

3869

1

T4

76

T17

123

T19

114

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3748

1

T4

58

T17

135

T19

109

auto[1]

2804

1

T4

54

T17

89

T19

83

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	174	1			T4	4		T17	4		T19	10
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T17	5		T19	1		T21	1
all_values[0]	auto[0]	auto[1]	auto[0]	158	1			T4	3		T17	2		T19	3
all_values[0]	auto[0]	auto[1]	auto[1]	74	1			T17	3		T19	3		T156	1
all_values[0]	auto[1]	auto[0]	auto[1]	185	1			T4	6		T17	9		T19	4
all_values[0]	auto[1]	auto[1]	auto[1]	150	1			T4	1		T17	5		T19	3
all_values[1]	auto[0]	auto[0]	auto[0]	191	1			T4	1		T17	7		T19	6
all_values[1]	auto[0]	auto[0]	auto[1]	69	1			T4	1		T17	3		T19	2
all_values[1]	auto[0]	auto[1]	auto[0]	123	1			T4	3		T17	1		T19	5
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T4	4		T17	2		T19	1
all_values[1]	auto[1]	auto[0]	auto[1]	204	1			T4	4		T17	11		T19	2
all_values[1]	auto[1]	auto[1]	auto[1]	156	1			T4	1		T17	4		T19	8
all_values[2]	auto[0]	auto[0]	auto[0]	167	1			T4	2		T17	7		T19	2
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T4	2		T17	1		T19	6
all_values[2]	auto[0]	auto[1]	auto[0]	150	1			T4	1		T17	8		T19	7
all_values[2]	auto[0]	auto[1]	auto[1]	60	1			T17	2		T21	2		T25	2
all_values[2]	auto[1]	auto[0]	auto[1]	190	1			T4	7		T17	6		T19	1
all_values[2]	auto[1]	auto[1]	auto[1]	168	1			T4	2		T17	4		T19	8
all_values[3]	auto[0]	auto[0]	auto[0]	152	1			T4	3		T17	6		T19	2
all_values[3]	auto[0]	auto[0]	auto[1]	85	1			T4	2		T17	2		T19	3
all_values[3]	auto[0]	auto[1]	auto[0]	120	1			T4	1		T17	4		T19	1
all_values[3]	auto[0]	auto[1]	auto[1]	82	1			T4	2		T17	3		T19	4
all_values[3]	auto[1]	auto[0]	auto[1]	191	1			T4	3		T17	6		T19	3
all_values[3]	auto[1]	auto[1]	auto[1]	189	1			T4	3		T17	7		T19	11
all_values[4]	auto[0]	auto[0]	auto[0]	190	1			T4	2		T17	8		T19	2
all_values[4]	auto[0]	auto[0]	auto[1]	57	1			T4	1		T17	3		T19	3
all_values[4]	auto[0]	auto[1]	auto[0]	156	1			T4	3		T17	10		T19	3
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T4	3		T19	3		T20	1
all_values[4]	auto[1]	auto[0]	auto[1]	181	1			T4	2		T17	3		T19	11
all_values[4]	auto[1]	auto[1]	auto[1]	157	1			T4	3		T17	4		T19	2
all_values[5]	auto[0]	auto[0]	auto[0]	229	1			T4	4		T17	10		T19	6
all_values[5]	auto[0]	auto[1]	auto[0]	255	1			T4	2		T17	10		T19	8
all_values[5]	auto[1]	auto[0]	auto[1]	184	1			T4	5		T17	5		T19	5
all_values[5]	auto[1]	auto[1]	auto[1]	151	1			T4	3		T17	3		T19	5
all_values[6]	auto[0]	auto[0]	auto[0]	184	1			T4	4		T17	8		T19	7
all_values[6]	auto[0]	auto[0]	auto[1]	64	1			T4	1		T17	4		T19	1
all_values[6]	auto[0]	auto[1]	auto[0]	148	1			T4	2		T17	5		T19	6
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T4	2		T21	2		T27	2
all_values[6]	auto[1]	auto[0]	auto[1]	184	1			T4	2		T17	8		T19	6
all_values[6]	auto[1]	auto[1]	auto[1]	162	1			T4	3		T17	3		T19	4
all_values[7]	auto[0]	auto[0]	auto[0]	159	1			T4	1		T17	4		T19	8
all_values[7]	auto[0]	auto[0]	auto[1]	95	1			T17	5		T21	2		T27	3
all_values[7]	auto[0]	auto[1]	auto[0]	127	1			T17	7		T19	2		T20	3
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T4	4		T17	1		T19	4
all_values[7]	auto[1]	auto[0]	auto[1]	176	1			T4	3		T17	9		T19	6
all_values[7]	auto[1]	auto[1]	auto[1]	176	1			T4	6		T17	2		T19	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal