Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1800

1

T2

4

T4

3

T8

3

auto[1]

1788

1

T2

3

T4

9

T8

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2153

1

T4

6

T8

8

T11

7

auto[1]

1435

1

T2

7

T4

6

T11

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2754

1

T2

7

T4

8

T8

7

auto[1]

834

1

T4

4

T8

1

T11

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	673	1			T2	1		T4	2		T22	1
valid[1]	776	1			T4	3		T8	2		T11	6
valid[2]	741	1			T2	2		T4	2		T8	4
valid[3]	687	1			T2	1		T4	3		T8	1
valid[4]	711	1			T2	3		T4	2		T8	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T29	3		T45	2		T56	2
auto[0]	auto[0]	valid[0]	auto[1]	157	1			T2	1		T4	1		T22	1
auto[0]	auto[0]	valid[1]	auto[0]	155	1			T4	1		T8	1		T11	2
auto[0]	auto[0]	valid[1]	auto[1]	132	1			T11	2		T23	1		T82	1
auto[0]	auto[0]	valid[2]	auto[0]	140	1			T11	1		T32	2		T29	3
auto[0]	auto[0]	valid[2]	auto[1]	147	1			T2	2		T11	2		T23	1
auto[0]	auto[0]	valid[3]	auto[0]	124	1			T8	1		T29	1		T56	1
auto[0]	auto[0]	valid[3]	auto[1]	118	1			T2	1		T23	1		T327	6
auto[0]	auto[0]	valid[4]	auto[0]	135	1			T32	1		T29	1		T45	4
auto[0]	auto[0]	valid[4]	auto[1]	138	1			T23	2		T82	1		T83	2
auto[0]	auto[1]	valid[0]	auto[0]	116	1			T14	1		T32	1		T45	1
auto[0]	auto[1]	valid[0]	auto[1]	137	1			T14	1		T23	2		T29	1
auto[0]	auto[1]	valid[1]	auto[0]	142	1			T8	1		T11	1		T14	4
auto[0]	auto[1]	valid[1]	auto[1]	167	1			T4	2		T14	1		T23	3
auto[0]	auto[1]	valid[2]	auto[0]	129	1			T8	4		T11	1		T14	1
auto[0]	auto[1]	valid[2]	auto[1]	161	1			T4	1		T11	1		T14	3
auto[0]	auto[1]	valid[3]	auto[0]	124	1			T4	1		T32	1		T29	1
auto[0]	auto[1]	valid[3]	auto[1]	136	1			T4	1		T11	1		T23	5
auto[0]	auto[1]	valid[4]	auto[0]	131	1			T32	1		T16	1		T323	1
auto[0]	auto[1]	valid[4]	auto[1]	142	1			T2	3		T4	1		T22	1
auto[1]	auto[0]	valid[0]	auto[0]	72	1			T14	1		T32	1		T29	1
auto[1]	auto[0]	valid[1]	auto[0]	98	1			T11	1		T45	1		T56	2
auto[1]	auto[0]	valid[2]	auto[0]	82	1			T4	1		T29	1		T45	1
auto[1]	auto[0]	valid[3]	auto[0]	92	1			T14	1		T32	1		T29	1
auto[1]	auto[0]	valid[4]	auto[0]	87	1			T8	1		T32	1		T45	1
auto[1]	auto[1]	valid[0]	auto[0]	68	1			T4	1		T14	1		T32	2
auto[1]	auto[1]	valid[1]	auto[0]	82	1			T14	3		T29	1		T30	1
auto[1]	auto[1]	valid[2]	auto[0]	82	1			T45	1		T56	2		T315	1
auto[1]	auto[1]	valid[3]	auto[0]	93	1			T4	1		T11	1		T14	2
auto[1]	auto[1]	valid[4]	auto[0]	78	1			T4	1		T14	3		T29	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal