Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52775

1

T4

167

T6

48

T8

191

auto[1]

14981

1

T2

7

T4

45

T11

97

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48755

1

T2

7

T4

128

T6

36

auto[1]

19001

1

T4

84

T6

12

T8

65

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34820	1			T2	7		T4	116		T6	21
others[1]	5631	1			T4	15		T6	5		T8	12
others[2]	5586	1			T4	15		T6	4		T8	17
others[3]	6627	1			T4	23		T6	7		T8	22
interest[1]	3781	1			T4	14		T6	4		T8	12
interest[4]	22794	1			T2	7		T4	70		T6	14
interest[64]	11311	1			T4	29		T6	7		T8	35

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17211	1			T4	47		T6	16		T8	66
auto[0]	auto[0]	others[1]	2791	1			T4	6		T6	3		T8	7
auto[0]	auto[0]	others[2]	2791	1			T4	1		T6	3		T8	11
auto[0]	auto[0]	others[3]	3330	1			T4	14		T6	4		T8	14
auto[0]	auto[0]	interest[1]	1959	1			T4	6		T6	3		T8	8
auto[0]	auto[0]	interest[4]	11232	1			T4	31		T6	10		T8	42
auto[0]	auto[0]	interest[64]	5692	1			T4	9		T6	7		T8	20
auto[0]	auto[1]	others[0]	7857	1			T2	7		T4	25		T11	55
auto[0]	auto[1]	others[1]	1267	1			T4	6		T11	9		T22	7
auto[0]	auto[1]	others[2]	1227	1			T4	4		T11	8		T22	2
auto[0]	auto[1]	others[3]	1418	1			T4	1		T11	8		T22	6
auto[0]	auto[1]	interest[1]	802	1			T4	4		T11	1		T22	2
auto[0]	auto[1]	interest[4]	5255	1			T2	7		T4	14		T11	33
auto[0]	auto[1]	interest[64]	2410	1			T4	5		T11	16		T22	3
auto[1]	auto[0]	others[0]	9752	1			T4	44		T6	5		T8	27
auto[1]	auto[0]	others[1]	1573	1			T4	3		T6	2		T8	5
auto[1]	auto[0]	others[2]	1568	1			T4	10		T6	1		T8	6
auto[1]	auto[0]	others[3]	1879	1			T4	8		T6	3		T8	8
auto[1]	auto[0]	interest[1]	1020	1			T4	4		T6	1		T8	4
auto[1]	auto[0]	interest[4]	6307	1			T4	25		T6	4		T8	18
auto[1]	auto[0]	interest[64]	3209	1			T4	15		T8	15		T11	16

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal