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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T1022 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1949039807 Aug 03 04:23:22 PM PDT 24 Aug 03 04:23:24 PM PDT 24 27745430 ps
T1023 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1919938898 Aug 03 04:21:55 PM PDT 24 Aug 03 04:21:57 PM PDT 24 266708186 ps
T109 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.851104713 Aug 03 04:22:06 PM PDT 24 Aug 03 04:22:09 PM PDT 24 397259591 ps
T118 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1998109000 Aug 03 04:22:01 PM PDT 24 Aug 03 04:22:03 PM PDT 24 80223273 ps
T162 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1733312178 Aug 03 04:21:19 PM PDT 24 Aug 03 04:21:34 PM PDT 24 1128881179 ps
T1024 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.502379355 Aug 03 04:21:39 PM PDT 24 Aug 03 04:21:40 PM PDT 24 70944866 ps
T81 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1482139116 Aug 03 04:24:00 PM PDT 24 Aug 03 04:24:01 PM PDT 24 61424357 ps
T1025 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3142687956 Aug 03 04:20:47 PM PDT 24 Aug 03 04:20:54 PM PDT 24 112903528 ps
T1026 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2973581263 Aug 03 04:22:28 PM PDT 24 Aug 03 04:22:29 PM PDT 24 13649216 ps
T106 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2633086669 Aug 03 04:20:50 PM PDT 24 Aug 03 04:20:58 PM PDT 24 4749709990 ps
T1027 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2465051256 Aug 03 04:22:51 PM PDT 24 Aug 03 04:22:52 PM PDT 24 32946116 ps
T1028 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1313799490 Aug 03 04:22:24 PM PDT 24 Aug 03 04:22:26 PM PDT 24 454263151 ps
T1029 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.479466010 Aug 03 04:22:22 PM PDT 24 Aug 03 04:22:24 PM PDT 24 40428399 ps
T1030 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.668176455 Aug 03 04:20:45 PM PDT 24 Aug 03 04:20:49 PM PDT 24 109462321 ps
T1031 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1407548481 Aug 03 04:22:54 PM PDT 24 Aug 03 04:22:55 PM PDT 24 87183682 ps
T1032 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1180161821 Aug 03 04:22:23 PM PDT 24 Aug 03 04:22:24 PM PDT 24 35302530 ps
T1033 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3759930977 Aug 03 04:21:39 PM PDT 24 Aug 03 04:21:40 PM PDT 24 98629366 ps
T1034 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1145490383 Aug 03 04:22:06 PM PDT 24 Aug 03 04:22:07 PM PDT 24 22620910 ps
T1035 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.629068232 Aug 03 04:22:05 PM PDT 24 Aug 03 04:22:08 PM PDT 24 99848022 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4194780720 Aug 03 04:24:25 PM PDT 24 Aug 03 04:24:38 PM PDT 24 207282188 ps
T120 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1364867475 Aug 03 04:23:57 PM PDT 24 Aug 03 04:24:21 PM PDT 24 5760823868 ps
T1036 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.763545549 Aug 03 04:22:48 PM PDT 24 Aug 03 04:22:50 PM PDT 24 41701946 ps
T1037 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3682587955 Aug 03 04:21:50 PM PDT 24 Aug 03 04:21:53 PM PDT 24 70290674 ps
T1038 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1462052333 Aug 03 04:21:39 PM PDT 24 Aug 03 04:21:42 PM PDT 24 723670797 ps
T99 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.909223980 Aug 03 04:21:55 PM PDT 24 Aug 03 04:22:00 PM PDT 24 268903810 ps
T1039 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1706142670 Aug 03 04:22:28 PM PDT 24 Aug 03 04:22:30 PM PDT 24 395761391 ps
T1040 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1818413572 Aug 03 04:21:54 PM PDT 24 Aug 03 04:21:57 PM PDT 24 431194736 ps
T122 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.208382602 Aug 03 04:21:49 PM PDT 24 Aug 03 04:21:51 PM PDT 24 19386002 ps
T103 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1616624358 Aug 03 04:22:21 PM PDT 24 Aug 03 04:22:24 PM PDT 24 46265975 ps
T1041 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3759987834 Aug 03 04:21:55 PM PDT 24 Aug 03 04:21:56 PM PDT 24 17603554 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3518228968 Aug 03 04:21:55 PM PDT 24 Aug 03 04:21:58 PM PDT 24 116858388 ps
T121 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1729008418 Aug 03 04:22:31 PM PDT 24 Aug 03 04:22:33 PM PDT 24 91679928 ps
T1043 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.231022159 Aug 03 04:22:41 PM PDT 24 Aug 03 04:22:42 PM PDT 24 43175110 ps
T166 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3446399368 Aug 03 04:22:01 PM PDT 24 Aug 03 04:22:14 PM PDT 24 200059904 ps
T1044 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1136756794 Aug 03 04:20:39 PM PDT 24 Aug 03 04:20:40 PM PDT 24 12700981 ps
T1045 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4256993981 Aug 03 04:21:55 PM PDT 24 Aug 03 04:21:58 PM PDT 24 161880538 ps
T1046 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3241287858 Aug 03 04:22:37 PM PDT 24 Aug 03 04:22:38 PM PDT 24 24091627 ps
T102 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2424528060 Aug 03 04:21:56 PM PDT 24 Aug 03 04:22:00 PM PDT 24 683253106 ps
T1047 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.432790843 Aug 03 04:23:45 PM PDT 24 Aug 03 04:23:56 PM PDT 24 201300178 ps
T163 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.92874909 Aug 03 04:22:04 PM PDT 24 Aug 03 04:22:12 PM PDT 24 1286433059 ps
T1048 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3716990352 Aug 03 04:22:26 PM PDT 24 Aug 03 04:22:27 PM PDT 24 38126877 ps
T1049 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2601059198 Aug 03 04:22:48 PM PDT 24 Aug 03 04:23:00 PM PDT 24 196895076 ps
T1050 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1181632824 Aug 03 04:23:08 PM PDT 24 Aug 03 04:23:10 PM PDT 24 54324579 ps
T101 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1927790412 Aug 03 04:21:40 PM PDT 24 Aug 03 04:21:43 PM PDT 24 51083168 ps
T1051 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2319714538 Aug 03 04:21:39 PM PDT 24 Aug 03 04:21:42 PM PDT 24 89936154 ps
T1052 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.681893689 Aug 03 04:22:02 PM PDT 24 Aug 03 04:22:05 PM PDT 24 45505141 ps
T1053 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3679130536 Aug 03 04:21:56 PM PDT 24 Aug 03 04:22:20 PM PDT 24 3791125406 ps
T1054 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.999523382 Aug 03 04:21:54 PM PDT 24 Aug 03 04:21:55 PM PDT 24 24819302 ps
T1055 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1577931218 Aug 03 04:23:46 PM PDT 24 Aug 03 04:23:47 PM PDT 24 26333384 ps
T1056 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3312421625 Aug 03 04:20:51 PM PDT 24 Aug 03 04:20:54 PM PDT 24 99373788 ps
T105 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.111440864 Aug 03 04:21:13 PM PDT 24 Aug 03 04:21:18 PM PDT 24 1267620379 ps
T1057 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1994301597 Aug 03 04:21:33 PM PDT 24 Aug 03 04:21:40 PM PDT 24 105615295 ps
T1058 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3810602261 Aug 03 04:21:19 PM PDT 24 Aug 03 04:21:20 PM PDT 24 332820594 ps
T1059 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1809815293 Aug 03 04:22:31 PM PDT 24 Aug 03 04:22:33 PM PDT 24 56964956 ps
T100 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1883686291 Aug 03 04:21:26 PM PDT 24 Aug 03 04:21:30 PM PDT 24 653953693 ps
T1060 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1613218787 Aug 03 04:23:23 PM PDT 24 Aug 03 04:23:24 PM PDT 24 139911247 ps
T1061 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3081479682 Aug 03 04:21:50 PM PDT 24 Aug 03 04:22:14 PM PDT 24 13378514958 ps
T1062 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3425323517 Aug 03 04:21:32 PM PDT 24 Aug 03 04:21:33 PM PDT 24 46095630 ps
T1063 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1364974484 Aug 03 04:22:46 PM PDT 24 Aug 03 04:22:50 PM PDT 24 148132867 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4200199348 Aug 03 04:20:44 PM PDT 24 Aug 03 04:21:17 PM PDT 24 616045102 ps
T1065 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3631539251 Aug 03 04:21:52 PM PDT 24 Aug 03 04:21:53 PM PDT 24 24775991 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3466996639 Aug 03 04:21:53 PM PDT 24 Aug 03 04:21:55 PM PDT 24 206686464 ps
T1067 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3711598843 Aug 03 04:22:28 PM PDT 24 Aug 03 04:22:28 PM PDT 24 37194388 ps
T164 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.460133289 Aug 03 04:21:57 PM PDT 24 Aug 03 04:22:11 PM PDT 24 562042016 ps
T1068 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1913577725 Aug 03 04:21:59 PM PDT 24 Aug 03 04:22:01 PM PDT 24 103158270 ps
T1069 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.642278062 Aug 03 04:22:08 PM PDT 24 Aug 03 04:22:11 PM PDT 24 97793210 ps
T1070 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1829347562 Aug 03 04:22:02 PM PDT 24 Aug 03 04:22:02 PM PDT 24 20622942 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4212400837 Aug 03 04:23:17 PM PDT 24 Aug 03 04:23:19 PM PDT 24 192995681 ps
T1072 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4083889374 Aug 03 04:22:20 PM PDT 24 Aug 03 04:22:23 PM PDT 24 193295393 ps
T161 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.722466406 Aug 03 04:21:39 PM PDT 24 Aug 03 04:21:43 PM PDT 24 118456813 ps
T1073 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2243512834 Aug 03 04:22:01 PM PDT 24 Aug 03 04:22:05 PM PDT 24 3015855657 ps
T1074 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.554405992 Aug 03 04:22:36 PM PDT 24 Aug 03 04:22:37 PM PDT 24 16726201 ps
T1075 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2082094299 Aug 03 04:21:43 PM PDT 24 Aug 03 04:21:43 PM PDT 24 98590784 ps
T1076 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1729185952 Aug 03 04:23:28 PM PDT 24 Aug 03 04:23:31 PM PDT 24 226346733 ps
T167 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2417828192 Aug 03 04:23:44 PM PDT 24 Aug 03 04:24:00 PM PDT 24 838653532 ps
T1077 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2577904724 Aug 03 04:22:02 PM PDT 24 Aug 03 04:22:03 PM PDT 24 11247929 ps
T1078 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2645872930 Aug 03 04:23:30 PM PDT 24 Aug 03 04:23:31 PM PDT 24 222925814 ps
T1079 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1348589175 Aug 03 04:24:17 PM PDT 24 Aug 03 04:24:19 PM PDT 24 336706746 ps
T1080 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3958027819 Aug 03 04:24:38 PM PDT 24 Aug 03 04:24:39 PM PDT 24 25013127 ps
T1081 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3421150384 Aug 03 04:22:20 PM PDT 24 Aug 03 04:22:28 PM PDT 24 397783647 ps
T1082 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4096677565 Aug 03 04:24:19 PM PDT 24 Aug 03 04:24:21 PM PDT 24 38701994 ps
T1083 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1032602689 Aug 03 04:23:38 PM PDT 24 Aug 03 04:23:47 PM PDT 24 251360250 ps
T1084 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.703904667 Aug 03 04:22:02 PM PDT 24 Aug 03 04:22:03 PM PDT 24 40521043 ps
T1085 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.345362012 Aug 03 04:22:35 PM PDT 24 Aug 03 04:22:36 PM PDT 24 16538544 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2549235508 Aug 03 04:21:35 PM PDT 24 Aug 03 04:21:36 PM PDT 24 31408892 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4008118345 Aug 03 04:21:54 PM PDT 24 Aug 03 04:22:19 PM PDT 24 1259410339 ps
T1088 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3911404313 Aug 03 04:22:23 PM PDT 24 Aug 03 04:22:26 PM PDT 24 102738920 ps
T1089 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2412173022 Aug 03 04:21:55 PM PDT 24 Aug 03 04:22:02 PM PDT 24 110127556 ps
T1090 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1006682653 Aug 03 04:21:31 PM PDT 24 Aug 03 04:21:33 PM PDT 24 83724344 ps
T1091 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3095186237 Aug 03 04:22:18 PM PDT 24 Aug 03 04:22:19 PM PDT 24 214729142 ps
T1092 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2844385475 Aug 03 04:22:02 PM PDT 24 Aug 03 04:22:03 PM PDT 24 93180389 ps
T1093 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.925827450 Aug 03 04:22:35 PM PDT 24 Aug 03 04:22:38 PM PDT 24 75853576 ps
T1094 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1433412295 Aug 03 04:23:02 PM PDT 24 Aug 03 04:23:04 PM PDT 24 79770356 ps
T1095 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3465734869 Aug 03 04:24:19 PM PDT 24 Aug 03 04:24:20 PM PDT 24 17456018 ps
T1096 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1145327536 Aug 03 04:22:55 PM PDT 24 Aug 03 04:22:58 PM PDT 24 1298868702 ps
T1097 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1975176783 Aug 03 04:22:51 PM PDT 24 Aug 03 04:22:54 PM PDT 24 280571228 ps
T1098 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4071442029 Aug 03 04:21:51 PM PDT 24 Aug 03 04:21:52 PM PDT 24 94473304 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1698492168 Aug 03 04:21:41 PM PDT 24 Aug 03 04:21:44 PM PDT 24 339306031 ps
T1100 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1246475603 Aug 03 04:21:58 PM PDT 24 Aug 03 04:21:59 PM PDT 24 17253332 ps
T1101 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4134693251 Aug 03 04:22:31 PM PDT 24 Aug 03 04:22:55 PM PDT 24 2577997681 ps
T1102 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.300851083 Aug 03 04:22:20 PM PDT 24 Aug 03 04:22:22 PM PDT 24 145224543 ps
T1103 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2440726960 Aug 03 04:23:57 PM PDT 24 Aug 03 04:24:00 PM PDT 24 469593735 ps
T1104 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2455207049 Aug 03 04:23:19 PM PDT 24 Aug 03 04:23:20 PM PDT 24 51250040 ps
T1105 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1314145077 Aug 03 04:22:04 PM PDT 24 Aug 03 04:22:04 PM PDT 24 10931509 ps
T1106 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2844680984 Aug 03 04:21:01 PM PDT 24 Aug 03 04:21:02 PM PDT 24 36116972 ps
T1107 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3550167711 Aug 03 04:23:45 PM PDT 24 Aug 03 04:23:46 PM PDT 24 14454263 ps
T1108 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2831993251 Aug 03 04:21:38 PM PDT 24 Aug 03 04:21:40 PM PDT 24 147335976 ps
T1109 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1516067745 Aug 03 04:23:04 PM PDT 24 Aug 03 04:23:04 PM PDT 24 12963677 ps
T1110 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4231873560 Aug 03 04:23:44 PM PDT 24 Aug 03 04:23:46 PM PDT 24 67238833 ps
T1111 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.403245387 Aug 03 04:22:25 PM PDT 24 Aug 03 04:22:28 PM PDT 24 45292478 ps
T1112 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2951072498 Aug 03 04:22:01 PM PDT 24 Aug 03 04:22:02 PM PDT 24 30121231 ps
T1113 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1141755628 Aug 03 04:22:22 PM PDT 24 Aug 03 04:22:24 PM PDT 24 2027167890 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.858684935 Aug 03 04:21:43 PM PDT 24 Aug 03 04:21:44 PM PDT 24 24111539 ps
T1115 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4091888286 Aug 03 04:23:46 PM PDT 24 Aug 03 04:23:47 PM PDT 24 25759905 ps
T1116 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2396686588 Aug 03 04:22:28 PM PDT 24 Aug 03 04:22:29 PM PDT 24 32228627 ps
T1117 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3318081187 Aug 03 04:22:17 PM PDT 24 Aug 03 04:22:24 PM PDT 24 534892797 ps
T1118 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4197983903 Aug 03 04:21:07 PM PDT 24 Aug 03 04:21:12 PM PDT 24 319267769 ps
T1119 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2515201386 Aug 03 04:22:25 PM PDT 24 Aug 03 04:22:38 PM PDT 24 651522189 ps
T1120 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2660381876 Aug 03 04:21:53 PM PDT 24 Aug 03 04:21:53 PM PDT 24 17315492 ps
T1121 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.764804647 Aug 03 04:21:47 PM PDT 24 Aug 03 04:21:50 PM PDT 24 147473399 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2068165605 Aug 03 04:21:50 PM PDT 24 Aug 03 04:21:52 PM PDT 24 140247303 ps
T1123 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3663108055 Aug 03 04:24:19 PM PDT 24 Aug 03 04:24:21 PM PDT 24 172924607 ps
T1124 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.927455762 Aug 03 04:23:38 PM PDT 24 Aug 03 04:23:39 PM PDT 24 89652017 ps
T1125 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3140621461 Aug 03 04:21:47 PM PDT 24 Aug 03 04:21:48 PM PDT 24 21014577 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3442446858 Aug 03 04:20:56 PM PDT 24 Aug 03 04:20:58 PM PDT 24 400406546 ps
T1127 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.738286066 Aug 03 04:22:14 PM PDT 24 Aug 03 04:22:14 PM PDT 24 23628741 ps
T165 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.794898587 Aug 03 04:20:41 PM PDT 24 Aug 03 04:20:58 PM PDT 24 375362603 ps
T1128 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3600753996 Aug 03 04:21:40 PM PDT 24 Aug 03 04:21:43 PM PDT 24 127500966 ps
T1129 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3605243757 Aug 03 04:22:33 PM PDT 24 Aug 03 04:22:34 PM PDT 24 15039116 ps
T1130 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.185373940 Aug 03 04:20:48 PM PDT 24 Aug 03 04:20:50 PM PDT 24 34961782 ps
T1131 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.154328719 Aug 03 04:21:39 PM PDT 24 Aug 03 04:21:40 PM PDT 24 46863863 ps

Test location /workspace/coverage/default/26.spi_device_stress_all.1963388599
Short name T4
Test name
Test status
Simulation time 19125687647 ps
CPU time 51.83 seconds
Started Aug 03 05:02:58 PM PDT 24
Finished Aug 03 05:03:50 PM PDT 24
Peak memory 240604 kb
Host smart-6d3e7514-f8f1-4e7c-a369-fd4cda0bfdac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963388599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1963388599
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3973159882
Short name T39
Test name
Test status
Simulation time 123217640843 ps
CPU time 249.19 seconds
Started Aug 03 05:03:41 PM PDT 24
Finished Aug 03 05:07:51 PM PDT 24
Peak memory 249516 kb
Host smart-5276632d-3251-4b34-8612-8d70c833d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973159882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3973159882
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3775462555
Short name T44
Test name
Test status
Simulation time 13363506732 ps
CPU time 200.79 seconds
Started Aug 03 05:03:38 PM PDT 24
Finished Aug 03 05:06:59 PM PDT 24
Peak memory 273836 kb
Host smart-9e0b46cd-bf1d-4011-b3ea-5c7664866840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775462555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3775462555
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1231365834
Short name T93
Test name
Test status
Simulation time 19577711343 ps
CPU time 21.62 seconds
Started Aug 03 04:21:52 PM PDT 24
Finished Aug 03 04:22:14 PM PDT 24
Peak memory 215240 kb
Host smart-ab622222-c09c-413c-8e02-e7b59900850b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231365834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1231365834
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.991298559
Short name T16
Test name
Test status
Simulation time 48774943889 ps
CPU time 107.34 seconds
Started Aug 03 05:03:41 PM PDT 24
Finished Aug 03 05:05:29 PM PDT 24
Peak memory 257876 kb
Host smart-89fe7194-5628-4eef-ba20-0f05a47812af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991298559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.991298559
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.841681015
Short name T169
Test name
Test status
Simulation time 884974555364 ps
CPU time 951.8 seconds
Started Aug 03 05:03:27 PM PDT 24
Finished Aug 03 05:19:19 PM PDT 24
Peak memory 298544 kb
Host smart-702f9534-611b-4382-9d73-ce921f160c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841681015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.841681015
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1111932229
Short name T26
Test name
Test status
Simulation time 58394813479 ps
CPU time 561.16 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:11:36 PM PDT 24
Peak memory 270172 kb
Host smart-20e7fa2b-26ae-4c31-883f-9d3e4a1c2b13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111932229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1111932229
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.301892366
Short name T64
Test name
Test status
Simulation time 22962222 ps
CPU time 0.74 seconds
Started Aug 03 05:01:43 PM PDT 24
Finished Aug 03 05:01:44 PM PDT 24
Peak memory 216420 kb
Host smart-cdac485b-7bb5-449a-a6f7-4dbeaa770e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301892366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.301892366
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4084216469
Short name T27
Test name
Test status
Simulation time 254176815515 ps
CPU time 603.61 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:14:00 PM PDT 24
Peak memory 266020 kb
Host smart-4dd392da-a897-45ff-afe1-4dcefd1ed9ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084216469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4084216469
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2532455125
Short name T159
Test name
Test status
Simulation time 5992132129 ps
CPU time 65.96 seconds
Started Aug 03 05:01:54 PM PDT 24
Finished Aug 03 05:03:00 PM PDT 24
Peak memory 251656 kb
Host smart-64697721-bc05-43b6-b1a3-eb1313bf46e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532455125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2532455125
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3559181684
Short name T18
Test name
Test status
Simulation time 88834234 ps
CPU time 1.02 seconds
Started Aug 03 05:01:48 PM PDT 24
Finished Aug 03 05:01:49 PM PDT 24
Peak memory 236888 kb
Host smart-d3c17e64-2f38-48c7-bef8-b3de88da2b58
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559181684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3559181684
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1100728951
Short name T151
Test name
Test status
Simulation time 12031660964 ps
CPU time 152.33 seconds
Started Aug 03 05:01:56 PM PDT 24
Finished Aug 03 05:04:28 PM PDT 24
Peak memory 270600 kb
Host smart-a5249aa4-d61d-4660-baf3-35dc1fdc08d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100728951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1100728951
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1032328059
Short name T94
Test name
Test status
Simulation time 49298496 ps
CPU time 3.1 seconds
Started Aug 03 04:21:53 PM PDT 24
Finished Aug 03 04:21:56 PM PDT 24
Peak memory 215412 kb
Host smart-06c45394-33ac-4ad3-91cc-9232da405d6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032328059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1032328059
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3977319288
Short name T142
Test name
Test status
Simulation time 1678175663 ps
CPU time 12.31 seconds
Started Aug 03 05:02:27 PM PDT 24
Finished Aug 03 05:02:40 PM PDT 24
Peak memory 241336 kb
Host smart-993973e7-195f-4e06-985e-6a3d98e19b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977319288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3977319288
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4058295622
Short name T130
Test name
Test status
Simulation time 65594292927 ps
CPU time 374.06 seconds
Started Aug 03 05:03:42 PM PDT 24
Finished Aug 03 05:09:56 PM PDT 24
Peak memory 267196 kb
Host smart-b3a320d5-b1a1-4e01-9c7b-5be5329afad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058295622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4058295622
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.957295977
Short name T42
Test name
Test status
Simulation time 98003886289 ps
CPU time 226.41 seconds
Started Aug 03 05:02:09 PM PDT 24
Finished Aug 03 05:05:56 PM PDT 24
Peak memory 265836 kb
Host smart-dd57d850-ba5d-4900-80b2-9108398d12a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957295977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.957295977
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1939535824
Short name T79
Test name
Test status
Simulation time 48674830 ps
CPU time 1.51 seconds
Started Aug 03 04:20:53 PM PDT 24
Finished Aug 03 04:20:54 PM PDT 24
Peak memory 216984 kb
Host smart-2d8799cf-b974-4bb7-b086-afd3799cb08b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939535824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1939535824
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3153590219
Short name T43
Test name
Test status
Simulation time 5728091508 ps
CPU time 63.41 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:03:16 PM PDT 24
Peak memory 249648 kb
Host smart-7cbd4426-41a7-4fb7-988c-176c908adb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153590219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3153590219
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3139125601
Short name T40
Test name
Test status
Simulation time 18225750873 ps
CPU time 126.81 seconds
Started Aug 03 05:02:47 PM PDT 24
Finished Aug 03 05:04:54 PM PDT 24
Peak memory 257272 kb
Host smart-9bbf8c93-8ca6-4f3e-a625-6fdac425f033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139125601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3139125601
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3434398182
Short name T187
Test name
Test status
Simulation time 16295087251 ps
CPU time 136.91 seconds
Started Aug 03 05:02:18 PM PDT 24
Finished Aug 03 05:04:35 PM PDT 24
Peak memory 265088 kb
Host smart-06a65b1b-d19e-4cef-9c40-f5004ea780c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434398182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3434398182
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2431100371
Short name T180
Test name
Test status
Simulation time 40761215798 ps
CPU time 268.67 seconds
Started Aug 03 05:02:01 PM PDT 24
Finished Aug 03 05:06:30 PM PDT 24
Peak memory 255992 kb
Host smart-da0bd7f9-1d1e-4c3b-9c62-795d0a2c17ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431100371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2431100371
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.21779389
Short name T199
Test name
Test status
Simulation time 59893085184 ps
CPU time 142.4 seconds
Started Aug 03 05:01:33 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 252208 kb
Host smart-b967b8ed-4d4d-4edd-a7bf-de2cc51d74af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21779389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.21779389
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.670690829
Short name T5
Test name
Test status
Simulation time 25478684708 ps
CPU time 121.45 seconds
Started Aug 03 05:01:52 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 247924 kb
Host smart-c734fafb-3c87-48ac-845b-d9685656bd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670690829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.670690829
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1066014102
Short name T52
Test name
Test status
Simulation time 4095215697 ps
CPU time 85.42 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:03:38 PM PDT 24
Peak memory 265988 kb
Host smart-5406c7cd-bd87-4a96-b660-f003daa53c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066014102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1066014102
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.909223980
Short name T99
Test name
Test status
Simulation time 268903810 ps
CPU time 4.79 seconds
Started Aug 03 04:21:55 PM PDT 24
Finished Aug 03 04:22:00 PM PDT 24
Peak memory 215044 kb
Host smart-40ecf14f-3519-4c2b-a8a7-fc8e4737c2df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909223980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.909223980
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1530806431
Short name T332
Test name
Test status
Simulation time 20240819 ps
CPU time 0.73 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:16 PM PDT 24
Peak memory 205236 kb
Host smart-7529c685-ed06-4390-8421-0f8fafa497bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530806431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1530806431
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3976264076
Short name T8
Test name
Test status
Simulation time 28019373127 ps
CPU time 70.28 seconds
Started Aug 03 05:02:34 PM PDT 24
Finished Aug 03 05:03:44 PM PDT 24
Peak memory 256840 kb
Host smart-cf10fffe-e04f-4dc8-b0f1-7807e48e5938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976264076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3976264076
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3189888585
Short name T213
Test name
Test status
Simulation time 5377441362 ps
CPU time 120.41 seconds
Started Aug 03 05:02:48 PM PDT 24
Finished Aug 03 05:04:48 PM PDT 24
Peak memory 257596 kb
Host smart-f7488dd4-5662-4728-b0dc-3edb22fa314d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189888585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3189888585
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1219110031
Short name T21
Test name
Test status
Simulation time 13203882609 ps
CPU time 116.52 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:04:52 PM PDT 24
Peak memory 262324 kb
Host smart-8e8471c5-7526-4ed3-a045-808e1a1a68d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219110031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1219110031
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.794898587
Short name T165
Test name
Test status
Simulation time 375362603 ps
CPU time 17.29 seconds
Started Aug 03 04:20:41 PM PDT 24
Finished Aug 03 04:20:58 PM PDT 24
Peak memory 214892 kb
Host smart-bc0e8931-78bf-4b72-b63c-884b528a9119
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794898587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.794898587
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.381201460
Short name T408
Test name
Test status
Simulation time 3891671130 ps
CPU time 66.53 seconds
Started Aug 03 05:01:33 PM PDT 24
Finished Aug 03 05:02:40 PM PDT 24
Peak memory 255076 kb
Host smart-beb96b36-b3b2-4f6b-a0a7-5ec35cc196a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381201460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
381201460
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.751391865
Short name T939
Test name
Test status
Simulation time 66153383324 ps
CPU time 674.6 seconds
Started Aug 03 05:02:32 PM PDT 24
Finished Aug 03 05:13:46 PM PDT 24
Peak memory 283384 kb
Host smart-19ed8261-6c38-4d1c-9518-7c99a83d233d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751391865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.751391865
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2238215385
Short name T181
Test name
Test status
Simulation time 127093645667 ps
CPU time 387.01 seconds
Started Aug 03 05:02:41 PM PDT 24
Finished Aug 03 05:09:08 PM PDT 24
Peak memory 253304 kb
Host smart-23e95a29-a02b-456e-b19e-c19fdc00f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238215385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2238215385
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2417828192
Short name T167
Test name
Test status
Simulation time 838653532 ps
CPU time 15.58 seconds
Started Aug 03 04:23:44 PM PDT 24
Finished Aug 03 04:24:00 PM PDT 24
Peak memory 215004 kb
Host smart-5a10074f-07ab-43d7-a52c-02f35e4ef802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417828192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2417828192
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3555135267
Short name T457
Test name
Test status
Simulation time 4981953536 ps
CPU time 17.1 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:02:29 PM PDT 24
Peak memory 241096 kb
Host smart-b670c7c8-1f28-4adc-aef2-d93eff798be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555135267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3555135267
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1783544798
Short name T20
Test name
Test status
Simulation time 11260967475 ps
CPU time 140.76 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:04:31 PM PDT 24
Peak memory 257860 kb
Host smart-c9d46ecb-07ec-4d64-b451-eda5ffac3fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783544798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1783544798
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.497711906
Short name T951
Test name
Test status
Simulation time 2340235754 ps
CPU time 31.08 seconds
Started Aug 03 05:03:42 PM PDT 24
Finished Aug 03 05:04:13 PM PDT 24
Peak memory 241388 kb
Host smart-08a82018-f9f4-4005-b48e-9fa673098ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497711906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.497711906
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1800136603
Short name T293
Test name
Test status
Simulation time 14282111861 ps
CPU time 68.06 seconds
Started Aug 03 05:04:01 PM PDT 24
Finished Aug 03 05:05:09 PM PDT 24
Peak memory 257104 kb
Host smart-27315909-1552-4a68-a93f-91a76981f0f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800136603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1800136603
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4264645325
Short name T88
Test name
Test status
Simulation time 116066376 ps
CPU time 2.61 seconds
Started Aug 03 05:02:08 PM PDT 24
Finished Aug 03 05:02:10 PM PDT 24
Peak memory 233080 kb
Host smart-8ec7e802-a4ae-43e8-b284-8911f45abe00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264645325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4264645325
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4224663157
Short name T275
Test name
Test status
Simulation time 1751756789 ps
CPU time 5.88 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:07 PM PDT 24
Peak memory 233080 kb
Host smart-59ed6ce4-3420-45c2-b029-a7ccd81825c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224663157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4224663157
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3123669982
Short name T341
Test name
Test status
Simulation time 1191141395 ps
CPU time 3.29 seconds
Started Aug 03 05:01:30 PM PDT 24
Finished Aug 03 05:01:34 PM PDT 24
Peak memory 216556 kb
Host smart-cdcee7f7-9f87-4fa9-9db1-7a04830cbac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123669982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3123669982
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4097274701
Short name T215
Test name
Test status
Simulation time 236425246377 ps
CPU time 187.29 seconds
Started Aug 03 05:01:48 PM PDT 24
Finished Aug 03 05:04:55 PM PDT 24
Peak memory 249592 kb
Host smart-3925f1d3-f59f-41e5-89d3-14094e808616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097274701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4097274701
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2117495202
Short name T279
Test name
Test status
Simulation time 21351637863 ps
CPU time 242.69 seconds
Started Aug 03 05:02:08 PM PDT 24
Finished Aug 03 05:06:11 PM PDT 24
Peak memory 266048 kb
Host smart-02d693e7-bdad-409f-bd08-e8fad415810f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117495202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2117495202
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.909952727
Short name T328
Test name
Test status
Simulation time 2120176234 ps
CPU time 4.03 seconds
Started Aug 03 05:02:10 PM PDT 24
Finished Aug 03 05:02:14 PM PDT 24
Peak memory 224752 kb
Host smart-8ab7bc26-e7d2-4472-ac07-98576568ccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909952727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.909952727
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_upload.163416734
Short name T175
Test name
Test status
Simulation time 2395580219 ps
CPU time 6.34 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:22 PM PDT 24
Peak memory 233116 kb
Host smart-96a75d20-62e1-445c-957c-48de74e8bf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163416734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.163416734
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.818607170
Short name T283
Test name
Test status
Simulation time 5408369655 ps
CPU time 40.04 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:55 PM PDT 24
Peak memory 249632 kb
Host smart-f16a968b-ac53-492e-b555-a7940c076df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818607170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.818607170
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3555491354
Short name T961
Test name
Test status
Simulation time 53777857011 ps
CPU time 223.04 seconds
Started Aug 03 05:02:17 PM PDT 24
Finished Aug 03 05:06:00 PM PDT 24
Peak memory 250924 kb
Host smart-cfa58cba-e26f-48ad-ae3e-20485a3bf733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555491354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3555491354
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1926886784
Short name T299
Test name
Test status
Simulation time 15872880320 ps
CPU time 89.94 seconds
Started Aug 03 05:02:47 PM PDT 24
Finished Aug 03 05:04:18 PM PDT 24
Peak memory 253588 kb
Host smart-4b3bc8e8-b7db-4767-a2d6-22e6bc33b744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926886784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1926886784
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2678617241
Short name T304
Test name
Test status
Simulation time 2104769610 ps
CPU time 11.25 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:03:11 PM PDT 24
Peak memory 239300 kb
Host smart-9c744342-9dd3-45bc-920c-97d91a62f62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678617241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2678617241
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3539332265
Short name T29
Test name
Test status
Simulation time 3100942881 ps
CPU time 51.34 seconds
Started Aug 03 05:03:17 PM PDT 24
Finished Aug 03 05:04:08 PM PDT 24
Peak memory 235468 kb
Host smart-d38a0aab-7dd9-43bf-b350-e4f83fdf22b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539332265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3539332265
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.111440864
Short name T105
Test name
Test status
Simulation time 1267620379 ps
CPU time 5.37 seconds
Started Aug 03 04:21:13 PM PDT 24
Finished Aug 03 04:21:18 PM PDT 24
Peak memory 215020 kb
Host smart-b11b1089-90ae-42a4-982a-ada3c1d5cd76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111440864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.111440864
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2686954312
Short name T146
Test name
Test status
Simulation time 1455631586 ps
CPU time 9.07 seconds
Started Aug 03 04:21:57 PM PDT 24
Finished Aug 03 04:22:06 PM PDT 24
Peak memory 214920 kb
Host smart-345e6ee7-5ebe-46fc-8363-f4c398041e5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686954312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2686954312
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4200199348
Short name T1064
Test name
Test status
Simulation time 616045102 ps
CPU time 33.41 seconds
Started Aug 03 04:20:44 PM PDT 24
Finished Aug 03 04:21:17 PM PDT 24
Peak memory 206748 kb
Host smart-1eef5ca9-5eec-43b0-958f-69b18c763225
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200199348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4200199348
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3312421625
Short name T1056
Test name
Test status
Simulation time 99373788 ps
CPU time 3.04 seconds
Started Aug 03 04:20:51 PM PDT 24
Finished Aug 03 04:20:54 PM PDT 24
Peak memory 216712 kb
Host smart-fef2919e-45b5-48f9-9ed3-161cd28e62d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312421625 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3312421625
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.185373940
Short name T1130
Test name
Test status
Simulation time 34961782 ps
CPU time 1.27 seconds
Started Aug 03 04:20:48 PM PDT 24
Finished Aug 03 04:20:50 PM PDT 24
Peak memory 214884 kb
Host smart-df80288b-a6e5-4eb4-b7c0-fe74779f72ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185373940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.185373940
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1136756794
Short name T1044
Test name
Test status
Simulation time 12700981 ps
CPU time 0.76 seconds
Started Aug 03 04:20:39 PM PDT 24
Finished Aug 03 04:20:40 PM PDT 24
Peak memory 203408 kb
Host smart-4b7be8f2-74ab-45dd-9aa8-d94dc12b4a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136756794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
136756794
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.208382602
Short name T122
Test name
Test status
Simulation time 19386002 ps
CPU time 1.43 seconds
Started Aug 03 04:21:49 PM PDT 24
Finished Aug 03 04:21:51 PM PDT 24
Peak memory 214808 kb
Host smart-b8deb094-51b7-4f0b-8b22-e4da5953576a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208382602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.208382602
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3605243757
Short name T1129
Test name
Test status
Simulation time 15039116 ps
CPU time 0.71 seconds
Started Aug 03 04:22:33 PM PDT 24
Finished Aug 03 04:22:34 PM PDT 24
Peak memory 203348 kb
Host smart-3c007ebb-393e-46fe-ab4e-17a2d9c22a8d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605243757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3605243757
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.668176455
Short name T1030
Test name
Test status
Simulation time 109462321 ps
CPU time 3.16 seconds
Started Aug 03 04:20:45 PM PDT 24
Finished Aug 03 04:20:49 PM PDT 24
Peak memory 214976 kb
Host smart-0f65e650-d3a9-44ea-859b-52e817271216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668176455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.668176455
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4197983903
Short name T1118
Test name
Test status
Simulation time 319267769 ps
CPU time 5.11 seconds
Started Aug 03 04:21:07 PM PDT 24
Finished Aug 03 04:21:12 PM PDT 24
Peak memory 215024 kb
Host smart-12c9ad8f-1b3c-490c-a2c3-bf9586b11e48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197983903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
197983903
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2216921254
Short name T113
Test name
Test status
Simulation time 2523925683 ps
CPU time 15.27 seconds
Started Aug 03 04:20:59 PM PDT 24
Finished Aug 03 04:21:15 PM PDT 24
Peak memory 214980 kb
Host smart-ef60b2f8-cd4a-496f-a6d7-aea7c35bba83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216921254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2216921254
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4134693251
Short name T1101
Test name
Test status
Simulation time 2577997681 ps
CPU time 23.84 seconds
Started Aug 03 04:22:31 PM PDT 24
Finished Aug 03 04:22:55 PM PDT 24
Peak memory 206768 kb
Host smart-40829fbb-88e3-4427-bf24-34fc73d0e1b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134693251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.4134693251
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2844680984
Short name T1106
Test name
Test status
Simulation time 36116972 ps
CPU time 1.3 seconds
Started Aug 03 04:21:01 PM PDT 24
Finished Aug 03 04:21:02 PM PDT 24
Peak memory 206720 kb
Host smart-aa14ab07-a9da-4ca1-9fbd-ea2b41fc5bfd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844680984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2844680984
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4088986423
Short name T91
Test name
Test status
Simulation time 97859936 ps
CPU time 3.46 seconds
Started Aug 03 04:21:31 PM PDT 24
Finished Aug 03 04:21:35 PM PDT 24
Peak memory 216956 kb
Host smart-c044c4b4-3355-40cc-a589-86eac74a3677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088986423 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4088986423
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3442446858
Short name T1126
Test name
Test status
Simulation time 400406546 ps
CPU time 1.45 seconds
Started Aug 03 04:20:56 PM PDT 24
Finished Aug 03 04:20:58 PM PDT 24
Peak memory 206644 kb
Host smart-bc6375fc-ff3e-47c4-9cce-40203e0d11be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442446858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
442446858
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2549235508
Short name T1086
Test name
Test status
Simulation time 31408892 ps
CPU time 0.78 seconds
Started Aug 03 04:21:35 PM PDT 24
Finished Aug 03 04:21:36 PM PDT 24
Peak memory 203740 kb
Host smart-44f59b7b-7228-4480-b8b4-a029f5d486aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549235508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
549235508
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2291282041
Short name T117
Test name
Test status
Simulation time 177780190 ps
CPU time 1.78 seconds
Started Aug 03 04:20:52 PM PDT 24
Finished Aug 03 04:20:54 PM PDT 24
Peak memory 214940 kb
Host smart-c8fc4c4d-2b50-49d2-8f66-6ff122679e37
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291282041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2291282041
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1246475603
Short name T1100
Test name
Test status
Simulation time 17253332 ps
CPU time 0.64 seconds
Started Aug 03 04:21:58 PM PDT 24
Finished Aug 03 04:21:59 PM PDT 24
Peak memory 203772 kb
Host smart-d31af1ba-a86d-409b-8a0c-0a781dd6e740
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246475603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1246475603
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3496517831
Short name T1021
Test name
Test status
Simulation time 26724233 ps
CPU time 1.78 seconds
Started Aug 03 04:20:54 PM PDT 24
Finished Aug 03 04:20:56 PM PDT 24
Peak memory 214932 kb
Host smart-5fc5e800-bb93-4b30-84f2-c5eef3bcebdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496517831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3496517831
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.722466406
Short name T161
Test name
Test status
Simulation time 118456813 ps
CPU time 3.8 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:43 PM PDT 24
Peak memory 215236 kb
Host smart-694eaa92-6ac7-4a29-8ada-1b6ba065221b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722466406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.722466406
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3142687956
Short name T1025
Test name
Test status
Simulation time 112903528 ps
CPU time 6.97 seconds
Started Aug 03 04:20:47 PM PDT 24
Finished Aug 03 04:20:54 PM PDT 24
Peak memory 215032 kb
Host smart-a74931b1-d45a-4444-af12-a05c1679ce00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142687956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3142687956
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3838866113
Short name T95
Test name
Test status
Simulation time 189869638 ps
CPU time 1.52 seconds
Started Aug 03 04:23:58 PM PDT 24
Finished Aug 03 04:24:00 PM PDT 24
Peak memory 214384 kb
Host smart-25352afe-5d65-4170-86a8-1a2c4ff6d6fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838866113 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3838866113
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2515598844
Short name T111
Test name
Test status
Simulation time 315502855 ps
CPU time 2.1 seconds
Started Aug 03 04:22:07 PM PDT 24
Finished Aug 03 04:22:09 PM PDT 24
Peak memory 215032 kb
Host smart-1150229b-e86c-404b-8302-9b46ade4ab97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515598844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2515598844
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2660381876
Short name T1120
Test name
Test status
Simulation time 17315492 ps
CPU time 0.71 seconds
Started Aug 03 04:21:53 PM PDT 24
Finished Aug 03 04:21:53 PM PDT 24
Peak memory 203728 kb
Host smart-e340e164-6324-4b8b-9ff5-64f6df094dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660381876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2660381876
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1364974484
Short name T1063
Test name
Test status
Simulation time 148132867 ps
CPU time 3.28 seconds
Started Aug 03 04:22:46 PM PDT 24
Finished Aug 03 04:22:50 PM PDT 24
Peak memory 214988 kb
Host smart-d4ab2f76-f6e7-49cd-8bb1-8a6c19bba3cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364974484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1364974484
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.642278062
Short name T1069
Test name
Test status
Simulation time 97793210 ps
CPU time 3.32 seconds
Started Aug 03 04:22:08 PM PDT 24
Finished Aug 03 04:22:11 PM PDT 24
Peak memory 214988 kb
Host smart-72f48126-ba14-42f1-bfe5-c409c0a919f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642278062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.642278062
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.460133289
Short name T164
Test name
Test status
Simulation time 562042016 ps
CPU time 13.84 seconds
Started Aug 03 04:21:57 PM PDT 24
Finished Aug 03 04:22:11 PM PDT 24
Peak memory 215140 kb
Host smart-95fe0a5a-10de-4342-ab22-c629ea2c5c51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460133289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.460133289
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.851104713
Short name T109
Test name
Test status
Simulation time 397259591 ps
CPU time 2.8 seconds
Started Aug 03 04:22:06 PM PDT 24
Finished Aug 03 04:22:09 PM PDT 24
Peak memory 216516 kb
Host smart-5ddb054e-7ca7-4376-96f5-27562602e47c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851104713 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.851104713
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1729008418
Short name T121
Test name
Test status
Simulation time 91679928 ps
CPU time 1.64 seconds
Started Aug 03 04:22:31 PM PDT 24
Finished Aug 03 04:22:33 PM PDT 24
Peak memory 206680 kb
Host smart-3ded9625-8973-43ee-87df-b8ec1aab251c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729008418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1729008418
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4103038683
Short name T1005
Test name
Test status
Simulation time 16073340 ps
CPU time 0.73 seconds
Started Aug 03 04:23:04 PM PDT 24
Finished Aug 03 04:23:05 PM PDT 24
Peak memory 203444 kb
Host smart-78292fa7-e82d-4c02-bd3a-d591455a287d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103038683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4103038683
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2179689890
Short name T139
Test name
Test status
Simulation time 23959666 ps
CPU time 1.61 seconds
Started Aug 03 04:21:52 PM PDT 24
Finished Aug 03 04:21:54 PM PDT 24
Peak memory 214880 kb
Host smart-542b05b9-8fa7-4eb9-b4c3-9d258bf313fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179689890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2179689890
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3911404313
Short name T1088
Test name
Test status
Simulation time 102738920 ps
CPU time 2.85 seconds
Started Aug 03 04:22:23 PM PDT 24
Finished Aug 03 04:22:26 PM PDT 24
Peak memory 215016 kb
Host smart-7d71a014-d58b-42ef-851c-e9dec466d5f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911404313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3911404313
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3421150384
Short name T1081
Test name
Test status
Simulation time 397783647 ps
CPU time 7.44 seconds
Started Aug 03 04:22:20 PM PDT 24
Finished Aug 03 04:22:28 PM PDT 24
Peak memory 214924 kb
Host smart-86ebe77c-81b4-4bf6-b8ff-b0ff13c04518
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421150384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3421150384
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.764804647
Short name T1121
Test name
Test status
Simulation time 147473399 ps
CPU time 2.55 seconds
Started Aug 03 04:21:47 PM PDT 24
Finished Aug 03 04:21:50 PM PDT 24
Peak memory 216264 kb
Host smart-d9af725e-4932-44b2-9476-748b6961b28f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764804647 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.764804647
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1706142670
Short name T1039
Test name
Test status
Simulation time 395761391 ps
CPU time 2.39 seconds
Started Aug 03 04:22:28 PM PDT 24
Finished Aug 03 04:22:30 PM PDT 24
Peak memory 214976 kb
Host smart-0d518a5b-9afd-4b77-919f-a3227fe6ed5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706142670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1706142670
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3759987834
Short name T1041
Test name
Test status
Simulation time 17603554 ps
CPU time 0.81 seconds
Started Aug 03 04:21:55 PM PDT 24
Finished Aug 03 04:21:56 PM PDT 24
Peak memory 203448 kb
Host smart-f230cb45-b1b8-4d1c-8528-2ca572807fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759987834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3759987834
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1313799490
Short name T1028
Test name
Test status
Simulation time 454263151 ps
CPU time 1.8 seconds
Started Aug 03 04:22:24 PM PDT 24
Finished Aug 03 04:22:26 PM PDT 24
Peak memory 214936 kb
Host smart-55c5d516-3176-4d92-9f4c-3aeea8339a6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313799490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1313799490
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1145327536
Short name T1096
Test name
Test status
Simulation time 1298868702 ps
CPU time 3.28 seconds
Started Aug 03 04:22:55 PM PDT 24
Finished Aug 03 04:22:58 PM PDT 24
Peak memory 215092 kb
Host smart-64637063-cfe6-42ec-9b80-d40c74798321
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145327536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1145327536
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2979247127
Short name T63
Test name
Test status
Simulation time 1118827856 ps
CPU time 6.96 seconds
Started Aug 03 04:22:10 PM PDT 24
Finished Aug 03 04:22:17 PM PDT 24
Peak memory 214964 kb
Host smart-e379ad8d-ea96-4be3-bffd-e8db40d7a707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979247127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2979247127
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2926541961
Short name T104
Test name
Test status
Simulation time 650222687 ps
CPU time 3.67 seconds
Started Aug 03 04:23:00 PM PDT 24
Finished Aug 03 04:23:04 PM PDT 24
Peak memory 216596 kb
Host smart-293e3c41-5560-47f4-ae51-9a96cdc2422e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926541961 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2926541961
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3661333060
Short name T148
Test name
Test status
Simulation time 158703682 ps
CPU time 2 seconds
Started Aug 03 04:22:28 PM PDT 24
Finished Aug 03 04:22:30 PM PDT 24
Peak memory 214948 kb
Host smart-4be8f693-61d7-45a1-8baf-afc814f4fc8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661333060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3661333060
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3958027819
Short name T1080
Test name
Test status
Simulation time 25013127 ps
CPU time 0.72 seconds
Started Aug 03 04:24:38 PM PDT 24
Finished Aug 03 04:24:39 PM PDT 24
Peak memory 203720 kb
Host smart-1ad7cb9c-e993-40d3-91f6-f23f8422c369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958027819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3958027819
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.403245387
Short name T1111
Test name
Test status
Simulation time 45292478 ps
CPU time 2.73 seconds
Started Aug 03 04:22:25 PM PDT 24
Finished Aug 03 04:22:28 PM PDT 24
Peak memory 214948 kb
Host smart-f8024699-eca6-4f54-aaaa-1d2911ddad7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403245387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.403245387
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3318081187
Short name T1117
Test name
Test status
Simulation time 534892797 ps
CPU time 6.76 seconds
Started Aug 03 04:22:17 PM PDT 24
Finished Aug 03 04:22:24 PM PDT 24
Peak memory 215504 kb
Host smart-4e07f0bd-ebf1-4b47-af88-a10ed22a1776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318081187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3318081187
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.763545549
Short name T1036
Test name
Test status
Simulation time 41701946 ps
CPU time 2.39 seconds
Started Aug 03 04:22:48 PM PDT 24
Finished Aug 03 04:22:50 PM PDT 24
Peak memory 217080 kb
Host smart-cc23b3e9-98bc-459d-a505-b4dc96364589
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763545549 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.763545549
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1919938898
Short name T1023
Test name
Test status
Simulation time 266708186 ps
CPU time 1.27 seconds
Started Aug 03 04:21:55 PM PDT 24
Finished Aug 03 04:21:57 PM PDT 24
Peak memory 214988 kb
Host smart-1e4fca6e-3226-4ffe-bb75-18fa7c26790a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919938898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1919938898
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.502379355
Short name T1024
Test name
Test status
Simulation time 70944866 ps
CPU time 0.81 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:40 PM PDT 24
Peak memory 203332 kb
Host smart-ea7b1a4b-09a5-42f2-ab0a-58dc61ecbc13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502379355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.502379355
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1237793922
Short name T1016
Test name
Test status
Simulation time 31662526 ps
CPU time 1.92 seconds
Started Aug 03 04:21:38 PM PDT 24
Finished Aug 03 04:21:40 PM PDT 24
Peak memory 214876 kb
Host smart-1adbfc4a-f86d-41a8-927c-557866ea1c2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237793922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1237793922
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1433256230
Short name T96
Test name
Test status
Simulation time 132286116 ps
CPU time 2.09 seconds
Started Aug 03 04:21:48 PM PDT 24
Finished Aug 03 04:21:50 PM PDT 24
Peak memory 214996 kb
Host smart-cc31a9c5-e509-4472-9e1f-62872982451f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433256230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1433256230
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.92874909
Short name T163
Test name
Test status
Simulation time 1286433059 ps
CPU time 6.95 seconds
Started Aug 03 04:22:04 PM PDT 24
Finished Aug 03 04:22:12 PM PDT 24
Peak memory 215128 kb
Host smart-3b95a85d-683b-4b2e-be0f-c07db8c3f41a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92874909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_
tl_intg_err.92874909
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.479466010
Short name T1029
Test name
Test status
Simulation time 40428399 ps
CPU time 2.55 seconds
Started Aug 03 04:22:22 PM PDT 24
Finished Aug 03 04:22:24 PM PDT 24
Peak memory 215952 kb
Host smart-0d895fd4-3fa6-4466-854b-e34fd1629a14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479466010 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.479466010
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2448846061
Short name T114
Test name
Test status
Simulation time 21689015 ps
CPU time 1.34 seconds
Started Aug 03 04:23:54 PM PDT 24
Finished Aug 03 04:23:56 PM PDT 24
Peak memory 205888 kb
Host smart-8973a1e1-334e-4801-9a35-b41c771dcd1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448846061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2448846061
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.738286066
Short name T1127
Test name
Test status
Simulation time 23628741 ps
CPU time 0.78 seconds
Started Aug 03 04:22:14 PM PDT 24
Finished Aug 03 04:22:14 PM PDT 24
Peak memory 203432 kb
Host smart-e19fd557-5d43-4ff3-9f1c-3ed5906b8ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738286066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.738286066
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3469653
Short name T147
Test name
Test status
Simulation time 81210485 ps
CPU time 1.91 seconds
Started Aug 03 04:23:29 PM PDT 24
Finished Aug 03 04:23:31 PM PDT 24
Peak memory 206636 kb
Host smart-146b8f19-43b6-4f26-8f73-3738221a78e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi
_device_same_csr_outstanding.3469653
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4197374148
Short name T98
Test name
Test status
Simulation time 81583934 ps
CPU time 2.06 seconds
Started Aug 03 04:22:27 PM PDT 24
Finished Aug 03 04:22:29 PM PDT 24
Peak memory 215132 kb
Host smart-70334928-e28e-4409-873d-8a1719c61a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197374148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4197374148
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.432790843
Short name T1047
Test name
Test status
Simulation time 201300178 ps
CPU time 11.56 seconds
Started Aug 03 04:23:45 PM PDT 24
Finished Aug 03 04:23:56 PM PDT 24
Peak memory 215032 kb
Host smart-0c448a97-c201-4280-9640-abe1a1e1b638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432790843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.432790843
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1729185952
Short name T1076
Test name
Test status
Simulation time 226346733 ps
CPU time 2.64 seconds
Started Aug 03 04:23:28 PM PDT 24
Finished Aug 03 04:23:31 PM PDT 24
Peak memory 216916 kb
Host smart-7a5bcb10-da59-4719-9dea-da9f5f381d7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729185952 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1729185952
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2440726960
Short name T1103
Test name
Test status
Simulation time 469593735 ps
CPU time 2.63 seconds
Started Aug 03 04:23:57 PM PDT 24
Finished Aug 03 04:24:00 PM PDT 24
Peak memory 214276 kb
Host smart-748f7920-a075-4901-94bf-7803efe20f59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440726960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2440726960
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4071442029
Short name T1098
Test name
Test status
Simulation time 94473304 ps
CPU time 0.7 seconds
Started Aug 03 04:21:51 PM PDT 24
Finished Aug 03 04:21:52 PM PDT 24
Peak memory 203432 kb
Host smart-efc5475a-b004-4b10-bd50-f0de1e519f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071442029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4071442029
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1708350062
Short name T1008
Test name
Test status
Simulation time 226800627 ps
CPU time 1.79 seconds
Started Aug 03 04:23:45 PM PDT 24
Finished Aug 03 04:23:47 PM PDT 24
Peak memory 214964 kb
Host smart-1a3d2dde-2239-40f5-9831-0b37eb671301
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708350062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1708350062
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2424528060
Short name T102
Test name
Test status
Simulation time 683253106 ps
CPU time 4.2 seconds
Started Aug 03 04:21:56 PM PDT 24
Finished Aug 03 04:22:00 PM PDT 24
Peak memory 214984 kb
Host smart-adf19f71-770b-4e93-ab8f-97344a1b076c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424528060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2424528060
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2601059198
Short name T1049
Test name
Test status
Simulation time 196895076 ps
CPU time 11.42 seconds
Started Aug 03 04:22:48 PM PDT 24
Finished Aug 03 04:23:00 PM PDT 24
Peak memory 214892 kb
Host smart-ed15ba39-54ea-4a11-8bf9-83fe8ea629ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601059198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2601059198
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.629068232
Short name T1035
Test name
Test status
Simulation time 99848022 ps
CPU time 2.6 seconds
Started Aug 03 04:22:05 PM PDT 24
Finished Aug 03 04:22:08 PM PDT 24
Peak memory 216792 kb
Host smart-737e5323-6556-484f-97a6-6ce56ffaee8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629068232 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.629068232
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2319714538
Short name T1051
Test name
Test status
Simulation time 89936154 ps
CPU time 2.6 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:42 PM PDT 24
Peak memory 214904 kb
Host smart-41964247-dbdc-4c32-a497-4478b2cebdb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319714538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2319714538
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.885114249
Short name T1019
Test name
Test status
Simulation time 13603201 ps
CPU time 0.69 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:39 PM PDT 24
Peak memory 203680 kb
Host smart-5472c05b-906f-4b50-aff0-829471055bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885114249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.885114249
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1141755628
Short name T1113
Test name
Test status
Simulation time 2027167890 ps
CPU time 2.77 seconds
Started Aug 03 04:22:22 PM PDT 24
Finished Aug 03 04:22:24 PM PDT 24
Peak memory 214924 kb
Host smart-f3d01714-5f91-40b5-accc-e6c5129a3883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141755628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1141755628
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1433412295
Short name T1094
Test name
Test status
Simulation time 79770356 ps
CPU time 1.93 seconds
Started Aug 03 04:23:02 PM PDT 24
Finished Aug 03 04:23:04 PM PDT 24
Peak memory 215040 kb
Host smart-d8fd57fa-f31a-4a11-b39c-24ae0ef2d637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433412295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1433412295
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3446399368
Short name T166
Test name
Test status
Simulation time 200059904 ps
CPU time 11.99 seconds
Started Aug 03 04:22:01 PM PDT 24
Finished Aug 03 04:22:14 PM PDT 24
Peak memory 214864 kb
Host smart-f0737e9a-e965-4408-8035-ffd9c2c7e017
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446399368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3446399368
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4256993981
Short name T1045
Test name
Test status
Simulation time 161880538 ps
CPU time 2.97 seconds
Started Aug 03 04:21:55 PM PDT 24
Finished Aug 03 04:21:58 PM PDT 24
Peak memory 217136 kb
Host smart-45768450-260c-4e55-af12-adf9921b86d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256993981 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4256993981
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1462052333
Short name T1038
Test name
Test status
Simulation time 723670797 ps
CPU time 2.26 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:42 PM PDT 24
Peak memory 214776 kb
Host smart-15c56145-1d13-4a4c-8395-eecb15e2a785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462052333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1462052333
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1145490383
Short name T1034
Test name
Test status
Simulation time 22620910 ps
CPU time 0.76 seconds
Started Aug 03 04:22:06 PM PDT 24
Finished Aug 03 04:22:07 PM PDT 24
Peak memory 203784 kb
Host smart-c3ed13c0-dc8b-479a-abab-e3503207fb68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145490383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1145490383
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3600753996
Short name T1128
Test name
Test status
Simulation time 127500966 ps
CPU time 2.83 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:21:43 PM PDT 24
Peak memory 214900 kb
Host smart-9c2288bf-f83b-4efb-b373-d247e72e486d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600753996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3600753996
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1348589175
Short name T1079
Test name
Test status
Simulation time 336706746 ps
CPU time 1.74 seconds
Started Aug 03 04:24:17 PM PDT 24
Finished Aug 03 04:24:19 PM PDT 24
Peak memory 215156 kb
Host smart-82d5d5ee-1bbc-4857-b3e2-c1fb2fe06273
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348589175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1348589175
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2831993251
Short name T1108
Test name
Test status
Simulation time 147335976 ps
CPU time 1.98 seconds
Started Aug 03 04:21:38 PM PDT 24
Finished Aug 03 04:21:40 PM PDT 24
Peak memory 214968 kb
Host smart-406d2bbd-d33e-48f0-b100-e4adc4eb5b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831993251 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2831993251
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4231873560
Short name T1110
Test name
Test status
Simulation time 67238833 ps
CPU time 1.33 seconds
Started Aug 03 04:23:44 PM PDT 24
Finished Aug 03 04:23:46 PM PDT 24
Peak memory 206672 kb
Host smart-60ff35b0-6b41-42bc-bb6b-d3a032d55b2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231873560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4231873560
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1314145077
Short name T1105
Test name
Test status
Simulation time 10931509 ps
CPU time 0.72 seconds
Started Aug 03 04:22:04 PM PDT 24
Finished Aug 03 04:22:04 PM PDT 24
Peak memory 203436 kb
Host smart-bb945869-568a-4b70-9551-1686f1870939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314145077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1314145077
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1975176783
Short name T1097
Test name
Test status
Simulation time 280571228 ps
CPU time 3.15 seconds
Started Aug 03 04:22:51 PM PDT 24
Finished Aug 03 04:22:54 PM PDT 24
Peak memory 215372 kb
Host smart-57dac9fe-bfd8-46f7-8610-6cb01839e875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975176783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1975176783
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3663108055
Short name T1123
Test name
Test status
Simulation time 172924607 ps
CPU time 1.55 seconds
Started Aug 03 04:24:19 PM PDT 24
Finished Aug 03 04:24:21 PM PDT 24
Peak memory 215076 kb
Host smart-1d9de512-ddb2-47e2-b3d6-f52f1266f787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663108055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3663108055
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1994301597
Short name T1057
Test name
Test status
Simulation time 105615295 ps
CPU time 6.62 seconds
Started Aug 03 04:21:33 PM PDT 24
Finished Aug 03 04:21:40 PM PDT 24
Peak memory 214672 kb
Host smart-60599fbc-e0ad-4fc5-af24-8afa8d682af2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994301597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1994301597
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3679130536
Short name T1053
Test name
Test status
Simulation time 3791125406 ps
CPU time 24.11 seconds
Started Aug 03 04:21:56 PM PDT 24
Finished Aug 03 04:22:20 PM PDT 24
Peak memory 214956 kb
Host smart-c1cfa923-d4ac-4bad-8854-b906244df4e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679130536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3679130536
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4008118345
Short name T1087
Test name
Test status
Simulation time 1259410339 ps
CPU time 24.44 seconds
Started Aug 03 04:21:54 PM PDT 24
Finished Aug 03 04:22:19 PM PDT 24
Peak memory 206724 kb
Host smart-87e303bb-c8ce-480d-8716-e5a38d775bc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008118345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4008118345
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1482139116
Short name T81
Test name
Test status
Simulation time 61424357 ps
CPU time 1.18 seconds
Started Aug 03 04:24:00 PM PDT 24
Finished Aug 03 04:24:01 PM PDT 24
Peak memory 205880 kb
Host smart-8021494b-b0bd-4f94-87b1-36ea3dd2688e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482139116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1482139116
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3466996639
Short name T1066
Test name
Test status
Simulation time 206686464 ps
CPU time 1.73 seconds
Started Aug 03 04:21:53 PM PDT 24
Finished Aug 03 04:21:55 PM PDT 24
Peak memory 215048 kb
Host smart-f62242b5-ce5e-444e-a1b8-da4855cf01f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466996639 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3466996639
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3706286460
Short name T116
Test name
Test status
Simulation time 160923689 ps
CPU time 2.15 seconds
Started Aug 03 04:21:52 PM PDT 24
Finished Aug 03 04:21:55 PM PDT 24
Peak memory 214892 kb
Host smart-921ed73d-20b1-440d-a62e-5de457872718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706286460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
706286460
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2455207049
Short name T1104
Test name
Test status
Simulation time 51250040 ps
CPU time 0.74 seconds
Started Aug 03 04:23:19 PM PDT 24
Finished Aug 03 04:23:20 PM PDT 24
Peak memory 203256 kb
Host smart-8997b87f-ce47-4c52-aa3a-8054faaa0402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455207049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
455207049
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1132560910
Short name T115
Test name
Test status
Simulation time 95861820 ps
CPU time 2.12 seconds
Started Aug 03 04:21:32 PM PDT 24
Finished Aug 03 04:21:34 PM PDT 24
Peak memory 214908 kb
Host smart-de9e00b3-de11-41de-b0a7-6030a1719824
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132560910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1132560910
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3425323517
Short name T1062
Test name
Test status
Simulation time 46095630 ps
CPU time 0.71 seconds
Started Aug 03 04:21:32 PM PDT 24
Finished Aug 03 04:21:33 PM PDT 24
Peak memory 203368 kb
Host smart-7486b1c3-7b45-4a6e-82ef-f8f3bb0c2594
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425323517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3425323517
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1818413572
Short name T1040
Test name
Test status
Simulation time 431194736 ps
CPU time 3.02 seconds
Started Aug 03 04:21:54 PM PDT 24
Finished Aug 03 04:21:57 PM PDT 24
Peak memory 214900 kb
Host smart-a3d038f1-86bd-47da-aead-2710a0a64ecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818413572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1818413572
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1006682653
Short name T1090
Test name
Test status
Simulation time 83724344 ps
CPU time 1.52 seconds
Started Aug 03 04:21:31 PM PDT 24
Finished Aug 03 04:21:33 PM PDT 24
Peak memory 215136 kb
Host smart-679ab051-8725-4771-a8fe-8c6704859bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006682653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
006682653
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2633086669
Short name T106
Test name
Test status
Simulation time 4749709990 ps
CPU time 8.1 seconds
Started Aug 03 04:20:50 PM PDT 24
Finished Aug 03 04:20:58 PM PDT 24
Peak memory 215044 kb
Host smart-e3c1ffe0-5d47-449f-9658-d49c742e2b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633086669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2633086669
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2534622996
Short name T1014
Test name
Test status
Simulation time 41089866 ps
CPU time 0.71 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:40 PM PDT 24
Peak memory 203368 kb
Host smart-71e6ba30-6189-4ee4-b93c-9d071a4bb98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534622996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2534622996
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3465734869
Short name T1095
Test name
Test status
Simulation time 17456018 ps
CPU time 0.67 seconds
Started Aug 03 04:24:19 PM PDT 24
Finished Aug 03 04:24:20 PM PDT 24
Peak memory 203412 kb
Host smart-3b4324e2-b292-4a15-aea0-e25441c81931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465734869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3465734869
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2577904724
Short name T1077
Test name
Test status
Simulation time 11247929 ps
CPU time 0.76 seconds
Started Aug 03 04:22:02 PM PDT 24
Finished Aug 03 04:22:03 PM PDT 24
Peak memory 203772 kb
Host smart-ffa6cf3e-8fc2-4175-953b-2583b3396111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577904724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2577904724
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2082094299
Short name T1075
Test name
Test status
Simulation time 98590784 ps
CPU time 0.77 seconds
Started Aug 03 04:21:43 PM PDT 24
Finished Aug 03 04:21:43 PM PDT 24
Peak memory 203528 kb
Host smart-abbcb663-2be6-4903-829e-ed41f25bc22b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082094299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2082094299
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1966151394
Short name T1013
Test name
Test status
Simulation time 14377727 ps
CPU time 0.69 seconds
Started Aug 03 04:22:52 PM PDT 24
Finished Aug 03 04:22:53 PM PDT 24
Peak memory 203412 kb
Host smart-635fc83d-98e8-4abc-b09e-fe8ee0acfdaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966151394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1966151394
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2844385475
Short name T1092
Test name
Test status
Simulation time 93180389 ps
CPU time 0.84 seconds
Started Aug 03 04:22:02 PM PDT 24
Finished Aug 03 04:22:03 PM PDT 24
Peak memory 203424 kb
Host smart-9d8183e3-3314-46e1-b2b5-9429fb4e1f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844385475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2844385475
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2951072498
Short name T1112
Test name
Test status
Simulation time 30121231 ps
CPU time 0.74 seconds
Started Aug 03 04:22:01 PM PDT 24
Finished Aug 03 04:22:02 PM PDT 24
Peak memory 203380 kb
Host smart-6c522d39-ea13-40c0-bc48-c7cebf62c948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951072498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2951072498
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2973581263
Short name T1026
Test name
Test status
Simulation time 13649216 ps
CPU time 0.8 seconds
Started Aug 03 04:22:28 PM PDT 24
Finished Aug 03 04:22:29 PM PDT 24
Peak memory 203432 kb
Host smart-c2d09b70-2beb-4196-b01b-04cfd6028fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973581263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2973581263
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2785267513
Short name T1010
Test name
Test status
Simulation time 14396493 ps
CPU time 0.72 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:16 PM PDT 24
Peak memory 203772 kb
Host smart-0a09b87a-2165-486a-9cac-5ee7f6f95990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785267513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2785267513
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2977084526
Short name T1009
Test name
Test status
Simulation time 21662815 ps
CPU time 0.69 seconds
Started Aug 03 04:22:31 PM PDT 24
Finished Aug 03 04:22:32 PM PDT 24
Peak memory 203740 kb
Host smart-6ddf5a0c-33cb-4687-ad27-827d34f6880e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977084526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2977084526
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2735043153
Short name T112
Test name
Test status
Simulation time 209645597 ps
CPU time 7.83 seconds
Started Aug 03 04:22:35 PM PDT 24
Finished Aug 03 04:22:43 PM PDT 24
Peak memory 215048 kb
Host smart-35228447-141f-490a-84b2-8996d4de4e62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735043153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2735043153
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3081479682
Short name T1061
Test name
Test status
Simulation time 13378514958 ps
CPU time 23.1 seconds
Started Aug 03 04:21:50 PM PDT 24
Finished Aug 03 04:22:14 PM PDT 24
Peak memory 206784 kb
Host smart-c9906e23-79c7-43aa-a94c-7f8d08c23840
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081479682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3081479682
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2294468883
Short name T80
Test name
Test status
Simulation time 43842158 ps
CPU time 1.35 seconds
Started Aug 03 04:21:51 PM PDT 24
Finished Aug 03 04:21:53 PM PDT 24
Peak memory 216008 kb
Host smart-031a0621-1014-4e45-a0d7-e45edcc1d3d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294468883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2294468883
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1698492168
Short name T1099
Test name
Test status
Simulation time 339306031 ps
CPU time 2.55 seconds
Started Aug 03 04:21:41 PM PDT 24
Finished Aug 03 04:21:44 PM PDT 24
Peak memory 216376 kb
Host smart-66cdfbbe-a98f-43d4-8906-f309c8f7cd26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698492168 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1698492168
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2068165605
Short name T1122
Test name
Test status
Simulation time 140247303 ps
CPU time 1.49 seconds
Started Aug 03 04:21:50 PM PDT 24
Finished Aug 03 04:21:52 PM PDT 24
Peak memory 206724 kb
Host smart-3369a99f-46ff-480e-ba17-c0ec60bddb69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068165605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
068165605
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.999523382
Short name T1054
Test name
Test status
Simulation time 24819302 ps
CPU time 0.67 seconds
Started Aug 03 04:21:54 PM PDT 24
Finished Aug 03 04:21:55 PM PDT 24
Peak memory 203468 kb
Host smart-54c850e1-a8ec-411f-accd-1da8682dd4f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999523382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.999523382
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4212400837
Short name T1071
Test name
Test status
Simulation time 192995681 ps
CPU time 1.59 seconds
Started Aug 03 04:23:17 PM PDT 24
Finished Aug 03 04:23:19 PM PDT 24
Peak memory 214204 kb
Host smart-8cd65da7-ebd8-494e-bc3a-1211b7c61bea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212400837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4212400837
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3140621461
Short name T1125
Test name
Test status
Simulation time 21014577 ps
CPU time 0.75 seconds
Started Aug 03 04:21:47 PM PDT 24
Finished Aug 03 04:21:48 PM PDT 24
Peak memory 203752 kb
Host smart-fb21e3e8-7870-424b-9dd8-3e46fd34407d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140621461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3140621461
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1581403569
Short name T1011
Test name
Test status
Simulation time 468047563 ps
CPU time 3.99 seconds
Started Aug 03 04:21:25 PM PDT 24
Finished Aug 03 04:21:29 PM PDT 24
Peak memory 214992 kb
Host smart-38d30eb6-55d6-4dce-b8f8-0e7b9bf4d42d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581403569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1581403569
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1174510517
Short name T61
Test name
Test status
Simulation time 163034575 ps
CPU time 2.48 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:42 PM PDT 24
Peak memory 214896 kb
Host smart-8785d994-3fe1-4eb7-b89b-702bad29afd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174510517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
174510517
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2412173022
Short name T1089
Test name
Test status
Simulation time 110127556 ps
CPU time 6.59 seconds
Started Aug 03 04:21:55 PM PDT 24
Finished Aug 03 04:22:02 PM PDT 24
Peak memory 215116 kb
Host smart-b6f4a126-b97c-4de0-9c7d-9220161d5ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412173022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2412173022
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1577931218
Short name T1055
Test name
Test status
Simulation time 26333384 ps
CPU time 0.77 seconds
Started Aug 03 04:23:46 PM PDT 24
Finished Aug 03 04:23:47 PM PDT 24
Peak memory 203380 kb
Host smart-36b14295-7d07-447b-bf9a-1f8488b0e91a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577931218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1577931218
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3716990352
Short name T1048
Test name
Test status
Simulation time 38126877 ps
CPU time 0.73 seconds
Started Aug 03 04:22:26 PM PDT 24
Finished Aug 03 04:22:27 PM PDT 24
Peak memory 203440 kb
Host smart-8825df4b-9a9e-4bd6-94d8-31b4938adad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716990352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3716990352
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2591871653
Short name T1006
Test name
Test status
Simulation time 54559452 ps
CPU time 0.78 seconds
Started Aug 03 04:23:46 PM PDT 24
Finished Aug 03 04:23:47 PM PDT 24
Peak memory 203404 kb
Host smart-df089db4-0444-4270-baea-c86746fdfe0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591871653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2591871653
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.345362012
Short name T1085
Test name
Test status
Simulation time 16538544 ps
CPU time 0.69 seconds
Started Aug 03 04:22:35 PM PDT 24
Finished Aug 03 04:22:36 PM PDT 24
Peak memory 203432 kb
Host smart-48786f01-ed06-498e-b05d-eb0dc9666b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345362012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.345362012
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4091888286
Short name T1115
Test name
Test status
Simulation time 25759905 ps
CPU time 0.71 seconds
Started Aug 03 04:23:46 PM PDT 24
Finished Aug 03 04:23:47 PM PDT 24
Peak memory 203400 kb
Host smart-99e834c8-ae52-4a4e-83cb-b8a3cca57431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091888286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4091888286
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1181632824
Short name T1050
Test name
Test status
Simulation time 54324579 ps
CPU time 0.78 seconds
Started Aug 03 04:23:08 PM PDT 24
Finished Aug 03 04:23:10 PM PDT 24
Peak memory 202224 kb
Host smart-89ce650a-bdf2-47c9-abd7-aeb240a5035e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181632824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1181632824
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1949039807
Short name T1022
Test name
Test status
Simulation time 27745430 ps
CPU time 0.73 seconds
Started Aug 03 04:23:22 PM PDT 24
Finished Aug 03 04:23:24 PM PDT 24
Peak memory 202488 kb
Host smart-fe560620-37f7-4cc6-ab8a-745e3552af1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949039807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1949039807
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.802159999
Short name T1007
Test name
Test status
Simulation time 23162290 ps
CPU time 0.69 seconds
Started Aug 03 04:23:46 PM PDT 24
Finished Aug 03 04:23:47 PM PDT 24
Peak memory 203408 kb
Host smart-56d7deb0-f09d-4693-8902-0d1b21ffca06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802159999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.802159999
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3241287858
Short name T1046
Test name
Test status
Simulation time 24091627 ps
CPU time 0.8 seconds
Started Aug 03 04:22:37 PM PDT 24
Finished Aug 03 04:22:38 PM PDT 24
Peak memory 203500 kb
Host smart-dd542578-39d9-4eb1-aa0d-d505d49537fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241287858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3241287858
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3095186237
Short name T1091
Test name
Test status
Simulation time 214729142 ps
CPU time 0.73 seconds
Started Aug 03 04:22:18 PM PDT 24
Finished Aug 03 04:22:19 PM PDT 24
Peak memory 203428 kb
Host smart-520fd0d9-de70-4c09-bf14-b91d355f3a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095186237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3095186237
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4194780720
Short name T119
Test name
Test status
Simulation time 207282188 ps
CPU time 13.77 seconds
Started Aug 03 04:24:25 PM PDT 24
Finished Aug 03 04:24:38 PM PDT 24
Peak memory 206768 kb
Host smart-b0eda795-cdaa-490a-a8bc-2bea0c488bf1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194780720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4194780720
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1364867475
Short name T120
Test name
Test status
Simulation time 5760823868 ps
CPU time 23.65 seconds
Started Aug 03 04:23:57 PM PDT 24
Finished Aug 03 04:24:21 PM PDT 24
Peak memory 206516 kb
Host smart-aef905fa-88f3-4126-b674-8a3aa4cb87d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364867475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1364867475
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3810602261
Short name T1058
Test name
Test status
Simulation time 332820594 ps
CPU time 1.04 seconds
Started Aug 03 04:21:19 PM PDT 24
Finished Aug 03 04:21:20 PM PDT 24
Peak memory 206624 kb
Host smart-12ea39ec-8eca-418d-b4ef-4367bc3a9401
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810602261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3810602261
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1616624358
Short name T103
Test name
Test status
Simulation time 46265975 ps
CPU time 3.12 seconds
Started Aug 03 04:22:21 PM PDT 24
Finished Aug 03 04:22:24 PM PDT 24
Peak memory 216848 kb
Host smart-9d3e7664-a8e1-4903-931e-368c2a76f0d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616624358 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1616624358
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3518228968
Short name T1042
Test name
Test status
Simulation time 116858388 ps
CPU time 2.65 seconds
Started Aug 03 04:21:55 PM PDT 24
Finished Aug 03 04:21:58 PM PDT 24
Peak memory 215020 kb
Host smart-a801f87d-3f90-43b6-ac3a-11e599be0b79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518228968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
518228968
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.858684935
Short name T1114
Test name
Test status
Simulation time 24111539 ps
CPU time 0.76 seconds
Started Aug 03 04:21:43 PM PDT 24
Finished Aug 03 04:21:44 PM PDT 24
Peak memory 203372 kb
Host smart-b86d1f1e-af72-4ddd-85ed-3b0271fb0b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858684935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.858684935
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1809815293
Short name T1059
Test name
Test status
Simulation time 56964956 ps
CPU time 1.89 seconds
Started Aug 03 04:22:31 PM PDT 24
Finished Aug 03 04:22:33 PM PDT 24
Peak memory 214896 kb
Host smart-b904e65d-7356-4c44-9fd3-2f8d3d36958f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809815293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1809815293
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.231022159
Short name T1043
Test name
Test status
Simulation time 43175110 ps
CPU time 0.66 seconds
Started Aug 03 04:22:41 PM PDT 24
Finished Aug 03 04:22:42 PM PDT 24
Peak memory 203736 kb
Host smart-7f3cea68-0306-4687-b761-110bb8e77bc8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231022159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.231022159
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2243512834
Short name T1073
Test name
Test status
Simulation time 3015855657 ps
CPU time 3.94 seconds
Started Aug 03 04:22:01 PM PDT 24
Finished Aug 03 04:22:05 PM PDT 24
Peak memory 214988 kb
Host smart-ba9787de-630b-4f25-a39b-dc175c6fe592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243512834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2243512834
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3645127575
Short name T92
Test name
Test status
Simulation time 278962047 ps
CPU time 6.93 seconds
Started Aug 03 04:21:53 PM PDT 24
Finished Aug 03 04:22:00 PM PDT 24
Peak memory 214936 kb
Host smart-07e518cc-84d6-4853-a161-0fd903386b30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645127575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3645127575
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1829347562
Short name T1070
Test name
Test status
Simulation time 20622942 ps
CPU time 0.7 seconds
Started Aug 03 04:22:02 PM PDT 24
Finished Aug 03 04:22:02 PM PDT 24
Peak memory 203432 kb
Host smart-76c65839-a9bc-4f98-a4be-6b5ddecb4177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829347562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1829347562
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1254448987
Short name T1012
Test name
Test status
Simulation time 32510350 ps
CPU time 0.78 seconds
Started Aug 03 04:22:00 PM PDT 24
Finished Aug 03 04:22:01 PM PDT 24
Peak memory 203712 kb
Host smart-d3abd2d1-25db-4fa1-9ac4-1605beb0336b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254448987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1254448987
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.703904667
Short name T1084
Test name
Test status
Simulation time 40521043 ps
CPU time 0.72 seconds
Started Aug 03 04:22:02 PM PDT 24
Finished Aug 03 04:22:03 PM PDT 24
Peak memory 203472 kb
Host smart-f0a2ac6d-b22c-44e0-a766-7aaa9526777e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703904667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.703904667
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2645872930
Short name T1078
Test name
Test status
Simulation time 222925814 ps
CPU time 0.73 seconds
Started Aug 03 04:23:30 PM PDT 24
Finished Aug 03 04:23:31 PM PDT 24
Peak memory 202256 kb
Host smart-74fa683c-d29b-407b-8993-089a0831dae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645872930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2645872930
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3711598843
Short name T1067
Test name
Test status
Simulation time 37194388 ps
CPU time 0.73 seconds
Started Aug 03 04:22:28 PM PDT 24
Finished Aug 03 04:22:28 PM PDT 24
Peak memory 203432 kb
Host smart-6f6f87b9-63c9-4ca7-b3a6-7fb46563e49f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711598843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3711598843
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.927455762
Short name T1124
Test name
Test status
Simulation time 89652017 ps
CPU time 0.68 seconds
Started Aug 03 04:23:38 PM PDT 24
Finished Aug 03 04:23:39 PM PDT 24
Peak memory 203436 kb
Host smart-64c293ed-7d5d-41ee-81c7-2d4735e2902b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927455762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.927455762
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1613218787
Short name T1060
Test name
Test status
Simulation time 139911247 ps
CPU time 0.81 seconds
Started Aug 03 04:23:23 PM PDT 24
Finished Aug 03 04:23:24 PM PDT 24
Peak memory 203268 kb
Host smart-d7dbb7de-e1ed-445d-87de-e09249dcde84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613218787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1613218787
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3550167711
Short name T1107
Test name
Test status
Simulation time 14454263 ps
CPU time 0.69 seconds
Started Aug 03 04:23:45 PM PDT 24
Finished Aug 03 04:23:46 PM PDT 24
Peak memory 203392 kb
Host smart-b1b6020e-db25-4e73-b81f-338f4254eda5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550167711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3550167711
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2396686588
Short name T1116
Test name
Test status
Simulation time 32228627 ps
CPU time 0.8 seconds
Started Aug 03 04:22:28 PM PDT 24
Finished Aug 03 04:22:29 PM PDT 24
Peak memory 203740 kb
Host smart-2040051e-41c8-40ce-b4f7-3fe82d019009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396686588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2396686588
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2465051256
Short name T1027
Test name
Test status
Simulation time 32946116 ps
CPU time 0.72 seconds
Started Aug 03 04:22:51 PM PDT 24
Finished Aug 03 04:22:52 PM PDT 24
Peak memory 203380 kb
Host smart-5456e42c-92dd-4400-9797-431c061b04f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465051256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2465051256
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2830246842
Short name T90
Test name
Test status
Simulation time 151863751 ps
CPU time 3.66 seconds
Started Aug 03 04:22:38 PM PDT 24
Finished Aug 03 04:22:42 PM PDT 24
Peak memory 217556 kb
Host smart-4b0c1976-01dd-4673-a4fc-f80231839c67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830246842 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2830246842
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.154328719
Short name T1131
Test name
Test status
Simulation time 46863863 ps
CPU time 1.36 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:40 PM PDT 24
Peak memory 206600 kb
Host smart-2d5da2f8-e5b4-42c8-90ea-ee02f8a67d66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154328719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.154328719
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3584470560
Short name T1018
Test name
Test status
Simulation time 19028913 ps
CPU time 0.72 seconds
Started Aug 03 04:22:04 PM PDT 24
Finished Aug 03 04:22:05 PM PDT 24
Peak memory 203448 kb
Host smart-c8120d7c-712e-468b-85db-2d41c7a4c575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584470560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
584470560
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.17441662
Short name T1015
Test name
Test status
Simulation time 303433867 ps
CPU time 3.87 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:43 PM PDT 24
Peak memory 214908 kb
Host smart-2f6cef30-b933-4917-84eb-f38bad334c47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17441662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi
_device_same_csr_outstanding.17441662
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1913577725
Short name T1068
Test name
Test status
Simulation time 103158270 ps
CPU time 1.71 seconds
Started Aug 03 04:21:59 PM PDT 24
Finished Aug 03 04:22:01 PM PDT 24
Peak memory 215004 kb
Host smart-6a5e3d10-ca10-4a17-acf8-1cb2dea82979
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913577725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
913577725
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2515201386
Short name T1119
Test name
Test status
Simulation time 651522189 ps
CPU time 13.65 seconds
Started Aug 03 04:22:25 PM PDT 24
Finished Aug 03 04:22:38 PM PDT 24
Peak memory 215008 kb
Host smart-3f7dcf61-ff3d-4df7-9c92-6366863b213e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515201386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2515201386
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3759930977
Short name T1033
Test name
Test status
Simulation time 98629366 ps
CPU time 1.69 seconds
Started Aug 03 04:21:39 PM PDT 24
Finished Aug 03 04:21:40 PM PDT 24
Peak memory 216092 kb
Host smart-e1760fd3-e763-4d56-99e9-03f50ed804e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759930977 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3759930977
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4096677565
Short name T1082
Test name
Test status
Simulation time 38701994 ps
CPU time 2.32 seconds
Started Aug 03 04:24:19 PM PDT 24
Finished Aug 03 04:24:21 PM PDT 24
Peak memory 214932 kb
Host smart-d05ddf9f-5c97-4ba7-8edc-9153918c64ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096677565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
096677565
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1180161821
Short name T1032
Test name
Test status
Simulation time 35302530 ps
CPU time 0.73 seconds
Started Aug 03 04:22:23 PM PDT 24
Finished Aug 03 04:22:24 PM PDT 24
Peak memory 203680 kb
Host smart-fae69550-df92-49d6-b0ad-8a565f67d34c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180161821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
180161821
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3682587955
Short name T1037
Test name
Test status
Simulation time 70290674 ps
CPU time 1.84 seconds
Started Aug 03 04:21:50 PM PDT 24
Finished Aug 03 04:21:53 PM PDT 24
Peak memory 206820 kb
Host smart-0ddc0f08-04f1-469c-9d37-fba96b2eb4b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682587955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3682587955
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1733312178
Short name T162
Test name
Test status
Simulation time 1128881179 ps
CPU time 14.91 seconds
Started Aug 03 04:21:19 PM PDT 24
Finished Aug 03 04:21:34 PM PDT 24
Peak memory 214888 kb
Host smart-ef3a2ef3-ba44-428b-a2fe-3abde3446ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733312178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1733312178
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.681893689
Short name T1052
Test name
Test status
Simulation time 45505141 ps
CPU time 2.9 seconds
Started Aug 03 04:22:02 PM PDT 24
Finished Aug 03 04:22:05 PM PDT 24
Peak memory 217096 kb
Host smart-c357c99f-a2e9-4a77-b762-4c3d9b80d811
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681893689 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.681893689
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4083889374
Short name T1072
Test name
Test status
Simulation time 193295393 ps
CPU time 2.79 seconds
Started Aug 03 04:22:20 PM PDT 24
Finished Aug 03 04:22:23 PM PDT 24
Peak memory 214964 kb
Host smart-3f30bb61-a147-4c3e-9c6e-e16918dbeff8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083889374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
083889374
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.554405992
Short name T1074
Test name
Test status
Simulation time 16726201 ps
CPU time 0.73 seconds
Started Aug 03 04:22:36 PM PDT 24
Finished Aug 03 04:22:37 PM PDT 24
Peak memory 203752 kb
Host smart-2fb53a67-44ed-48ea-b244-b1e846105aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554405992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.554405992
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.925827450
Short name T1093
Test name
Test status
Simulation time 75853576 ps
CPU time 2.75 seconds
Started Aug 03 04:22:35 PM PDT 24
Finished Aug 03 04:22:38 PM PDT 24
Peak memory 214880 kb
Host smart-e15158ab-2c08-404d-ba51-2f3116370ede
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925827450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.925827450
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1032602689
Short name T1083
Test name
Test status
Simulation time 251360250 ps
CPU time 5.58 seconds
Started Aug 03 04:23:38 PM PDT 24
Finished Aug 03 04:23:47 PM PDT 24
Peak memory 215072 kb
Host smart-f30b58c2-d5f6-44ef-9aa5-a56089b22181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032602689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
032602689
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1407548481
Short name T1031
Test name
Test status
Simulation time 87183682 ps
CPU time 1.6 seconds
Started Aug 03 04:22:54 PM PDT 24
Finished Aug 03 04:22:55 PM PDT 24
Peak memory 215052 kb
Host smart-60f3a38c-4f0b-4c5e-9e4d-4d23ff93572f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407548481 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1407548481
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1763044979
Short name T1017
Test name
Test status
Simulation time 39225839 ps
CPU time 1.47 seconds
Started Aug 03 04:21:26 PM PDT 24
Finished Aug 03 04:21:28 PM PDT 24
Peak memory 206680 kb
Host smart-b0854bd2-ca8b-4afc-81e9-cfbde1ac31ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763044979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
763044979
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1516067745
Short name T1109
Test name
Test status
Simulation time 12963677 ps
CPU time 0.74 seconds
Started Aug 03 04:23:04 PM PDT 24
Finished Aug 03 04:23:04 PM PDT 24
Peak memory 203800 kb
Host smart-99ca4e02-268c-44c0-b456-0b6054de2e81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516067745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
516067745
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2023030887
Short name T1020
Test name
Test status
Simulation time 117265896 ps
CPU time 2.79 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:21:43 PM PDT 24
Peak memory 214856 kb
Host smart-cf84d6be-d99c-45f2-8b41-37d3fb80551e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023030887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2023030887
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1927790412
Short name T101
Test name
Test status
Simulation time 51083168 ps
CPU time 3.08 seconds
Started Aug 03 04:21:40 PM PDT 24
Finished Aug 03 04:21:43 PM PDT 24
Peak memory 214976 kb
Host smart-624ba05a-843a-428a-895c-42d99c950105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927790412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
927790412
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1915087355
Short name T62
Test name
Test status
Simulation time 901509272 ps
CPU time 20.31 seconds
Started Aug 03 04:22:02 PM PDT 24
Finished Aug 03 04:22:22 PM PDT 24
Peak memory 215224 kb
Host smart-6482f93b-7567-47de-9b85-8f4a8cab95f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915087355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1915087355
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2894702857
Short name T107
Test name
Test status
Simulation time 835557433 ps
CPU time 3.69 seconds
Started Aug 03 04:22:08 PM PDT 24
Finished Aug 03 04:22:11 PM PDT 24
Peak memory 216504 kb
Host smart-17e1c576-7d25-46b5-8276-81acc465306c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894702857 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2894702857
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1998109000
Short name T118
Test name
Test status
Simulation time 80223273 ps
CPU time 1.32 seconds
Started Aug 03 04:22:01 PM PDT 24
Finished Aug 03 04:22:03 PM PDT 24
Peak memory 206600 kb
Host smart-2e008c4a-f685-4c16-8254-d736488c3b89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998109000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
998109000
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3631539251
Short name T1065
Test name
Test status
Simulation time 24775991 ps
CPU time 0.78 seconds
Started Aug 03 04:21:52 PM PDT 24
Finished Aug 03 04:21:53 PM PDT 24
Peak memory 203404 kb
Host smart-f3e4997f-0a68-4dcf-b715-7dec1988c708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631539251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
631539251
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.300851083
Short name T1102
Test name
Test status
Simulation time 145224543 ps
CPU time 1.94 seconds
Started Aug 03 04:22:20 PM PDT 24
Finished Aug 03 04:22:22 PM PDT 24
Peak memory 214996 kb
Host smart-ea154375-02bc-4117-ae71-ac54fab424c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300851083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.300851083
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1883686291
Short name T100
Test name
Test status
Simulation time 653953693 ps
CPU time 4.38 seconds
Started Aug 03 04:21:26 PM PDT 24
Finished Aug 03 04:21:30 PM PDT 24
Peak memory 215124 kb
Host smart-42adab0f-1b20-4e28-9534-200f8afa2275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883686291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
883686291
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1312640512
Short name T108
Test name
Test status
Simulation time 646753555 ps
CPU time 18.28 seconds
Started Aug 03 04:22:49 PM PDT 24
Finished Aug 03 04:23:08 PM PDT 24
Peak memory 214928 kb
Host smart-76fe6dcf-43d6-4396-aa30-c2782b26c65b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312640512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1312640512
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2910444715
Short name T527
Test name
Test status
Simulation time 65211559 ps
CPU time 0.77 seconds
Started Aug 03 05:01:43 PM PDT 24
Finished Aug 03 05:01:44 PM PDT 24
Peak memory 205268 kb
Host smart-6032294c-d5f9-4cc6-949e-8e3c73508080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910444715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
910444715
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.560664701
Short name T590
Test name
Test status
Simulation time 238658985 ps
CPU time 4.14 seconds
Started Aug 03 05:01:27 PM PDT 24
Finished Aug 03 05:01:31 PM PDT 24
Peak memory 233140 kb
Host smart-8d7d2256-0632-461c-b7d9-17108f7cc616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560664701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.560664701
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2681787889
Short name T684
Test name
Test status
Simulation time 32429230 ps
CPU time 0.78 seconds
Started Aug 03 05:01:27 PM PDT 24
Finished Aug 03 05:01:28 PM PDT 24
Peak memory 206996 kb
Host smart-f046c8cb-abd0-4f3d-8ce6-67a1e804780a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681787889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2681787889
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1480288876
Short name T663
Test name
Test status
Simulation time 46393796151 ps
CPU time 190.39 seconds
Started Aug 03 05:01:37 PM PDT 24
Finished Aug 03 05:04:47 PM PDT 24
Peak memory 255044 kb
Host smart-c2a4f38d-65e6-4974-a103-b99df9f41800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480288876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1480288876
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.329896412
Short name T133
Test name
Test status
Simulation time 86124486867 ps
CPU time 431.42 seconds
Started Aug 03 05:01:45 PM PDT 24
Finished Aug 03 05:08:57 PM PDT 24
Peak memory 266592 kb
Host smart-755178d6-91bf-4829-b97e-6cc419a6cfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329896412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.329896412
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3693407081
Short name T31
Test name
Test status
Simulation time 10739995196 ps
CPU time 99.63 seconds
Started Aug 03 05:01:41 PM PDT 24
Finished Aug 03 05:03:21 PM PDT 24
Peak memory 255284 kb
Host smart-dcd24396-0911-4bc2-aae1-3638d4494141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693407081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3693407081
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3567580658
Short name T371
Test name
Test status
Simulation time 3090780141 ps
CPU time 13.09 seconds
Started Aug 03 05:01:37 PM PDT 24
Finished Aug 03 05:01:50 PM PDT 24
Peak memory 249596 kb
Host smart-a937d9c3-0189-492b-b59f-8096ad7c3900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567580658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3567580658
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3733383691
Short name T286
Test name
Test status
Simulation time 10369524652 ps
CPU time 48.75 seconds
Started Aug 03 05:01:22 PM PDT 24
Finished Aug 03 05:02:10 PM PDT 24
Peak memory 237616 kb
Host smart-da90d8e8-7a94-4e84-8ab8-f9319b8a565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733383691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3733383691
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1274352130
Short name T38
Test name
Test status
Simulation time 1315052225 ps
CPU time 8.43 seconds
Started Aug 03 05:01:49 PM PDT 24
Finished Aug 03 05:01:58 PM PDT 24
Peak memory 220116 kb
Host smart-e2f1762e-280c-4e7f-9e8d-c003fc371e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274352130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1274352130
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3308844999
Short name T787
Test name
Test status
Simulation time 26069406024 ps
CPU time 35.88 seconds
Started Aug 03 05:01:36 PM PDT 24
Finished Aug 03 05:02:12 PM PDT 24
Peak memory 249512 kb
Host smart-98ffc112-786b-4cda-b68f-dcce4e8124cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308844999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3308844999
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1069182025
Short name T938
Test name
Test status
Simulation time 415690552 ps
CPU time 5.32 seconds
Started Aug 03 05:01:28 PM PDT 24
Finished Aug 03 05:01:33 PM PDT 24
Peak memory 233096 kb
Host smart-0f0cc325-9247-44b5-88b4-376765b180de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069182025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1069182025
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.231332722
Short name T873
Test name
Test status
Simulation time 742612109 ps
CPU time 2.1 seconds
Started Aug 03 05:01:26 PM PDT 24
Finished Aug 03 05:01:28 PM PDT 24
Peak memory 224936 kb
Host smart-c869d306-82b8-4099-8d0b-2635f8e7c7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231332722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.231332722
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1174628260
Short name T976
Test name
Test status
Simulation time 1028045634 ps
CPU time 14.58 seconds
Started Aug 03 05:01:25 PM PDT 24
Finished Aug 03 05:01:39 PM PDT 24
Peak memory 220832 kb
Host smart-0aa533ac-4f8f-480b-a9d2-f6decf53f45a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1174628260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1174628260
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1857681748
Short name T68
Test name
Test status
Simulation time 36692755 ps
CPU time 0.98 seconds
Started Aug 03 05:01:28 PM PDT 24
Finished Aug 03 05:01:29 PM PDT 24
Peak memory 236276 kb
Host smart-c82422c0-eaa7-4acc-8ed3-7fc7e0087a25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857681748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1857681748
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.999229140
Short name T783
Test name
Test status
Simulation time 485833234 ps
CPU time 0.99 seconds
Started Aug 03 05:01:26 PM PDT 24
Finished Aug 03 05:01:27 PM PDT 24
Peak memory 207204 kb
Host smart-e65869e8-e30d-4f4d-85de-0e1b69328d49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999229140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.999229140
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2641298190
Short name T965
Test name
Test status
Simulation time 1783990182 ps
CPU time 6.1 seconds
Started Aug 03 05:01:26 PM PDT 24
Finished Aug 03 05:01:33 PM PDT 24
Peak memory 216724 kb
Host smart-f5bddb3e-467f-41a8-99cd-1a451bb80f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641298190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2641298190
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1576602123
Short name T559
Test name
Test status
Simulation time 37150530 ps
CPU time 0.92 seconds
Started Aug 03 05:01:44 PM PDT 24
Finished Aug 03 05:01:45 PM PDT 24
Peak memory 207692 kb
Host smart-68f42177-9d40-467d-8db1-a04ee4d149bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576602123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1576602123
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.319180970
Short name T794
Test name
Test status
Simulation time 77464067 ps
CPU time 0.94 seconds
Started Aug 03 05:01:25 PM PDT 24
Finished Aug 03 05:01:26 PM PDT 24
Peak memory 206384 kb
Host smart-69927dde-e815-46d4-9d86-9e8405bd8659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319180970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.319180970
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2585364364
Short name T184
Test name
Test status
Simulation time 584561037 ps
CPU time 3.4 seconds
Started Aug 03 05:01:40 PM PDT 24
Finished Aug 03 05:01:44 PM PDT 24
Peak memory 224936 kb
Host smart-f1ca85c8-4ba6-46af-9d9b-d60d754a5e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585364364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2585364364
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1489996262
Short name T705
Test name
Test status
Simulation time 38600388 ps
CPU time 0.72 seconds
Started Aug 03 05:01:48 PM PDT 24
Finished Aug 03 05:01:49 PM PDT 24
Peak memory 206120 kb
Host smart-5cd03e99-aa67-4e52-aa0b-0757d1ee554e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489996262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
489996262
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3015672328
Short name T804
Test name
Test status
Simulation time 720423678 ps
CPU time 2.22 seconds
Started Aug 03 05:01:48 PM PDT 24
Finished Aug 03 05:01:50 PM PDT 24
Peak memory 224924 kb
Host smart-e66caaac-9894-4786-aa4d-52088a41af23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015672328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3015672328
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3011546110
Short name T533
Test name
Test status
Simulation time 26020502 ps
CPU time 0.78 seconds
Started Aug 03 05:01:34 PM PDT 24
Finished Aug 03 05:01:35 PM PDT 24
Peak memory 206884 kb
Host smart-5e7fa4b4-ed26-4f0d-b5cd-febe759d07d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011546110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3011546110
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2126433022
Short name T812
Test name
Test status
Simulation time 83467732147 ps
CPU time 418.28 seconds
Started Aug 03 05:01:37 PM PDT 24
Finished Aug 03 05:08:35 PM PDT 24
Peak memory 267048 kb
Host smart-2f585378-f55f-4bcd-bb35-2e7d35212d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126433022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2126433022
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.869105966
Short name T247
Test name
Test status
Simulation time 22994923320 ps
CPU time 226.68 seconds
Started Aug 03 05:01:49 PM PDT 24
Finished Aug 03 05:05:36 PM PDT 24
Peak memory 252120 kb
Host smart-f29a5c52-93b1-49fc-a224-a5d71f7af5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869105966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
869105966
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.132148229
Short name T514
Test name
Test status
Simulation time 130692668 ps
CPU time 2.19 seconds
Started Aug 03 05:01:39 PM PDT 24
Finished Aug 03 05:01:42 PM PDT 24
Peak memory 225064 kb
Host smart-9d4c56a4-3504-4e38-8c0d-4970191be0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132148229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.132148229
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3981419426
Short name T126
Test name
Test status
Simulation time 32978821 ps
CPU time 2.45 seconds
Started Aug 03 05:01:31 PM PDT 24
Finished Aug 03 05:01:34 PM PDT 24
Peak memory 232780 kb
Host smart-56e17110-ba0a-4fd1-a063-7b0a0f4e2da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981419426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3981419426
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3335014491
Short name T881
Test name
Test status
Simulation time 54107403291 ps
CPU time 80.15 seconds
Started Aug 03 05:01:40 PM PDT 24
Finished Aug 03 05:03:00 PM PDT 24
Peak memory 237276 kb
Host smart-0b645ddb-7503-47af-a05e-51697c32933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335014491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3335014491
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3093420685
Short name T217
Test name
Test status
Simulation time 17136780787 ps
CPU time 16.27 seconds
Started Aug 03 05:01:46 PM PDT 24
Finished Aug 03 05:02:02 PM PDT 24
Peak memory 233192 kb
Host smart-8b3e5eb1-2aa0-4b75-8c55-c4898a4874c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093420685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3093420685
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1178622681
Short name T950
Test name
Test status
Simulation time 9109218018 ps
CPU time 6.21 seconds
Started Aug 03 05:01:49 PM PDT 24
Finished Aug 03 05:01:55 PM PDT 24
Peak memory 224776 kb
Host smart-db5f8a6c-0bfc-411e-806c-1b27a85a6ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178622681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1178622681
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3898437089
Short name T36
Test name
Test status
Simulation time 3006017728 ps
CPU time 7.49 seconds
Started Aug 03 05:01:34 PM PDT 24
Finished Aug 03 05:01:41 PM PDT 24
Peak memory 222556 kb
Host smart-361b298f-2082-41e9-8522-a12910431d66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3898437089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3898437089
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2814316873
Short name T67
Test name
Test status
Simulation time 150642760 ps
CPU time 0.97 seconds
Started Aug 03 05:01:43 PM PDT 24
Finished Aug 03 05:01:44 PM PDT 24
Peak memory 235780 kb
Host smart-96e0774c-212a-41ab-ba45-cf871eb47abf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814316873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2814316873
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1616248798
Short name T566
Test name
Test status
Simulation time 9505121201 ps
CPU time 125.45 seconds
Started Aug 03 05:01:47 PM PDT 24
Finished Aug 03 05:03:53 PM PDT 24
Peak memory 269424 kb
Host smart-859b8406-9521-4fdd-a650-16da03e71363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616248798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1616248798
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.779647646
Short name T878
Test name
Test status
Simulation time 891509843 ps
CPU time 7.55 seconds
Started Aug 03 05:01:49 PM PDT 24
Finished Aug 03 05:01:56 PM PDT 24
Peak memory 216656 kb
Host smart-1893064a-e357-4131-8cd1-9dd96b7e3710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779647646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.779647646
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2975591548
Short name T900
Test name
Test status
Simulation time 477674634 ps
CPU time 2.05 seconds
Started Aug 03 05:01:28 PM PDT 24
Finished Aug 03 05:01:30 PM PDT 24
Peak memory 216488 kb
Host smart-100cea0c-b9d6-4ad3-b5de-1c92c39f9412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975591548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2975591548
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2169732152
Short name T906
Test name
Test status
Simulation time 115545456 ps
CPU time 1.6 seconds
Started Aug 03 05:01:49 PM PDT 24
Finished Aug 03 05:01:51 PM PDT 24
Peak memory 216564 kb
Host smart-c56fd65c-868b-4898-8964-18f1ec71477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169732152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2169732152
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.539152211
Short name T619
Test name
Test status
Simulation time 34922364 ps
CPU time 0.79 seconds
Started Aug 03 05:01:30 PM PDT 24
Finished Aug 03 05:01:31 PM PDT 24
Peak memory 206324 kb
Host smart-48f06358-9beb-4e94-a56c-27a1ffdaa487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539152211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.539152211
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.4158187329
Short name T879
Test name
Test status
Simulation time 584333679 ps
CPU time 5.45 seconds
Started Aug 03 05:01:36 PM PDT 24
Finished Aug 03 05:01:42 PM PDT 24
Peak memory 238740 kb
Host smart-6de99e60-8ddc-4fbd-82db-761ad97fa841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158187329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4158187329
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1671380844
Short name T964
Test name
Test status
Simulation time 24895868 ps
CPU time 0.7 seconds
Started Aug 03 05:02:08 PM PDT 24
Finished Aug 03 05:02:09 PM PDT 24
Peak memory 205280 kb
Host smart-e23eb591-6fcd-4bb7-8335-021b9f67de98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671380844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1671380844
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1176732740
Short name T603
Test name
Test status
Simulation time 30650804 ps
CPU time 0.76 seconds
Started Aug 03 05:02:06 PM PDT 24
Finished Aug 03 05:02:07 PM PDT 24
Peak memory 207288 kb
Host smart-6d01de1b-c0c8-4fb1-8b91-ff6f50033d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176732740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1176732740
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1791942697
Short name T1002
Test name
Test status
Simulation time 11621380675 ps
CPU time 160.57 seconds
Started Aug 03 05:02:08 PM PDT 24
Finished Aug 03 05:04:49 PM PDT 24
Peak memory 265160 kb
Host smart-c1e5aebb-3be6-4c68-abdb-7c6fef045f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791942697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1791942697
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1279215727
Short name T986
Test name
Test status
Simulation time 7370985795 ps
CPU time 72.51 seconds
Started Aug 03 05:02:07 PM PDT 24
Finished Aug 03 05:03:20 PM PDT 24
Peak memory 254248 kb
Host smart-ef581c1e-34c9-4acf-aca2-c6878d96baf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279215727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1279215727
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2573820433
Short name T834
Test name
Test status
Simulation time 36154397 ps
CPU time 0.79 seconds
Started Aug 03 05:02:09 PM PDT 24
Finished Aug 03 05:02:10 PM PDT 24
Peak memory 216068 kb
Host smart-49238205-d169-4ab1-812e-e5e5bbc88a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573820433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2573820433
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.473515368
Short name T625
Test name
Test status
Simulation time 745890038 ps
CPU time 10.23 seconds
Started Aug 03 05:02:10 PM PDT 24
Finished Aug 03 05:02:21 PM PDT 24
Peak memory 233108 kb
Host smart-937b2e54-5979-44ea-9a2c-fee5f9161737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473515368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.473515368
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4090239695
Short name T257
Test name
Test status
Simulation time 984734302 ps
CPU time 12.46 seconds
Started Aug 03 05:02:08 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 233136 kb
Host smart-cdb03b13-3804-461c-a12c-31ead161c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090239695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4090239695
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1998565162
Short name T784
Test name
Test status
Simulation time 444831770 ps
CPU time 3.04 seconds
Started Aug 03 05:02:10 PM PDT 24
Finished Aug 03 05:02:13 PM PDT 24
Peak memory 224876 kb
Host smart-b112ef2a-2119-4d36-aa2c-6898cdb4fbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998565162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1998565162
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3884430337
Short name T230
Test name
Test status
Simulation time 1993653788 ps
CPU time 11.46 seconds
Started Aug 03 05:02:08 PM PDT 24
Finished Aug 03 05:02:19 PM PDT 24
Peak memory 224788 kb
Host smart-4565f355-e6fd-4eb7-81cd-a0cb5c15a57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884430337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3884430337
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.369444149
Short name T743
Test name
Test status
Simulation time 1784318474 ps
CPU time 5.32 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:16 PM PDT 24
Peak memory 220776 kb
Host smart-28111b3e-1ff8-45a9-b4c3-50de604a93ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=369444149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.369444149
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3245437971
Short name T810
Test name
Test status
Simulation time 44191806405 ps
CPU time 388.07 seconds
Started Aug 03 05:02:09 PM PDT 24
Finished Aug 03 05:08:37 PM PDT 24
Peak memory 257788 kb
Host smart-607b2f60-6797-41c0-9a2f-75c1b968403a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245437971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3245437971
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2102834441
Short name T647
Test name
Test status
Simulation time 10578325708 ps
CPU time 49.98 seconds
Started Aug 03 05:02:07 PM PDT 24
Finished Aug 03 05:02:58 PM PDT 24
Peak memory 216792 kb
Host smart-7260186b-c8e1-45b5-b813-9b2cb6f7f074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102834441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2102834441
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1738231117
Short name T710
Test name
Test status
Simulation time 127140941 ps
CPU time 1.15 seconds
Started Aug 03 05:02:00 PM PDT 24
Finished Aug 03 05:02:01 PM PDT 24
Peak memory 208220 kb
Host smart-2b8725e3-09ae-4405-ad85-5316e821828a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738231117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1738231117
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1126108343
Short name T902
Test name
Test status
Simulation time 56445661 ps
CPU time 1.14 seconds
Started Aug 03 05:02:17 PM PDT 24
Finished Aug 03 05:02:19 PM PDT 24
Peak memory 207756 kb
Host smart-53857155-1366-4388-ba59-b2619f12c05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126108343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1126108343
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1376151799
Short name T473
Test name
Test status
Simulation time 257455693 ps
CPU time 0.93 seconds
Started Aug 03 05:02:10 PM PDT 24
Finished Aug 03 05:02:11 PM PDT 24
Peak memory 206352 kb
Host smart-c123a6cc-141e-4d43-a354-d0ee43bbf630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376151799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1376151799
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.491708233
Short name T594
Test name
Test status
Simulation time 601271519 ps
CPU time 3.62 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:15 PM PDT 24
Peak memory 233128 kb
Host smart-bf34a3a1-d7df-42fc-90cc-af9c0a4c01b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491708233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.491708233
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2132104460
Short name T532
Test name
Test status
Simulation time 13722538 ps
CPU time 0.7 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:02:13 PM PDT 24
Peak memory 205136 kb
Host smart-e58bd3aa-b03f-47dd-b58e-d597f25816a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132104460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2132104460
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.333124188
Short name T863
Test name
Test status
Simulation time 151410462 ps
CPU time 3.01 seconds
Started Aug 03 05:02:10 PM PDT 24
Finished Aug 03 05:02:13 PM PDT 24
Peak memory 224852 kb
Host smart-bb388cfb-f65e-4327-ab6d-bf6bee1a0c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333124188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.333124188
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3468491231
Short name T659
Test name
Test status
Simulation time 45655684 ps
CPU time 0.73 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:02:13 PM PDT 24
Peak memory 206168 kb
Host smart-078208c6-6383-44bd-8a62-d5a0a8163808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468491231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3468491231
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2035292666
Short name T677
Test name
Test status
Simulation time 1318511559 ps
CPU time 25.17 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:02:37 PM PDT 24
Peak memory 239152 kb
Host smart-7b259061-0f84-4e64-92c6-6f323d940acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035292666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2035292666
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3646054878
Short name T441
Test name
Test status
Simulation time 6027819692 ps
CPU time 56.13 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:03:09 PM PDT 24
Peak memory 233172 kb
Host smart-0cb37f7c-2b29-4e66-aabc-893102ae6595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646054878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3646054878
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1414910281
Short name T757
Test name
Test status
Simulation time 24103316 ps
CPU time 0.78 seconds
Started Aug 03 05:02:09 PM PDT 24
Finished Aug 03 05:02:10 PM PDT 24
Peak memory 216024 kb
Host smart-704dd6d3-e196-4759-8603-35507c9f0713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414910281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1414910281
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.790167066
Short name T800
Test name
Test status
Simulation time 65337338 ps
CPU time 2.97 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:19 PM PDT 24
Peak memory 233048 kb
Host smart-c2edfa86-8b83-47d6-8526-dd167317ca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790167066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.790167066
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1225007074
Short name T391
Test name
Test status
Simulation time 265408435 ps
CPU time 3.32 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:14 PM PDT 24
Peak memory 219444 kb
Host smart-b6960c1e-54c1-47f9-8204-f240c3070c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225007074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1225007074
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3018281162
Short name T206
Test name
Test status
Simulation time 423800114 ps
CPU time 3 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:14 PM PDT 24
Peak memory 224868 kb
Host smart-8e7441fc-482e-4db2-a5e1-bc6f5790011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018281162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3018281162
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.4004977664
Short name T75
Test name
Test status
Simulation time 93458860049 ps
CPU time 30.22 seconds
Started Aug 03 05:02:07 PM PDT 24
Finished Aug 03 05:02:37 PM PDT 24
Peak memory 239160 kb
Host smart-c40b4659-8881-4297-89df-550a28a2b666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004977664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.4004977664
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1133014339
Short name T144
Test name
Test status
Simulation time 1070246405 ps
CPU time 9.93 seconds
Started Aug 03 05:02:08 PM PDT 24
Finished Aug 03 05:02:18 PM PDT 24
Peak memory 221972 kb
Host smart-5ccd1e95-babb-40d1-afb9-f9793f122c57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1133014339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1133014339
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3804737600
Short name T432
Test name
Test status
Simulation time 104015990 ps
CPU time 0.69 seconds
Started Aug 03 05:02:10 PM PDT 24
Finished Aug 03 05:02:11 PM PDT 24
Peak memory 206088 kb
Host smart-d694049e-99b6-4508-9649-5889f7424e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804737600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3804737600
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.973178551
Short name T443
Test name
Test status
Simulation time 75969676 ps
CPU time 1.28 seconds
Started Aug 03 05:02:13 PM PDT 24
Finished Aug 03 05:02:14 PM PDT 24
Peak memory 208212 kb
Host smart-af2761d4-efdb-49a7-912e-5a1812583c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973178551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.973178551
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.472597760
Short name T891
Test name
Test status
Simulation time 1242312811 ps
CPU time 2.86 seconds
Started Aug 03 05:02:09 PM PDT 24
Finished Aug 03 05:02:12 PM PDT 24
Peak memory 216684 kb
Host smart-5df2d48b-91f7-4052-943a-9880da9380dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472597760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.472597760
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2893160486
Short name T816
Test name
Test status
Simulation time 38168394 ps
CPU time 0.75 seconds
Started Aug 03 05:02:08 PM PDT 24
Finished Aug 03 05:02:09 PM PDT 24
Peak memory 206368 kb
Host smart-e0b6a8bb-26f9-42c9-840c-94fb3f84e08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893160486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2893160486
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3433262009
Short name T587
Test name
Test status
Simulation time 3580194625 ps
CPU time 11.4 seconds
Started Aug 03 05:02:09 PM PDT 24
Finished Aug 03 05:02:21 PM PDT 24
Peak memory 241128 kb
Host smart-685f300e-521c-4f4a-98d5-6e939948c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433262009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3433262009
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.675216351
Short name T989
Test name
Test status
Simulation time 32114224 ps
CPU time 0.73 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:11 PM PDT 24
Peak memory 205312 kb
Host smart-5f332844-c558-44ca-b661-e853a4970e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675216351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.675216351
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1217932992
Short name T926
Test name
Test status
Simulation time 2295824905 ps
CPU time 6.65 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:18 PM PDT 24
Peak memory 225000 kb
Host smart-8b65c1e4-d4d9-4fec-b5e6-f62a96afcb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217932992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1217932992
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.912330510
Short name T967
Test name
Test status
Simulation time 17834780 ps
CPU time 0.76 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:12 PM PDT 24
Peak memory 206984 kb
Host smart-a5c105c4-64f9-42c2-b784-8dd2506a5034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912330510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.912330510
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3904088637
Short name T846
Test name
Test status
Simulation time 1865738234 ps
CPU time 32.18 seconds
Started Aug 03 05:02:08 PM PDT 24
Finished Aug 03 05:02:40 PM PDT 24
Peak memory 240504 kb
Host smart-27186015-5b0c-4219-a040-b1451f541257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904088637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3904088637
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3640838852
Short name T47
Test name
Test status
Simulation time 65643117002 ps
CPU time 274.13 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:06:50 PM PDT 24
Peak memory 256020 kb
Host smart-91dd461c-70cd-4fc1-aa8d-77ad7bcd9ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640838852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3640838852
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.728787894
Short name T382
Test name
Test status
Simulation time 5778638829 ps
CPU time 26.66 seconds
Started Aug 03 05:02:09 PM PDT 24
Finished Aug 03 05:02:36 PM PDT 24
Peak memory 224976 kb
Host smart-8cd0bcbe-8981-433d-8f4f-6deaa1bb6994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728787894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.728787894
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2289759420
Short name T243
Test name
Test status
Simulation time 31906442906 ps
CPU time 255.09 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:06:28 PM PDT 24
Peak memory 265924 kb
Host smart-d2379ad9-865d-4821-8d40-b1f76933a0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289759420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2289759420
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3950005084
Short name T263
Test name
Test status
Simulation time 779044945 ps
CPU time 9.61 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 224860 kb
Host smart-2211b8c9-4745-47f2-afd7-00034a14ef77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950005084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3950005084
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4014684882
Short name T860
Test name
Test status
Simulation time 1006472889 ps
CPU time 12.3 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:23 PM PDT 24
Peak memory 241056 kb
Host smart-d2b031dc-4f93-48d7-bf79-952ffeb000a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014684882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4014684882
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1503119428
Short name T444
Test name
Test status
Simulation time 6100564581 ps
CPU time 17.6 seconds
Started Aug 03 05:02:09 PM PDT 24
Finished Aug 03 05:02:27 PM PDT 24
Peak memory 224888 kb
Host smart-f6889bde-ddf1-480a-ac76-066e9e3882bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503119428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1503119428
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2937793137
Short name T994
Test name
Test status
Simulation time 646040079 ps
CPU time 4.53 seconds
Started Aug 03 05:02:10 PM PDT 24
Finished Aug 03 05:02:15 PM PDT 24
Peak memory 233132 kb
Host smart-5ce722f4-d807-43e6-9a96-7d4a5229973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937793137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2937793137
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3288488341
Short name T611
Test name
Test status
Simulation time 73761299 ps
CPU time 3.88 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:15 PM PDT 24
Peak memory 223664 kb
Host smart-2ab657aa-5b94-48d9-bd88-00561120711d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3288488341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3288488341
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1822582540
Short name T273
Test name
Test status
Simulation time 170591349446 ps
CPU time 451.5 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:09:44 PM PDT 24
Peak memory 257668 kb
Host smart-28ea400b-4458-4853-8aa5-50ce67da5c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822582540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1822582540
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3705475911
Short name T646
Test name
Test status
Simulation time 1911942765 ps
CPU time 9.26 seconds
Started Aug 03 05:02:10 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 216716 kb
Host smart-e502daaf-ccf0-490d-ade9-f0adb42fa2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705475911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3705475911
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.461796485
Short name T747
Test name
Test status
Simulation time 17332652054 ps
CPU time 5.31 seconds
Started Aug 03 05:02:09 PM PDT 24
Finished Aug 03 05:02:15 PM PDT 24
Peak memory 216644 kb
Host smart-a214cb8c-3ff2-4dcc-9904-0cab3b58a156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461796485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.461796485
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4125534893
Short name T476
Test name
Test status
Simulation time 20266719 ps
CPU time 1.02 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:17 PM PDT 24
Peak memory 206988 kb
Host smart-576be49e-7335-4601-82a2-71e6198a2b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125534893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4125534893
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.14558383
Short name T336
Test name
Test status
Simulation time 131278312 ps
CPU time 0.91 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:02:13 PM PDT 24
Peak memory 206348 kb
Host smart-7ea91c39-0bac-4370-bc54-25483dac4425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14558383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.14558383
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.605659749
Short name T513
Test name
Test status
Simulation time 54820713 ps
CPU time 0.75 seconds
Started Aug 03 05:02:17 PM PDT 24
Finished Aug 03 05:02:18 PM PDT 24
Peak memory 206132 kb
Host smart-7c67af60-cdfa-4160-b06f-15bb851f6c58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605659749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.605659749
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4007547101
Short name T1
Test name
Test status
Simulation time 353620256 ps
CPU time 3.81 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:15 PM PDT 24
Peak memory 224908 kb
Host smart-1c492efe-b247-4513-a119-40842cd135db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007547101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4007547101
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1255797794
Short name T127
Test name
Test status
Simulation time 24854313 ps
CPU time 0.85 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:12 PM PDT 24
Peak memory 207012 kb
Host smart-6b8ff7d2-a2f1-4cd7-9dac-a643f5859083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255797794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1255797794
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3053886502
Short name T636
Test name
Test status
Simulation time 6159981753 ps
CPU time 51.79 seconds
Started Aug 03 05:02:13 PM PDT 24
Finished Aug 03 05:03:05 PM PDT 24
Peak memory 249556 kb
Host smart-d39d25b1-8a81-49f3-8727-0c6ce399d350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053886502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3053886502
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2053061076
Short name T921
Test name
Test status
Simulation time 5710996602 ps
CPU time 34.19 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:46 PM PDT 24
Peak memory 223764 kb
Host smart-eb7b08d7-7bed-400a-9092-250142415f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053061076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2053061076
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2834056335
Short name T959
Test name
Test status
Simulation time 97894410872 ps
CPU time 100.93 seconds
Started Aug 03 05:02:13 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 257656 kb
Host smart-ea0233be-5cc9-4bf9-b6e1-932ed799b5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834056335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2834056335
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1426422997
Short name T219
Test name
Test status
Simulation time 2242817453 ps
CPU time 33.02 seconds
Started Aug 03 05:02:17 PM PDT 24
Finished Aug 03 05:02:51 PM PDT 24
Peak memory 239108 kb
Host smart-7439cb46-8f24-422e-b493-c836f11ca848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426422997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1426422997
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1240841640
Short name T176
Test name
Test status
Simulation time 5718726673 ps
CPU time 14.6 seconds
Started Aug 03 05:02:16 PM PDT 24
Finished Aug 03 05:02:36 PM PDT 24
Peak memory 233224 kb
Host smart-45ae3269-fd35-45ff-9ef3-d38038966d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240841640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1240841640
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4205289335
Short name T349
Test name
Test status
Simulation time 39641390 ps
CPU time 2.04 seconds
Started Aug 03 05:02:16 PM PDT 24
Finished Aug 03 05:02:18 PM PDT 24
Peak memory 224356 kb
Host smart-410587ea-ee29-427e-ab44-588d284e8632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205289335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4205289335
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3193068011
Short name T552
Test name
Test status
Simulation time 53452980 ps
CPU time 2.54 seconds
Started Aug 03 05:02:18 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 233156 kb
Host smart-dc5ba1c8-fea7-45ce-90c6-03b20fb3911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193068011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3193068011
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1364769323
Short name T182
Test name
Test status
Simulation time 203386859 ps
CPU time 4.03 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:02:16 PM PDT 24
Peak memory 233112 kb
Host smart-f49ddc0c-a134-4079-a43e-80e1d7644fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364769323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1364769323
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1933440370
Short name T905
Test name
Test status
Simulation time 1595666422 ps
CPU time 5.47 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:02:17 PM PDT 24
Peak memory 223452 kb
Host smart-ee08fe88-260a-40e8-8c78-eab69a3966df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1933440370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1933440370
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3667249959
Short name T17
Test name
Test status
Simulation time 95551630 ps
CPU time 1.05 seconds
Started Aug 03 05:02:11 PM PDT 24
Finished Aug 03 05:02:12 PM PDT 24
Peak memory 207256 kb
Host smart-01d2ca81-8fcc-4209-a81a-c07606da5007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667249959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3667249959
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2573855103
Short name T807
Test name
Test status
Simulation time 29815551298 ps
CPU time 23.13 seconds
Started Aug 03 05:02:12 PM PDT 24
Finished Aug 03 05:02:35 PM PDT 24
Peak memory 216716 kb
Host smart-517bbd6e-beac-4364-96dd-5c85f0905c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573855103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2573855103
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2521889458
Short name T450
Test name
Test status
Simulation time 6639089889 ps
CPU time 6.74 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:21 PM PDT 24
Peak memory 216692 kb
Host smart-644f5541-e7d2-4e42-a94b-dddf6680d3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521889458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2521889458
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1336301655
Short name T524
Test name
Test status
Simulation time 592058489 ps
CPU time 2.66 seconds
Started Aug 03 05:02:09 PM PDT 24
Finished Aug 03 05:02:12 PM PDT 24
Peak memory 216532 kb
Host smart-632760e6-d906-4bbe-b9c1-187ad5662ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336301655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1336301655
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3888523745
Short name T564
Test name
Test status
Simulation time 97966597 ps
CPU time 0.91 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:16 PM PDT 24
Peak memory 206352 kb
Host smart-7169c909-6db5-4f14-8612-8f0a7f498cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888523745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3888523745
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2608119838
Short name T379
Test name
Test status
Simulation time 34797630 ps
CPU time 2.38 seconds
Started Aug 03 05:02:16 PM PDT 24
Finished Aug 03 05:02:19 PM PDT 24
Peak memory 224640 kb
Host smart-f3ee9193-6348-4c9c-b1ae-4b81db73a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608119838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2608119838
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3559016038
Short name T239
Test name
Test status
Simulation time 68743143 ps
CPU time 2.66 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:18 PM PDT 24
Peak memory 233076 kb
Host smart-6d1a628b-6ed7-48bc-970c-93af139f656b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559016038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3559016038
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3088897469
Short name T563
Test name
Test status
Simulation time 18870074 ps
CPU time 0.79 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:16 PM PDT 24
Peak memory 207344 kb
Host smart-f74101bd-5749-4248-b98d-24b031e28f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088897469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3088897469
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2725619943
Short name T876
Test name
Test status
Simulation time 102020896461 ps
CPU time 111.57 seconds
Started Aug 03 05:02:16 PM PDT 24
Finished Aug 03 05:04:08 PM PDT 24
Peak memory 272124 kb
Host smart-649aabb6-3ffc-4d97-a22d-5303cbf120f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725619943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2725619943
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.4162880138
Short name T285
Test name
Test status
Simulation time 36011016925 ps
CPU time 92.16 seconds
Started Aug 03 05:02:18 PM PDT 24
Finished Aug 03 05:03:50 PM PDT 24
Peak memory 251540 kb
Host smart-0ee7515a-ecff-4441-b197-e5a7678dae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162880138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.4162880138
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3006460971
Short name T635
Test name
Test status
Simulation time 4093028986 ps
CPU time 8.85 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:02:23 PM PDT 24
Peak memory 233116 kb
Host smart-666adec2-2ca9-4142-bb26-03ca2f8dd31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006460971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3006460971
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1130228269
Short name T982
Test name
Test status
Simulation time 202955536046 ps
CPU time 378.88 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:08:33 PM PDT 24
Peak memory 254984 kb
Host smart-c23edbcb-932b-481e-92d6-4d7fe385dddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130228269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1130228269
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2104809829
Short name T516
Test name
Test status
Simulation time 1319039807 ps
CPU time 4.37 seconds
Started Aug 03 05:02:17 PM PDT 24
Finished Aug 03 05:02:21 PM PDT 24
Peak memory 233156 kb
Host smart-eee22a9e-bb8a-44e1-af0a-bfd80e9a362d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104809829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2104809829
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4246778876
Short name T782
Test name
Test status
Simulation time 330583188 ps
CPU time 5.72 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 233140 kb
Host smart-70abb2c3-bbe8-4a8f-8fc5-c5d5de571bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246778876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4246778876
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2306428313
Short name T291
Test name
Test status
Simulation time 2327258378 ps
CPU time 12.59 seconds
Started Aug 03 05:02:17 PM PDT 24
Finished Aug 03 05:02:30 PM PDT 24
Peak memory 233120 kb
Host smart-b0733fc5-6859-46e9-b216-24060901aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306428313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2306428313
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3204707838
Short name T224
Test name
Test status
Simulation time 12626579418 ps
CPU time 17.07 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:02:31 PM PDT 24
Peak memory 233244 kb
Host smart-a3e83728-0894-45fa-ad24-597089769261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204707838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3204707838
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1430221076
Short name T352
Test name
Test status
Simulation time 5373706255 ps
CPU time 12.52 seconds
Started Aug 03 05:02:16 PM PDT 24
Finished Aug 03 05:02:29 PM PDT 24
Peak memory 223620 kb
Host smart-9a4dd2d4-8ec4-4c98-86a3-18001bae467d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1430221076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1430221076
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3952883966
Short name T507
Test name
Test status
Simulation time 2581275100 ps
CPU time 18.03 seconds
Started Aug 03 05:02:17 PM PDT 24
Finished Aug 03 05:02:35 PM PDT 24
Peak memory 216876 kb
Host smart-be4b2504-b7d1-4108-9847-af1737405c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952883966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3952883966
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1858247325
Short name T765
Test name
Test status
Simulation time 42472687 ps
CPU time 0.72 seconds
Started Aug 03 05:02:17 PM PDT 24
Finished Aug 03 05:02:18 PM PDT 24
Peak memory 206024 kb
Host smart-fc5909aa-c9b9-4268-8fdf-0752312104d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858247325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1858247325
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3256234792
Short name T591
Test name
Test status
Simulation time 45967944 ps
CPU time 0.7 seconds
Started Aug 03 05:02:35 PM PDT 24
Finished Aug 03 05:02:36 PM PDT 24
Peak memory 205992 kb
Host smart-efd44efd-7704-4a3e-850e-d18c460ebb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256234792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3256234792
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1705054904
Short name T394
Test name
Test status
Simulation time 23711766 ps
CPU time 0.73 seconds
Started Aug 03 05:02:19 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 206364 kb
Host smart-06584494-b35f-4670-a6d9-f6b5e70e698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705054904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1705054904
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1059917452
Short name T558
Test name
Test status
Simulation time 672784145 ps
CPU time 7.28 seconds
Started Aug 03 05:02:13 PM PDT 24
Finished Aug 03 05:02:31 PM PDT 24
Peak memory 233268 kb
Host smart-d4fd264c-a280-493a-9d90-36d6d90be6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059917452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1059917452
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1224225502
Short name T882
Test name
Test status
Simulation time 14062970 ps
CPU time 0.72 seconds
Started Aug 03 05:02:19 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 205968 kb
Host smart-255490a8-716c-49a0-9aec-f92c3e76288e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224225502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1224225502
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1177257619
Short name T872
Test name
Test status
Simulation time 3183574512 ps
CPU time 16.62 seconds
Started Aug 03 05:02:27 PM PDT 24
Finished Aug 03 05:02:43 PM PDT 24
Peak memory 233192 kb
Host smart-a3559f7a-ae81-4140-bbcc-030282f25422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177257619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1177257619
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1139145562
Short name T373
Test name
Test status
Simulation time 64200277 ps
CPU time 0.74 seconds
Started Aug 03 05:02:27 PM PDT 24
Finished Aug 03 05:02:27 PM PDT 24
Peak memory 206236 kb
Host smart-8a038ec8-6025-4958-b932-e6eb5de4dd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139145562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1139145562
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3471334079
Short name T255
Test name
Test status
Simulation time 5432035739 ps
CPU time 50.2 seconds
Started Aug 03 05:02:35 PM PDT 24
Finished Aug 03 05:03:25 PM PDT 24
Peak memory 255756 kb
Host smart-996d6e82-e86d-4370-a468-f3bf93d5b965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471334079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3471334079
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.647818755
Short name T761
Test name
Test status
Simulation time 37170735153 ps
CPU time 165.64 seconds
Started Aug 03 05:02:24 PM PDT 24
Finished Aug 03 05:05:09 PM PDT 24
Peak memory 253904 kb
Host smart-88c85fb6-9f3e-48fa-87f1-84cd9882e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647818755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.647818755
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1282600681
Short name T595
Test name
Test status
Simulation time 201760826629 ps
CPU time 300.23 seconds
Started Aug 03 05:02:18 PM PDT 24
Finished Aug 03 05:07:19 PM PDT 24
Peak memory 269876 kb
Host smart-b83dcc6d-03d4-40f3-8381-8a9d790d6923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282600681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1282600681
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2398320160
Short name T340
Test name
Test status
Simulation time 75233930 ps
CPU time 2.43 seconds
Started Aug 03 05:02:18 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 224876 kb
Host smart-7b140ed9-1292-43ea-849a-1f3a51f9d996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398320160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2398320160
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2367638696
Short name T519
Test name
Test status
Simulation time 1189635972 ps
CPU time 17.56 seconds
Started Aug 03 05:02:19 PM PDT 24
Finished Aug 03 05:02:37 PM PDT 24
Peak memory 237380 kb
Host smart-a4b09278-bbd3-415d-8613-6f3959ec52d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367638696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2367638696
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1372120034
Short name T868
Test name
Test status
Simulation time 415661229 ps
CPU time 3.36 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:18 PM PDT 24
Peak memory 233108 kb
Host smart-c5ac5189-29dc-4e81-b5e2-c4c107c6d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372120034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1372120034
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.766281346
Short name T698
Test name
Test status
Simulation time 3487669982 ps
CPU time 38.68 seconds
Started Aug 03 05:02:42 PM PDT 24
Finished Aug 03 05:03:21 PM PDT 24
Peak memory 249564 kb
Host smart-e4399ad1-cccb-4a2f-8de9-f39b85cbfd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766281346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.766281346
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2012294675
Short name T736
Test name
Test status
Simulation time 168733887 ps
CPU time 2.74 seconds
Started Aug 03 05:02:18 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 232996 kb
Host smart-65e84387-7ef2-41b4-92d3-004de945a8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012294675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2012294675
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2994650678
Short name T895
Test name
Test status
Simulation time 2923589225 ps
CPU time 10.98 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:26 PM PDT 24
Peak memory 224972 kb
Host smart-d9f74dde-8201-4552-8b87-405fd12cae52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994650678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2994650678
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.354975903
Short name T385
Test name
Test status
Simulation time 941492060 ps
CPU time 5.7 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:21 PM PDT 24
Peak memory 223324 kb
Host smart-bcca8694-afea-4cb3-a830-148540249d76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=354975903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.354975903
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.378697316
Short name T890
Test name
Test status
Simulation time 225130666 ps
CPU time 1.02 seconds
Started Aug 03 05:02:18 PM PDT 24
Finished Aug 03 05:02:19 PM PDT 24
Peak memory 207148 kb
Host smart-cd1c2b3d-fd59-4dfe-ba4e-e28bf836bb64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378697316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.378697316
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4216854081
Short name T781
Test name
Test status
Simulation time 1466527297 ps
CPU time 22.76 seconds
Started Aug 03 05:02:15 PM PDT 24
Finished Aug 03 05:02:38 PM PDT 24
Peak memory 216592 kb
Host smart-9a621681-e57f-43cd-a2d9-f008622390ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216854081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4216854081
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.4291471614
Short name T540
Test name
Test status
Simulation time 1841704376 ps
CPU time 3.09 seconds
Started Aug 03 05:02:16 PM PDT 24
Finished Aug 03 05:02:19 PM PDT 24
Peak memory 216648 kb
Host smart-19597032-7031-46ab-a14b-87e62fa1aee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291471614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4291471614
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.420558005
Short name T337
Test name
Test status
Simulation time 105965195 ps
CPU time 0.95 seconds
Started Aug 03 05:02:18 PM PDT 24
Finished Aug 03 05:02:19 PM PDT 24
Peak memory 207264 kb
Host smart-55c2dcfd-1ebb-496c-a304-fb2e60bc0d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420558005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.420558005
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3562401184
Short name T644
Test name
Test status
Simulation time 20287676 ps
CPU time 0.74 seconds
Started Aug 03 05:02:16 PM PDT 24
Finished Aug 03 05:02:16 PM PDT 24
Peak memory 206328 kb
Host smart-9a6ac939-c641-49a3-b38e-516f5dfc692d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562401184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3562401184
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1246600252
Short name T653
Test name
Test status
Simulation time 41049204326 ps
CPU time 33.78 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:02:48 PM PDT 24
Peak memory 241236 kb
Host smart-67053599-000e-4a5a-9f99-7a363264cecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246600252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1246600252
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3142950728
Short name T995
Test name
Test status
Simulation time 56501135 ps
CPU time 0.73 seconds
Started Aug 03 05:02:20 PM PDT 24
Finished Aug 03 05:02:21 PM PDT 24
Peak memory 205276 kb
Host smart-f9397781-33d3-40b3-bad6-cfc06c5b762f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142950728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3142950728
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.635223841
Short name T364
Test name
Test status
Simulation time 7986108536 ps
CPU time 16.69 seconds
Started Aug 03 05:02:16 PM PDT 24
Finished Aug 03 05:02:33 PM PDT 24
Peak memory 224836 kb
Host smart-84115e91-655e-41a8-8758-efff789b79f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635223841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.635223841
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2393116962
Short name T690
Test name
Test status
Simulation time 36522555 ps
CPU time 0.78 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:02:15 PM PDT 24
Peak memory 206272 kb
Host smart-37048d89-65a0-4dd4-932f-715ff106ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393116962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2393116962
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2479268238
Short name T183
Test name
Test status
Simulation time 21193757256 ps
CPU time 205.15 seconds
Started Aug 03 05:02:13 PM PDT 24
Finished Aug 03 05:05:39 PM PDT 24
Peak memory 265912 kb
Host smart-f7812f5f-fb88-4b4f-bfd9-0c06347ca269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479268238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2479268238
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1964920869
Short name T581
Test name
Test status
Simulation time 1429933747 ps
CPU time 20.09 seconds
Started Aug 03 05:02:26 PM PDT 24
Finished Aug 03 05:02:46 PM PDT 24
Peak memory 224952 kb
Host smart-ca0b73c0-7988-42ec-88e3-6fd2021b0c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964920869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1964920869
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1649579200
Short name T214
Test name
Test status
Simulation time 1385463945 ps
CPU time 9.46 seconds
Started Aug 03 05:02:13 PM PDT 24
Finished Aug 03 05:02:22 PM PDT 24
Peak memory 239828 kb
Host smart-95878530-116e-4326-af1d-089eb7386d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649579200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1649579200
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2744821732
Short name T701
Test name
Test status
Simulation time 4392169663 ps
CPU time 20.72 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:02:35 PM PDT 24
Peak memory 224916 kb
Host smart-3d0d4394-a4f3-4954-ac04-7f77a885a931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744821732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2744821732
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1595074007
Short name T236
Test name
Test status
Simulation time 1461934256 ps
CPU time 21.66 seconds
Started Aug 03 05:02:17 PM PDT 24
Finished Aug 03 05:02:39 PM PDT 24
Peak memory 249908 kb
Host smart-c6f0f9b8-6918-4aa0-a021-1fa9ca01e922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595074007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1595074007
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2830912513
Short name T665
Test name
Test status
Simulation time 8051634437 ps
CPU time 16.7 seconds
Started Aug 03 05:02:19 PM PDT 24
Finished Aug 03 05:02:36 PM PDT 24
Peak memory 241220 kb
Host smart-392f3bfc-08a1-4cd9-97e7-a3b798812e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830912513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2830912513
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2621269218
Short name T15
Test name
Test status
Simulation time 721718544 ps
CPU time 7.05 seconds
Started Aug 03 05:02:20 PM PDT 24
Finished Aug 03 05:02:27 PM PDT 24
Peak memory 233132 kb
Host smart-727cdf0e-0e08-4007-9337-69ed1d3bdc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621269218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2621269218
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1757529245
Short name T141
Test name
Test status
Simulation time 263504171 ps
CPU time 4.4 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:02:19 PM PDT 24
Peak memory 223336 kb
Host smart-d1fcb628-bb01-4d57-9184-4d1578788ed8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1757529245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1757529245
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4033864710
Short name T138
Test name
Test status
Simulation time 160998529849 ps
CPU time 367.46 seconds
Started Aug 03 05:02:38 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 249988 kb
Host smart-fd7e19cc-cf24-40df-91bf-9cfcfbd7df12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033864710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4033864710
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1983134425
Short name T435
Test name
Test status
Simulation time 79711855 ps
CPU time 1.88 seconds
Started Aug 03 05:02:16 PM PDT 24
Finished Aug 03 05:02:18 PM PDT 24
Peak memory 217684 kb
Host smart-f733bb14-73f8-417d-bf1a-ef5c9f5603d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983134425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1983134425
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3276647075
Short name T362
Test name
Test status
Simulation time 15656998314 ps
CPU time 10.68 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:02:25 PM PDT 24
Peak memory 216772 kb
Host smart-c66cbf6e-a222-4476-be9f-78508b731c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276647075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3276647075
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2236887956
Short name T446
Test name
Test status
Simulation time 186534033 ps
CPU time 2.31 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:02:16 PM PDT 24
Peak memory 216648 kb
Host smart-b0af24c2-5eb1-4baf-a9db-0dd1edbeb889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236887956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2236887956
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2012654050
Short name T83
Test name
Test status
Simulation time 33881103 ps
CPU time 0.81 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:02:15 PM PDT 24
Peak memory 206340 kb
Host smart-561806fc-ca53-458b-b10b-3a2fb0b2e78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012654050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2012654050
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.217373136
Short name T545
Test name
Test status
Simulation time 3457776930 ps
CPU time 11.05 seconds
Started Aug 03 05:02:17 PM PDT 24
Finished Aug 03 05:02:28 PM PDT 24
Peak memory 241264 kb
Host smart-00452227-1d1e-4f0b-b5dd-2608d62e391f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217373136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.217373136
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3910803636
Short name T770
Test name
Test status
Simulation time 34445761 ps
CPU time 0.73 seconds
Started Aug 03 05:02:27 PM PDT 24
Finished Aug 03 05:02:28 PM PDT 24
Peak memory 205868 kb
Host smart-0e2097f4-d985-40ad-86d5-40c537872db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910803636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3910803636
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2212542760
Short name T774
Test name
Test status
Simulation time 1404747476 ps
CPU time 16.92 seconds
Started Aug 03 05:02:16 PM PDT 24
Finished Aug 03 05:02:33 PM PDT 24
Peak memory 224852 kb
Host smart-3463324f-17f1-463b-b708-9dcd43ba58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212542760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2212542760
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3644032378
Short name T626
Test name
Test status
Simulation time 36003745 ps
CPU time 0.78 seconds
Started Aug 03 05:02:18 PM PDT 24
Finished Aug 03 05:02:19 PM PDT 24
Peak memory 206964 kb
Host smart-ef96fda2-96e3-4f89-959e-a6ee424d410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644032378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3644032378
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1628748689
Short name T855
Test name
Test status
Simulation time 4537203996 ps
CPU time 59.2 seconds
Started Aug 03 05:02:37 PM PDT 24
Finished Aug 03 05:03:37 PM PDT 24
Peak memory 253040 kb
Host smart-d0422cb6-7564-4a64-8c0a-80f5ad461054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628748689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1628748689
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1251159481
Short name T927
Test name
Test status
Simulation time 8492683518 ps
CPU time 13.49 seconds
Started Aug 03 05:02:31 PM PDT 24
Finished Aug 03 05:02:44 PM PDT 24
Peak memory 239100 kb
Host smart-b4d104b1-cfdf-40bd-814a-83dcf151a11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251159481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1251159481
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.674870573
Short name T203
Test name
Test status
Simulation time 6275552804 ps
CPU time 79.92 seconds
Started Aug 03 05:02:32 PM PDT 24
Finished Aug 03 05:03:52 PM PDT 24
Peak memory 256164 kb
Host smart-75b3accd-d9ce-4e59-aa53-29e96f7dfa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674870573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.674870573
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3663573444
Short name T617
Test name
Test status
Simulation time 449577591 ps
CPU time 5.77 seconds
Started Aug 03 05:02:14 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 224840 kb
Host smart-cd711652-53a1-48be-817b-f9f35143f7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663573444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3663573444
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3052972361
Short name T185
Test name
Test status
Simulation time 3801255698 ps
CPU time 51.95 seconds
Started Aug 03 05:02:20 PM PDT 24
Finished Aug 03 05:03:12 PM PDT 24
Peak memory 225012 kb
Host smart-648b359e-6397-47bf-b72a-5e17a37cef64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052972361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3052972361
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3084735734
Short name T630
Test name
Test status
Simulation time 101119346 ps
CPU time 2.39 seconds
Started Aug 03 05:02:20 PM PDT 24
Finished Aug 03 05:02:22 PM PDT 24
Peak memory 224580 kb
Host smart-8d12701d-f40b-49fa-bfa6-327806451a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084735734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3084735734
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3457348962
Short name T259
Test name
Test status
Simulation time 574228460 ps
CPU time 3.81 seconds
Started Aug 03 05:02:21 PM PDT 24
Finished Aug 03 05:02:25 PM PDT 24
Peak memory 225120 kb
Host smart-c0ea7a9c-5728-499c-a492-45a637875ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457348962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3457348962
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1054946422
Short name T772
Test name
Test status
Simulation time 476668824 ps
CPU time 6.05 seconds
Started Aug 03 05:02:38 PM PDT 24
Finished Aug 03 05:02:44 PM PDT 24
Peak memory 222552 kb
Host smart-c515d783-d4cb-4dfa-b8e7-5ae93529e468
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1054946422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1054946422
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2546440611
Short name T294
Test name
Test status
Simulation time 544357997781 ps
CPU time 366.88 seconds
Started Aug 03 05:02:26 PM PDT 24
Finished Aug 03 05:08:33 PM PDT 24
Peak memory 269304 kb
Host smart-e11ee728-fb5d-4919-8c91-28a23cf7904a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546440611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2546440611
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2757991856
Short name T702
Test name
Test status
Simulation time 3402999200 ps
CPU time 4.55 seconds
Started Aug 03 05:02:25 PM PDT 24
Finished Aug 03 05:02:30 PM PDT 24
Peak memory 216636 kb
Host smart-80f473f0-37b7-4172-a07f-2ee64a8bfd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757991856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2757991856
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2171264729
Short name T675
Test name
Test status
Simulation time 1080864118 ps
CPU time 5.28 seconds
Started Aug 03 05:02:18 PM PDT 24
Finished Aug 03 05:02:24 PM PDT 24
Peak memory 216596 kb
Host smart-77a679db-8ee7-43b8-b727-7fdbb117d207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171264729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2171264729
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3692811179
Short name T605
Test name
Test status
Simulation time 454397539 ps
CPU time 4.34 seconds
Started Aug 03 05:02:20 PM PDT 24
Finished Aug 03 05:02:24 PM PDT 24
Peak memory 216644 kb
Host smart-82198645-8da4-49d7-980e-ac97f7b94657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692811179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3692811179
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.167808707
Short name T778
Test name
Test status
Simulation time 29541126 ps
CPU time 0.7 seconds
Started Aug 03 05:02:21 PM PDT 24
Finished Aug 03 05:02:22 PM PDT 24
Peak memory 206324 kb
Host smart-e4308d6f-63b7-44b6-99fe-925b2bd58954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167808707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.167808707
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2430621023
Short name T649
Test name
Test status
Simulation time 5973393630 ps
CPU time 23.82 seconds
Started Aug 03 05:02:29 PM PDT 24
Finished Aug 03 05:02:53 PM PDT 24
Peak memory 249276 kb
Host smart-d322cc28-c806-4451-889b-016a6ae9cf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430621023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2430621023
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2652136984
Short name T622
Test name
Test status
Simulation time 18429245 ps
CPU time 0.7 seconds
Started Aug 03 05:02:24 PM PDT 24
Finished Aug 03 05:02:25 PM PDT 24
Peak memory 205820 kb
Host smart-72480ae4-0ff7-4373-865d-04169f66d971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652136984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2652136984
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1179749899
Short name T673
Test name
Test status
Simulation time 1203888505 ps
CPU time 3.67 seconds
Started Aug 03 05:02:41 PM PDT 24
Finished Aug 03 05:02:45 PM PDT 24
Peak memory 233064 kb
Host smart-0d5db71b-8dc4-416b-afd9-56190cd3c8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179749899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1179749899
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1532205687
Short name T344
Test name
Test status
Simulation time 162009443 ps
CPU time 0.75 seconds
Started Aug 03 05:02:38 PM PDT 24
Finished Aug 03 05:02:39 PM PDT 24
Peak memory 207300 kb
Host smart-1e66923a-6255-4715-ad9a-d92a01930567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532205687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1532205687
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3862348683
Short name T716
Test name
Test status
Simulation time 31236932181 ps
CPU time 43.91 seconds
Started Aug 03 05:02:20 PM PDT 24
Finished Aug 03 05:03:04 PM PDT 24
Peak memory 251072 kb
Host smart-81f29b74-d680-45fd-befa-cd1f01892e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862348683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3862348683
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1744609371
Short name T241
Test name
Test status
Simulation time 98529422061 ps
CPU time 279.66 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:07:29 PM PDT 24
Peak memory 257348 kb
Host smart-3a88a7af-29a6-4f8f-a7c7-5a8e51acbb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744609371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1744609371
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.143784158
Short name T918
Test name
Test status
Simulation time 13297895151 ps
CPU time 54.4 seconds
Started Aug 03 05:02:37 PM PDT 24
Finished Aug 03 05:03:31 PM PDT 24
Peak memory 249552 kb
Host smart-166a2914-869f-45c1-916a-572a16215ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143784158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.143784158
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2330062165
Short name T522
Test name
Test status
Simulation time 385558509 ps
CPU time 5.3 seconds
Started Aug 03 05:02:36 PM PDT 24
Finished Aug 03 05:02:42 PM PDT 24
Peak memory 249516 kb
Host smart-f60b0e92-3ca1-4671-9c0b-63626af84c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330062165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2330062165
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3779975849
Short name T494
Test name
Test status
Simulation time 5577611700 ps
CPU time 81.51 seconds
Started Aug 03 05:02:42 PM PDT 24
Finished Aug 03 05:04:03 PM PDT 24
Peak memory 257764 kb
Host smart-8ccf5888-f510-4a5b-a682-6d68d60233d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779975849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3779975849
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2350181516
Short name T218
Test name
Test status
Simulation time 45202875270 ps
CPU time 30.82 seconds
Started Aug 03 05:02:42 PM PDT 24
Finished Aug 03 05:03:12 PM PDT 24
Peak memory 221148 kb
Host smart-012f5fd4-3f31-4a9e-b90d-22a05f8fcc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350181516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2350181516
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2019160692
Short name T33
Test name
Test status
Simulation time 135099883 ps
CPU time 5.51 seconds
Started Aug 03 05:02:48 PM PDT 24
Finished Aug 03 05:02:54 PM PDT 24
Peak memory 224888 kb
Host smart-bcd52b4d-e18c-4142-9224-a8957d8bfd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019160692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2019160692
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3117011686
Short name T89
Test name
Test status
Simulation time 1285708727 ps
CPU time 4.84 seconds
Started Aug 03 05:02:22 PM PDT 24
Finished Aug 03 05:02:27 PM PDT 24
Peak memory 224856 kb
Host smart-1d097c16-6268-4955-871d-73050f7f9a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117011686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3117011686
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1337322191
Short name T932
Test name
Test status
Simulation time 338388958 ps
CPU time 4.64 seconds
Started Aug 03 05:02:22 PM PDT 24
Finished Aug 03 05:02:27 PM PDT 24
Peak memory 233096 kb
Host smart-2c4177ec-0b64-4101-b1b5-76959fd61e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337322191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1337322191
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2050496835
Short name T403
Test name
Test status
Simulation time 158602636 ps
CPU time 4.03 seconds
Started Aug 03 05:02:31 PM PDT 24
Finished Aug 03 05:02:35 PM PDT 24
Peak memory 222844 kb
Host smart-8a04a0dc-3502-4843-81b6-9046d07cd847
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2050496835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2050496835
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3612743
Short name T281
Test name
Test status
Simulation time 35272837433 ps
CPU time 225.02 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:06:34 PM PDT 24
Peak memory 264176 kb
Host smart-dba5f311-ec17-4387-ad8e-1057bfcf6285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_
all.3612743
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.913756608
Short name T732
Test name
Test status
Simulation time 1677262392 ps
CPU time 14.19 seconds
Started Aug 03 05:02:24 PM PDT 24
Finished Aug 03 05:02:38 PM PDT 24
Peak memory 216840 kb
Host smart-5c41a5c4-c68e-4c53-9e40-f41c69bfdf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913756608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.913756608
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4262635045
Short name T978
Test name
Test status
Simulation time 2403093775 ps
CPU time 7.57 seconds
Started Aug 03 05:02:37 PM PDT 24
Finished Aug 03 05:02:44 PM PDT 24
Peak memory 216668 kb
Host smart-91faecd6-0301-44fb-b354-888717e3a974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262635045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4262635045
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1542326700
Short name T984
Test name
Test status
Simulation time 46041685 ps
CPU time 1.2 seconds
Started Aug 03 05:02:43 PM PDT 24
Finished Aug 03 05:02:44 PM PDT 24
Peak memory 216668 kb
Host smart-b18a1782-5ba1-4791-b9b1-c93fbd961659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542326700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1542326700
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2420709185
Short name T359
Test name
Test status
Simulation time 81896884 ps
CPU time 0.73 seconds
Started Aug 03 05:02:42 PM PDT 24
Finished Aug 03 05:02:43 PM PDT 24
Peak memory 206296 kb
Host smart-8a3339ac-a51c-49ef-8e9e-0919ea265510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420709185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2420709185
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2099492098
Short name T867
Test name
Test status
Simulation time 712381196 ps
CPU time 3.9 seconds
Started Aug 03 05:02:40 PM PDT 24
Finished Aug 03 05:02:44 PM PDT 24
Peak memory 224868 kb
Host smart-dd7127d0-d756-4181-ad30-cdbbdcb44dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099492098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2099492098
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.492024117
Short name T406
Test name
Test status
Simulation time 23222677 ps
CPU time 0.73 seconds
Started Aug 03 05:02:26 PM PDT 24
Finished Aug 03 05:02:27 PM PDT 24
Peak memory 205792 kb
Host smart-fc4fe942-a104-425a-bf1b-5703fdd199fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492024117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.492024117
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3308404543
Short name T354
Test name
Test status
Simulation time 178045409 ps
CPU time 2.92 seconds
Started Aug 03 05:02:43 PM PDT 24
Finished Aug 03 05:02:46 PM PDT 24
Peak memory 233136 kb
Host smart-21fcac96-d7e3-40a5-b5c1-85d198b51f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308404543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3308404543
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2973425563
Short name T741
Test name
Test status
Simulation time 14515498 ps
CPU time 0.78 seconds
Started Aug 03 05:02:24 PM PDT 24
Finished Aug 03 05:02:25 PM PDT 24
Peak memory 207304 kb
Host smart-ec5f4f8e-53a5-487b-8419-3b69c7f68418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973425563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2973425563
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4175205602
Short name T178
Test name
Test status
Simulation time 837390263 ps
CPU time 14.07 seconds
Started Aug 03 05:02:32 PM PDT 24
Finished Aug 03 05:02:47 PM PDT 24
Peak memory 253284 kb
Host smart-ff94a1d4-0d2d-4ffb-bcd9-b6ae272c5b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175205602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4175205602
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4025172530
Short name T670
Test name
Test status
Simulation time 712181230445 ps
CPU time 325.68 seconds
Started Aug 03 05:02:38 PM PDT 24
Finished Aug 03 05:08:09 PM PDT 24
Peak memory 252384 kb
Host smart-a343353d-bd59-4c2c-bd17-6e4e99b00984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025172530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4025172530
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3372502030
Short name T14
Test name
Test status
Simulation time 6178882490 ps
CPU time 22.67 seconds
Started Aug 03 05:02:47 PM PDT 24
Finished Aug 03 05:03:10 PM PDT 24
Peak memory 238616 kb
Host smart-70c47bcd-01bd-4acc-abaf-38ad4de197c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372502030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3372502030
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3780043666
Short name T289
Test name
Test status
Simulation time 808320236 ps
CPU time 19.7 seconds
Started Aug 03 05:02:22 PM PDT 24
Finished Aug 03 05:02:42 PM PDT 24
Peak memory 249556 kb
Host smart-52a1d0c4-f448-4bc3-8839-6a2ec33029bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780043666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3780043666
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.716327476
Short name T920
Test name
Test status
Simulation time 551574832 ps
CPU time 5.14 seconds
Started Aug 03 05:02:24 PM PDT 24
Finished Aug 03 05:02:29 PM PDT 24
Peak memory 224876 kb
Host smart-6a26d8b3-ba4d-4378-882d-fb16916f8e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716327476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.716327476
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3850405278
Short name T210
Test name
Test status
Simulation time 1844374044 ps
CPU time 10.2 seconds
Started Aug 03 05:02:38 PM PDT 24
Finished Aug 03 05:02:48 PM PDT 24
Peak memory 233136 kb
Host smart-c2b82f4b-4964-46ef-9eb7-ec59895546ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850405278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3850405278
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.887445993
Short name T602
Test name
Test status
Simulation time 286066489 ps
CPU time 2.6 seconds
Started Aug 03 05:02:43 PM PDT 24
Finished Aug 03 05:02:46 PM PDT 24
Peak memory 224784 kb
Host smart-866af794-851e-4afd-9d79-76e86ff32d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887445993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.887445993
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2154641270
Short name T216
Test name
Test status
Simulation time 5507944530 ps
CPU time 7.39 seconds
Started Aug 03 05:02:25 PM PDT 24
Finished Aug 03 05:02:32 PM PDT 24
Peak memory 233180 kb
Host smart-f6d3847e-5164-4137-8aa7-76240791dc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154641270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2154641270
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4043214151
Short name T399
Test name
Test status
Simulation time 3268039587 ps
CPU time 4.83 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:02:53 PM PDT 24
Peak memory 219308 kb
Host smart-5a8de857-cd42-4b7d-9bd8-bb5a94576c44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4043214151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4043214151
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4117412159
Short name T32
Test name
Test status
Simulation time 44831264497 ps
CPU time 29.79 seconds
Started Aug 03 05:02:22 PM PDT 24
Finished Aug 03 05:02:51 PM PDT 24
Peak memory 217812 kb
Host smart-89e2ea02-dd2a-40ac-88be-cef2a8864d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117412159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4117412159
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1521838635
Short name T980
Test name
Test status
Simulation time 521095761 ps
CPU time 3.51 seconds
Started Aug 03 05:02:23 PM PDT 24
Finished Aug 03 05:02:26 PM PDT 24
Peak memory 216652 kb
Host smart-23a7fee5-9a0b-4128-8c33-e6897255a0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521838635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1521838635
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.518202373
Short name T763
Test name
Test status
Simulation time 98310816 ps
CPU time 2.4 seconds
Started Aug 03 05:02:24 PM PDT 24
Finished Aug 03 05:02:26 PM PDT 24
Peak memory 216692 kb
Host smart-88dd8e2e-3535-4cd6-865f-d3e33febdcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518202373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.518202373
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.694935805
Short name T704
Test name
Test status
Simulation time 20863351 ps
CPU time 0.81 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:02:49 PM PDT 24
Peak memory 206308 kb
Host smart-30717e34-2795-4536-855c-08bcc45ff5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694935805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.694935805
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1569710691
Short name T620
Test name
Test status
Simulation time 232309488 ps
CPU time 3 seconds
Started Aug 03 05:02:25 PM PDT 24
Finished Aug 03 05:02:28 PM PDT 24
Peak memory 233132 kb
Host smart-f197be03-b8ac-4e97-a29d-6895fe8448dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569710691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1569710691
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2904294537
Short name T60
Test name
Test status
Simulation time 85814652 ps
CPU time 0.73 seconds
Started Aug 03 05:01:35 PM PDT 24
Finished Aug 03 05:01:36 PM PDT 24
Peak memory 205876 kb
Host smart-f1d67b95-289b-4971-9cd6-8204b6796ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904294537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
904294537
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4221998276
Short name T983
Test name
Test status
Simulation time 271562015 ps
CPU time 3.58 seconds
Started Aug 03 05:01:38 PM PDT 24
Finished Aug 03 05:01:42 PM PDT 24
Peak memory 233104 kb
Host smart-f04bbde5-37aa-4742-ad66-59c876a105e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221998276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4221998276
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2744001536
Short name T824
Test name
Test status
Simulation time 13044879 ps
CPU time 0.76 seconds
Started Aug 03 05:01:35 PM PDT 24
Finished Aug 03 05:01:35 PM PDT 24
Peak memory 206996 kb
Host smart-a301c804-fe47-4161-8aac-859331665152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744001536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2744001536
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2529680891
Short name T966
Test name
Test status
Simulation time 32161771305 ps
CPU time 67.93 seconds
Started Aug 03 05:01:36 PM PDT 24
Finished Aug 03 05:02:44 PM PDT 24
Peak memory 238588 kb
Host smart-bf190dc5-9dff-46bb-ac60-bd274f0a0080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529680891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2529680891
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3322699400
Short name T377
Test name
Test status
Simulation time 46590449451 ps
CPU time 222.11 seconds
Started Aug 03 05:01:31 PM PDT 24
Finished Aug 03 05:05:13 PM PDT 24
Peak memory 249564 kb
Host smart-edfe4313-cf1a-4d49-95ce-72c4c0800f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322699400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3322699400
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1778785286
Short name T724
Test name
Test status
Simulation time 92105151 ps
CPU time 2.81 seconds
Started Aug 03 05:01:34 PM PDT 24
Finished Aug 03 05:01:37 PM PDT 24
Peak memory 233124 kb
Host smart-e8a778bc-9fe5-4e88-b455-c1a877433187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778785286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1778785286
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.4279375812
Short name T546
Test name
Test status
Simulation time 38348747185 ps
CPU time 105.12 seconds
Started Aug 03 05:01:50 PM PDT 24
Finished Aug 03 05:03:36 PM PDT 24
Peak memory 262576 kb
Host smart-86157429-63ee-462f-ba5d-c2329c400492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279375812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.4279375812
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.618353951
Short name T589
Test name
Test status
Simulation time 163574914 ps
CPU time 2.97 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:01:54 PM PDT 24
Peak memory 233160 kb
Host smart-39d93eb5-31f2-485c-b167-bf3dac4c9bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618353951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.618353951
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.640029250
Short name T599
Test name
Test status
Simulation time 2642785916 ps
CPU time 27.11 seconds
Started Aug 03 05:01:34 PM PDT 24
Finished Aug 03 05:02:01 PM PDT 24
Peak memory 224916 kb
Host smart-94b0ad4d-3c02-4592-99b0-59b8ce28e722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640029250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.640029250
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1611644292
Short name T268
Test name
Test status
Simulation time 2058761639 ps
CPU time 5.4 seconds
Started Aug 03 05:01:47 PM PDT 24
Finished Aug 03 05:01:52 PM PDT 24
Peak memory 224756 kb
Host smart-54512d17-a24f-436a-b5e5-9a6f16ed52e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611644292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1611644292
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1165373516
Short name T742
Test name
Test status
Simulation time 934469087 ps
CPU time 7.82 seconds
Started Aug 03 05:01:40 PM PDT 24
Finished Aug 03 05:01:48 PM PDT 24
Peak memory 240188 kb
Host smart-6cee4b68-9488-45b4-bcdc-f29ccb39b5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165373516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1165373516
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.557056824
Short name T618
Test name
Test status
Simulation time 8965643378 ps
CPU time 17.52 seconds
Started Aug 03 05:01:38 PM PDT 24
Finished Aug 03 05:01:55 PM PDT 24
Peak memory 220960 kb
Host smart-18bf2660-129c-40a1-977f-5fa4bcf214c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=557056824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.557056824
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2844894467
Short name T65
Test name
Test status
Simulation time 676729468 ps
CPU time 1.14 seconds
Started Aug 03 05:01:30 PM PDT 24
Finished Aug 03 05:01:31 PM PDT 24
Peak memory 236372 kb
Host smart-bd8384cb-b7a3-42b1-82fa-3553b83474e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844894467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2844894467
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3501229452
Short name T739
Test name
Test status
Simulation time 394987447403 ps
CPU time 245.84 seconds
Started Aug 03 05:01:32 PM PDT 24
Finished Aug 03 05:05:38 PM PDT 24
Peak memory 265924 kb
Host smart-9bbd608a-f533-4214-beff-39a55ccca600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501229452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3501229452
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2494486724
Short name T45
Test name
Test status
Simulation time 7036327296 ps
CPU time 43 seconds
Started Aug 03 05:01:32 PM PDT 24
Finished Aug 03 05:02:15 PM PDT 24
Peak memory 216684 kb
Host smart-38867d85-b7db-48bf-b774-e1db6ee6d133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494486724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2494486724
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1809864074
Short name T505
Test name
Test status
Simulation time 251756631 ps
CPU time 1.77 seconds
Started Aug 03 05:01:44 PM PDT 24
Finished Aug 03 05:01:46 PM PDT 24
Peak memory 208228 kb
Host smart-957bbf77-f6d7-4454-a749-5d0d192c667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809864074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1809864074
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4217050186
Short name T383
Test name
Test status
Simulation time 316182354 ps
CPU time 1.76 seconds
Started Aug 03 05:01:33 PM PDT 24
Finished Aug 03 05:01:35 PM PDT 24
Peak memory 216604 kb
Host smart-a644da3d-2757-4956-a97e-3dde692175a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217050186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4217050186
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3686803836
Short name T478
Test name
Test status
Simulation time 29457859 ps
CPU time 0.66 seconds
Started Aug 03 05:01:31 PM PDT 24
Finished Aug 03 05:01:32 PM PDT 24
Peak memory 206020 kb
Host smart-773e85f8-7ed8-4da5-8ea3-b1a4f25b0a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686803836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3686803836
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3383515644
Short name T225
Test name
Test status
Simulation time 525792100 ps
CPU time 3.39 seconds
Started Aug 03 05:01:34 PM PDT 24
Finished Aug 03 05:01:37 PM PDT 24
Peak memory 224804 kb
Host smart-6d9a1fc4-af82-44e0-8d24-bf48090c6b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383515644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3383515644
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.241931556
Short name T411
Test name
Test status
Simulation time 42781579 ps
CPU time 0.73 seconds
Started Aug 03 05:02:26 PM PDT 24
Finished Aug 03 05:02:27 PM PDT 24
Peak memory 205268 kb
Host smart-38fb2f3f-ad20-4f3d-926c-d355d91a562c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241931556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.241931556
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2041189542
Short name T262
Test name
Test status
Simulation time 336924633 ps
CPU time 3.64 seconds
Started Aug 03 05:02:28 PM PDT 24
Finished Aug 03 05:02:31 PM PDT 24
Peak memory 224888 kb
Host smart-25809f8b-dabf-427d-a6ba-11a1ab579a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041189542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2041189542
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2474119121
Short name T442
Test name
Test status
Simulation time 46936087 ps
CPU time 0.76 seconds
Started Aug 03 05:02:30 PM PDT 24
Finished Aug 03 05:02:32 PM PDT 24
Peak memory 206180 kb
Host smart-c46dd30a-3689-452d-99eb-777f77a46c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474119121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2474119121
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3376006363
Short name T278
Test name
Test status
Simulation time 58983042368 ps
CPU time 430.24 seconds
Started Aug 03 05:02:29 PM PDT 24
Finished Aug 03 05:09:39 PM PDT 24
Peak memory 256240 kb
Host smart-2c106018-9569-4cd4-90c4-5d4d38776c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376006363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3376006363
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2653221486
Short name T738
Test name
Test status
Simulation time 326098131922 ps
CPU time 227.68 seconds
Started Aug 03 05:02:43 PM PDT 24
Finished Aug 03 05:06:31 PM PDT 24
Peak memory 265800 kb
Host smart-231dcebb-5049-46d2-9a00-3a8c8eddf346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653221486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2653221486
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.407920921
Short name T686
Test name
Test status
Simulation time 11874751949 ps
CPU time 87.32 seconds
Started Aug 03 05:02:32 PM PDT 24
Finished Aug 03 05:03:59 PM PDT 24
Peak memory 263024 kb
Host smart-118598f4-c806-458f-af78-e7f98a22aef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407920921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.407920921
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1091024208
Short name T306
Test name
Test status
Simulation time 506782761 ps
CPU time 7.2 seconds
Started Aug 03 05:02:27 PM PDT 24
Finished Aug 03 05:02:34 PM PDT 24
Peak memory 241272 kb
Host smart-f9de10a8-e85d-4435-a345-77a5faeaf8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091024208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1091024208
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.734654470
Short name T922
Test name
Test status
Simulation time 14796348054 ps
CPU time 68.9 seconds
Started Aug 03 05:02:44 PM PDT 24
Finished Aug 03 05:03:53 PM PDT 24
Peak memory 257760 kb
Host smart-dd5fbffb-7307-4f96-8ce2-fccef2d015a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734654470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.734654470
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2493156136
Short name T857
Test name
Test status
Simulation time 164841656 ps
CPU time 4.25 seconds
Started Aug 03 05:02:31 PM PDT 24
Finished Aug 03 05:02:36 PM PDT 24
Peak memory 224904 kb
Host smart-9abd54c4-1092-4e40-a009-c5e7fa54605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493156136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2493156136
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4094686948
Short name T818
Test name
Test status
Simulation time 454240242 ps
CPU time 9.55 seconds
Started Aug 03 05:02:31 PM PDT 24
Finished Aug 03 05:02:40 PM PDT 24
Peak memory 233016 kb
Host smart-4bea3c75-824e-4abf-976e-352c09f4f969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094686948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4094686948
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2760547248
Short name T833
Test name
Test status
Simulation time 2259970265 ps
CPU time 9.78 seconds
Started Aug 03 05:02:32 PM PDT 24
Finished Aug 03 05:02:41 PM PDT 24
Peak memory 238112 kb
Host smart-507f2280-6b4d-4a05-93cc-b1b38b91f634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760547248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2760547248
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1273956701
Short name T668
Test name
Test status
Simulation time 106251374 ps
CPU time 2.27 seconds
Started Aug 03 05:02:46 PM PDT 24
Finished Aug 03 05:02:49 PM PDT 24
Peak memory 223964 kb
Host smart-338d064e-4222-4434-81b4-897c3d7524bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273956701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1273956701
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.869624093
Short name T998
Test name
Test status
Simulation time 2112380329 ps
CPU time 5.8 seconds
Started Aug 03 05:02:26 PM PDT 24
Finished Aug 03 05:02:32 PM PDT 24
Peak memory 222772 kb
Host smart-76dbb4a3-5bb6-48ab-b3ff-b16c6e6644b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=869624093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.869624093
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2145798170
Short name T19
Test name
Test status
Simulation time 1969704197 ps
CPU time 34.25 seconds
Started Aug 03 05:02:26 PM PDT 24
Finished Aug 03 05:03:00 PM PDT 24
Peak memory 249528 kb
Host smart-f45a1b7a-b764-4afa-a00d-80042a658951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145798170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2145798170
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4182675332
Short name T817
Test name
Test status
Simulation time 859646672 ps
CPU time 8.72 seconds
Started Aug 03 05:02:44 PM PDT 24
Finished Aug 03 05:02:53 PM PDT 24
Peak memory 216648 kb
Host smart-1708544e-c420-4ea3-922a-5bd45bbc517d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182675332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4182675332
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2656932994
Short name T384
Test name
Test status
Simulation time 1502115673 ps
CPU time 5.6 seconds
Started Aug 03 05:02:29 PM PDT 24
Finished Aug 03 05:02:35 PM PDT 24
Peak memory 216728 kb
Host smart-3a714e26-403f-448d-a0ea-ed7bdd4ab0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656932994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2656932994
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1543408175
Short name T388
Test name
Test status
Simulation time 336070247 ps
CPU time 3.24 seconds
Started Aug 03 05:02:45 PM PDT 24
Finished Aug 03 05:02:48 PM PDT 24
Peak memory 216568 kb
Host smart-98e167ff-7118-4315-a785-dfcff60590d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543408175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1543408175
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2603439123
Short name T537
Test name
Test status
Simulation time 88905733 ps
CPU time 0.78 seconds
Started Aug 03 05:02:26 PM PDT 24
Finished Aug 03 05:02:27 PM PDT 24
Peak memory 206344 kb
Host smart-0612022d-3add-4219-b439-77107e2005f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603439123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2603439123
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3514787387
Short name T240
Test name
Test status
Simulation time 10950618501 ps
CPU time 17.89 seconds
Started Aug 03 05:02:29 PM PDT 24
Finished Aug 03 05:02:47 PM PDT 24
Peak memory 225004 kb
Host smart-5eb6bbaa-7c68-44ce-b787-65523cbbc863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514787387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3514787387
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1844942753
Short name T848
Test name
Test status
Simulation time 23297522 ps
CPU time 0.75 seconds
Started Aug 03 05:02:36 PM PDT 24
Finished Aug 03 05:02:37 PM PDT 24
Peak memory 205824 kb
Host smart-8838b142-dc6e-4871-be10-f9ee40bc2f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844942753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1844942753
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2575802407
Short name T699
Test name
Test status
Simulation time 62184445 ps
CPU time 2.04 seconds
Started Aug 03 05:02:30 PM PDT 24
Finished Aug 03 05:02:32 PM PDT 24
Peak memory 224828 kb
Host smart-dbde5be0-fced-403a-b858-89fcbc151826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575802407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2575802407
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2051389570
Short name T947
Test name
Test status
Simulation time 32650303 ps
CPU time 0.78 seconds
Started Aug 03 05:02:31 PM PDT 24
Finished Aug 03 05:02:32 PM PDT 24
Peak memory 206948 kb
Host smart-fbc6fa72-721e-450a-b430-9176ac189bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051389570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2051389570
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1815019305
Short name T562
Test name
Test status
Simulation time 506319771 ps
CPU time 0.87 seconds
Started Aug 03 05:02:32 PM PDT 24
Finished Aug 03 05:02:33 PM PDT 24
Peak memory 216300 kb
Host smart-f87e0434-df65-4382-858d-821317e4a734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815019305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1815019305
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1898463024
Short name T134
Test name
Test status
Simulation time 5507118010 ps
CPU time 73.65 seconds
Started Aug 03 05:02:29 PM PDT 24
Finished Aug 03 05:03:43 PM PDT 24
Peak memory 261304 kb
Host smart-3b411991-31d5-4e63-a538-16d1bfd1f9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898463024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1898463024
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.827296055
Short name T50
Test name
Test status
Simulation time 16876912182 ps
CPU time 185.34 seconds
Started Aug 03 05:02:43 PM PDT 24
Finished Aug 03 05:05:48 PM PDT 24
Peak memory 266284 kb
Host smart-6b0b8f16-b39b-411e-bd7e-3dc42fed6852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827296055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.827296055
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3690156403
Short name T311
Test name
Test status
Simulation time 8253642508 ps
CPU time 30.93 seconds
Started Aug 03 05:02:30 PM PDT 24
Finished Aug 03 05:03:01 PM PDT 24
Peak memory 233232 kb
Host smart-d3ca5902-f0dc-42dd-a6cf-373ca162908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690156403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3690156403
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.733020757
Short name T610
Test name
Test status
Simulation time 1356386414 ps
CPU time 24.06 seconds
Started Aug 03 05:02:31 PM PDT 24
Finished Aug 03 05:02:56 PM PDT 24
Peak memory 249492 kb
Host smart-b1a13615-4c27-49a0-8501-67423bd6d2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733020757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.733020757
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.239349169
Short name T948
Test name
Test status
Simulation time 320285931 ps
CPU time 4.31 seconds
Started Aug 03 05:02:48 PM PDT 24
Finished Aug 03 05:02:53 PM PDT 24
Peak memory 233144 kb
Host smart-727d6a55-a217-4085-927d-34fe8946097b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239349169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.239349169
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.102609383
Short name T405
Test name
Test status
Simulation time 200748264 ps
CPU time 5.7 seconds
Started Aug 03 05:02:29 PM PDT 24
Finished Aug 03 05:02:34 PM PDT 24
Peak memory 240400 kb
Host smart-004aca0d-5b30-4ebb-a676-68730b6319fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102609383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.102609383
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1839342959
Short name T179
Test name
Test status
Simulation time 4371343727 ps
CPU time 14.05 seconds
Started Aug 03 05:02:32 PM PDT 24
Finished Aug 03 05:02:46 PM PDT 24
Peak memory 224940 kb
Host smart-54d93324-dd5d-4028-af0b-83067068db28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839342959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1839342959
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2133085361
Short name T235
Test name
Test status
Simulation time 174022631 ps
CPU time 3.74 seconds
Started Aug 03 05:02:35 PM PDT 24
Finished Aug 03 05:02:39 PM PDT 24
Peak memory 233132 kb
Host smart-1f0d29d7-c9e8-457d-aa75-2b11f880290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133085361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2133085361
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.4044067006
Short name T954
Test name
Test status
Simulation time 2695481258 ps
CPU time 10.87 seconds
Started Aug 03 05:02:30 PM PDT 24
Finished Aug 03 05:02:43 PM PDT 24
Peak memory 223436 kb
Host smart-e7914252-dac4-460d-85a7-6578547d8e76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4044067006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.4044067006
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1592976796
Short name T917
Test name
Test status
Simulation time 35721835859 ps
CPU time 342.71 seconds
Started Aug 03 05:02:30 PM PDT 24
Finished Aug 03 05:08:12 PM PDT 24
Peak memory 273832 kb
Host smart-5d812c1c-f85f-4ee5-b692-aa198b0e8cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592976796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1592976796
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.371197953
Short name T897
Test name
Test status
Simulation time 999531004 ps
CPU time 5.41 seconds
Started Aug 03 05:02:31 PM PDT 24
Finished Aug 03 05:02:36 PM PDT 24
Peak memory 216652 kb
Host smart-d356ec5d-46c1-4478-8ed5-dc044e66fa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371197953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.371197953
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.999927509
Short name T407
Test name
Test status
Simulation time 5186924576 ps
CPU time 9.15 seconds
Started Aug 03 05:02:29 PM PDT 24
Finished Aug 03 05:02:38 PM PDT 24
Peak memory 216768 kb
Host smart-433b3442-d8bf-4429-b7dd-ca7ab726d53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999927509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.999927509
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1836439171
Short name T409
Test name
Test status
Simulation time 165953871 ps
CPU time 1.64 seconds
Started Aug 03 05:02:48 PM PDT 24
Finished Aug 03 05:02:49 PM PDT 24
Peak memory 216624 kb
Host smart-eda5f6b5-5081-4a56-a10e-70e6a213963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836439171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1836439171
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1378488772
Short name T425
Test name
Test status
Simulation time 259101322 ps
CPU time 0.9 seconds
Started Aug 03 05:02:47 PM PDT 24
Finished Aug 03 05:02:48 PM PDT 24
Peak memory 206356 kb
Host smart-40c774f1-b7aa-412a-8713-7a1a3357722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378488772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1378488772
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4084624673
Short name T463
Test name
Test status
Simulation time 155196929 ps
CPU time 2.2 seconds
Started Aug 03 05:02:32 PM PDT 24
Finished Aug 03 05:02:35 PM PDT 24
Peak memory 234508 kb
Host smart-23e60706-442c-4a5d-a5d0-85c381b60b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084624673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4084624673
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.249930998
Short name T461
Test name
Test status
Simulation time 14582380 ps
CPU time 0.71 seconds
Started Aug 03 05:02:47 PM PDT 24
Finished Aug 03 05:02:48 PM PDT 24
Peak memory 206140 kb
Host smart-e28bc4f0-6450-4e96-b740-9643f1948552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249930998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.249930998
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2057791409
Short name T222
Test name
Test status
Simulation time 2807505422 ps
CPU time 12.5 seconds
Started Aug 03 05:02:35 PM PDT 24
Finished Aug 03 05:02:48 PM PDT 24
Peak memory 233136 kb
Host smart-44894f63-fa4f-4ea3-8695-f64a74cd0973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057791409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2057791409
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.868929933
Short name T509
Test name
Test status
Simulation time 55569308 ps
CPU time 0.75 seconds
Started Aug 03 05:02:40 PM PDT 24
Finished Aug 03 05:02:41 PM PDT 24
Peak memory 205916 kb
Host smart-93752338-5dec-4cd6-9e2d-2c172b84b272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868929933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.868929933
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3367700826
Short name T78
Test name
Test status
Simulation time 21313275457 ps
CPU time 179.75 seconds
Started Aug 03 05:02:54 PM PDT 24
Finished Aug 03 05:05:54 PM PDT 24
Peak memory 269956 kb
Host smart-671c096d-dbf3-4705-822e-e91028298038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367700826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3367700826
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3081395814
Short name T323
Test name
Test status
Simulation time 3624896115 ps
CPU time 26.28 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:03:15 PM PDT 24
Peak memory 217952 kb
Host smart-efcd6f51-d6e9-43f3-9621-99e2178647e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081395814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3081395814
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2091098145
Short name T191
Test name
Test status
Simulation time 58992800334 ps
CPU time 165.84 seconds
Started Aug 03 05:02:32 PM PDT 24
Finished Aug 03 05:05:18 PM PDT 24
Peak memory 249628 kb
Host smart-4d513467-0164-4b06-a9d3-a6fa09adaa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091098145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2091098145
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.629199839
Short name T401
Test name
Test status
Simulation time 3323738634 ps
CPU time 49.61 seconds
Started Aug 03 05:02:44 PM PDT 24
Finished Aug 03 05:03:34 PM PDT 24
Peak memory 227220 kb
Host smart-011ed289-fee7-4744-85c2-faa1efc83574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629199839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.629199839
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1438563898
Short name T431
Test name
Test status
Simulation time 10320419865 ps
CPU time 74.72 seconds
Started Aug 03 05:02:35 PM PDT 24
Finished Aug 03 05:03:50 PM PDT 24
Peak memory 254948 kb
Host smart-ea3c0df0-10fc-4944-b25c-2c2863270896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438563898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1438563898
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.178481615
Short name T539
Test name
Test status
Simulation time 73124009 ps
CPU time 3.1 seconds
Started Aug 03 05:02:35 PM PDT 24
Finished Aug 03 05:02:38 PM PDT 24
Peak memory 233164 kb
Host smart-937b6dfa-14f7-4953-ac4a-f6d7947d381b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178481615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.178481615
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.782897019
Short name T820
Test name
Test status
Simulation time 408828203 ps
CPU time 6.4 seconds
Started Aug 03 05:02:39 PM PDT 24
Finished Aug 03 05:02:46 PM PDT 24
Peak memory 224932 kb
Host smart-92259e84-ea51-451a-b9f8-035733396b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782897019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.782897019
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3500116318
Short name T654
Test name
Test status
Simulation time 3552657914 ps
CPU time 13.77 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:03:03 PM PDT 24
Peak memory 233152 kb
Host smart-7843e104-48ca-4389-b93b-dcbc8c3a79a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500116318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3500116318
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3452836623
Short name T712
Test name
Test status
Simulation time 67128921 ps
CPU time 2.13 seconds
Started Aug 03 05:02:38 PM PDT 24
Finished Aug 03 05:02:40 PM PDT 24
Peak memory 232656 kb
Host smart-91d3f662-b3f7-4aa0-9ca7-75433afb5021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452836623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3452836623
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2478970608
Short name T404
Test name
Test status
Simulation time 2268517920 ps
CPU time 12.79 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:03:08 PM PDT 24
Peak memory 220852 kb
Host smart-2b11b7dc-4bda-4678-bc05-a167cfa089f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2478970608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2478970608
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1850149195
Short name T819
Test name
Test status
Simulation time 97685121 ps
CPU time 1.14 seconds
Started Aug 03 05:02:40 PM PDT 24
Finished Aug 03 05:02:41 PM PDT 24
Peak memory 207464 kb
Host smart-ed527e15-98ad-447d-a51d-71363523929e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850149195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1850149195
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2535446562
Short name T314
Test name
Test status
Simulation time 7013090864 ps
CPU time 15.86 seconds
Started Aug 03 05:02:32 PM PDT 24
Finished Aug 03 05:02:48 PM PDT 24
Peak memory 216664 kb
Host smart-e384b335-c2f3-4875-a815-2015bd620beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535446562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2535446562
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2747183784
Short name T588
Test name
Test status
Simulation time 2089836339 ps
CPU time 4.23 seconds
Started Aug 03 05:02:32 PM PDT 24
Finished Aug 03 05:02:36 PM PDT 24
Peak memory 216552 kb
Host smart-d5bfb019-cac3-4108-97a4-5bfe56b8c1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747183784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2747183784
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2171153797
Short name T614
Test name
Test status
Simulation time 26344067 ps
CPU time 0.8 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:02:50 PM PDT 24
Peak memory 207340 kb
Host smart-9e107bf2-d5c8-4fb2-83f8-2bb6c846af5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171153797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2171153797
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.970106779
Short name T1000
Test name
Test status
Simulation time 20119091 ps
CPU time 0.76 seconds
Started Aug 03 05:02:46 PM PDT 24
Finished Aug 03 05:02:47 PM PDT 24
Peak memory 206360 kb
Host smart-56a88dcb-c7b8-4062-831b-215f1ec6566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970106779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.970106779
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2587709669
Short name T531
Test name
Test status
Simulation time 2064500783 ps
CPU time 13 seconds
Started Aug 03 05:02:35 PM PDT 24
Finished Aug 03 05:02:48 PM PDT 24
Peak memory 241292 kb
Host smart-b649247a-02dc-416b-964e-ff43ce7e8636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587709669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2587709669
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.369623400
Short name T615
Test name
Test status
Simulation time 13713746 ps
CPU time 0.71 seconds
Started Aug 03 05:02:34 PM PDT 24
Finished Aug 03 05:02:35 PM PDT 24
Peak memory 205796 kb
Host smart-f4807f56-7cfe-40a3-a6dd-ba51bad8699e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369623400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.369623400
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3203895488
Short name T258
Test name
Test status
Simulation time 7083198518 ps
CPU time 18.54 seconds
Started Aug 03 05:02:38 PM PDT 24
Finished Aug 03 05:02:57 PM PDT 24
Peak memory 233140 kb
Host smart-6129f883-113e-4e52-adbe-99e77a75b7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203895488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3203895488
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1166090425
Short name T57
Test name
Test status
Simulation time 17209590 ps
CPU time 0.77 seconds
Started Aug 03 05:02:47 PM PDT 24
Finished Aug 03 05:02:47 PM PDT 24
Peak memory 207256 kb
Host smart-f27c924f-9ccc-4c41-938f-3aaac5c5659d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166090425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1166090425
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3676654896
Short name T523
Test name
Test status
Simulation time 16523794 ps
CPU time 0.79 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:02:50 PM PDT 24
Peak memory 216024 kb
Host smart-ca9b3458-4fab-4362-88ed-5676ea0b579d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676654896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3676654896
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3560209674
Short name T916
Test name
Test status
Simulation time 722717977 ps
CPU time 13.98 seconds
Started Aug 03 05:02:48 PM PDT 24
Finished Aug 03 05:03:02 PM PDT 24
Peak memory 222944 kb
Host smart-ac485093-0dc3-44bd-9be2-60c741ffc6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560209674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3560209674
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1243256166
Short name T309
Test name
Test status
Simulation time 163133572 ps
CPU time 8.28 seconds
Started Aug 03 05:02:44 PM PDT 24
Finished Aug 03 05:02:52 PM PDT 24
Peak memory 233132 kb
Host smart-a1343138-57ad-4f15-bdc0-875a35860abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243256166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1243256166
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.978978643
Short name T87
Test name
Test status
Simulation time 185188130809 ps
CPU time 121.45 seconds
Started Aug 03 05:02:36 PM PDT 24
Finished Aug 03 05:04:37 PM PDT 24
Peak memory 250324 kb
Host smart-5f4e12ce-999e-4f0d-8d6d-d5b0527d77c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978978643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.978978643
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2556672706
Short name T779
Test name
Test status
Simulation time 563295582 ps
CPU time 3.74 seconds
Started Aug 03 05:02:33 PM PDT 24
Finished Aug 03 05:02:37 PM PDT 24
Peak memory 224844 kb
Host smart-e6350ba1-cd47-4d36-8b98-43cb1e2b283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556672706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2556672706
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1418217960
Short name T666
Test name
Test status
Simulation time 2350586209 ps
CPU time 24.25 seconds
Started Aug 03 05:02:34 PM PDT 24
Finished Aug 03 05:02:58 PM PDT 24
Peak memory 224908 kb
Host smart-51234741-9316-4d46-a6c1-36e432c747c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418217960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1418217960
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2116814465
Short name T261
Test name
Test status
Simulation time 1275095932 ps
CPU time 5.98 seconds
Started Aug 03 05:02:47 PM PDT 24
Finished Aug 03 05:02:53 PM PDT 24
Peak memory 233000 kb
Host smart-73918e34-9f75-4c08-b447-444c6089fcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116814465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2116814465
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.272247822
Short name T449
Test name
Test status
Simulation time 864094511 ps
CPU time 3.62 seconds
Started Aug 03 05:02:33 PM PDT 24
Finished Aug 03 05:02:37 PM PDT 24
Peak memory 233120 kb
Host smart-dc891579-7db0-452b-98cc-78c4e9da62ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272247822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.272247822
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3482163608
Short name T428
Test name
Test status
Simulation time 2290750385 ps
CPU time 6.9 seconds
Started Aug 03 05:02:40 PM PDT 24
Finished Aug 03 05:02:47 PM PDT 24
Peak memory 220996 kb
Host smart-f2177970-09a7-4bee-a2b0-59a726697ae1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482163608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3482163608
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3815171852
Short name T322
Test name
Test status
Simulation time 17966992715 ps
CPU time 170.85 seconds
Started Aug 03 05:02:34 PM PDT 24
Finished Aug 03 05:05:25 PM PDT 24
Peak memory 256980 kb
Host smart-f540d440-2aa7-48a2-9184-dd727d420a22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815171852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3815171852
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.307002895
Short name T574
Test name
Test status
Simulation time 7135228535 ps
CPU time 17.39 seconds
Started Aug 03 05:02:38 PM PDT 24
Finished Aug 03 05:02:56 PM PDT 24
Peak memory 216716 kb
Host smart-165631b5-5b6e-46f8-8b83-86bda9f73695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307002895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.307002895
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3867652137
Short name T866
Test name
Test status
Simulation time 2191683546 ps
CPU time 4.24 seconds
Started Aug 03 05:02:47 PM PDT 24
Finished Aug 03 05:02:51 PM PDT 24
Peak memory 216700 kb
Host smart-3687d3fa-a2b2-4090-9bc8-7c38a52e03f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867652137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3867652137
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1146194428
Short name T358
Test name
Test status
Simulation time 110623924 ps
CPU time 1.74 seconds
Started Aug 03 05:02:50 PM PDT 24
Finished Aug 03 05:02:51 PM PDT 24
Peak memory 216656 kb
Host smart-5b9ab0bc-3ed4-4cf9-8ab2-ffacffea19ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146194428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1146194428
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2396545495
Short name T733
Test name
Test status
Simulation time 78269596 ps
CPU time 0.82 seconds
Started Aug 03 05:02:54 PM PDT 24
Finished Aug 03 05:02:55 PM PDT 24
Peak memory 206356 kb
Host smart-b6147c0d-58ce-41f0-ba4b-87fea53ec5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396545495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2396545495
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.964891401
Short name T1003
Test name
Test status
Simulation time 7289275940 ps
CPU time 8.46 seconds
Started Aug 03 05:02:45 PM PDT 24
Finished Aug 03 05:02:54 PM PDT 24
Peak memory 224884 kb
Host smart-67230ffb-45c0-4ee0-91d8-0bc722f03338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964891401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.964891401
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2760140904
Short name T339
Test name
Test status
Simulation time 43117374 ps
CPU time 0.72 seconds
Started Aug 03 05:02:43 PM PDT 24
Finished Aug 03 05:02:44 PM PDT 24
Peak memory 205244 kb
Host smart-85218567-e9ae-40fa-8901-c80a56b3ba0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760140904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2760140904
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.593230399
Short name T553
Test name
Test status
Simulation time 289484239 ps
CPU time 2.51 seconds
Started Aug 03 05:02:51 PM PDT 24
Finished Aug 03 05:02:54 PM PDT 24
Peak memory 224860 kb
Host smart-8147e116-58a4-405b-a235-cddae219035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593230399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.593230399
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3912087674
Short name T935
Test name
Test status
Simulation time 81059884 ps
CPU time 0.82 seconds
Started Aug 03 05:02:39 PM PDT 24
Finished Aug 03 05:02:39 PM PDT 24
Peak memory 206964 kb
Host smart-456e84eb-5e68-46e5-9ead-14763ff05b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912087674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3912087674
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.490919813
Short name T791
Test name
Test status
Simulation time 11866632175 ps
CPU time 62.31 seconds
Started Aug 03 05:02:50 PM PDT 24
Finished Aug 03 05:03:52 PM PDT 24
Peak memory 264612 kb
Host smart-27799fe0-6c92-454e-9161-a266899ff076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490919813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.490919813
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4049578031
Short name T242
Test name
Test status
Simulation time 30538655448 ps
CPU time 298.17 seconds
Started Aug 03 05:02:41 PM PDT 24
Finished Aug 03 05:07:39 PM PDT 24
Peak memory 257756 kb
Host smart-7480705d-3119-4a88-822d-aecfabbbd5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049578031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4049578031
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1851153164
Short name T308
Test name
Test status
Simulation time 695347719 ps
CPU time 11.59 seconds
Started Aug 03 05:02:50 PM PDT 24
Finished Aug 03 05:03:01 PM PDT 24
Peak memory 249424 kb
Host smart-2525e2c4-90f1-4e51-bf69-5e5ae4fa534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851153164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1851153164
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2179547508
Short name T288
Test name
Test status
Simulation time 39854016747 ps
CPU time 279.27 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:07:28 PM PDT 24
Peak memory 255140 kb
Host smart-039865f7-f594-47f3-8dad-e3a86a039e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179547508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2179547508
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1394827713
Short name T194
Test name
Test status
Simulation time 4744310067 ps
CPU time 12.86 seconds
Started Aug 03 05:02:41 PM PDT 24
Finished Aug 03 05:02:54 PM PDT 24
Peak memory 233196 kb
Host smart-6339ef51-657d-46dc-a189-00c35ff86d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394827713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1394827713
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.784322976
Short name T683
Test name
Test status
Simulation time 1609220937 ps
CPU time 21.68 seconds
Started Aug 03 05:02:41 PM PDT 24
Finished Aug 03 05:03:02 PM PDT 24
Peak memory 249196 kb
Host smart-7d457a4d-4e5d-4c9d-9649-b9803f56125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784322976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.784322976
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2104204266
Short name T576
Test name
Test status
Simulation time 1216451138 ps
CPU time 3.14 seconds
Started Aug 03 05:02:42 PM PDT 24
Finished Aug 03 05:02:46 PM PDT 24
Peak memory 233060 kb
Host smart-ae53a948-5cd1-46c1-8075-5463ccd39f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104204266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2104204266
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.393087289
Short name T526
Test name
Test status
Simulation time 1064442899 ps
CPU time 4.36 seconds
Started Aug 03 05:02:36 PM PDT 24
Finished Aug 03 05:02:41 PM PDT 24
Peak memory 219284 kb
Host smart-ab81305b-d437-4a24-bd03-cd8175040e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393087289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.393087289
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1389999875
Short name T767
Test name
Test status
Simulation time 1187583156 ps
CPU time 4.48 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:03:00 PM PDT 24
Peak memory 223472 kb
Host smart-56f0907d-be04-4375-9d9c-3f4f099416df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1389999875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1389999875
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2912104685
Short name T156
Test name
Test status
Simulation time 184191271 ps
CPU time 1.03 seconds
Started Aug 03 05:02:50 PM PDT 24
Finished Aug 03 05:02:52 PM PDT 24
Peak memory 208056 kb
Host smart-0e114dcb-2a79-403c-85df-a2a9675ed79c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912104685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2912104685
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2874087943
Short name T536
Test name
Test status
Simulation time 32084449 ps
CPU time 0.72 seconds
Started Aug 03 05:02:35 PM PDT 24
Finished Aug 03 05:02:36 PM PDT 24
Peak memory 206124 kb
Host smart-202efa75-36c2-48bf-965e-3b6feae52c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874087943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2874087943
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2262737719
Short name T567
Test name
Test status
Simulation time 25538246 ps
CPU time 0.72 seconds
Started Aug 03 05:02:38 PM PDT 24
Finished Aug 03 05:02:38 PM PDT 24
Peak memory 205928 kb
Host smart-a45bbfb4-8562-4289-b17e-449ec971336f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262737719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2262737719
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3868039442
Short name T999
Test name
Test status
Simulation time 185315255 ps
CPU time 1.85 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:02:51 PM PDT 24
Peak memory 216632 kb
Host smart-273d1416-aaa5-4f60-9057-943730ee3e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868039442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3868039442
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2151285045
Short name T838
Test name
Test status
Simulation time 66384464 ps
CPU time 0.76 seconds
Started Aug 03 05:02:45 PM PDT 24
Finished Aug 03 05:02:46 PM PDT 24
Peak memory 206244 kb
Host smart-7e7d30d5-0aa9-4f79-b923-dab3cfcfc593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151285045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2151285045
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2658347160
Short name T943
Test name
Test status
Simulation time 1831499110 ps
CPU time 7.2 seconds
Started Aug 03 05:02:42 PM PDT 24
Finished Aug 03 05:02:49 PM PDT 24
Peak memory 233080 kb
Host smart-1f46300a-e259-44f4-ba9b-f43e8641416d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658347160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2658347160
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.420190639
Short name T953
Test name
Test status
Simulation time 46285958 ps
CPU time 0.71 seconds
Started Aug 03 05:02:41 PM PDT 24
Finished Aug 03 05:02:42 PM PDT 24
Peak memory 205860 kb
Host smart-61f6263a-480b-4d4d-aa91-4ff437842dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420190639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.420190639
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3623217545
Short name T334
Test name
Test status
Simulation time 141556499 ps
CPU time 2.18 seconds
Started Aug 03 05:02:50 PM PDT 24
Finished Aug 03 05:02:53 PM PDT 24
Peak memory 224372 kb
Host smart-41b5222a-d3e4-4c8a-a51a-486b78cef4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623217545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3623217545
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.445742858
Short name T438
Test name
Test status
Simulation time 36534970 ps
CPU time 0.77 seconds
Started Aug 03 05:02:47 PM PDT 24
Finished Aug 03 05:02:48 PM PDT 24
Peak memory 206948 kb
Host smart-da816038-3ad4-4108-b468-de508958030e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445742858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.445742858
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3113315744
Short name T54
Test name
Test status
Simulation time 20379000398 ps
CPU time 36.96 seconds
Started Aug 03 05:02:41 PM PDT 24
Finished Aug 03 05:03:18 PM PDT 24
Peak memory 224900 kb
Host smart-22e6d5d5-aa8d-46fc-8473-822324f6c860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113315744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3113315744
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.916186109
Short name T284
Test name
Test status
Simulation time 21626900036 ps
CPU time 163.76 seconds
Started Aug 03 05:02:47 PM PDT 24
Finished Aug 03 05:05:31 PM PDT 24
Peak memory 250096 kb
Host smart-f4e7ef20-9c25-4ef5-b438-49d59285a7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916186109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.916186109
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1860712784
Short name T329
Test name
Test status
Simulation time 5993641317 ps
CPU time 97.88 seconds
Started Aug 03 05:02:43 PM PDT 24
Finished Aug 03 05:04:21 PM PDT 24
Peak memory 257792 kb
Host smart-352120b8-6161-4722-be81-c2654818e9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860712784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1860712784
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3072800091
Short name T252
Test name
Test status
Simulation time 164528170342 ps
CPU time 304.58 seconds
Started Aug 03 05:02:43 PM PDT 24
Finished Aug 03 05:07:47 PM PDT 24
Peak memory 267552 kb
Host smart-3f1f78f3-64c3-4438-87f6-011afd7a51be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072800091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3072800091
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3883057869
Short name T766
Test name
Test status
Simulation time 388939492 ps
CPU time 5.5 seconds
Started Aug 03 05:02:51 PM PDT 24
Finished Aug 03 05:02:57 PM PDT 24
Peak memory 224840 kb
Host smart-be45e3f7-7122-4cec-a734-e71ebe588fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883057869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3883057869
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1220872617
Short name T584
Test name
Test status
Simulation time 84413595733 ps
CPU time 44.63 seconds
Started Aug 03 05:02:58 PM PDT 24
Finished Aug 03 05:03:43 PM PDT 24
Peak memory 240988 kb
Host smart-87bd8830-1d85-4e74-ab64-24ba3eff2715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220872617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1220872617
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1401194552
Short name T455
Test name
Test status
Simulation time 54103429 ps
CPU time 1.99 seconds
Started Aug 03 05:02:41 PM PDT 24
Finished Aug 03 05:02:43 PM PDT 24
Peak memory 224808 kb
Host smart-e86900c1-91be-407c-b366-16085701166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401194552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1401194552
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3136775332
Short name T422
Test name
Test status
Simulation time 10052411717 ps
CPU time 24.21 seconds
Started Aug 03 05:02:40 PM PDT 24
Finished Aug 03 05:03:04 PM PDT 24
Peak memory 225040 kb
Host smart-2cb99af6-ed74-47a6-bfa0-388fa4957097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136775332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3136775332
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4044738305
Short name T925
Test name
Test status
Simulation time 7067477165 ps
CPU time 6.94 seconds
Started Aug 03 05:02:41 PM PDT 24
Finished Aug 03 05:02:48 PM PDT 24
Peak memory 219392 kb
Host smart-94823962-ce86-4ebc-9543-7ef4150f56c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4044738305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4044738305
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.495297639
Short name T48
Test name
Test status
Simulation time 47257302645 ps
CPU time 92.67 seconds
Started Aug 03 05:02:41 PM PDT 24
Finished Aug 03 05:04:14 PM PDT 24
Peak memory 249644 kb
Host smart-d9b42616-2d55-47f5-a147-20300c173a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495297639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.495297639
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1854254583
Short name T360
Test name
Test status
Simulation time 754937223 ps
CPU time 3.16 seconds
Started Aug 03 05:02:50 PM PDT 24
Finished Aug 03 05:02:53 PM PDT 24
Peak memory 216620 kb
Host smart-58d1526f-d228-4960-aa71-d9cca7acacaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854254583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1854254583
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.405940066
Short name T464
Test name
Test status
Simulation time 12037763 ps
CPU time 0.74 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:02:56 PM PDT 24
Peak memory 206096 kb
Host smart-8963e321-7f34-4103-a523-90ce09c9beff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405940066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.405940066
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2794376511
Short name T508
Test name
Test status
Simulation time 431958242 ps
CPU time 1.19 seconds
Started Aug 03 05:02:50 PM PDT 24
Finished Aug 03 05:02:52 PM PDT 24
Peak memory 207216 kb
Host smart-b21c03c7-96d2-4a96-8bdb-837fea331870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794376511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2794376511
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4275439015
Short name T73
Test name
Test status
Simulation time 26924579 ps
CPU time 0.85 seconds
Started Aug 03 05:02:51 PM PDT 24
Finished Aug 03 05:02:52 PM PDT 24
Peak memory 206344 kb
Host smart-47bafd10-16fd-4c92-a41c-c417dd02afb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275439015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4275439015
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2824375715
Short name T267
Test name
Test status
Simulation time 1204487263 ps
CPU time 5.93 seconds
Started Aug 03 05:02:40 PM PDT 24
Finished Aug 03 05:02:46 PM PDT 24
Peak memory 223320 kb
Host smart-e735e8a4-4197-40d4-be98-1797ce73ba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824375715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2824375715
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1188181246
Short name T396
Test name
Test status
Simulation time 21812867 ps
CPU time 0.71 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:03:00 PM PDT 24
Peak memory 205788 kb
Host smart-d005763e-c62e-4a66-a86b-9a65316474ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188181246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1188181246
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1667886152
Short name T960
Test name
Test status
Simulation time 168691167 ps
CPU time 3.11 seconds
Started Aug 03 05:02:53 PM PDT 24
Finished Aug 03 05:02:56 PM PDT 24
Peak memory 224960 kb
Host smart-432276db-e7d0-4940-b07d-f58e5ddff533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667886152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1667886152
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1997682898
Short name T346
Test name
Test status
Simulation time 62424296 ps
CPU time 0.8 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:02 PM PDT 24
Peak memory 206988 kb
Host smart-59b1efd6-bebb-4cae-9a58-e54180e29dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997682898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1997682898
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3916086012
Short name T276
Test name
Test status
Simulation time 493404169712 ps
CPU time 520.21 seconds
Started Aug 03 05:02:52 PM PDT 24
Finished Aug 03 05:11:32 PM PDT 24
Peak memory 269776 kb
Host smart-301ac92b-250b-4a82-8922-7219c1721d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916086012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3916086012
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.373352418
Short name T244
Test name
Test status
Simulation time 115033653478 ps
CPU time 525.69 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:11:35 PM PDT 24
Peak memory 249576 kb
Host smart-f2e825d1-bd00-4af0-bf38-debc9f0b3551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373352418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.373352418
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1009383139
Short name T369
Test name
Test status
Simulation time 623847765 ps
CPU time 3.98 seconds
Started Aug 03 05:02:57 PM PDT 24
Finished Aug 03 05:03:01 PM PDT 24
Peak memory 233076 kb
Host smart-d6443f76-03d0-46d9-8518-b12fd3c70139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009383139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1009383139
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.327195923
Short name T172
Test name
Test status
Simulation time 24714950484 ps
CPU time 54.3 seconds
Started Aug 03 05:02:52 PM PDT 24
Finished Aug 03 05:03:47 PM PDT 24
Peak memory 250952 kb
Host smart-08f267c4-ff7c-4ce7-babb-5618fa944e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327195923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.327195923
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1393882100
Short name T363
Test name
Test status
Simulation time 205276012 ps
CPU time 4.66 seconds
Started Aug 03 05:02:54 PM PDT 24
Finished Aug 03 05:02:59 PM PDT 24
Peak memory 224840 kb
Host smart-64ec3fc8-48fa-4963-a0bf-71050c251ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393882100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1393882100
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.399090826
Short name T923
Test name
Test status
Simulation time 18193634421 ps
CPU time 38.12 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:03:39 PM PDT 24
Peak memory 233168 kb
Host smart-a542ac5e-ddd3-4536-94e5-12fa2199c5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399090826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.399090826
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3051297063
Short name T437
Test name
Test status
Simulation time 1274031752 ps
CPU time 3.67 seconds
Started Aug 03 05:02:51 PM PDT 24
Finished Aug 03 05:02:55 PM PDT 24
Peak memory 224884 kb
Host smart-544a5066-edcd-4244-9628-379628cc4013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051297063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3051297063
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2669072522
Short name T658
Test name
Test status
Simulation time 4093845948 ps
CPU time 16.42 seconds
Started Aug 03 05:02:57 PM PDT 24
Finished Aug 03 05:03:14 PM PDT 24
Peak memory 241408 kb
Host smart-44db7b4e-b8b4-4b9e-a45c-68ace0141fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669072522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2669072522
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2349164665
Short name T13
Test name
Test status
Simulation time 676688476 ps
CPU time 10.87 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:03:06 PM PDT 24
Peak memory 220416 kb
Host smart-62ae8a8f-89be-44a6-91c7-8a248cc2dc79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2349164665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2349164665
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1849309689
Short name T870
Test name
Test status
Simulation time 12726101848 ps
CPU time 29.59 seconds
Started Aug 03 05:02:53 PM PDT 24
Finished Aug 03 05:03:22 PM PDT 24
Peak memory 216940 kb
Host smart-f0934282-b634-49c4-956b-9fa944bd99a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849309689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1849309689
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4074410101
Short name T640
Test name
Test status
Simulation time 1384484466 ps
CPU time 8.37 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:09 PM PDT 24
Peak memory 216648 kb
Host smart-137cae1b-9cc9-4a38-ae15-8040b2175e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074410101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4074410101
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1254511838
Short name T580
Test name
Test status
Simulation time 183871436 ps
CPU time 0.95 seconds
Started Aug 03 05:02:58 PM PDT 24
Finished Aug 03 05:02:59 PM PDT 24
Peak memory 207436 kb
Host smart-67002846-0f9b-40a7-baf3-1b0fa274ab2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254511838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1254511838
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2624809679
Short name T981
Test name
Test status
Simulation time 39350880 ps
CPU time 0.86 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:03:01 PM PDT 24
Peak memory 207524 kb
Host smart-cb9f3b2a-4f0c-4ad2-bdc0-9d14f9fc72a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624809679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2624809679
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1185661366
Short name T489
Test name
Test status
Simulation time 2414121359 ps
CPU time 6.21 seconds
Started Aug 03 05:02:52 PM PDT 24
Finished Aug 03 05:02:58 PM PDT 24
Peak memory 233172 kb
Host smart-9fa749f1-6331-43c1-ab81-701cf8c56caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185661366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1185661366
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2002456307
Short name T485
Test name
Test status
Simulation time 11406034 ps
CPU time 0.72 seconds
Started Aug 03 05:02:54 PM PDT 24
Finished Aug 03 05:02:55 PM PDT 24
Peak memory 205228 kb
Host smart-45d92ddc-423e-4140-98b2-5c932bb68823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002456307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2002456307
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1834713902
Short name T837
Test name
Test status
Simulation time 149488523 ps
CPU time 3.96 seconds
Started Aug 03 05:02:58 PM PDT 24
Finished Aug 03 05:03:02 PM PDT 24
Peak memory 233112 kb
Host smart-a872c851-568c-44c6-833b-f8105f8f6fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834713902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1834713902
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1702520311
Short name T692
Test name
Test status
Simulation time 36421739 ps
CPU time 0.8 seconds
Started Aug 03 05:03:04 PM PDT 24
Finished Aug 03 05:03:05 PM PDT 24
Peak memory 206988 kb
Host smart-a8e369dc-3faf-41eb-8d2f-14ee41b1f2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702520311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1702520311
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1429313881
Short name T198
Test name
Test status
Simulation time 4019716112 ps
CPU time 18.73 seconds
Started Aug 03 05:02:59 PM PDT 24
Finished Aug 03 05:03:17 PM PDT 24
Peak memory 241356 kb
Host smart-2f376a5d-cbde-411b-8f43-58f1164f8200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429313881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1429313881
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1097707800
Short name T295
Test name
Test status
Simulation time 105797540373 ps
CPU time 438.94 seconds
Started Aug 03 05:02:51 PM PDT 24
Finished Aug 03 05:10:10 PM PDT 24
Peak memory 252620 kb
Host smart-2ef490e5-9066-428f-a2ae-da7ebff895b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097707800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1097707800
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2387750301
Short name T246
Test name
Test status
Simulation time 5761279363 ps
CPU time 83.01 seconds
Started Aug 03 05:02:56 PM PDT 24
Finished Aug 03 05:04:19 PM PDT 24
Peak memory 249880 kb
Host smart-94b3f5b1-3658-40d8-9d27-3de4e5379d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387750301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2387750301
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3854735762
Short name T302
Test name
Test status
Simulation time 8126320509 ps
CPU time 17.67 seconds
Started Aug 03 05:02:47 PM PDT 24
Finished Aug 03 05:03:05 PM PDT 24
Peak memory 233216 kb
Host smart-2df162fa-c03f-4c9b-bb43-15416381fe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854735762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3854735762
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.658858040
Short name T621
Test name
Test status
Simulation time 361796082 ps
CPU time 10.35 seconds
Started Aug 03 05:03:04 PM PDT 24
Finished Aug 03 05:03:15 PM PDT 24
Peak memory 237128 kb
Host smart-50c78a17-0649-4142-bb09-c31736098a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658858040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.658858040
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2359216920
Short name T851
Test name
Test status
Simulation time 6155192115 ps
CPU time 16.38 seconds
Started Aug 03 05:02:49 PM PDT 24
Finished Aug 03 05:03:06 PM PDT 24
Peak memory 233128 kb
Host smart-874801ea-1852-43b2-a9b4-ad9bfb71cce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359216920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2359216920
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2962105848
Short name T37
Test name
Test status
Simulation time 9494217624 ps
CPU time 78.35 seconds
Started Aug 03 05:03:04 PM PDT 24
Finished Aug 03 05:04:22 PM PDT 24
Peak memory 224596 kb
Host smart-c3b8a5b6-1ead-4f9a-adca-1734738b82bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962105848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2962105848
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3067430183
Short name T197
Test name
Test status
Simulation time 10346706125 ps
CPU time 13.54 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:03:13 PM PDT 24
Peak memory 224940 kb
Host smart-97e42ab3-3165-47f5-b00c-a06d9cfb92dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067430183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3067430183
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4145312869
Short name T642
Test name
Test status
Simulation time 2070741438 ps
CPU time 6.59 seconds
Started Aug 03 05:02:52 PM PDT 24
Finished Aug 03 05:02:59 PM PDT 24
Peak memory 236732 kb
Host smart-1310ce08-4132-4be3-aa1a-4dccf13e3899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145312869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4145312869
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3691302958
Short name T372
Test name
Test status
Simulation time 7222529998 ps
CPU time 14.5 seconds
Started Aug 03 05:02:48 PM PDT 24
Finished Aug 03 05:03:02 PM PDT 24
Peak memory 221196 kb
Host smart-8373c971-47b1-44d0-b824-d32ba7730042
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3691302958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3691302958
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1945335133
Short name T973
Test name
Test status
Simulation time 9593658604 ps
CPU time 59.8 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 237208 kb
Host smart-8f99a9ae-687f-45c4-ba5d-c4dc37e59ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945335133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1945335133
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.956638947
Short name T318
Test name
Test status
Simulation time 2412595625 ps
CPU time 14.98 seconds
Started Aug 03 05:02:54 PM PDT 24
Finished Aug 03 05:03:09 PM PDT 24
Peak memory 216676 kb
Host smart-e6fde7c3-6a3c-4077-8301-19f2728b8d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956638947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.956638947
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1609832456
Short name T679
Test name
Test status
Simulation time 11449777661 ps
CPU time 8.92 seconds
Started Aug 03 05:02:53 PM PDT 24
Finished Aug 03 05:03:02 PM PDT 24
Peak memory 216724 kb
Host smart-34c2af30-e8a0-43ad-b52f-457867e92b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609832456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1609832456
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2061129493
Short name T637
Test name
Test status
Simulation time 28884621 ps
CPU time 1.52 seconds
Started Aug 03 05:02:54 PM PDT 24
Finished Aug 03 05:02:56 PM PDT 24
Peak memory 216564 kb
Host smart-41632cdb-396f-4fa5-877d-73cee457a4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061129493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2061129493
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3156668220
Short name T734
Test name
Test status
Simulation time 31100046 ps
CPU time 0.73 seconds
Started Aug 03 05:03:04 PM PDT 24
Finished Aug 03 05:03:05 PM PDT 24
Peak memory 206244 kb
Host smart-3b71bdb1-c7d9-4575-a0e1-777289298fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156668220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3156668220
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2688127420
Short name T889
Test name
Test status
Simulation time 53094910 ps
CPU time 2.47 seconds
Started Aug 03 05:02:52 PM PDT 24
Finished Aug 03 05:02:54 PM PDT 24
Peak memory 224968 kb
Host smart-bfa41329-c444-405c-97cb-69a9637bdfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688127420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2688127420
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1712789334
Short name T331
Test name
Test status
Simulation time 31635264 ps
CPU time 0.75 seconds
Started Aug 03 05:02:54 PM PDT 24
Finished Aug 03 05:02:55 PM PDT 24
Peak memory 205248 kb
Host smart-f18f743e-07fa-4089-a5d1-19c19e4b11ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712789334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1712789334
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.438759338
Short name T583
Test name
Test status
Simulation time 3871943454 ps
CPU time 3.59 seconds
Started Aug 03 05:03:05 PM PDT 24
Finished Aug 03 05:03:09 PM PDT 24
Peak memory 224896 kb
Host smart-29386801-219b-4f0d-930b-4122609b746d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438759338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.438759338
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3337543038
Short name T386
Test name
Test status
Simulation time 18920489 ps
CPU time 0.78 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:02:55 PM PDT 24
Peak memory 205920 kb
Host smart-050d60b1-9ae2-4674-9476-a1249adf8b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337543038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3337543038
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3620723747
Short name T177
Test name
Test status
Simulation time 14333053205 ps
CPU time 98.34 seconds
Started Aug 03 05:03:02 PM PDT 24
Finished Aug 03 05:04:40 PM PDT 24
Peak memory 240788 kb
Host smart-b1248cfb-e206-43eb-a731-cc3056820c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620723747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3620723747
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2560348728
Short name T353
Test name
Test status
Simulation time 24574913 ps
CPU time 0.82 seconds
Started Aug 03 05:02:54 PM PDT 24
Finished Aug 03 05:02:55 PM PDT 24
Peak memory 217492 kb
Host smart-398cfd55-cdd6-4b35-a28c-c9458faae7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560348728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2560348728
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1027286721
Short name T330
Test name
Test status
Simulation time 3130725725 ps
CPU time 51 seconds
Started Aug 03 05:03:08 PM PDT 24
Finished Aug 03 05:03:59 PM PDT 24
Peak memory 252476 kb
Host smart-4cc0e1fa-d7a2-46cf-9010-fd3fc1d96317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027286721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1027286721
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3371867328
Short name T307
Test name
Test status
Simulation time 1154342275 ps
CPU time 9.76 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:11 PM PDT 24
Peak memory 235400 kb
Host smart-d178b230-5ea3-4217-a5ea-e350f2569d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371867328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3371867328
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2869063790
Short name T667
Test name
Test status
Simulation time 43997661727 ps
CPU time 47.45 seconds
Started Aug 03 05:02:53 PM PDT 24
Finished Aug 03 05:03:40 PM PDT 24
Peak memory 233172 kb
Host smart-4464999a-8b7f-4c79-9f94-192b1af7a777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869063790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2869063790
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2116160071
Short name T570
Test name
Test status
Simulation time 257302450 ps
CPU time 4.02 seconds
Started Aug 03 05:03:02 PM PDT 24
Finished Aug 03 05:03:06 PM PDT 24
Peak memory 233128 kb
Host smart-ffea6c12-d6c1-42bc-b661-2e859bea8449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116160071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2116160071
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2966623512
Short name T854
Test name
Test status
Simulation time 10480259069 ps
CPU time 26.09 seconds
Started Aug 03 05:03:07 PM PDT 24
Finished Aug 03 05:03:33 PM PDT 24
Peak memory 241172 kb
Host smart-6011e0ed-e672-42c4-88d2-da3abf49d993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966623512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2966623512
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2314386462
Short name T977
Test name
Test status
Simulation time 459762778 ps
CPU time 3.32 seconds
Started Aug 03 05:02:53 PM PDT 24
Finished Aug 03 05:02:56 PM PDT 24
Peak memory 224864 kb
Host smart-70be3499-1ce7-45c9-99d8-54d8d8aa62f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314386462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2314386462
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2318848089
Short name T238
Test name
Test status
Simulation time 236442438 ps
CPU time 3.32 seconds
Started Aug 03 05:02:56 PM PDT 24
Finished Aug 03 05:02:59 PM PDT 24
Peak memory 233132 kb
Host smart-368fff11-c543-49ba-b607-c20682928e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318848089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2318848089
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4276850226
Short name T35
Test name
Test status
Simulation time 269623434 ps
CPU time 3.18 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:02:58 PM PDT 24
Peak memory 219412 kb
Host smart-8e0125fb-c71e-459b-89b8-5e90cfebb174
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4276850226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4276850226
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3162749354
Short name T135
Test name
Test status
Simulation time 69908457593 ps
CPU time 298.07 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:07:58 PM PDT 24
Peak memory 268728 kb
Host smart-ac11c99a-0320-47c2-889f-becd5965305f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162749354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3162749354
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3731994290
Short name T535
Test name
Test status
Simulation time 1390890027 ps
CPU time 8.06 seconds
Started Aug 03 05:02:53 PM PDT 24
Finished Aug 03 05:03:02 PM PDT 24
Peak memory 216660 kb
Host smart-8c1c0ea9-43f7-461f-9183-cf8fc2d31914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731994290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3731994290
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2092738576
Short name T713
Test name
Test status
Simulation time 2847278185 ps
CPU time 2.59 seconds
Started Aug 03 05:03:05 PM PDT 24
Finished Aug 03 05:03:08 PM PDT 24
Peak memory 208204 kb
Host smart-ad7c6f3a-7266-4fb5-8f14-0c07cebadb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092738576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2092738576
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2323176820
Short name T695
Test name
Test status
Simulation time 476592134 ps
CPU time 8.6 seconds
Started Aug 03 05:02:58 PM PDT 24
Finished Aug 03 05:03:06 PM PDT 24
Peak memory 216584 kb
Host smart-a90136b3-be78-4bb9-822f-0901587d990e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323176820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2323176820
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3197579
Short name T490
Test name
Test status
Simulation time 12033733 ps
CPU time 0.71 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:02:56 PM PDT 24
Peak memory 206024 kb
Host smart-711a881d-5704-4452-b77f-a7f984b6979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3197579
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2978318396
Short name T521
Test name
Test status
Simulation time 191212165 ps
CPU time 4.5 seconds
Started Aug 03 05:03:14 PM PDT 24
Finished Aug 03 05:03:18 PM PDT 24
Peak memory 233116 kb
Host smart-d53972c0-82f2-40ce-a55f-5c3c42818173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978318396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2978318396
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.886974061
Short name T797
Test name
Test status
Simulation time 31927335 ps
CPU time 0.74 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:02:56 PM PDT 24
Peak memory 205300 kb
Host smart-c2a73e1e-438a-495f-8bb9-121b418ba607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886974061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.886974061
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1386737043
Short name T84
Test name
Test status
Simulation time 571420878 ps
CPU time 7.88 seconds
Started Aug 03 05:02:58 PM PDT 24
Finished Aug 03 05:03:06 PM PDT 24
Peak memory 232940 kb
Host smart-707913ff-ee1d-4dbf-a004-1ac25a76129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386737043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1386737043
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3887188181
Short name T607
Test name
Test status
Simulation time 54939150 ps
CPU time 0.72 seconds
Started Aug 03 05:02:59 PM PDT 24
Finished Aug 03 05:02:59 PM PDT 24
Peak memory 205972 kb
Host smart-11c73186-18c5-43b4-a40d-e989b9ea4f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887188181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3887188181
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1761152255
Short name T209
Test name
Test status
Simulation time 76767972784 ps
CPU time 202.94 seconds
Started Aug 03 05:02:57 PM PDT 24
Finished Aug 03 05:06:20 PM PDT 24
Peak memory 256688 kb
Host smart-601459ff-a6e5-42c4-9712-a278da72fa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761152255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1761152255
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1600163477
Short name T193
Test name
Test status
Simulation time 368153920737 ps
CPU time 724.01 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:15:05 PM PDT 24
Peak memory 274120 kb
Host smart-c59b7fe6-bf5c-4c70-a848-7ff4bee00009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600163477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1600163477
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3358599395
Short name T836
Test name
Test status
Simulation time 41868409911 ps
CPU time 173.38 seconds
Started Aug 03 05:02:58 PM PDT 24
Finished Aug 03 05:05:51 PM PDT 24
Peak memory 249608 kb
Host smart-7bbbe13a-26f4-445f-ae13-b0e58e9e1184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358599395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3358599395
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2952874717
Short name T70
Test name
Test status
Simulation time 616471368 ps
CPU time 13.87 seconds
Started Aug 03 05:03:08 PM PDT 24
Finished Aug 03 05:03:22 PM PDT 24
Peak memory 241292 kb
Host smart-2212249a-3daf-403b-aec2-06811ca95eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952874717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2952874717
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1314277873
Short name T952
Test name
Test status
Simulation time 20549575148 ps
CPU time 68.98 seconds
Started Aug 03 05:03:04 PM PDT 24
Finished Aug 03 05:04:13 PM PDT 24
Peak memory 252576 kb
Host smart-cd677877-b0c2-472f-aa7e-9b98c19a4d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314277873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1314277873
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4229169021
Short name T538
Test name
Test status
Simulation time 1545938092 ps
CPU time 14.36 seconds
Started Aug 03 05:02:57 PM PDT 24
Finished Aug 03 05:03:12 PM PDT 24
Peak memory 224872 kb
Host smart-e970ec1c-09d4-4189-83cc-d9b1dd06b939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229169021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4229169021
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1757459335
Short name T746
Test name
Test status
Simulation time 7039319895 ps
CPU time 20.01 seconds
Started Aug 03 05:03:13 PM PDT 24
Finished Aug 03 05:03:34 PM PDT 24
Peak memory 224972 kb
Host smart-c6d71765-38b9-40da-bb50-37e1474d6811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757459335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1757459335
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3654143887
Short name T773
Test name
Test status
Simulation time 647987717 ps
CPU time 3.67 seconds
Started Aug 03 05:02:56 PM PDT 24
Finished Aug 03 05:03:00 PM PDT 24
Peak memory 224828 kb
Host smart-e75f72dc-8929-485e-9e19-13dbc010f56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654143887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3654143887
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3368059698
Short name T452
Test name
Test status
Simulation time 676054255 ps
CPU time 5.31 seconds
Started Aug 03 05:02:54 PM PDT 24
Finished Aug 03 05:03:00 PM PDT 24
Peak memory 233144 kb
Host smart-b6a8c165-e0e6-4e89-be35-c1daa2e3fd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368059698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3368059698
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3729281827
Short name T145
Test name
Test status
Simulation time 1704743283 ps
CPU time 6.48 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:03:02 PM PDT 24
Peak memory 219804 kb
Host smart-e64e4182-308d-408a-877f-0e4e3cd401bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3729281827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3729281827
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.9517108
Short name T826
Test name
Test status
Simulation time 110234066 ps
CPU time 0.72 seconds
Started Aug 03 05:03:04 PM PDT 24
Finished Aug 03 05:03:05 PM PDT 24
Peak memory 205836 kb
Host smart-6d6852e7-505f-4e1e-a6b7-8ce0fda1f6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9517108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.9517108
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3872560519
Short name T502
Test name
Test status
Simulation time 1649582940 ps
CPU time 3.67 seconds
Started Aug 03 05:02:57 PM PDT 24
Finished Aug 03 05:03:01 PM PDT 24
Peak memory 216728 kb
Host smart-1d8b1322-9c15-4009-a707-f3fd702f140a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872560519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3872560519
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2432095340
Short name T319
Test name
Test status
Simulation time 468479145 ps
CPU time 2.01 seconds
Started Aug 03 05:02:57 PM PDT 24
Finished Aug 03 05:02:59 PM PDT 24
Peak memory 216736 kb
Host smart-23841722-7356-4d0f-88f2-35747eca1b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432095340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2432095340
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3691725943
Short name T420
Test name
Test status
Simulation time 11734624 ps
CPU time 0.69 seconds
Started Aug 03 05:03:07 PM PDT 24
Finished Aug 03 05:03:08 PM PDT 24
Peak memory 206012 kb
Host smart-75407db3-489c-4b65-b44e-79f4df564369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691725943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3691725943
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.50640514
Short name T661
Test name
Test status
Simulation time 479558120 ps
CPU time 4.7 seconds
Started Aug 03 05:02:58 PM PDT 24
Finished Aug 03 05:03:03 PM PDT 24
Peak memory 224936 kb
Host smart-aa177d3e-8abd-4ffb-a248-44f3a7dfb4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50640514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.50640514
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3027615410
Short name T434
Test name
Test status
Simulation time 49388605 ps
CPU time 0.74 seconds
Started Aug 03 05:01:41 PM PDT 24
Finished Aug 03 05:01:42 PM PDT 24
Peak memory 205824 kb
Host smart-e2bf327d-d779-4ba4-88d1-b6c40e129844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027615410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
027615410
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1178917980
Short name T85
Test name
Test status
Simulation time 689523470 ps
CPU time 10.29 seconds
Started Aug 03 05:01:34 PM PDT 24
Finished Aug 03 05:01:44 PM PDT 24
Peak memory 233048 kb
Host smart-03703101-8386-43d3-9ce4-b8cb7548da3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178917980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1178917980
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1988149426
Short name T366
Test name
Test status
Simulation time 15879892 ps
CPU time 0.77 seconds
Started Aug 03 05:01:33 PM PDT 24
Finished Aug 03 05:01:34 PM PDT 24
Peak memory 205908 kb
Host smart-f39cc657-123a-4693-ad25-309823e54738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988149426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1988149426
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1138095934
Short name T569
Test name
Test status
Simulation time 3607434088 ps
CPU time 65.63 seconds
Started Aug 03 05:01:41 PM PDT 24
Finished Aug 03 05:02:47 PM PDT 24
Peak memory 263736 kb
Host smart-e7cd875c-81e6-4b99-a7d2-b5365e1a03ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138095934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1138095934
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.762426285
Short name T946
Test name
Test status
Simulation time 29138998252 ps
CPU time 148.22 seconds
Started Aug 03 05:01:34 PM PDT 24
Finished Aug 03 05:04:03 PM PDT 24
Peak memory 273928 kb
Host smart-4ac45bfd-294b-4ef1-a5f3-57ba7cd9b882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762426285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.762426285
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2713449624
Short name T754
Test name
Test status
Simulation time 779111540 ps
CPU time 16.07 seconds
Started Aug 03 05:01:53 PM PDT 24
Finished Aug 03 05:02:10 PM PDT 24
Peak memory 224936 kb
Host smart-28613172-4609-4cee-8da8-b58e50fa7ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713449624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2713449624
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2167804500
Short name T577
Test name
Test status
Simulation time 822618966 ps
CPU time 8.11 seconds
Started Aug 03 05:01:37 PM PDT 24
Finished Aug 03 05:01:45 PM PDT 24
Peak memory 233132 kb
Host smart-1e2361d7-5d26-4301-8f28-5b4575059e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167804500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2167804500
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1731946473
Short name T565
Test name
Test status
Simulation time 113713731967 ps
CPU time 190.84 seconds
Started Aug 03 05:01:38 PM PDT 24
Finished Aug 03 05:04:49 PM PDT 24
Peak memory 249576 kb
Host smart-c6015917-4c38-4538-8855-6c454adc6bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731946473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1731946473
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2487415917
Short name T202
Test name
Test status
Simulation time 2010659344 ps
CPU time 13.56 seconds
Started Aug 03 05:01:50 PM PDT 24
Finished Aug 03 05:02:03 PM PDT 24
Peak memory 224904 kb
Host smart-d6fd4a5b-bbd4-4b55-a886-80b243e1c176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487415917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2487415917
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3610361224
Short name T12
Test name
Test status
Simulation time 731627384 ps
CPU time 12.41 seconds
Started Aug 03 05:01:44 PM PDT 24
Finished Aug 03 05:01:56 PM PDT 24
Peak memory 251176 kb
Host smart-32449114-0162-4219-8904-6cbf9d5b77ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610361224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3610361224
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2293062487
Short name T750
Test name
Test status
Simulation time 1195213172 ps
CPU time 5.59 seconds
Started Aug 03 05:01:48 PM PDT 24
Finished Aug 03 05:01:54 PM PDT 24
Peak memory 233080 kb
Host smart-b7070d06-8689-48b3-847b-4cfa2c6299e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293062487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2293062487
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2994069452
Short name T233
Test name
Test status
Simulation time 1673035351 ps
CPU time 4.55 seconds
Started Aug 03 05:01:43 PM PDT 24
Finished Aug 03 05:01:48 PM PDT 24
Peak memory 233076 kb
Host smart-3cc6363f-b356-4553-8968-b3e2854a8aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994069452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2994069452
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1431291379
Short name T979
Test name
Test status
Simulation time 2568484726 ps
CPU time 11.27 seconds
Started Aug 03 05:01:46 PM PDT 24
Finished Aug 03 05:01:57 PM PDT 24
Peak memory 222240 kb
Host smart-c082f532-9a61-471f-be9c-6a0d8ad6211f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1431291379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1431291379
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3130029260
Short name T136
Test name
Test status
Simulation time 50168231430 ps
CPU time 428.06 seconds
Started Aug 03 05:01:38 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 257792 kb
Host smart-4cbfd8e3-2b00-40c2-b224-b33f72831c6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130029260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3130029260
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3749626151
Short name T56
Test name
Test status
Simulation time 6298854739 ps
CPU time 30.44 seconds
Started Aug 03 05:01:49 PM PDT 24
Finished Aug 03 05:02:19 PM PDT 24
Peak memory 216696 kb
Host smart-6e2c5cd0-eafb-4326-8fc7-c4e869947976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749626151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3749626151
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.538314185
Short name T845
Test name
Test status
Simulation time 8177215435 ps
CPU time 21.32 seconds
Started Aug 03 05:01:39 PM PDT 24
Finished Aug 03 05:02:00 PM PDT 24
Peak memory 216684 kb
Host smart-5adc6fed-39a5-46f0-9951-8b885d581aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538314185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.538314185
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2257376177
Short name T361
Test name
Test status
Simulation time 43522891 ps
CPU time 2.55 seconds
Started Aug 03 05:01:34 PM PDT 24
Finished Aug 03 05:01:37 PM PDT 24
Peak memory 216656 kb
Host smart-b3cfd050-ab04-4fc7-bc93-ed2b0049aefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257376177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2257376177
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1902488823
Short name T708
Test name
Test status
Simulation time 160115297 ps
CPU time 0.81 seconds
Started Aug 03 05:01:43 PM PDT 24
Finished Aug 03 05:01:44 PM PDT 24
Peak memory 206332 kb
Host smart-cad81a8f-0366-4642-af32-5399ff4a6ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902488823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1902488823
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2307883239
Short name T811
Test name
Test status
Simulation time 66782246 ps
CPU time 2.56 seconds
Started Aug 03 05:01:52 PM PDT 24
Finished Aug 03 05:01:55 PM PDT 24
Peak memory 232820 kb
Host smart-b1d2dd9b-b3c8-472f-8edc-43aa934229ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307883239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2307883239
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1424261515
Short name T472
Test name
Test status
Simulation time 138542757 ps
CPU time 0.71 seconds
Started Aug 03 05:03:08 PM PDT 24
Finished Aug 03 05:03:09 PM PDT 24
Peak memory 205828 kb
Host smart-30e6a49e-11d5-41de-93dd-db7ebc4582e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424261515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1424261515
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1694594880
Short name T751
Test name
Test status
Simulation time 7652216118 ps
CPU time 17.83 seconds
Started Aug 03 05:03:14 PM PDT 24
Finished Aug 03 05:03:32 PM PDT 24
Peak memory 233176 kb
Host smart-62cbe539-1a36-4e61-a5a3-90f78c10168a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694594880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1694594880
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.271466422
Short name T652
Test name
Test status
Simulation time 16297418 ps
CPU time 0.76 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:02 PM PDT 24
Peak memory 205964 kb
Host smart-a199e2a2-f26a-4be9-bbd3-e0b9f6d4b347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271466422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.271466422
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.432902348
Short name T598
Test name
Test status
Simulation time 69368546084 ps
CPU time 145.57 seconds
Started Aug 03 05:03:09 PM PDT 24
Finished Aug 03 05:05:35 PM PDT 24
Peak memory 254724 kb
Host smart-e8aaf8cf-154b-4ca4-9a7f-2694c9901444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432902348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.432902348
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.329004367
Short name T271
Test name
Test status
Simulation time 6069166848 ps
CPU time 77.97 seconds
Started Aug 03 05:02:59 PM PDT 24
Finished Aug 03 05:04:18 PM PDT 24
Peak memory 255200 kb
Host smart-f2deac0d-958f-4211-b0da-c5bf637bbb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329004367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.329004367
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3570182091
Short name T123
Test name
Test status
Simulation time 66699967089 ps
CPU time 298.93 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:08:00 PM PDT 24
Peak memory 265980 kb
Host smart-2931bb53-a4b3-4cc6-9551-503ca25646a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570182091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3570182091
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2516066713
Short name T510
Test name
Test status
Simulation time 5022858229 ps
CPU time 42.23 seconds
Started Aug 03 05:02:59 PM PDT 24
Finished Aug 03 05:03:41 PM PDT 24
Peak memory 233164 kb
Host smart-b6bc4475-9eed-467f-be26-0fd516a44ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516066713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2516066713
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2482037271
Short name T345
Test name
Test status
Simulation time 24287913 ps
CPU time 0.74 seconds
Started Aug 03 05:02:56 PM PDT 24
Finished Aug 03 05:02:57 PM PDT 24
Peak memory 216108 kb
Host smart-70b2b5f9-557b-449b-836e-7ad61b528872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482037271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2482037271
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1134320486
Short name T462
Test name
Test status
Simulation time 480582841 ps
CPU time 2.16 seconds
Started Aug 03 05:03:05 PM PDT 24
Finished Aug 03 05:03:07 PM PDT 24
Peak memory 224476 kb
Host smart-73f9d158-9e9e-4a81-bfad-d696d92da476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134320486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1134320486
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2311673189
Short name T515
Test name
Test status
Simulation time 6891206570 ps
CPU time 9.43 seconds
Started Aug 03 05:02:56 PM PDT 24
Finished Aug 03 05:03:06 PM PDT 24
Peak memory 224980 kb
Host smart-8588e259-65c7-4009-b617-4e507b400d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311673189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2311673189
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.855559166
Short name T945
Test name
Test status
Simulation time 407346042 ps
CPU time 4.59 seconds
Started Aug 03 05:02:56 PM PDT 24
Finished Aug 03 05:03:00 PM PDT 24
Peak memory 233092 kb
Host smart-2b7ce4d4-bfcb-4864-b54f-5ada898679cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855559166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.855559166
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1441243598
Short name T205
Test name
Test status
Simulation time 511798219 ps
CPU time 3.18 seconds
Started Aug 03 05:02:55 PM PDT 24
Finished Aug 03 05:02:58 PM PDT 24
Peak memory 224788 kb
Host smart-72810b35-b281-488e-8b23-fe0975119fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441243598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1441243598
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4088953570
Short name T955
Test name
Test status
Simulation time 167580444 ps
CPU time 3.78 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:05 PM PDT 24
Peak memory 219788 kb
Host smart-121f885b-f384-448a-ad36-eedccdc19879
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4088953570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4088953570
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1767639281
Short name T958
Test name
Test status
Simulation time 10034673718 ps
CPU time 85.12 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:04:26 PM PDT 24
Peak memory 249616 kb
Host smart-5de23223-1498-4394-b47a-60f0d5d1d3c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767639281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1767639281
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.476416666
Short name T651
Test name
Test status
Simulation time 13965572596 ps
CPU time 36.69 seconds
Started Aug 03 05:03:13 PM PDT 24
Finished Aug 03 05:03:50 PM PDT 24
Peak memory 216660 kb
Host smart-2d9b489c-1f9d-42d7-90c4-0c6bdb7c682a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476416666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.476416666
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.109660185
Short name T814
Test name
Test status
Simulation time 929295851 ps
CPU time 4.03 seconds
Started Aug 03 05:02:56 PM PDT 24
Finished Aug 03 05:03:00 PM PDT 24
Peak memory 216592 kb
Host smart-e94161ba-f84a-42da-8c6e-d1842db9289a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109660185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.109660185
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2598245643
Short name T357
Test name
Test status
Simulation time 22871301 ps
CPU time 1.22 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:03:02 PM PDT 24
Peak memory 216700 kb
Host smart-935d0802-7f75-496b-b9fd-52413c36297b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598245643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2598245643
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2228201415
Short name T125
Test name
Test status
Simulation time 15891114 ps
CPU time 0.73 seconds
Started Aug 03 05:02:56 PM PDT 24
Finished Aug 03 05:02:56 PM PDT 24
Peak memory 206344 kb
Host smart-ded89d04-ac67-4323-b731-3fb21ad69aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228201415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2228201415
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.337979232
Short name T204
Test name
Test status
Simulation time 2990356539 ps
CPU time 6.89 seconds
Started Aug 03 05:02:54 PM PDT 24
Finished Aug 03 05:03:01 PM PDT 24
Peak memory 233244 kb
Host smart-aa41a8c4-f424-4f23-82b5-56a812afa153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337979232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.337979232
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3516121291
Short name T398
Test name
Test status
Simulation time 27127903 ps
CPU time 0.69 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:03:01 PM PDT 24
Peak memory 205784 kb
Host smart-4a0c39c5-2e95-4048-9728-53fc94bb870c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516121291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3516121291
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.644362293
Short name T676
Test name
Test status
Simulation time 10585359006 ps
CPU time 13.79 seconds
Started Aug 03 05:03:06 PM PDT 24
Finished Aug 03 05:03:19 PM PDT 24
Peak memory 233208 kb
Host smart-4b8153b2-87fb-45f0-9722-1e04989803d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644362293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.644362293
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1543258778
Short name T53
Test name
Test status
Simulation time 30085839 ps
CPU time 0.83 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:02 PM PDT 24
Peak memory 206984 kb
Host smart-35dac722-aa34-4620-b068-1cf35cffb2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543258778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1543258778
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3224963629
Short name T997
Test name
Test status
Simulation time 51006293323 ps
CPU time 83.92 seconds
Started Aug 03 05:03:04 PM PDT 24
Finished Aug 03 05:04:28 PM PDT 24
Peak memory 233220 kb
Host smart-36963b11-f040-4271-b422-d06c4e22357f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224963629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3224963629
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2471371134
Short name T908
Test name
Test status
Simulation time 7481287899 ps
CPU time 54.5 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:56 PM PDT 24
Peak memory 241412 kb
Host smart-39cfa042-5b74-4ae4-99d0-11806ea96881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471371134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2471371134
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1553077002
Short name T697
Test name
Test status
Simulation time 9855177116 ps
CPU time 103.33 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:04:45 PM PDT 24
Peak memory 250772 kb
Host smart-507be2d7-0c50-4662-bb79-4b6855f468b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553077002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1553077002
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.516992021
Short name T207
Test name
Test status
Simulation time 911834806 ps
CPU time 13.33 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:15 PM PDT 24
Peak memory 234972 kb
Host smart-5fc7b3ff-91d1-44ab-a400-4f586c272412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516992021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.516992021
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2639121843
Short name T436
Test name
Test status
Simulation time 38958442 ps
CPU time 0.77 seconds
Started Aug 03 05:03:04 PM PDT 24
Finished Aug 03 05:03:05 PM PDT 24
Peak memory 216312 kb
Host smart-3034cb3a-9b70-44ca-a38f-090bd0635087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639121843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2639121843
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2219615828
Short name T479
Test name
Test status
Simulation time 696552041 ps
CPU time 5.78 seconds
Started Aug 03 05:03:09 PM PDT 24
Finished Aug 03 05:03:14 PM PDT 24
Peak memory 230076 kb
Host smart-f6055a14-6423-4e57-90ff-724b197c0a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219615828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2219615828
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2917099970
Short name T468
Test name
Test status
Simulation time 671391138 ps
CPU time 5.02 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:06 PM PDT 24
Peak memory 237820 kb
Host smart-3d1f1116-e6ec-4bf7-936a-22beb753f60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917099970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2917099970
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2826942521
Short name T685
Test name
Test status
Simulation time 1618199345 ps
CPU time 8.56 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:09 PM PDT 24
Peak memory 233140 kb
Host smart-10e8e969-6ec5-485d-abf8-6d7ad6df28cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826942521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2826942521
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.149152952
Short name T806
Test name
Test status
Simulation time 14903500138 ps
CPU time 17.27 seconds
Started Aug 03 05:03:05 PM PDT 24
Finished Aug 03 05:03:22 PM PDT 24
Peak memory 233108 kb
Host smart-f3d28bdc-5bbe-497d-a59d-80a5be0687ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149152952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.149152952
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.487428116
Short name T928
Test name
Test status
Simulation time 427348367 ps
CPU time 5.92 seconds
Started Aug 03 05:03:02 PM PDT 24
Finished Aug 03 05:03:08 PM PDT 24
Peak memory 220492 kb
Host smart-35cddabb-7fea-4e52-bab3-e7f661686440
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=487428116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.487428116
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3851229094
Short name T152
Test name
Test status
Simulation time 15115592813 ps
CPU time 205.61 seconds
Started Aug 03 05:03:05 PM PDT 24
Finished Aug 03 05:06:36 PM PDT 24
Peak memory 267240 kb
Host smart-c64f5b67-b8f6-4033-ad21-870c9db54069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851229094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3851229094
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1523785406
Short name T840
Test name
Test status
Simulation time 6207586236 ps
CPU time 10.33 seconds
Started Aug 03 05:03:02 PM PDT 24
Finished Aug 03 05:03:12 PM PDT 24
Peak memory 216792 kb
Host smart-0aff4d4d-dff5-492d-af2b-739e80cdbc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523785406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1523785406
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2941105346
Short name T795
Test name
Test status
Simulation time 6857748092 ps
CPU time 14.29 seconds
Started Aug 03 05:03:03 PM PDT 24
Finished Aug 03 05:03:17 PM PDT 24
Peak memory 216752 kb
Host smart-fa8ca897-2ee3-471f-b6af-c8542717e09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941105346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2941105346
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2562481282
Short name T74
Test name
Test status
Simulation time 565067690 ps
CPU time 6.52 seconds
Started Aug 03 05:03:02 PM PDT 24
Finished Aug 03 05:03:09 PM PDT 24
Peak memory 216656 kb
Host smart-c96310f6-fb7d-42fd-9c9f-8589faf6b4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562481282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2562481282
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.780807096
Short name T71
Test name
Test status
Simulation time 1034975624 ps
CPU time 0.94 seconds
Started Aug 03 05:03:06 PM PDT 24
Finished Aug 03 05:03:07 PM PDT 24
Peak memory 206308 kb
Host smart-ff0555f8-271b-4d68-a4bd-2b3a50917436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780807096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.780807096
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3694843384
Short name T760
Test name
Test status
Simulation time 1264014657 ps
CPU time 7.52 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:09 PM PDT 24
Peak memory 233076 kb
Host smart-08046745-d983-4776-8873-be525a185f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694843384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3694843384
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4195231110
Short name T416
Test name
Test status
Simulation time 30599041 ps
CPU time 0.78 seconds
Started Aug 03 05:03:03 PM PDT 24
Finished Aug 03 05:03:04 PM PDT 24
Peak memory 205848 kb
Host smart-045259d0-aac0-4333-98fc-8ca3d2a87748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195231110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4195231110
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1677008031
Short name T972
Test name
Test status
Simulation time 19650467834 ps
CPU time 26.7 seconds
Started Aug 03 05:03:04 PM PDT 24
Finished Aug 03 05:03:30 PM PDT 24
Peak memory 233152 kb
Host smart-2c9bf267-4e79-48b2-8eca-03397fb5fc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677008031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1677008031
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1011827467
Short name T655
Test name
Test status
Simulation time 70760668 ps
CPU time 0.85 seconds
Started Aug 03 05:03:05 PM PDT 24
Finished Aug 03 05:03:06 PM PDT 24
Peak memory 206940 kb
Host smart-37f7e2f9-9d1d-427c-9c93-9e27164edb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011827467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1011827467
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1142725723
Short name T280
Test name
Test status
Simulation time 28549031632 ps
CPU time 115.83 seconds
Started Aug 03 05:03:03 PM PDT 24
Finished Aug 03 05:04:59 PM PDT 24
Peak memory 241380 kb
Host smart-d2ee2609-78de-4aaf-a75d-2562ab0ca848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142725723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1142725723
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1463368287
Short name T503
Test name
Test status
Simulation time 2928040556 ps
CPU time 69.04 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:04:11 PM PDT 24
Peak memory 257420 kb
Host smart-438b52ec-be60-4c1e-a792-8e5f8b44be1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463368287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1463368287
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3279022285
Short name T706
Test name
Test status
Simulation time 27522758213 ps
CPU time 85.35 seconds
Started Aug 03 05:03:04 PM PDT 24
Finished Aug 03 05:04:29 PM PDT 24
Peak memory 241372 kb
Host smart-99998485-f106-4481-8492-6e925377fcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279022285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3279022285
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1183125124
Short name T731
Test name
Test status
Simulation time 4240131257 ps
CPU time 15.36 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:03:16 PM PDT 24
Peak memory 224976 kb
Host smart-63b0f944-ccf4-4784-bfcf-ce1c92f825e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183125124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1183125124
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3549028811
Short name T378
Test name
Test status
Simulation time 138403181 ps
CPU time 0.88 seconds
Started Aug 03 05:03:08 PM PDT 24
Finished Aug 03 05:03:09 PM PDT 24
Peak memory 216344 kb
Host smart-c4221b04-ebef-45bd-a4ff-f6dc991915e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549028811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3549028811
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4065775812
Short name T865
Test name
Test status
Simulation time 2289427464 ps
CPU time 12.21 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:03:12 PM PDT 24
Peak memory 233216 kb
Host smart-68a81355-d967-4d49-afe3-4472395fba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065775812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4065775812
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2947814830
Short name T423
Test name
Test status
Simulation time 305345544 ps
CPU time 5.83 seconds
Started Aug 03 05:03:00 PM PDT 24
Finished Aug 03 05:03:06 PM PDT 24
Peak memory 233128 kb
Host smart-c5c26994-c7b5-4b2e-a549-d2de115252d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947814830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2947814830
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1676444908
Short name T924
Test name
Test status
Simulation time 461352437 ps
CPU time 2.72 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:03:04 PM PDT 24
Peak memory 224780 kb
Host smart-98c95662-d0dd-40e8-aeb4-05c0ee78de5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676444908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1676444908
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2176002767
Short name T842
Test name
Test status
Simulation time 3838406823 ps
CPU time 11.18 seconds
Started Aug 03 05:03:03 PM PDT 24
Finished Aug 03 05:03:15 PM PDT 24
Peak memory 222812 kb
Host smart-4286b94f-1691-4043-be0c-d329a9de43b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2176002767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2176002767
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2236926475
Short name T124
Test name
Test status
Simulation time 12467790495 ps
CPU time 128.7 seconds
Started Aug 03 05:03:01 PM PDT 24
Finished Aug 03 05:05:10 PM PDT 24
Peak memory 256196 kb
Host smart-3c4309b5-a2bf-4e9d-8f3c-7b2e7382ac66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236926475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2236926475
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.906628391
Short name T313
Test name
Test status
Simulation time 23444791157 ps
CPU time 37.34 seconds
Started Aug 03 05:03:05 PM PDT 24
Finished Aug 03 05:03:42 PM PDT 24
Peak memory 217012 kb
Host smart-bc37006d-b152-4118-9a14-ac41901c307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906628391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.906628391
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3477361361
Short name T338
Test name
Test status
Simulation time 11200784207 ps
CPU time 10.66 seconds
Started Aug 03 05:03:08 PM PDT 24
Finished Aug 03 05:03:19 PM PDT 24
Peak memory 216736 kb
Host smart-999fbce4-19c0-4975-9971-4b8f8fea83a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477361361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3477361361
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1150528905
Short name T326
Test name
Test status
Simulation time 61091665 ps
CPU time 1.06 seconds
Started Aug 03 05:03:03 PM PDT 24
Finished Aug 03 05:03:04 PM PDT 24
Peak memory 207924 kb
Host smart-6245702e-b6ae-455c-a801-59165c3f94c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150528905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1150528905
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1410481509
Short name T544
Test name
Test status
Simulation time 102166128 ps
CPU time 0.83 seconds
Started Aug 03 05:03:06 PM PDT 24
Finished Aug 03 05:03:07 PM PDT 24
Peak memory 206384 kb
Host smart-3b2af138-8d15-4483-a0fe-7629f99447e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410481509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1410481509
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3372244517
Short name T777
Test name
Test status
Simulation time 5207341595 ps
CPU time 22.94 seconds
Started Aug 03 05:03:02 PM PDT 24
Finished Aug 03 05:03:25 PM PDT 24
Peak memory 249576 kb
Host smart-b3bda582-a0a4-4a6f-b673-6772f203b1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372244517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3372244517
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4245594990
Short name T650
Test name
Test status
Simulation time 13323479 ps
CPU time 0.72 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:03:13 PM PDT 24
Peak memory 205236 kb
Host smart-97f540ce-69fc-491a-8477-31462304a367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245594990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4245594990
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1449220353
Short name T885
Test name
Test status
Simulation time 845056906 ps
CPU time 10.7 seconds
Started Aug 03 05:03:07 PM PDT 24
Finished Aug 03 05:03:18 PM PDT 24
Peak memory 233168 kb
Host smart-597e36b2-67c7-4021-932b-40790d23e1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449220353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1449220353
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.81981656
Short name T730
Test name
Test status
Simulation time 39020449 ps
CPU time 0.78 seconds
Started Aug 03 05:03:05 PM PDT 24
Finished Aug 03 05:03:06 PM PDT 24
Peak memory 205924 kb
Host smart-1c663574-5c41-455d-941f-9f037865352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81981656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.81981656
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.576126691
Short name T41
Test name
Test status
Simulation time 32890185979 ps
CPU time 259.88 seconds
Started Aug 03 05:03:10 PM PDT 24
Finished Aug 03 05:07:30 PM PDT 24
Peak memory 257328 kb
Host smart-2d5c1b3d-686b-4cb1-bb0d-bf581b5c08b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576126691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.576126691
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2344938225
Short name T7
Test name
Test status
Simulation time 6440224596 ps
CPU time 69.78 seconds
Started Aug 03 05:03:14 PM PDT 24
Finished Aug 03 05:04:24 PM PDT 24
Peak memory 254156 kb
Host smart-28ab6471-849c-4588-ba94-be65c8b32134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344938225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2344938225
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.4032011865
Short name T49
Test name
Test status
Simulation time 1981913438 ps
CPU time 51 seconds
Started Aug 03 05:03:09 PM PDT 24
Finished Aug 03 05:04:00 PM PDT 24
Peak memory 256696 kb
Host smart-4b530405-0d8c-4b39-99b2-2cadf6d22439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032011865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.4032011865
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3305703409
Short name T312
Test name
Test status
Simulation time 170626786 ps
CPU time 6.17 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:03:18 PM PDT 24
Peak memory 233164 kb
Host smart-dfdef246-71cc-4b40-abc5-c521f430a779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305703409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3305703409
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.4072505032
Short name T292
Test name
Test status
Simulation time 7869229458 ps
CPU time 101.96 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:04:54 PM PDT 24
Peak memory 266924 kb
Host smart-8ce85fbf-47b7-4539-9218-6663ccfdb2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072505032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.4072505032
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4015953073
Short name T805
Test name
Test status
Simulation time 3793154797 ps
CPU time 7.69 seconds
Started Aug 03 05:03:13 PM PDT 24
Finished Aug 03 05:03:21 PM PDT 24
Peak memory 219308 kb
Host smart-20adc651-6ba5-4518-88d2-05aacc60db3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015953073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4015953073
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.628331505
Short name T254
Test name
Test status
Simulation time 307513615 ps
CPU time 3.12 seconds
Started Aug 03 05:03:10 PM PDT 24
Finished Aug 03 05:03:13 PM PDT 24
Peak memory 233116 kb
Host smart-2c3c9723-442c-4d8e-9b80-0afece41369c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628331505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.628331505
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2067628405
Short name T196
Test name
Test status
Simulation time 3336808240 ps
CPU time 17.64 seconds
Started Aug 03 05:03:11 PM PDT 24
Finished Aug 03 05:03:29 PM PDT 24
Peak memory 233192 kb
Host smart-27b4e379-913c-499a-b5e8-6337ec76f65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067628405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2067628405
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.975383580
Short name T641
Test name
Test status
Simulation time 296317622 ps
CPU time 6.57 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:03:19 PM PDT 24
Peak memory 233024 kb
Host smart-e59d0e69-bfc8-4420-a0e6-3b909973d921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975383580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.975383580
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.411401506
Short name T829
Test name
Test status
Simulation time 3260481533 ps
CPU time 13.35 seconds
Started Aug 03 05:03:08 PM PDT 24
Finished Aug 03 05:03:21 PM PDT 24
Peak memory 221604 kb
Host smart-f84cc0c8-4c7b-48dd-af99-bfba37123987
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=411401506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.411401506
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.231186535
Short name T887
Test name
Test status
Simulation time 8381781710 ps
CPU time 25.98 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:03:38 PM PDT 24
Peak memory 235740 kb
Host smart-78562cb3-31e1-4792-ba57-dc01f9f7f911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231186535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.231186535
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.799140372
Short name T792
Test name
Test status
Simulation time 3702452100 ps
CPU time 21.2 seconds
Started Aug 03 05:03:02 PM PDT 24
Finished Aug 03 05:03:23 PM PDT 24
Peak memory 217096 kb
Host smart-2b3938ba-3327-4d5a-8936-b7020eec5a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799140372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.799140372
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.234240924
Short name T681
Test name
Test status
Simulation time 5981411840 ps
CPU time 18.72 seconds
Started Aug 03 05:03:02 PM PDT 24
Finished Aug 03 05:03:20 PM PDT 24
Peak memory 216688 kb
Host smart-064c1144-e5da-4f07-ba35-bc84926e40da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234240924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.234240924
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.627142977
Short name T453
Test name
Test status
Simulation time 99599887 ps
CPU time 1.57 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:03:13 PM PDT 24
Peak memory 216664 kb
Host smart-0ef6f7bb-4ac9-4d14-9c0a-8abe5204948d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627142977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.627142977
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4239913545
Short name T898
Test name
Test status
Simulation time 279684687 ps
CPU time 0.92 seconds
Started Aug 03 05:03:13 PM PDT 24
Finished Aug 03 05:03:14 PM PDT 24
Peak memory 207348 kb
Host smart-db9987f9-a82a-45c3-ab1c-d083c061c327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239913545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4239913545
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1171503492
Short name T862
Test name
Test status
Simulation time 13501273400 ps
CPU time 10.39 seconds
Started Aug 03 05:03:10 PM PDT 24
Finished Aug 03 05:03:21 PM PDT 24
Peak memory 239952 kb
Host smart-30dd9c2c-d0e4-40db-a5f6-eea1677b6af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171503492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1171503492
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1337681422
Short name T769
Test name
Test status
Simulation time 17856148 ps
CPU time 0.71 seconds
Started Aug 03 05:03:16 PM PDT 24
Finished Aug 03 05:03:17 PM PDT 24
Peak memory 206132 kb
Host smart-be30e174-8d7a-4c67-badb-b4f219ceb6c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337681422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1337681422
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.407397586
Short name T55
Test name
Test status
Simulation time 136224699 ps
CPU time 2.73 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:03:15 PM PDT 24
Peak memory 233096 kb
Host smart-530537ac-55e8-4835-a90b-dc9d57c35911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407397586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.407397586
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3309608896
Short name T460
Test name
Test status
Simulation time 16561685 ps
CPU time 0.78 seconds
Started Aug 03 05:03:08 PM PDT 24
Finished Aug 03 05:03:09 PM PDT 24
Peak memory 207288 kb
Host smart-1a6d235d-4528-4bb3-b85f-00bbe11aa47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309608896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3309608896
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3352140696
Short name T413
Test name
Test status
Simulation time 20452587 ps
CPU time 0.76 seconds
Started Aug 03 05:03:14 PM PDT 24
Finished Aug 03 05:03:15 PM PDT 24
Peak memory 216040 kb
Host smart-3e639bcd-7af3-4bef-ac95-902a14385a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352140696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3352140696
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3869909565
Short name T477
Test name
Test status
Simulation time 8410001532 ps
CPU time 51.48 seconds
Started Aug 03 05:03:15 PM PDT 24
Finished Aug 03 05:04:07 PM PDT 24
Peak memory 254148 kb
Host smart-7234fd05-d90a-459d-986b-067d9147a0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869909565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3869909565
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2823663147
Short name T470
Test name
Test status
Simulation time 2464093959 ps
CPU time 6.51 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:03:19 PM PDT 24
Peak memory 241308 kb
Host smart-d709cfad-ef3d-4d87-8487-718d4aabeb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823663147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2823663147
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2999360814
Short name T480
Test name
Test status
Simulation time 5846677329 ps
CPU time 12.88 seconds
Started Aug 03 05:03:09 PM PDT 24
Finished Aug 03 05:03:22 PM PDT 24
Peak memory 236192 kb
Host smart-466ee43b-a6fa-4538-83df-0037f69feafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999360814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2999360814
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2454380968
Short name T725
Test name
Test status
Simulation time 226147650 ps
CPU time 3.56 seconds
Started Aug 03 05:03:11 PM PDT 24
Finished Aug 03 05:03:15 PM PDT 24
Peak memory 224832 kb
Host smart-5e6eab3a-fb9b-4ba2-a3bd-109d2b4b1cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454380968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2454380968
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2922818018
Short name T547
Test name
Test status
Simulation time 5038745926 ps
CPU time 9.64 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:03:22 PM PDT 24
Peak memory 233112 kb
Host smart-2c610b57-56e1-4f5b-9606-bbd30bd9eef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922818018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2922818018
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3566548443
Short name T381
Test name
Test status
Simulation time 1664334965 ps
CPU time 6.49 seconds
Started Aug 03 05:03:14 PM PDT 24
Finished Aug 03 05:03:21 PM PDT 24
Peak memory 233104 kb
Host smart-0d98cc62-cc77-4aa8-a035-136be148bc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566548443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3566548443
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2052529482
Short name T843
Test name
Test status
Simulation time 16870767722 ps
CPU time 16.02 seconds
Started Aug 03 05:03:10 PM PDT 24
Finished Aug 03 05:03:27 PM PDT 24
Peak memory 224908 kb
Host smart-8ccd51ff-4632-43a0-988a-a14f0bbc2ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052529482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2052529482
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3486994146
Short name T707
Test name
Test status
Simulation time 106453415 ps
CPU time 3.83 seconds
Started Aug 03 05:03:15 PM PDT 24
Finished Aug 03 05:03:19 PM PDT 24
Peak memory 220616 kb
Host smart-717109d2-7214-4d75-95f8-759c84257061
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3486994146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3486994146
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1740916116
Short name T287
Test name
Test status
Simulation time 142283700773 ps
CPU time 289.95 seconds
Started Aug 03 05:03:15 PM PDT 24
Finished Aug 03 05:08:05 PM PDT 24
Peak memory 249604 kb
Host smart-f2d31f48-c6fe-4bef-aef9-99e49fd1e8c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740916116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1740916116
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3478157324
Short name T913
Test name
Test status
Simulation time 2757532632 ps
CPU time 14.9 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:03:27 PM PDT 24
Peak memory 219676 kb
Host smart-77caa0e2-cab2-470a-9330-365e5d412e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478157324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3478157324
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4246394310
Short name T788
Test name
Test status
Simulation time 40683977418 ps
CPU time 20.6 seconds
Started Aug 03 05:03:13 PM PDT 24
Finished Aug 03 05:03:33 PM PDT 24
Peak memory 216708 kb
Host smart-51d32e74-8649-4619-b45c-77206ef236ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246394310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4246394310
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1886508007
Short name T714
Test name
Test status
Simulation time 10581766 ps
CPU time 0.72 seconds
Started Aug 03 05:03:07 PM PDT 24
Finished Aug 03 05:03:08 PM PDT 24
Peak memory 206036 kb
Host smart-566ae68d-97c3-43c6-a2f9-31c6318354a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886508007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1886508007
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.875702950
Short name T815
Test name
Test status
Simulation time 304234443 ps
CPU time 0.87 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:03:13 PM PDT 24
Peak memory 206284 kb
Host smart-da30bd8e-0881-4b82-8408-d29ae99e7866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875702950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.875702950
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1408936376
Short name T631
Test name
Test status
Simulation time 1525964717 ps
CPU time 3.21 seconds
Started Aug 03 05:03:12 PM PDT 24
Finished Aug 03 05:03:15 PM PDT 24
Peak memory 224988 kb
Host smart-93da4ede-85e6-45fa-8f8f-dc704ccabc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408936376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1408936376
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3126737826
Short name T486
Test name
Test status
Simulation time 19157364 ps
CPU time 0.7 seconds
Started Aug 03 05:03:15 PM PDT 24
Finished Aug 03 05:03:15 PM PDT 24
Peak memory 205784 kb
Host smart-2aae663c-1d03-4411-8f7f-b41c924fcdda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126737826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3126737826
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.559462232
Short name T600
Test name
Test status
Simulation time 34664184 ps
CPU time 2.34 seconds
Started Aug 03 05:03:13 PM PDT 24
Finished Aug 03 05:03:16 PM PDT 24
Peak memory 233080 kb
Host smart-f7dd30ca-c91e-44f2-aaa0-969844956a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559462232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.559462232
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3849047161
Short name T901
Test name
Test status
Simulation time 74800115 ps
CPU time 0.72 seconds
Started Aug 03 05:03:18 PM PDT 24
Finished Aug 03 05:03:19 PM PDT 24
Peak memory 206856 kb
Host smart-12acc4a7-feb3-4315-8636-3143084a50a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849047161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3849047161
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.812952389
Short name T632
Test name
Test status
Simulation time 2390906347 ps
CPU time 21.63 seconds
Started Aug 03 05:03:21 PM PDT 24
Finished Aug 03 05:03:42 PM PDT 24
Peak memory 241360 kb
Host smart-21a6ec38-65b6-431f-94f7-c6154a5751a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812952389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.812952389
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1349986002
Short name T451
Test name
Test status
Simulation time 3644347297 ps
CPU time 65.66 seconds
Started Aug 03 05:03:15 PM PDT 24
Finished Aug 03 05:04:21 PM PDT 24
Peak memory 249812 kb
Host smart-5cc47fb0-73a6-42ae-9890-ce24cba0d7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349986002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1349986002
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2522180534
Short name T858
Test name
Test status
Simulation time 3099127730 ps
CPU time 11.32 seconds
Started Aug 03 05:03:22 PM PDT 24
Finished Aug 03 05:03:34 PM PDT 24
Peak memory 224860 kb
Host smart-4a632345-a01e-42d7-a512-cf9cfd44b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522180534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2522180534
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.328741849
Short name T949
Test name
Test status
Simulation time 258777580 ps
CPU time 3.02 seconds
Started Aug 03 05:03:17 PM PDT 24
Finished Aug 03 05:03:21 PM PDT 24
Peak memory 224964 kb
Host smart-f435549e-227e-4ec8-b896-66b9d3e0636a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328741849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.328741849
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1401743035
Short name T974
Test name
Test status
Simulation time 5070632723 ps
CPU time 24.58 seconds
Started Aug 03 05:03:17 PM PDT 24
Finished Aug 03 05:03:41 PM PDT 24
Peak memory 252104 kb
Host smart-cae8d01b-0b01-4141-845f-7e97a5c9f1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401743035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1401743035
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2869397572
Short name T465
Test name
Test status
Simulation time 118172671 ps
CPU time 1.95 seconds
Started Aug 03 05:03:13 PM PDT 24
Finished Aug 03 05:03:15 PM PDT 24
Peak memory 223580 kb
Host smart-dc49ddf5-3727-401c-bce6-9a5ecef50e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869397572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2869397572
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.887945121
Short name T694
Test name
Test status
Simulation time 7949932824 ps
CPU time 13.86 seconds
Started Aug 03 05:03:19 PM PDT 24
Finished Aug 03 05:03:33 PM PDT 24
Peak memory 241216 kb
Host smart-cd3afc19-3c4c-49ed-b1c5-d9f4690e3a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887945121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.887945121
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3335400511
Short name T996
Test name
Test status
Simulation time 1337627833 ps
CPU time 4.89 seconds
Started Aug 03 05:03:20 PM PDT 24
Finished Aug 03 05:03:25 PM PDT 24
Peak memory 225024 kb
Host smart-84177e78-b165-4d46-a27b-b1c06584986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335400511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3335400511
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.902113092
Short name T990
Test name
Test status
Simulation time 3099582444 ps
CPU time 11.6 seconds
Started Aug 03 05:03:19 PM PDT 24
Finished Aug 03 05:03:31 PM PDT 24
Peak memory 238968 kb
Host smart-a028fad4-7a37-49ea-a29a-b36da34c2786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902113092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.902113092
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3089522059
Short name T871
Test name
Test status
Simulation time 1310456018 ps
CPU time 8.66 seconds
Started Aug 03 05:03:24 PM PDT 24
Finished Aug 03 05:03:33 PM PDT 24
Peak memory 223480 kb
Host smart-29a27e53-a9c3-4509-873b-3982ddcf1f1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3089522059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3089522059
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2166887830
Short name T875
Test name
Test status
Simulation time 353874402 ps
CPU time 1.1 seconds
Started Aug 03 05:03:14 PM PDT 24
Finished Aug 03 05:03:16 PM PDT 24
Peak memory 207524 kb
Host smart-2012a639-1cf0-49a3-b85d-3dbdd4c935da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166887830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2166887830
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1010355046
Short name T500
Test name
Test status
Simulation time 6347740654 ps
CPU time 10.25 seconds
Started Aug 03 05:03:19 PM PDT 24
Finished Aug 03 05:03:30 PM PDT 24
Peak memory 217088 kb
Host smart-3bfa6027-9cb0-411a-a2c9-5b23e3d47464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010355046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1010355046
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2391171976
Short name T822
Test name
Test status
Simulation time 90421513 ps
CPU time 0.7 seconds
Started Aug 03 05:03:15 PM PDT 24
Finished Aug 03 05:03:26 PM PDT 24
Peak memory 206060 kb
Host smart-d02b82f9-8cdd-4612-9054-d676a16c3c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391171976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2391171976
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2634418878
Short name T395
Test name
Test status
Simulation time 256153568 ps
CPU time 2.4 seconds
Started Aug 03 05:03:16 PM PDT 24
Finished Aug 03 05:03:19 PM PDT 24
Peak memory 216680 kb
Host smart-d964632c-a6d2-4ee3-8265-025f2a4e2845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634418878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2634418878
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1606777825
Short name T578
Test name
Test status
Simulation time 98827805 ps
CPU time 0.75 seconds
Started Aug 03 05:03:16 PM PDT 24
Finished Aug 03 05:03:17 PM PDT 24
Peak memory 206368 kb
Host smart-82ec8410-51fa-4a57-b50f-25aa2695afdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606777825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1606777825
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3402147027
Short name T586
Test name
Test status
Simulation time 750897188 ps
CPU time 7.15 seconds
Started Aug 03 05:03:15 PM PDT 24
Finished Aug 03 05:03:22 PM PDT 24
Peak memory 233100 kb
Host smart-0d1c4db1-c299-4637-a53c-cb4fe0a15d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402147027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3402147027
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.377191590
Short name T629
Test name
Test status
Simulation time 12334868 ps
CPU time 0.69 seconds
Started Aug 03 05:03:16 PM PDT 24
Finished Aug 03 05:03:17 PM PDT 24
Peak memory 205816 kb
Host smart-245893ec-3846-4584-ace6-3210a45b3535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377191590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.377191590
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2916498129
Short name T170
Test name
Test status
Simulation time 503593862 ps
CPU time 2.53 seconds
Started Aug 03 05:03:19 PM PDT 24
Finished Aug 03 05:03:22 PM PDT 24
Peak memory 224856 kb
Host smart-bca44042-acda-4e2e-a404-2bc178a34355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916498129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2916498129
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4207681859
Short name T745
Test name
Test status
Simulation time 54503353 ps
CPU time 0.78 seconds
Started Aug 03 05:03:15 PM PDT 24
Finished Aug 03 05:03:16 PM PDT 24
Peak memory 206976 kb
Host smart-11a3a7f4-fd3d-4fef-ba2a-52c472b2a764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207681859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4207681859
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2850940748
Short name T987
Test name
Test status
Simulation time 15426628487 ps
CPU time 71.69 seconds
Started Aug 03 05:03:24 PM PDT 24
Finished Aug 03 05:04:36 PM PDT 24
Peak memory 253824 kb
Host smart-f38b5cf6-b5b2-4be7-ba94-bc2231b8d145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850940748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2850940748
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2560202175
Short name T740
Test name
Test status
Simulation time 9378774848 ps
CPU time 74.2 seconds
Started Aug 03 05:03:21 PM PDT 24
Finished Aug 03 05:04:35 PM PDT 24
Peak memory 233240 kb
Host smart-ea92ada5-2348-43d2-bf90-f26ca341b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560202175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2560202175
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3294067626
Short name T474
Test name
Test status
Simulation time 456535472154 ps
CPU time 253.1 seconds
Started Aug 03 05:03:37 PM PDT 24
Finished Aug 03 05:07:51 PM PDT 24
Peak memory 256264 kb
Host smart-d1cc294b-7d29-406a-9e42-b6d022fa951e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294067626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3294067626
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3172585706
Short name T301
Test name
Test status
Simulation time 1727636537 ps
CPU time 17.49 seconds
Started Aug 03 05:03:19 PM PDT 24
Finished Aug 03 05:03:37 PM PDT 24
Peak memory 233076 kb
Host smart-32884ba2-dd8e-4a77-a20c-fa460fd54215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172585706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3172585706
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.553094525
Short name T722
Test name
Test status
Simulation time 4246965062 ps
CPU time 55.61 seconds
Started Aug 03 05:03:17 PM PDT 24
Finished Aug 03 05:04:12 PM PDT 24
Peak memory 251384 kb
Host smart-77c16fba-bd73-4120-b40f-916d6b77ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553094525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.553094525
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.385349681
Short name T269
Test name
Test status
Simulation time 1220803795 ps
CPU time 6.83 seconds
Started Aug 03 05:03:22 PM PDT 24
Finished Aug 03 05:03:29 PM PDT 24
Peak memory 233124 kb
Host smart-767fdea9-b530-4e49-880f-a0844c1974d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385349681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.385349681
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3809169739
Short name T856
Test name
Test status
Simulation time 9978789955 ps
CPU time 22.72 seconds
Started Aug 03 05:03:17 PM PDT 24
Finished Aug 03 05:03:40 PM PDT 24
Peak memory 241196 kb
Host smart-7de745bd-c2a2-4e86-a472-13e845828e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809169739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3809169739
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.998039959
Short name T298
Test name
Test status
Simulation time 754777356 ps
CPU time 3.66 seconds
Started Aug 03 05:03:20 PM PDT 24
Finished Aug 03 05:03:24 PM PDT 24
Peak memory 225040 kb
Host smart-9421e88d-9cf2-4c5a-90d8-76d1e6980f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998039959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.998039959
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1368714131
Short name T192
Test name
Test status
Simulation time 681515658 ps
CPU time 5.38 seconds
Started Aug 03 05:03:24 PM PDT 24
Finished Aug 03 05:03:30 PM PDT 24
Peak memory 233312 kb
Host smart-e54bf852-0d31-4999-8bf5-49e9e04ac714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368714131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1368714131
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2644999914
Short name T914
Test name
Test status
Simulation time 1855456569 ps
CPU time 11.26 seconds
Started Aug 03 05:03:17 PM PDT 24
Finished Aug 03 05:03:28 PM PDT 24
Peak memory 222720 kb
Host smart-c403cee0-32fc-4617-9b31-1ca565b0e8a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2644999914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2644999914
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.485887476
Short name T150
Test name
Test status
Simulation time 9813198084 ps
CPU time 94.65 seconds
Started Aug 03 05:03:15 PM PDT 24
Finished Aug 03 05:04:50 PM PDT 24
Peak memory 249692 kb
Host smart-19e76c95-8a3a-41b5-bc75-bded6e6e2950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485887476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.485887476
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3813583968
Short name T426
Test name
Test status
Simulation time 184014549 ps
CPU time 3.54 seconds
Started Aug 03 05:03:15 PM PDT 24
Finished Aug 03 05:03:19 PM PDT 24
Peak memory 219512 kb
Host smart-389bfa2b-11dc-4556-be63-11ec2a2a1266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813583968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3813583968
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2472164711
Short name T899
Test name
Test status
Simulation time 13352473443 ps
CPU time 16.15 seconds
Started Aug 03 05:03:13 PM PDT 24
Finished Aug 03 05:03:29 PM PDT 24
Peak memory 216716 kb
Host smart-9648000d-371e-4ecc-9b34-dcacc41e292f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472164711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2472164711
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1005829189
Short name T721
Test name
Test status
Simulation time 240908271 ps
CPU time 2.1 seconds
Started Aug 03 05:03:19 PM PDT 24
Finished Aug 03 05:03:22 PM PDT 24
Peak memory 216572 kb
Host smart-79d81565-6119-4b19-95d3-18bb71665130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005829189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1005829189
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2204170822
Short name T342
Test name
Test status
Simulation time 69907741 ps
CPU time 0.88 seconds
Started Aug 03 05:03:15 PM PDT 24
Finished Aug 03 05:03:16 PM PDT 24
Peak memory 206352 kb
Host smart-363d18eb-6127-481a-97a8-0ab12cb3e3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204170822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2204170822
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.886094542
Short name T419
Test name
Test status
Simulation time 303466468 ps
CPU time 2.11 seconds
Started Aug 03 05:03:16 PM PDT 24
Finished Aug 03 05:03:18 PM PDT 24
Peak memory 224836 kb
Host smart-df048597-533f-4191-b174-8030157aac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886094542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.886094542
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3178342350
Short name T723
Test name
Test status
Simulation time 38372123 ps
CPU time 0.71 seconds
Started Aug 03 05:03:22 PM PDT 24
Finished Aug 03 05:03:23 PM PDT 24
Peak memory 205876 kb
Host smart-8297d59f-eac6-4a3a-8b11-d652ab2f865c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178342350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3178342350
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2437458018
Short name T831
Test name
Test status
Simulation time 305260619 ps
CPU time 4.92 seconds
Started Aug 03 05:03:23 PM PDT 24
Finished Aug 03 05:03:28 PM PDT 24
Peak memory 233152 kb
Host smart-cc871b2e-7486-426d-b4c7-6b11c112ce6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437458018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2437458018
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.981149325
Short name T808
Test name
Test status
Simulation time 27526178 ps
CPU time 0.79 seconds
Started Aug 03 05:03:21 PM PDT 24
Finished Aug 03 05:03:21 PM PDT 24
Peak memory 206948 kb
Host smart-0eae785b-66da-4f4d-870f-5d84a28bfec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981149325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.981149325
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3612087900
Short name T487
Test name
Test status
Simulation time 5048643630 ps
CPU time 22.53 seconds
Started Aug 03 05:03:26 PM PDT 24
Finished Aug 03 05:03:49 PM PDT 24
Peak memory 254084 kb
Host smart-7ec34ca5-69d3-4ad3-a5f3-b6f00cca2bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612087900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3612087900
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2633949746
Short name T555
Test name
Test status
Simulation time 6712322655 ps
CPU time 62.69 seconds
Started Aug 03 05:03:22 PM PDT 24
Finished Aug 03 05:04:25 PM PDT 24
Peak memory 250272 kb
Host smart-d950e75e-ad0b-41eb-b391-9d79ac1d0118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633949746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2633949746
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.207818509
Short name T296
Test name
Test status
Simulation time 46070806560 ps
CPU time 390.84 seconds
Started Aug 03 05:03:46 PM PDT 24
Finished Aug 03 05:10:17 PM PDT 24
Peak memory 255716 kb
Host smart-7f9c7b78-9182-4998-a48a-0a259eab898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207818509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.207818509
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2210664673
Short name T310
Test name
Test status
Simulation time 114870592 ps
CPU time 5.35 seconds
Started Aug 03 05:03:31 PM PDT 24
Finished Aug 03 05:03:37 PM PDT 24
Peak memory 233136 kb
Host smart-406fbcba-8be8-4267-9366-e93f8e8a481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210664673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2210664673
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3548397274
Short name T168
Test name
Test status
Simulation time 84946846765 ps
CPU time 582.51 seconds
Started Aug 03 05:03:38 PM PDT 24
Finished Aug 03 05:13:21 PM PDT 24
Peak memory 256208 kb
Host smart-1e0b59ff-493e-4e31-96a9-01434e360f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548397274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3548397274
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.535299652
Short name T475
Test name
Test status
Simulation time 192677847 ps
CPU time 4.05 seconds
Started Aug 03 05:03:21 PM PDT 24
Finished Aug 03 05:03:25 PM PDT 24
Peak memory 233104 kb
Host smart-ed3bbc49-6b87-43b5-8880-ad538d01f2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535299652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.535299652
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1744039338
Short name T232
Test name
Test status
Simulation time 2678764691 ps
CPU time 22.62 seconds
Started Aug 03 05:03:21 PM PDT 24
Finished Aug 03 05:03:44 PM PDT 24
Peak memory 233168 kb
Host smart-9aff034e-08ca-4a4a-bb13-48a66b6abebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744039338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1744039338
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1006172759
Short name T253
Test name
Test status
Simulation time 608323791 ps
CPU time 4.38 seconds
Started Aug 03 05:03:21 PM PDT 24
Finished Aug 03 05:03:26 PM PDT 24
Peak memory 233132 kb
Host smart-97b1931b-707c-4609-8fcd-b4359f81f505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006172759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1006172759
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.498972570
Short name T809
Test name
Test status
Simulation time 12256034734 ps
CPU time 13.19 seconds
Started Aug 03 05:03:32 PM PDT 24
Finished Aug 03 05:03:46 PM PDT 24
Peak memory 234512 kb
Host smart-a5f59b1c-6d78-4858-95b3-2e3f56a9c5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498972570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.498972570
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.518846190
Short name T110
Test name
Test status
Simulation time 1143360061 ps
CPU time 16.86 seconds
Started Aug 03 05:03:22 PM PDT 24
Finished Aug 03 05:03:39 PM PDT 24
Peak memory 220440 kb
Host smart-9591e381-cc86-446a-ba1b-78e8169bcae8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=518846190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.518846190
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3756019255
Short name T274
Test name
Test status
Simulation time 75663315426 ps
CPU time 619.59 seconds
Started Aug 03 05:03:32 PM PDT 24
Finished Aug 03 05:13:52 PM PDT 24
Peak memory 271312 kb
Host smart-02522b27-7669-4ea4-bf67-4f14089ee86c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756019255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3756019255
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4076517315
Short name T320
Test name
Test status
Simulation time 2282664406 ps
CPU time 18.21 seconds
Started Aug 03 05:03:37 PM PDT 24
Finished Aug 03 05:03:56 PM PDT 24
Peak memory 216628 kb
Host smart-22c4afbe-1658-4392-9bff-2abb3ddb6a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076517315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4076517315
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3784638970
Short name T542
Test name
Test status
Simulation time 5291889567 ps
CPU time 15.49 seconds
Started Aug 03 05:03:18 PM PDT 24
Finished Aug 03 05:03:33 PM PDT 24
Peak memory 216596 kb
Host smart-704a1dee-12e1-475c-ab72-5f9ed10e9ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784638970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3784638970
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2281095124
Short name T321
Test name
Test status
Simulation time 180477167 ps
CPU time 4.45 seconds
Started Aug 03 05:03:27 PM PDT 24
Finished Aug 03 05:03:31 PM PDT 24
Peak memory 216628 kb
Host smart-2d7b9b25-3896-433d-8fa0-0f3e43883bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281095124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2281095124
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.566503205
Short name T417
Test name
Test status
Simulation time 117349962 ps
CPU time 0.84 seconds
Started Aug 03 05:03:25 PM PDT 24
Finished Aug 03 05:03:26 PM PDT 24
Peak memory 206372 kb
Host smart-cd8b04bd-ebd0-456b-b425-5acf73bd45e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566503205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.566503205
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3821760617
Short name T796
Test name
Test status
Simulation time 5073045143 ps
CPU time 4.05 seconds
Started Aug 03 05:03:31 PM PDT 24
Finished Aug 03 05:03:35 PM PDT 24
Peak memory 233200 kb
Host smart-cd11646d-848a-43c8-8c93-337a2eb6cecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821760617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3821760617
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4245690183
Short name T803
Test name
Test status
Simulation time 17008215 ps
CPU time 0.72 seconds
Started Aug 03 05:03:34 PM PDT 24
Finished Aug 03 05:03:35 PM PDT 24
Peak memory 206128 kb
Host smart-e85120b2-52b9-4c25-beb2-8b334b241559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245690183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4245690183
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2153470806
Short name T696
Test name
Test status
Simulation time 80555574 ps
CPU time 2.3 seconds
Started Aug 03 05:03:28 PM PDT 24
Finished Aug 03 05:03:31 PM PDT 24
Peak memory 224936 kb
Host smart-f47e853e-9321-44f0-a6af-0baaefb835f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153470806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2153470806
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3699254486
Short name T370
Test name
Test status
Simulation time 88880140 ps
CPU time 0.77 seconds
Started Aug 03 05:03:27 PM PDT 24
Finished Aug 03 05:03:28 PM PDT 24
Peak memory 207268 kb
Host smart-fb730d11-584e-451e-971a-159c9c314676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699254486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3699254486
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4008607573
Short name T883
Test name
Test status
Simulation time 16322013056 ps
CPU time 141.92 seconds
Started Aug 03 05:03:21 PM PDT 24
Finished Aug 03 05:05:43 PM PDT 24
Peak memory 253516 kb
Host smart-a2f7d2de-8452-470a-ad7e-ed652c212cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008607573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4008607573
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2970509122
Short name T726
Test name
Test status
Simulation time 33297621849 ps
CPU time 336.9 seconds
Started Aug 03 05:03:22 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 268128 kb
Host smart-eeb4807f-9f43-4dfa-befc-142ac9d581d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970509122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2970509122
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1289166724
Short name T51
Test name
Test status
Simulation time 172425762168 ps
CPU time 320.67 seconds
Started Aug 03 05:03:24 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 256168 kb
Host smart-2141a0df-67ae-49b7-9984-262c7cb7e9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289166724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1289166724
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3068254546
Short name T131
Test name
Test status
Simulation time 65751079 ps
CPU time 4.18 seconds
Started Aug 03 05:03:28 PM PDT 24
Finished Aug 03 05:03:32 PM PDT 24
Peak memory 233140 kb
Host smart-4b153d11-c099-49c9-8bfe-9e445c387b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068254546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3068254546
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2686547235
Short name T847
Test name
Test status
Simulation time 50574586526 ps
CPU time 85.11 seconds
Started Aug 03 05:03:33 PM PDT 24
Finished Aug 03 05:04:58 PM PDT 24
Peak memory 241260 kb
Host smart-0fa501e1-fee5-4b3f-ad88-fe2e08a20f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686547235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2686547235
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3692335550
Short name T643
Test name
Test status
Simulation time 2886741027 ps
CPU time 21.02 seconds
Started Aug 03 05:03:22 PM PDT 24
Finished Aug 03 05:03:43 PM PDT 24
Peak memory 224936 kb
Host smart-60ccc19f-1a78-4ede-ad6e-ea5db272e80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692335550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3692335550
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.422135443
Short name T608
Test name
Test status
Simulation time 4927875077 ps
CPU time 17.58 seconds
Started Aug 03 05:03:27 PM PDT 24
Finished Aug 03 05:03:45 PM PDT 24
Peak memory 233140 kb
Host smart-bf81494b-62b7-4f46-b404-e3ad12084539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422135443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.422135443
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3299264877
Short name T427
Test name
Test status
Simulation time 929766386 ps
CPU time 6.51 seconds
Started Aug 03 05:03:30 PM PDT 24
Finished Aug 03 05:03:42 PM PDT 24
Peak memory 224960 kb
Host smart-f1c9743f-0920-4beb-9d91-6a5f143c556d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299264877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3299264877
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.711557055
Short name T525
Test name
Test status
Simulation time 5369561803 ps
CPU time 8.55 seconds
Started Aug 03 05:03:33 PM PDT 24
Finished Aug 03 05:03:41 PM PDT 24
Peak memory 233080 kb
Host smart-09415189-9180-4649-885a-0a4a17d1e050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711557055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.711557055
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3557071003
Short name T912
Test name
Test status
Simulation time 2367591345 ps
CPU time 10.39 seconds
Started Aug 03 05:03:39 PM PDT 24
Finished Aug 03 05:03:49 PM PDT 24
Peak memory 219204 kb
Host smart-9175689d-8cf8-442a-811d-56f6aef191fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3557071003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3557071003
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4009118568
Short name T919
Test name
Test status
Simulation time 40144252391 ps
CPU time 172.6 seconds
Started Aug 03 05:03:25 PM PDT 24
Finished Aug 03 05:06:18 PM PDT 24
Peak memory 257780 kb
Host smart-f1a50942-68aa-423c-895b-209e17d11a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009118568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4009118568
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3312298638
Short name T317
Test name
Test status
Simulation time 20219343914 ps
CPU time 20.53 seconds
Started Aug 03 05:03:22 PM PDT 24
Finished Aug 03 05:03:43 PM PDT 24
Peak memory 216892 kb
Host smart-6cc84ad3-eba3-40b5-a491-534347f15da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312298638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3312298638
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.263248070
Short name T638
Test name
Test status
Simulation time 18270516077 ps
CPU time 14.32 seconds
Started Aug 03 05:03:24 PM PDT 24
Finished Aug 03 05:03:38 PM PDT 24
Peak memory 217680 kb
Host smart-90a2922c-a904-43e0-b428-5f01cf7af3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263248070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.263248070
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.523101313
Short name T633
Test name
Test status
Simulation time 283258152 ps
CPU time 5.47 seconds
Started Aug 03 05:03:21 PM PDT 24
Finished Aug 03 05:03:26 PM PDT 24
Peak memory 216656 kb
Host smart-8aebc9b5-48ee-43bf-8e4a-1cabb4d39d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523101313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.523101313
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.284915235
Short name T711
Test name
Test status
Simulation time 30325822 ps
CPU time 0.81 seconds
Started Aug 03 05:03:21 PM PDT 24
Finished Aug 03 05:03:22 PM PDT 24
Peak memory 206244 kb
Host smart-49cfb52b-a5bd-4677-a344-a2e717b0b755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284915235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.284915235
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2405439217
Short name T937
Test name
Test status
Simulation time 2162528526 ps
CPU time 3.76 seconds
Started Aug 03 05:03:33 PM PDT 24
Finished Aug 03 05:03:37 PM PDT 24
Peak memory 224896 kb
Host smart-b0212048-8b7d-473d-b19f-64f9c8f48507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405439217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2405439217
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2637702798
Short name T481
Test name
Test status
Simulation time 36723473 ps
CPU time 0.71 seconds
Started Aug 03 05:03:37 PM PDT 24
Finished Aug 03 05:03:38 PM PDT 24
Peak memory 205776 kb
Host smart-c6989f46-959b-497e-808f-c4b59a426394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637702798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2637702798
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.622745234
Short name T786
Test name
Test status
Simulation time 159736092 ps
CPU time 2.49 seconds
Started Aug 03 05:03:26 PM PDT 24
Finished Aug 03 05:03:29 PM PDT 24
Peak memory 224836 kb
Host smart-ee6cf026-c188-4c19-b3d6-8e85512989a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622745234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.622745234
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4087347430
Short name T755
Test name
Test status
Simulation time 18506012 ps
CPU time 0.83 seconds
Started Aug 03 05:03:34 PM PDT 24
Finished Aug 03 05:03:35 PM PDT 24
Peak memory 206952 kb
Host smart-f34f6957-64c8-4053-ab9c-53110c5c2ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087347430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4087347430
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1671904572
Short name T157
Test name
Test status
Simulation time 112510032084 ps
CPU time 191.33 seconds
Started Aug 03 05:03:28 PM PDT 24
Finished Aug 03 05:06:39 PM PDT 24
Peak memory 252720 kb
Host smart-442af001-228b-4ac1-975d-db92dd600e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671904572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1671904572
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3092885169
Short name T511
Test name
Test status
Simulation time 6822975463 ps
CPU time 30.07 seconds
Started Aug 03 05:03:27 PM PDT 24
Finished Aug 03 05:03:57 PM PDT 24
Peak memory 252384 kb
Host smart-1771641f-eee6-424c-a152-cc4726d96ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092885169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3092885169
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4179090577
Short name T971
Test name
Test status
Simulation time 9596800980 ps
CPU time 71.81 seconds
Started Aug 03 05:03:39 PM PDT 24
Finished Aug 03 05:04:51 PM PDT 24
Peak memory 254616 kb
Host smart-09139d86-8250-4ff8-beef-a7a18f14431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179090577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4179090577
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3785915189
Short name T909
Test name
Test status
Simulation time 305248229 ps
CPU time 3.33 seconds
Started Aug 03 05:03:33 PM PDT 24
Finished Aug 03 05:03:36 PM PDT 24
Peak memory 233132 kb
Host smart-f1712c0a-6110-4f79-a0ce-f487bd6f0639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785915189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3785915189
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2042892173
Short name T827
Test name
Test status
Simulation time 3991506463 ps
CPU time 48.4 seconds
Started Aug 03 05:03:41 PM PDT 24
Finished Aug 03 05:04:30 PM PDT 24
Peak memory 258888 kb
Host smart-9e936ef5-665e-4df1-a816-fa23984019a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042892173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2042892173
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3919023267
Short name T264
Test name
Test status
Simulation time 243364046 ps
CPU time 3.07 seconds
Started Aug 03 05:03:39 PM PDT 24
Finished Aug 03 05:03:42 PM PDT 24
Peak memory 233136 kb
Host smart-c7d5ee3e-4c3a-4d6f-b642-3515a7473ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919023267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3919023267
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3574971377
Short name T680
Test name
Test status
Simulation time 14657462709 ps
CPU time 36.14 seconds
Started Aug 03 05:03:34 PM PDT 24
Finished Aug 03 05:04:10 PM PDT 24
Peak memory 224828 kb
Host smart-b26293c9-f161-4f4d-bbc8-385ac2226a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574971377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3574971377
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.653382833
Short name T250
Test name
Test status
Simulation time 5355436631 ps
CPU time 11.85 seconds
Started Aug 03 05:03:38 PM PDT 24
Finished Aug 03 05:03:49 PM PDT 24
Peak memory 233196 kb
Host smart-fc0d1dcf-810f-4f69-8be8-3017958a4e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653382833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.653382833
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.975610035
Short name T223
Test name
Test status
Simulation time 203888900 ps
CPU time 2.71 seconds
Started Aug 03 05:03:29 PM PDT 24
Finished Aug 03 05:03:32 PM PDT 24
Peak memory 224912 kb
Host smart-9fd2d2e1-4e5a-40fc-8bc4-d147ff37fae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975610035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.975610035
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4152324154
Short name T672
Test name
Test status
Simulation time 3100313113 ps
CPU time 8.35 seconds
Started Aug 03 05:03:30 PM PDT 24
Finished Aug 03 05:03:39 PM PDT 24
Peak memory 220660 kb
Host smart-351273ec-9960-446c-a031-1b0f8b639bb2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4152324154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4152324154
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.243812888
Short name T907
Test name
Test status
Simulation time 5386015095 ps
CPU time 6.14 seconds
Started Aug 03 05:03:26 PM PDT 24
Finished Aug 03 05:03:33 PM PDT 24
Peak memory 216720 kb
Host smart-ee09e2bc-cb92-4a3a-ac20-1707ac651f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243812888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.243812888
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.835606030
Short name T23
Test name
Test status
Simulation time 1233650957 ps
CPU time 3.48 seconds
Started Aug 03 05:03:28 PM PDT 24
Finished Aug 03 05:03:32 PM PDT 24
Peak memory 216504 kb
Host smart-54d8c468-c717-4ab1-a57f-c9d9e35668e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835606030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.835606030
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3101097789
Short name T628
Test name
Test status
Simulation time 104440602 ps
CPU time 2.15 seconds
Started Aug 03 05:03:30 PM PDT 24
Finished Aug 03 05:03:32 PM PDT 24
Peak memory 216596 kb
Host smart-86b5c1fd-f7aa-4a0f-ba4c-fbb5d508c52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101097789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3101097789
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.915191228
Short name T933
Test name
Test status
Simulation time 80055826 ps
CPU time 0.72 seconds
Started Aug 03 05:03:35 PM PDT 24
Finished Aug 03 05:03:36 PM PDT 24
Peak memory 206336 kb
Host smart-a6c8b015-7a07-4f6c-8042-a75b8b63839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915191228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.915191228
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3292324821
Short name T333
Test name
Test status
Simulation time 73880650 ps
CPU time 2.58 seconds
Started Aug 03 05:03:26 PM PDT 24
Finished Aug 03 05:03:29 PM PDT 24
Peak memory 234828 kb
Host smart-b4990c4e-cd14-4eab-bae0-bb8ae3c4c3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292324821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3292324821
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1255445299
Short name T72
Test name
Test status
Simulation time 19400548 ps
CPU time 0.72 seconds
Started Aug 03 05:01:50 PM PDT 24
Finished Aug 03 05:01:51 PM PDT 24
Peak memory 206176 kb
Host smart-96c1bdc6-b78c-4d8d-baac-9b61007978f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255445299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
255445299
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2734172766
Short name T904
Test name
Test status
Simulation time 110922022 ps
CPU time 3.48 seconds
Started Aug 03 05:01:35 PM PDT 24
Finished Aug 03 05:01:39 PM PDT 24
Peak memory 224908 kb
Host smart-1253a99c-fc4c-4b89-a6da-e15f84534285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734172766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2734172766
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.909100686
Short name T528
Test name
Test status
Simulation time 153765436 ps
CPU time 0.85 seconds
Started Aug 03 05:01:35 PM PDT 24
Finished Aug 03 05:01:36 PM PDT 24
Peak memory 207008 kb
Host smart-f2451a47-1b7b-44a0-891b-2e154780d2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909100686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.909100686
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1304102869
Short name T195
Test name
Test status
Simulation time 44215678892 ps
CPU time 228.12 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:05:39 PM PDT 24
Peak memory 257216 kb
Host smart-2d6dad96-6528-4506-9e17-d5968db01f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304102869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1304102869
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2494638618
Short name T189
Test name
Test status
Simulation time 22743338132 ps
CPU time 164.97 seconds
Started Aug 03 05:01:43 PM PDT 24
Finished Aug 03 05:04:29 PM PDT 24
Peak memory 267860 kb
Host smart-18a2c471-d803-4682-b84b-230b0ded4c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494638618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2494638618
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2570371654
Short name T3
Test name
Test status
Simulation time 1257866576 ps
CPU time 10.33 seconds
Started Aug 03 05:01:37 PM PDT 24
Finished Aug 03 05:01:48 PM PDT 24
Peak memory 233044 kb
Host smart-1e40d747-c26b-4e83-b0cb-982efc6efc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570371654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2570371654
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3556819639
Short name T759
Test name
Test status
Simulation time 388627940 ps
CPU time 0.96 seconds
Started Aug 03 05:01:35 PM PDT 24
Finished Aug 03 05:01:36 PM PDT 24
Peak memory 216344 kb
Host smart-a305b5aa-6143-4802-b08a-7fdbc2d2b8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556819639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3556819639
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4122084434
Short name T227
Test name
Test status
Simulation time 4776436181 ps
CPU time 5 seconds
Started Aug 03 05:01:48 PM PDT 24
Finished Aug 03 05:01:53 PM PDT 24
Peak memory 224932 kb
Host smart-014222f0-8cf6-44a1-8aba-8831f5e554ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122084434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4122084434
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3349020868
Short name T529
Test name
Test status
Simulation time 5290159385 ps
CPU time 17.68 seconds
Started Aug 03 05:01:37 PM PDT 24
Finished Aug 03 05:01:55 PM PDT 24
Peak memory 241112 kb
Host smart-024e45e4-5c4f-467b-aa41-49de0086e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349020868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3349020868
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2915807292
Short name T389
Test name
Test status
Simulation time 109555839 ps
CPU time 2.38 seconds
Started Aug 03 05:01:48 PM PDT 24
Finished Aug 03 05:01:50 PM PDT 24
Peak memory 232792 kb
Host smart-c84dd38b-9f16-4669-a2ad-a0c1a41040a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915807292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2915807292
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1239367647
Short name T129
Test name
Test status
Simulation time 13919754536 ps
CPU time 14.45 seconds
Started Aug 03 05:01:38 PM PDT 24
Finished Aug 03 05:01:52 PM PDT 24
Peak memory 233200 kb
Host smart-735a692e-b93a-4e31-b0ae-6155e8ea9fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239367647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1239367647
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2700187903
Short name T365
Test name
Test status
Simulation time 5745752739 ps
CPU time 12.09 seconds
Started Aug 03 05:01:50 PM PDT 24
Finished Aug 03 05:02:03 PM PDT 24
Peak memory 220712 kb
Host smart-b1d07b8d-bc25-49e6-ba47-9b4c63eccfbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2700187903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2700187903
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3057993444
Short name T66
Test name
Test status
Simulation time 258499736 ps
CPU time 1.13 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:01:52 PM PDT 24
Peak memory 236408 kb
Host smart-73842007-2555-4e04-978b-ade5e4500ffb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057993444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3057993444
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1029123152
Short name T992
Test name
Test status
Simulation time 92491301039 ps
CPU time 508.2 seconds
Started Aug 03 05:02:07 PM PDT 24
Finished Aug 03 05:10:35 PM PDT 24
Peak memory 298800 kb
Host smart-b589c682-06ca-4d76-80e8-097d371f2782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029123152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1029123152
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.242175818
Short name T561
Test name
Test status
Simulation time 5337775048 ps
CPU time 7.48 seconds
Started Aug 03 05:01:39 PM PDT 24
Finished Aug 03 05:01:46 PM PDT 24
Peak memory 216652 kb
Host smart-631cf0ef-3d51-40e5-924f-86bf030d3c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242175818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.242175818
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.714607587
Short name T82
Test name
Test status
Simulation time 564303752 ps
CPU time 2.76 seconds
Started Aug 03 05:01:53 PM PDT 24
Finished Aug 03 05:01:56 PM PDT 24
Peak memory 216648 kb
Host smart-31a0ada7-09d9-40ca-9d0c-986fd04f1fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714607587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.714607587
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3256339518
Short name T988
Test name
Test status
Simulation time 483709655 ps
CPU time 2.6 seconds
Started Aug 03 05:01:36 PM PDT 24
Finished Aug 03 05:01:39 PM PDT 24
Peak memory 216672 kb
Host smart-e798d188-7478-4886-8d29-d51f803e6e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256339518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3256339518
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3999424046
Short name T850
Test name
Test status
Simulation time 211930321 ps
CPU time 0.82 seconds
Started Aug 03 05:01:48 PM PDT 24
Finished Aug 03 05:01:49 PM PDT 24
Peak memory 206340 kb
Host smart-33417748-448f-4ab6-83d6-7f8dafae67b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999424046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3999424046
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3916725412
Short name T841
Test name
Test status
Simulation time 2523834326 ps
CPU time 11.36 seconds
Started Aug 03 05:01:41 PM PDT 24
Finished Aug 03 05:01:53 PM PDT 24
Peak memory 233144 kb
Host smart-96d05dd3-2672-422e-b37c-06bab46db283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916725412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3916725412
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1347534782
Short name T59
Test name
Test status
Simulation time 12982221 ps
CPU time 0.72 seconds
Started Aug 03 05:03:49 PM PDT 24
Finished Aug 03 05:03:50 PM PDT 24
Peak memory 205780 kb
Host smart-2d9c07bd-b83c-4830-a8f6-2adafc3f7563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347534782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1347534782
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.40866406
Short name T616
Test name
Test status
Simulation time 902161443 ps
CPU time 2.38 seconds
Started Aug 03 05:03:30 PM PDT 24
Finished Aug 03 05:03:33 PM PDT 24
Peak memory 224888 kb
Host smart-882d18f3-033a-43b1-a584-2e7618bbaeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40866406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.40866406
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2433343904
Short name T488
Test name
Test status
Simulation time 19034431 ps
CPU time 0.77 seconds
Started Aug 03 05:03:27 PM PDT 24
Finished Aug 03 05:03:27 PM PDT 24
Peak memory 205916 kb
Host smart-a7fd8c19-c0d5-4182-aa9f-801c1b7bcd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433343904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2433343904
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3930659791
Short name T888
Test name
Test status
Simulation time 11156662239 ps
CPU time 88.26 seconds
Started Aug 03 05:03:33 PM PDT 24
Finished Aug 03 05:05:01 PM PDT 24
Peak memory 235468 kb
Host smart-1bfe0864-ff82-499b-b099-7e2dda5b70de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930659791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3930659791
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2784933396
Short name T30
Test name
Test status
Simulation time 83552987286 ps
CPU time 245.26 seconds
Started Aug 03 05:03:36 PM PDT 24
Finished Aug 03 05:07:42 PM PDT 24
Peak memory 253732 kb
Host smart-26640bbc-6a29-4be1-9fd4-1b97c8bf99e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784933396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2784933396
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3279345340
Short name T830
Test name
Test status
Simulation time 30329963103 ps
CPU time 289.26 seconds
Started Aug 03 05:03:38 PM PDT 24
Finished Aug 03 05:08:27 PM PDT 24
Peak memory 252296 kb
Host smart-cc587eb9-b2f1-4f18-a38b-d5429f173d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279345340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3279345340
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1367212537
Short name T823
Test name
Test status
Simulation time 7141603481 ps
CPU time 26.87 seconds
Started Aug 03 05:03:39 PM PDT 24
Finished Aug 03 05:04:06 PM PDT 24
Peak memory 235632 kb
Host smart-db9ec0fc-8555-4585-8d7c-768e009b53a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367212537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1367212537
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2210424257
Short name T551
Test name
Test status
Simulation time 2914074700 ps
CPU time 19.15 seconds
Started Aug 03 05:03:30 PM PDT 24
Finished Aug 03 05:03:49 PM PDT 24
Peak memory 233164 kb
Host smart-3b585c07-a5a8-4dc6-835e-59cbebb2d3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210424257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2210424257
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4039101543
Short name T200
Test name
Test status
Simulation time 1100732179 ps
CPU time 6.29 seconds
Started Aug 03 05:03:32 PM PDT 24
Finished Aug 03 05:03:38 PM PDT 24
Peak memory 219244 kb
Host smart-ed12c019-c8a7-4981-8912-77f7456376d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039101543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4039101543
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2493633550
Short name T771
Test name
Test status
Simulation time 12259410838 ps
CPU time 13.76 seconds
Started Aug 03 05:03:39 PM PDT 24
Finished Aug 03 05:03:53 PM PDT 24
Peak memory 241200 kb
Host smart-246dba61-8ec9-4cec-9159-bd9cc9e54428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493633550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2493633550
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3945120616
Short name T762
Test name
Test status
Simulation time 1350480768 ps
CPU time 10.68 seconds
Started Aug 03 05:03:38 PM PDT 24
Finished Aug 03 05:03:49 PM PDT 24
Peak memory 240184 kb
Host smart-0f36a6e4-d978-42a8-b4ef-537a2166102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945120616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3945120616
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3710599996
Short name T560
Test name
Test status
Simulation time 5714044566 ps
CPU time 7.06 seconds
Started Aug 03 05:03:27 PM PDT 24
Finished Aug 03 05:03:34 PM PDT 24
Peak memory 224972 kb
Host smart-eaf51b19-5ce1-4f43-bedb-60f6fce12854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710599996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3710599996
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1669787623
Short name T400
Test name
Test status
Simulation time 755028685 ps
CPU time 9.92 seconds
Started Aug 03 05:03:28 PM PDT 24
Finished Aug 03 05:03:38 PM PDT 24
Peak memory 221964 kb
Host smart-860db39d-2023-4fb9-857c-54b7998e59cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1669787623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1669787623
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1285505662
Short name T153
Test name
Test status
Simulation time 152525621816 ps
CPU time 220.59 seconds
Started Aug 03 05:03:51 PM PDT 24
Finished Aug 03 05:07:32 PM PDT 24
Peak memory 257804 kb
Host smart-2b53a653-0977-46b3-a046-fec5ca7c913f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285505662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1285505662
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3181927842
Short name T753
Test name
Test status
Simulation time 15956361181 ps
CPU time 20.72 seconds
Started Aug 03 05:03:26 PM PDT 24
Finished Aug 03 05:03:47 PM PDT 24
Peak memory 216580 kb
Host smart-a6c9599e-3d1b-4b2f-a4da-7d0e9a40fb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181927842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3181927842
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3375244899
Short name T970
Test name
Test status
Simulation time 191833217 ps
CPU time 1.72 seconds
Started Aug 03 05:03:34 PM PDT 24
Finished Aug 03 05:03:36 PM PDT 24
Peak memory 208248 kb
Host smart-7913e16f-8bc5-4bc9-b2d4-04286c3c3d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375244899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3375244899
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4064333820
Short name T802
Test name
Test status
Simulation time 147496570 ps
CPU time 0.7 seconds
Started Aug 03 05:03:32 PM PDT 24
Finished Aug 03 05:03:33 PM PDT 24
Peak memory 205952 kb
Host smart-72c48290-ba9b-4c6e-9e58-4df7d3d15cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064333820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4064333820
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3533862125
Short name T662
Test name
Test status
Simulation time 84498246 ps
CPU time 0.88 seconds
Started Aug 03 05:03:31 PM PDT 24
Finished Aug 03 05:03:31 PM PDT 24
Peak memory 206308 kb
Host smart-9f523466-cfce-4c29-a108-e588d5aea180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533862125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3533862125
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3792318029
Short name T669
Test name
Test status
Simulation time 1988750392 ps
CPU time 7.98 seconds
Started Aug 03 05:03:26 PM PDT 24
Finished Aug 03 05:03:35 PM PDT 24
Peak memory 233176 kb
Host smart-56e2ac0d-3942-4b54-968b-bfc308ea0eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792318029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3792318029
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3897032444
Short name T467
Test name
Test status
Simulation time 34658251 ps
CPU time 0.74 seconds
Started Aug 03 05:03:39 PM PDT 24
Finished Aug 03 05:03:40 PM PDT 24
Peak memory 205868 kb
Host smart-a6f8da72-279f-488f-b5e3-bf4aed888e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897032444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3897032444
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.858187769
Short name T548
Test name
Test status
Simulation time 598568956 ps
CPU time 2.83 seconds
Started Aug 03 05:03:37 PM PDT 24
Finished Aug 03 05:03:40 PM PDT 24
Peak memory 224816 kb
Host smart-f3b18b84-17f7-4cbf-8e4d-d75a47314862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858187769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.858187769
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1750593194
Short name T678
Test name
Test status
Simulation time 62381528 ps
CPU time 0.8 seconds
Started Aug 03 05:03:42 PM PDT 24
Finished Aug 03 05:03:43 PM PDT 24
Peak memory 207252 kb
Host smart-58b0e2ea-c01a-4fb0-affa-883110bfa240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750593194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1750593194
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3927913122
Short name T612
Test name
Test status
Simulation time 843634400 ps
CPU time 17.13 seconds
Started Aug 03 05:03:38 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 234632 kb
Host smart-741a2659-fbee-4e7b-8699-02d3df710f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927913122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3927913122
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4151760451
Short name T158
Test name
Test status
Simulation time 2640991798 ps
CPU time 68.25 seconds
Started Aug 03 05:03:46 PM PDT 24
Finished Aug 03 05:04:54 PM PDT 24
Peak memory 249680 kb
Host smart-e5418e4f-d607-4b62-a773-d27c4d9f631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151760451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4151760451
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3027600773
Short name T799
Test name
Test status
Simulation time 3911873648 ps
CPU time 46.53 seconds
Started Aug 03 05:03:49 PM PDT 24
Finished Aug 03 05:04:36 PM PDT 24
Peak memory 249572 kb
Host smart-915169ac-c082-4e22-8107-47aa4f7ccfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027600773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3027600773
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.947027372
Short name T190
Test name
Test status
Simulation time 25744863508 ps
CPU time 108.88 seconds
Started Aug 03 05:03:37 PM PDT 24
Finished Aug 03 05:05:26 PM PDT 24
Peak memory 249492 kb
Host smart-d4f732dc-7cc6-4520-9b48-1cd1a92bd3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947027372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.947027372
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1480016492
Short name T825
Test name
Test status
Simulation time 484088299 ps
CPU time 7.27 seconds
Started Aug 03 05:03:44 PM PDT 24
Finished Aug 03 05:03:52 PM PDT 24
Peak memory 233072 kb
Host smart-d735194d-4852-46bc-b07c-5156babd2cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480016492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1480016492
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2828946677
Short name T447
Test name
Test status
Simulation time 3802999877 ps
CPU time 32.2 seconds
Started Aug 03 05:03:37 PM PDT 24
Finished Aug 03 05:04:10 PM PDT 24
Peak memory 224984 kb
Host smart-4e31b7dc-8325-4db9-8e5d-5f8387dac474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828946677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2828946677
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1870073263
Short name T414
Test name
Test status
Simulation time 15196671833 ps
CPU time 10.47 seconds
Started Aug 03 05:03:41 PM PDT 24
Finished Aug 03 05:03:52 PM PDT 24
Peak memory 233200 kb
Host smart-7b1dff14-f324-4db1-ab1c-cd0a629314dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870073263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1870073263
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1612996818
Short name T896
Test name
Test status
Simulation time 1525160141 ps
CPU time 7.27 seconds
Started Aug 03 05:03:41 PM PDT 24
Finished Aug 03 05:03:48 PM PDT 24
Peak memory 232996 kb
Host smart-5acd0e33-a779-4d35-aec7-5e6c0a3bca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612996818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1612996818
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.418736399
Short name T568
Test name
Test status
Simulation time 691205359 ps
CPU time 4.93 seconds
Started Aug 03 05:03:37 PM PDT 24
Finished Aug 03 05:03:42 PM PDT 24
Peak memory 223636 kb
Host smart-60eac8fe-a591-40e0-ad33-1fc661a40be0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=418736399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.418736399
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3399518222
Short name T439
Test name
Test status
Simulation time 37377335 ps
CPU time 0.87 seconds
Started Aug 03 05:03:41 PM PDT 24
Finished Aug 03 05:03:42 PM PDT 24
Peak memory 206328 kb
Host smart-bf00f425-9759-4f8d-984d-05597663ddf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399518222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3399518222
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1066326441
Short name T324
Test name
Test status
Simulation time 13055064289 ps
CPU time 18.31 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:04:09 PM PDT 24
Peak memory 220500 kb
Host smart-aa045dfa-6116-4de6-a2e7-f0301624d7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066326441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1066326441
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2522236918
Short name T627
Test name
Test status
Simulation time 4492555710 ps
CPU time 11.59 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:04:04 PM PDT 24
Peak memory 216700 kb
Host smart-ce5cab79-01ce-45d2-aa5f-ab982cb73b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522236918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2522236918
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1318771795
Short name T128
Test name
Test status
Simulation time 562378087 ps
CPU time 6.7 seconds
Started Aug 03 05:03:39 PM PDT 24
Finished Aug 03 05:03:46 PM PDT 24
Peak memory 216704 kb
Host smart-c5775d5d-de12-4ff1-9b08-0d355dbc388f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318771795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1318771795
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.4215396666
Short name T798
Test name
Test status
Simulation time 14992882 ps
CPU time 0.74 seconds
Started Aug 03 05:03:36 PM PDT 24
Finished Aug 03 05:03:37 PM PDT 24
Peak memory 206316 kb
Host smart-be515d3c-810b-43f5-a538-35442cb09798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215396666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.4215396666
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1950689938
Short name T171
Test name
Test status
Simulation time 628078414 ps
CPU time 2.29 seconds
Started Aug 03 05:03:40 PM PDT 24
Finished Aug 03 05:03:42 PM PDT 24
Peak memory 225104 kb
Host smart-50e92d27-1e27-46a6-a204-56932ba28319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950689938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1950689938
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3782408946
Short name T390
Test name
Test status
Simulation time 158262238 ps
CPU time 0.71 seconds
Started Aug 03 05:03:49 PM PDT 24
Finished Aug 03 05:03:50 PM PDT 24
Peak memory 205796 kb
Host smart-9db232b3-e9f1-4d9f-94f2-71d5c629f6e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782408946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3782408946
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.227938469
Short name T671
Test name
Test status
Simulation time 157574085 ps
CPU time 3 seconds
Started Aug 03 05:03:40 PM PDT 24
Finished Aug 03 05:03:43 PM PDT 24
Peak memory 233064 kb
Host smart-73138e95-d2b9-4b20-b83e-61219531963c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227938469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.227938469
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3974636569
Short name T10
Test name
Test status
Simulation time 46554714 ps
CPU time 0.75 seconds
Started Aug 03 05:03:37 PM PDT 24
Finished Aug 03 05:03:38 PM PDT 24
Peak memory 206960 kb
Host smart-9df80426-e21f-4760-80a8-ba26a02b35c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974636569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3974636569
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4098446667
Short name T249
Test name
Test status
Simulation time 23574149648 ps
CPU time 40.1 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:04:31 PM PDT 24
Peak memory 233024 kb
Host smart-b8e049ad-4e4e-4d24-ba91-b157d0d1edea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098446667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4098446667
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.121362384
Short name T756
Test name
Test status
Simulation time 30716996125 ps
CPU time 209.75 seconds
Started Aug 03 05:03:42 PM PDT 24
Finished Aug 03 05:07:12 PM PDT 24
Peak memory 249564 kb
Host smart-aaef5093-ad06-4cda-a4f4-55086e924546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121362384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.121362384
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1884312136
Short name T596
Test name
Test status
Simulation time 13417966641 ps
CPU time 147.46 seconds
Started Aug 03 05:03:40 PM PDT 24
Finished Aug 03 05:06:07 PM PDT 24
Peak memory 250692 kb
Host smart-e2695b50-24fb-4146-af15-a2367b009684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884312136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1884312136
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2179602444
Short name T530
Test name
Test status
Simulation time 474384011 ps
CPU time 10.53 seconds
Started Aug 03 05:03:40 PM PDT 24
Finished Aug 03 05:03:51 PM PDT 24
Peak memory 241312 kb
Host smart-4b71c374-f100-49dc-b97f-87e72d2b556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179602444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2179602444
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1754445988
Short name T282
Test name
Test status
Simulation time 7970856655 ps
CPU time 105.93 seconds
Started Aug 03 05:03:37 PM PDT 24
Finished Aug 03 05:05:23 PM PDT 24
Peak memory 255016 kb
Host smart-724b997c-2d07-40eb-87f1-458703649a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754445988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1754445988
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1288337220
Short name T380
Test name
Test status
Simulation time 4798015821 ps
CPU time 19.06 seconds
Started Aug 03 05:03:35 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 233088 kb
Host smart-fb762b12-5f2a-4c27-acf4-4da6b2bec68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288337220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1288337220
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2942371068
Short name T266
Test name
Test status
Simulation time 528771110 ps
CPU time 3.37 seconds
Started Aug 03 05:03:37 PM PDT 24
Finished Aug 03 05:03:40 PM PDT 24
Peak memory 233172 kb
Host smart-581a43aa-05f0-41f7-b067-7357d0f296b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942371068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2942371068
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1939955558
Short name T374
Test name
Test status
Simulation time 877219370 ps
CPU time 5.92 seconds
Started Aug 03 05:03:39 PM PDT 24
Finished Aug 03 05:03:45 PM PDT 24
Peak memory 233108 kb
Host smart-ab7e6ff4-1aad-47c2-ac4c-8b14c6d56184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939955558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1939955558
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1163718464
Short name T717
Test name
Test status
Simulation time 976121221 ps
CPU time 5.89 seconds
Started Aug 03 05:03:41 PM PDT 24
Finished Aug 03 05:03:47 PM PDT 24
Peak memory 233176 kb
Host smart-b65aec7e-28ab-432d-86bf-45873a5bae59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163718464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1163718464
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2876309618
Short name T688
Test name
Test status
Simulation time 670531255 ps
CPU time 9.46 seconds
Started Aug 03 05:03:37 PM PDT 24
Finished Aug 03 05:03:47 PM PDT 24
Peak memory 223448 kb
Host smart-c407bcf9-a1f6-4feb-a6f0-dac060367e91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2876309618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2876309618
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1411452223
Short name T149
Test name
Test status
Simulation time 2139962936 ps
CPU time 33.13 seconds
Started Aug 03 05:03:44 PM PDT 24
Finished Aug 03 05:04:17 PM PDT 24
Peak memory 241352 kb
Host smart-76d0eed3-6291-421d-9579-9d10024ea59e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411452223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1411452223
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3214619116
Short name T315
Test name
Test status
Simulation time 14260079653 ps
CPU time 41.14 seconds
Started Aug 03 05:03:38 PM PDT 24
Finished Aug 03 05:04:19 PM PDT 24
Peak memory 216688 kb
Host smart-2db62980-8e86-4ed6-bdd6-381f3b773ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214619116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3214619116
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3251468462
Short name T557
Test name
Test status
Simulation time 212681326 ps
CPU time 1.62 seconds
Started Aug 03 05:03:46 PM PDT 24
Finished Aug 03 05:03:48 PM PDT 24
Peak memory 208224 kb
Host smart-84b5e627-fd01-42d6-8eb7-a759b68ed8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251468462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3251468462
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.157693590
Short name T482
Test name
Test status
Simulation time 67655338 ps
CPU time 1.17 seconds
Started Aug 03 05:03:38 PM PDT 24
Finished Aug 03 05:03:40 PM PDT 24
Peak memory 208256 kb
Host smart-f11c53a0-27d3-4744-8540-0cfcb509f042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157693590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.157693590
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.519275896
Short name T375
Test name
Test status
Simulation time 134947989 ps
CPU time 0.88 seconds
Started Aug 03 05:03:39 PM PDT 24
Finished Aug 03 05:03:40 PM PDT 24
Peak memory 207248 kb
Host smart-3a2c651b-1d14-4870-b8b3-0655844c0bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519275896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.519275896
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2089969227
Short name T397
Test name
Test status
Simulation time 339059531 ps
CPU time 2.68 seconds
Started Aug 03 05:03:40 PM PDT 24
Finished Aug 03 05:03:42 PM PDT 24
Peak memory 241300 kb
Host smart-0d64f306-9b7b-4ac2-8da7-172921496ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089969227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2089969227
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1700072122
Short name T592
Test name
Test status
Simulation time 12949352 ps
CPU time 0.71 seconds
Started Aug 03 05:03:49 PM PDT 24
Finished Aug 03 05:03:49 PM PDT 24
Peak memory 205816 kb
Host smart-206956a0-faa4-465f-997e-d12fdcd448e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700072122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1700072122
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2671357093
Short name T492
Test name
Test status
Simulation time 2877406824 ps
CPU time 14.33 seconds
Started Aug 03 05:03:40 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 224952 kb
Host smart-cfa8bba1-9efd-47ef-aede-d6ed5f6564c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671357093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2671357093
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1849919370
Short name T402
Test name
Test status
Simulation time 48679769 ps
CPU time 0.77 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:03:51 PM PDT 24
Peak memory 207284 kb
Host smart-99004efe-d7c5-42ca-bb5f-14983403f8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849919370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1849919370
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2902134345
Short name T776
Test name
Test status
Simulation time 5729126674 ps
CPU time 42.89 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:04:33 PM PDT 24
Peak memory 234292 kb
Host smart-04a5f42c-e7f4-42cd-bcda-1ec9212a1cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902134345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2902134345
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3828601484
Short name T550
Test name
Test status
Simulation time 92996003086 ps
CPU time 91.83 seconds
Started Aug 03 05:03:40 PM PDT 24
Finished Aug 03 05:05:12 PM PDT 24
Peak memory 233236 kb
Host smart-2095bfd1-33ea-497d-8cc0-bb752b6b8380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828601484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3828601484
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2629269388
Short name T957
Test name
Test status
Simulation time 21026214361 ps
CPU time 86.82 seconds
Started Aug 03 05:03:45 PM PDT 24
Finished Aug 03 05:05:12 PM PDT 24
Peak memory 262424 kb
Host smart-c39c53a3-79e6-4898-ab55-91dfb57a3eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629269388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2629269388
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2707222385
Short name T801
Test name
Test status
Simulation time 9756782978 ps
CPU time 34.19 seconds
Started Aug 03 05:03:43 PM PDT 24
Finished Aug 03 05:04:17 PM PDT 24
Peak memory 224936 kb
Host smart-64c51f20-c7dd-4cfc-a795-bfcb1a97fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707222385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2707222385
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2707448247
Short name T277
Test name
Test status
Simulation time 3413199363 ps
CPU time 11.18 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:04:03 PM PDT 24
Peak memory 233160 kb
Host smart-7c97d7d3-6400-435a-91d3-4beebb25cf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707448247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2707448247
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3666387528
Short name T228
Test name
Test status
Simulation time 4366848864 ps
CPU time 20.85 seconds
Started Aug 03 05:03:48 PM PDT 24
Finished Aug 03 05:04:09 PM PDT 24
Peak memory 224992 kb
Host smart-c8f5d561-1dda-4972-be20-e69d964d5fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666387528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3666387528
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.805356941
Short name T727
Test name
Test status
Simulation time 7829946183 ps
CPU time 60.82 seconds
Started Aug 03 05:03:42 PM PDT 24
Finished Aug 03 05:04:43 PM PDT 24
Peak memory 251128 kb
Host smart-a62451f3-8c68-4b78-b14c-459226a791d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805356941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.805356941
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1743327540
Short name T429
Test name
Test status
Simulation time 109539445 ps
CPU time 2.56 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:03:53 PM PDT 24
Peak memory 232560 kb
Host smart-db17953e-e548-48e2-97e7-b54d93d34175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743327540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1743327540
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2624995192
Short name T936
Test name
Test status
Simulation time 12630355240 ps
CPU time 6.27 seconds
Started Aug 03 05:03:45 PM PDT 24
Finished Aug 03 05:03:51 PM PDT 24
Peak memory 233184 kb
Host smart-d754bacf-459f-4048-9559-deb100b803e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624995192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2624995192
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3117031048
Short name T575
Test name
Test status
Simulation time 1067866038 ps
CPU time 9.69 seconds
Started Aug 03 05:03:53 PM PDT 24
Finished Aug 03 05:04:03 PM PDT 24
Peak memory 220456 kb
Host smart-727f1404-eef8-46ef-883a-abefc02f17b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3117031048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3117031048
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3904926496
Short name T466
Test name
Test status
Simulation time 1160072091 ps
CPU time 3.06 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 216420 kb
Host smart-e7fd5792-5b18-4a2a-adc4-1c79c1fb4d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904926496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3904926496
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.960882649
Short name T22
Test name
Test status
Simulation time 138450072 ps
CPU time 1.54 seconds
Started Aug 03 05:03:41 PM PDT 24
Finished Aug 03 05:03:43 PM PDT 24
Peak memory 208236 kb
Host smart-d35e5a92-75f9-4178-93ca-6b43f0df579d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960882649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.960882649
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1420697853
Short name T689
Test name
Test status
Simulation time 322274802 ps
CPU time 3.05 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 216600 kb
Host smart-fe9c4b9c-baa8-4ec9-b95b-2015cc96d376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420697853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1420697853
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1398429933
Short name T682
Test name
Test status
Simulation time 13191655 ps
CPU time 0.7 seconds
Started Aug 03 05:03:45 PM PDT 24
Finished Aug 03 05:03:46 PM PDT 24
Peak memory 206132 kb
Host smart-5ba26ac0-dcfe-489c-8f99-040fc4ec9609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398429933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1398429933
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1141120536
Short name T993
Test name
Test status
Simulation time 3874116976 ps
CPU time 7.97 seconds
Started Aug 03 05:03:49 PM PDT 24
Finished Aug 03 05:03:57 PM PDT 24
Peak memory 233204 kb
Host smart-3fa93b52-abff-4482-a71a-70bad56ce37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141120536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1141120536
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2285597323
Short name T963
Test name
Test status
Simulation time 16206180 ps
CPU time 0.75 seconds
Started Aug 03 05:03:42 PM PDT 24
Finished Aug 03 05:03:43 PM PDT 24
Peak memory 205880 kb
Host smart-367c2ac2-789a-459e-af2b-1342bf3871ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285597323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2285597323
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1426250625
Short name T1001
Test name
Test status
Simulation time 1215368642 ps
CPU time 5.33 seconds
Started Aug 03 05:03:43 PM PDT 24
Finished Aug 03 05:03:48 PM PDT 24
Peak memory 233112 kb
Host smart-4217801c-119e-4135-8c32-f0d78c19fbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426250625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1426250625
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2819800722
Short name T793
Test name
Test status
Simulation time 59459033 ps
CPU time 0.79 seconds
Started Aug 03 05:03:43 PM PDT 24
Finished Aug 03 05:03:44 PM PDT 24
Peak memory 206964 kb
Host smart-f1d28b66-ce3e-4973-ae6c-ef6f0deb9a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819800722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2819800722
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3705119049
Short name T76
Test name
Test status
Simulation time 1361461009 ps
CPU time 14.1 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:04:11 PM PDT 24
Peak memory 235936 kb
Host smart-e2b5883d-412c-4337-89ab-0fac5d1de429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705119049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3705119049
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1144800905
Short name T220
Test name
Test status
Simulation time 35963523744 ps
CPU time 108.96 seconds
Started Aug 03 05:03:44 PM PDT 24
Finished Aug 03 05:05:33 PM PDT 24
Peak memory 265020 kb
Host smart-d147ea1d-adf6-4a13-aca7-786d8b1c3d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144800905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1144800905
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3397356446
Short name T930
Test name
Test status
Simulation time 22060301070 ps
CPU time 177.57 seconds
Started Aug 03 05:03:51 PM PDT 24
Finished Aug 03 05:06:48 PM PDT 24
Peak memory 257804 kb
Host smart-a6ee7da9-d67e-419e-be4e-0bce252e9ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397356446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3397356446
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_intercept.613501001
Short name T418
Test name
Test status
Simulation time 11714472173 ps
CPU time 9.16 seconds
Started Aug 03 05:03:47 PM PDT 24
Finished Aug 03 05:03:56 PM PDT 24
Peak memory 224820 kb
Host smart-0549070d-25c0-446a-8a54-701c5d2c0066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613501001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.613501001
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2045664271
Short name T140
Test name
Test status
Simulation time 217154564 ps
CPU time 2.4 seconds
Started Aug 03 05:03:49 PM PDT 24
Finished Aug 03 05:03:52 PM PDT 24
Peak memory 232792 kb
Host smart-ee559b49-0960-40e7-92ac-234e10492d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045664271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2045664271
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2954292353
Short name T657
Test name
Test status
Simulation time 5866576779 ps
CPU time 10.51 seconds
Started Aug 03 05:03:41 PM PDT 24
Finished Aug 03 05:03:52 PM PDT 24
Peak memory 224824 kb
Host smart-9704bcbd-2776-4fae-82a2-0844a39c7372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954292353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2954292353
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1530188116
Short name T97
Test name
Test status
Simulation time 4564738808 ps
CPU time 13.48 seconds
Started Aug 03 05:03:40 PM PDT 24
Finished Aug 03 05:03:53 PM PDT 24
Peak memory 225040 kb
Host smart-979b8613-7c15-49c4-850c-2b844cf74c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530188116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1530188116
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1432680270
Short name T748
Test name
Test status
Simulation time 2101731339 ps
CPU time 4.17 seconds
Started Aug 03 05:03:51 PM PDT 24
Finished Aug 03 05:03:56 PM PDT 24
Peak memory 223588 kb
Host smart-3815fe73-c974-4098-8ab0-9f37e14c8eec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1432680270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1432680270
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2120993859
Short name T703
Test name
Test status
Simulation time 493697602 ps
CPU time 4.06 seconds
Started Aug 03 05:03:47 PM PDT 24
Finished Aug 03 05:03:51 PM PDT 24
Peak memory 216620 kb
Host smart-fba5b66b-e9dd-4c02-9e24-806cf8af1cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120993859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2120993859
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1927851089
Short name T597
Test name
Test status
Simulation time 19556436704 ps
CPU time 15.31 seconds
Started Aug 03 05:03:46 PM PDT 24
Finished Aug 03 05:04:01 PM PDT 24
Peak memory 216740 kb
Host smart-6514341e-ffc4-472a-8f82-df62d212cae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927851089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1927851089
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2476651505
Short name T458
Test name
Test status
Simulation time 1741319915 ps
CPU time 3.86 seconds
Started Aug 03 05:03:51 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 216684 kb
Host smart-31b3077d-682d-4542-9d2e-c28921eb968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476651505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2476651505
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1054914227
Short name T877
Test name
Test status
Simulation time 57962576 ps
CPU time 0.88 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:03:53 PM PDT 24
Peak memory 206368 kb
Host smart-f88e8cb7-97ef-43b7-b5c1-5ba2cb29b180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054914227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1054914227
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3180735484
Short name T226
Test name
Test status
Simulation time 2604966818 ps
CPU time 8.67 seconds
Started Aug 03 05:03:45 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 234356 kb
Host smart-8d6ec347-827e-466c-96d9-cbadef1464b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180735484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3180735484
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1811714244
Short name T709
Test name
Test status
Simulation time 20650612 ps
CPU time 0.78 seconds
Started Aug 03 05:03:55 PM PDT 24
Finished Aug 03 05:03:56 PM PDT 24
Peak memory 205132 kb
Host smart-8f5865d5-34d8-460f-99b5-f16767f3e466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811714244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1811714244
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1507913930
Short name T234
Test name
Test status
Simulation time 691954245 ps
CPU time 3.95 seconds
Started Aug 03 05:03:53 PM PDT 24
Finished Aug 03 05:03:57 PM PDT 24
Peak memory 224848 kb
Host smart-75cec6c0-9457-4edb-96a5-603e9bc806ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507913930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1507913930
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4249986399
Short name T491
Test name
Test status
Simulation time 13938784 ps
CPU time 0.77 seconds
Started Aug 03 05:03:51 PM PDT 24
Finished Aug 03 05:03:52 PM PDT 24
Peak memory 207296 kb
Host smart-51c678e7-46f7-4c3f-b924-6a8670e978f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249986399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4249986399
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1161729516
Short name T272
Test name
Test status
Simulation time 385748159272 ps
CPU time 431.61 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:11:06 PM PDT 24
Peak memory 257684 kb
Host smart-9b0de65e-5ab9-4408-974e-8eae12e20dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161729516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1161729516
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2112826250
Short name T749
Test name
Test status
Simulation time 15797505281 ps
CPU time 54.49 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:04:49 PM PDT 24
Peak memory 250560 kb
Host smart-ca222ce3-a92d-4f6e-956b-d2cc46634738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112826250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2112826250
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2256136845
Short name T297
Test name
Test status
Simulation time 23361966626 ps
CPU time 108.19 seconds
Started Aug 03 05:03:55 PM PDT 24
Finished Aug 03 05:05:44 PM PDT 24
Peak memory 257748 kb
Host smart-96cc1d11-5dc3-4dae-866c-756e6cb0d4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256136845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2256136845
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3289576243
Short name T430
Test name
Test status
Simulation time 137046520 ps
CPU time 4.35 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 224908 kb
Host smart-3bd20451-1c11-4188-8bb7-7d63c45c5e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289576243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3289576243
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.957953842
Short name T34
Test name
Test status
Simulation time 58812202693 ps
CPU time 403.16 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:10:37 PM PDT 24
Peak memory 257656 kb
Host smart-3ce1bab2-e4da-4630-9d0a-c9bdb4cce436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957953842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.957953842
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1000632121
Short name T237
Test name
Test status
Simulation time 3712612623 ps
CPU time 23.43 seconds
Started Aug 03 05:03:42 PM PDT 24
Finished Aug 03 05:04:05 PM PDT 24
Peak memory 233204 kb
Host smart-3ebc3735-c4e4-41fe-ba81-5523c2d8c4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000632121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1000632121
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1263300027
Short name T448
Test name
Test status
Simulation time 13426451368 ps
CPU time 31.34 seconds
Started Aug 03 05:03:40 PM PDT 24
Finished Aug 03 05:04:12 PM PDT 24
Peak memory 233108 kb
Host smart-21bd21b5-944b-431a-bb8d-4fc927d2fd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263300027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1263300027
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1994501830
Short name T624
Test name
Test status
Simulation time 162953950 ps
CPU time 4.06 seconds
Started Aug 03 05:03:53 PM PDT 24
Finished Aug 03 05:03:57 PM PDT 24
Peak memory 241172 kb
Host smart-e48552e3-ab2f-4a4a-a0be-046ab1b7622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994501830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1994501830
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2087963250
Short name T484
Test name
Test status
Simulation time 3581174442 ps
CPU time 6.22 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:04:02 PM PDT 24
Peak memory 224976 kb
Host smart-eddb2d97-9aca-400a-80a3-85d04a5885a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087963250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2087963250
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.533913689
Short name T506
Test name
Test status
Simulation time 4604698552 ps
CPU time 16.36 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:04:10 PM PDT 24
Peak memory 220556 kb
Host smart-dc789e00-7872-4e01-bb87-9272416bdd67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=533913689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.533913689
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1727498326
Short name T154
Test name
Test status
Simulation time 47158676526 ps
CPU time 154.02 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:06:27 PM PDT 24
Peak memory 241332 kb
Host smart-63159c07-8ab0-48e0-b975-8f72486b0952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727498326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1727498326
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3725125404
Short name T497
Test name
Test status
Simulation time 23439671765 ps
CPU time 27.73 seconds
Started Aug 03 05:03:42 PM PDT 24
Finished Aug 03 05:04:10 PM PDT 24
Peak memory 216436 kb
Host smart-0e4e023d-3460-419a-ad22-52e9fcbf6055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725125404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3725125404
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.254774947
Short name T469
Test name
Test status
Simulation time 1206154481 ps
CPU time 6.81 seconds
Started Aug 03 05:03:51 PM PDT 24
Finished Aug 03 05:03:58 PM PDT 24
Peak memory 216476 kb
Host smart-752fdad6-76ed-4ac4-81fa-6153553a2fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254774947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.254774947
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3155593289
Short name T348
Test name
Test status
Simulation time 60353660 ps
CPU time 1.08 seconds
Started Aug 03 05:03:45 PM PDT 24
Finished Aug 03 05:03:46 PM PDT 24
Peak memory 208240 kb
Host smart-01fcfb98-4b08-4611-9890-29bfcab64859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155593289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3155593289
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1946448796
Short name T861
Test name
Test status
Simulation time 129597871 ps
CPU time 0.88 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:03:52 PM PDT 24
Peak memory 206376 kb
Host smart-66720bd5-c021-4e31-8d8d-bae165af5a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946448796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1946448796
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2335636776
Short name T864
Test name
Test status
Simulation time 772862690 ps
CPU time 2.34 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:03:57 PM PDT 24
Peak memory 224872 kb
Host smart-5c329f33-c1d1-4805-9a22-f6c94a978621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335636776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2335636776
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3845511493
Short name T350
Test name
Test status
Simulation time 64889319 ps
CPU time 0.74 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:03:51 PM PDT 24
Peak memory 206176 kb
Host smart-29ee05a3-1342-4e87-a0de-e140682e9d1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845511493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3845511493
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1342454414
Short name T504
Test name
Test status
Simulation time 346118395 ps
CPU time 3.06 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 233020 kb
Host smart-1883d157-3839-4865-85bb-99a44994dce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342454414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1342454414
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3321718398
Short name T752
Test name
Test status
Simulation time 134527865 ps
CPU time 0.78 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:03:57 PM PDT 24
Peak memory 206924 kb
Host smart-f05430fd-079d-4a2b-8d4e-0a74e9706a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321718398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3321718398
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1503342966
Short name T501
Test name
Test status
Simulation time 10808139656 ps
CPU time 21.38 seconds
Started Aug 03 05:03:51 PM PDT 24
Finished Aug 03 05:04:12 PM PDT 24
Peak memory 240468 kb
Host smart-f13fe46c-ccdf-4503-bef3-b28eee7cd7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503342966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1503342966
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1109886816
Short name T186
Test name
Test status
Simulation time 107766092160 ps
CPU time 200.43 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:07:10 PM PDT 24
Peak memory 250932 kb
Host smart-8fa1ef30-e0f3-4dba-b9b9-6ac217c31600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109886816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1109886816
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3365890088
Short name T290
Test name
Test status
Simulation time 4084321181 ps
CPU time 101.6 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:05:37 PM PDT 24
Peak memory 257404 kb
Host smart-2f1be7f1-34d3-4ed0-9025-16674245e917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365890088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3365890088
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4267897266
Short name T305
Test name
Test status
Simulation time 3067216511 ps
CPU time 12.52 seconds
Started Aug 03 05:03:47 PM PDT 24
Finished Aug 03 05:03:59 PM PDT 24
Peak memory 233120 kb
Host smart-f2c5dfb6-d80f-442b-b6a9-3f7ccebcddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267897266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4267897266
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1162219675
Short name T821
Test name
Test status
Simulation time 199524529 ps
CPU time 0.97 seconds
Started Aug 03 05:03:48 PM PDT 24
Finished Aug 03 05:03:49 PM PDT 24
Peak memory 216268 kb
Host smart-543c0411-1204-427b-b53d-e876af02534d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162219675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1162219675
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3972233983
Short name T660
Test name
Test status
Simulation time 5948835637 ps
CPU time 22.14 seconds
Started Aug 03 05:03:51 PM PDT 24
Finished Aug 03 05:04:13 PM PDT 24
Peak memory 224940 kb
Host smart-0699341a-c0e7-4ca1-84a3-d0e7d834b4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972233983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3972233983
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3920103209
Short name T512
Test name
Test status
Simulation time 5842055766 ps
CPU time 17.69 seconds
Started Aug 03 05:03:49 PM PDT 24
Finished Aug 03 05:04:07 PM PDT 24
Peak memory 233168 kb
Host smart-f9191fb8-5cf0-4680-8227-6e8759e082d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920103209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3920103209
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.684523614
Short name T645
Test name
Test status
Simulation time 5574999084 ps
CPU time 12.89 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:04:05 PM PDT 24
Peak memory 233184 kb
Host smart-5d3d4ab2-8823-486e-9f6b-2525a534520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684523614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.684523614
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1696930455
Short name T648
Test name
Test status
Simulation time 1309232869 ps
CPU time 9.92 seconds
Started Aug 03 05:03:48 PM PDT 24
Finished Aug 03 05:03:58 PM PDT 24
Peak memory 233116 kb
Host smart-bf5bb5e0-9cd9-44da-90bb-03a08abe73de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696930455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1696930455
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3521987861
Short name T664
Test name
Test status
Simulation time 204344020 ps
CPU time 4.73 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:03:59 PM PDT 24
Peak memory 220648 kb
Host smart-af3d9da4-0f75-4436-9ca8-22274bfd8939
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3521987861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3521987861
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2676631872
Short name T245
Test name
Test status
Simulation time 439990252852 ps
CPU time 486.71 seconds
Started Aug 03 05:03:49 PM PDT 24
Finished Aug 03 05:11:56 PM PDT 24
Peak memory 266028 kb
Host smart-3c285ee8-a9b6-498a-a644-796c1dcf7f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676631872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2676631872
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3004950924
Short name T604
Test name
Test status
Simulation time 7460782587 ps
CPU time 22.38 seconds
Started Aug 03 05:03:57 PM PDT 24
Finished Aug 03 05:04:20 PM PDT 24
Peak memory 216752 kb
Host smart-a996c4ef-eacf-4ee5-99b3-54a1779af42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004950924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3004950924
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2861358382
Short name T1004
Test name
Test status
Simulation time 6405216450 ps
CPU time 4.79 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 217752 kb
Host smart-c5d08789-39eb-40ea-b25a-69d4c0dc80e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861358382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2861358382
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3225570766
Short name T886
Test name
Test status
Simulation time 59818771 ps
CPU time 1.99 seconds
Started Aug 03 05:03:53 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 216624 kb
Host smart-08c95ee2-48ad-4657-9d1d-fead36415ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225570766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3225570766
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.104033967
Short name T844
Test name
Test status
Simulation time 80690352 ps
CPU time 0.93 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:03:57 PM PDT 24
Peak memory 206280 kb
Host smart-cc2e6de5-1fc3-4a10-89ff-b28754d5c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104033967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.104033967
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3952027941
Short name T229
Test name
Test status
Simulation time 218806132 ps
CPU time 3.65 seconds
Started Aug 03 05:03:55 PM PDT 24
Finished Aug 03 05:03:58 PM PDT 24
Peak memory 224912 kb
Host smart-a61908a2-4c36-4339-af8c-e9ceb29f92ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952027941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3952027941
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3643489117
Short name T356
Test name
Test status
Simulation time 25546058 ps
CPU time 0.8 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 205972 kb
Host smart-318c8b0e-4220-45b6-81b3-3d97da75fef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643489117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3643489117
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2060722968
Short name T231
Test name
Test status
Simulation time 113485002 ps
CPU time 2.46 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 224900 kb
Host smart-580c9f6a-f8a6-453c-81aa-5c7910cb3f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060722968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2060722968
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2507404288
Short name T367
Test name
Test status
Simulation time 57879077 ps
CPU time 0.77 seconds
Started Aug 03 05:03:49 PM PDT 24
Finished Aug 03 05:03:50 PM PDT 24
Peak memory 206016 kb
Host smart-61c9fed7-b9c6-4b3a-bc99-b39261597d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507404288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2507404288
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3942902520
Short name T911
Test name
Test status
Simulation time 18268677724 ps
CPU time 83.42 seconds
Started Aug 03 05:03:53 PM PDT 24
Finished Aug 03 05:05:16 PM PDT 24
Peak memory 263500 kb
Host smart-565ce44a-dbee-4186-85b6-1adac109e67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942902520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3942902520
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3683936487
Short name T433
Test name
Test status
Simulation time 3518650968 ps
CPU time 22.47 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:04:17 PM PDT 24
Peak memory 217832 kb
Host smart-eb1a39cb-c22c-4d7d-9713-f022f21d3df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683936487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3683936487
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.499525321
Short name T639
Test name
Test status
Simulation time 118608571061 ps
CPU time 288.8 seconds
Started Aug 03 05:03:47 PM PDT 24
Finished Aug 03 05:08:36 PM PDT 24
Peak memory 255356 kb
Host smart-ebb998fb-d2ea-44cc-9c20-b68bad7ad5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499525321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.499525321
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4160991509
Short name T554
Test name
Test status
Simulation time 1264607711 ps
CPU time 14.07 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:04:10 PM PDT 24
Peak memory 224880 kb
Host smart-7bd268d3-c93c-4e8b-ba81-21db15122557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160991509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4160991509
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.13763981
Short name T869
Test name
Test status
Simulation time 5084412046 ps
CPU time 53.83 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:04:45 PM PDT 24
Peak memory 241356 kb
Host smart-e2464626-32fc-4f8a-8937-b8977763a83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13763981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.13763981
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3413709239
Short name T880
Test name
Test status
Simulation time 2584068212 ps
CPU time 12.66 seconds
Started Aug 03 05:03:53 PM PDT 24
Finished Aug 03 05:04:06 PM PDT 24
Peak memory 225180 kb
Host smart-bfa77619-171e-4d7d-a26e-4cd6c3c90de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413709239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3413709239
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2602993553
Short name T424
Test name
Test status
Simulation time 5091063459 ps
CPU time 30.21 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:04:26 PM PDT 24
Peak memory 233160 kb
Host smart-6ae489b4-bf38-4ce4-8ac0-076fafd75ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602993553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2602993553
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3614774883
Short name T571
Test name
Test status
Simulation time 842878544 ps
CPU time 2.13 seconds
Started Aug 03 05:03:53 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 223500 kb
Host smart-e3fcd677-4ccf-4c24-b92a-83ce660f6735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614774883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3614774883
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2309991654
Short name T549
Test name
Test status
Simulation time 886434639 ps
CPU time 5.86 seconds
Started Aug 03 05:03:48 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 233084 kb
Host smart-d464da42-3d81-4ca3-b5a2-a60b142eb8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309991654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2309991654
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2732174157
Short name T929
Test name
Test status
Simulation time 980357828 ps
CPU time 7.13 seconds
Started Aug 03 05:03:47 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 219736 kb
Host smart-1baa5452-f3f0-462a-b555-c4db336bcd5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2732174157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2732174157
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2582592408
Short name T728
Test name
Test status
Simulation time 26926708931 ps
CPU time 81.52 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:05:17 PM PDT 24
Peak memory 249572 kb
Host smart-dff09ec0-1cbd-468f-aae4-89339e12850e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582592408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2582592408
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2642369197
Short name T6
Test name
Test status
Simulation time 3484425482 ps
CPU time 5.77 seconds
Started Aug 03 05:03:58 PM PDT 24
Finished Aug 03 05:04:04 PM PDT 24
Peak memory 216760 kb
Host smart-ea834ba6-7e8e-4b17-91ac-dbab976b489f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642369197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2642369197
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3025488414
Short name T347
Test name
Test status
Simulation time 273930826 ps
CPU time 2.85 seconds
Started Aug 03 05:03:58 PM PDT 24
Finished Aug 03 05:04:01 PM PDT 24
Peak memory 216564 kb
Host smart-076bb140-3482-45ac-8d7c-c4db0c584056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025488414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3025488414
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2066549206
Short name T940
Test name
Test status
Simulation time 41368570 ps
CPU time 1.73 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:03:52 PM PDT 24
Peak memory 208468 kb
Host smart-34a9b93e-3fb9-4d5f-987e-02ff48ff0da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066549206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2066549206
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1575517386
Short name T623
Test name
Test status
Simulation time 294898119 ps
CPU time 0.94 seconds
Started Aug 03 05:03:55 PM PDT 24
Finished Aug 03 05:03:56 PM PDT 24
Peak memory 207292 kb
Host smart-f0b6dba1-f099-4ff9-b447-9c926ace28e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575517386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1575517386
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1443032555
Short name T445
Test name
Test status
Simulation time 346647495 ps
CPU time 3.42 seconds
Started Aug 03 05:03:50 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 233108 kb
Host smart-3f6f52eb-b1a2-48ec-9c5b-3ec199662eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443032555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1443032555
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3802117855
Short name T456
Test name
Test status
Simulation time 43074196 ps
CPU time 0.78 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 205236 kb
Host smart-b8948441-69fc-43ca-bdc8-6c7515c67b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802117855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3802117855
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3847926192
Short name T86
Test name
Test status
Simulation time 323327089 ps
CPU time 4.16 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:03:56 PM PDT 24
Peak memory 224916 kb
Host smart-ec8fd6ec-aaca-46cd-9cbc-4d3eabbf4589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847926192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3847926192
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.57205771
Short name T593
Test name
Test status
Simulation time 41736281 ps
CPU time 0.74 seconds
Started Aug 03 05:03:55 PM PDT 24
Finished Aug 03 05:03:56 PM PDT 24
Peak memory 207016 kb
Host smart-5f687365-9aaa-49b9-941b-9fababc40c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57205771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.57205771
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2312504337
Short name T764
Test name
Test status
Simulation time 15764522854 ps
CPU time 27.03 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:04:23 PM PDT 24
Peak memory 236716 kb
Host smart-67683ad3-9ae2-4ab3-aea4-1f36a1173dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312504337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2312504337
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.963408646
Short name T828
Test name
Test status
Simulation time 26287981462 ps
CPU time 33.51 seconds
Started Aug 03 05:03:53 PM PDT 24
Finished Aug 03 05:04:26 PM PDT 24
Peak memory 224968 kb
Host smart-46db4bf8-33ab-47bf-870d-665af30cdd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963408646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.963408646
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3243552290
Short name T835
Test name
Test status
Simulation time 2465388213 ps
CPU time 61.41 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:04:58 PM PDT 24
Peak memory 249928 kb
Host smart-c71315d3-d8a6-4b2d-b84b-9ac417aa9fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243552290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3243552290
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.583053646
Short name T155
Test name
Test status
Simulation time 84095480 ps
CPU time 2.69 seconds
Started Aug 03 05:03:57 PM PDT 24
Finished Aug 03 05:03:59 PM PDT 24
Peak memory 224900 kb
Host smart-709cde53-d98c-478a-a7aa-165488a81eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583053646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.583053646
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2122916937
Short name T160
Test name
Test status
Simulation time 590126871 ps
CPU time 12.54 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:04:07 PM PDT 24
Peak memory 234116 kb
Host smart-3ca77488-cda3-405b-966d-08e2348c9a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122916937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2122916937
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1242523438
Short name T368
Test name
Test status
Simulation time 770632043 ps
CPU time 5.45 seconds
Started Aug 03 05:04:03 PM PDT 24
Finished Aug 03 05:04:08 PM PDT 24
Peak memory 224752 kb
Host smart-4702b3a7-c2a8-4c6f-beec-924ec929c11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242523438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1242523438
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2728878264
Short name T174
Test name
Test status
Simulation time 19867216881 ps
CPU time 65.72 seconds
Started Aug 03 05:03:55 PM PDT 24
Finished Aug 03 05:05:01 PM PDT 24
Peak memory 233212 kb
Host smart-ae5922c0-d8fe-4fed-8f3d-a7cb9661fe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728878264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2728878264
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3454845666
Short name T188
Test name
Test status
Simulation time 466828534 ps
CPU time 5.78 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:03:58 PM PDT 24
Peak memory 233020 kb
Host smart-dadad09f-df03-4469-80c1-8206982c8f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454845666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3454845666
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1904182463
Short name T541
Test name
Test status
Simulation time 34579176 ps
CPU time 2.38 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 232724 kb
Host smart-e7c7f0b7-a3aa-4125-87ff-9b8a5013bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904182463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1904182463
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.582925304
Short name T693
Test name
Test status
Simulation time 3523450290 ps
CPU time 18.19 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:04:12 PM PDT 24
Peak memory 220988 kb
Host smart-a8eb7c70-1d9e-4f7a-b4de-d72dddc353a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=582925304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.582925304
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3596730902
Short name T316
Test name
Test status
Simulation time 15578607672 ps
CPU time 16.61 seconds
Started Aug 03 05:03:53 PM PDT 24
Finished Aug 03 05:04:10 PM PDT 24
Peak memory 216792 kb
Host smart-afd0bfe2-b034-421c-ad82-f6301645b306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596730902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3596730902
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2450768588
Short name T613
Test name
Test status
Simulation time 4427861355 ps
CPU time 3.93 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:03:56 PM PDT 24
Peak memory 216780 kb
Host smart-ba9e307a-02ff-4ec8-8c84-b368a57b4fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450768588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2450768588
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.591770929
Short name T454
Test name
Test status
Simulation time 669255171 ps
CPU time 4.46 seconds
Started Aug 03 05:03:55 PM PDT 24
Finished Aug 03 05:03:59 PM PDT 24
Peak memory 216568 kb
Host smart-3c1cbd37-a305-4d9e-bd88-3be068889b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591770929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.591770929
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3149829586
Short name T892
Test name
Test status
Simulation time 48221219 ps
CPU time 0.84 seconds
Started Aug 03 05:04:00 PM PDT 24
Finished Aug 03 05:04:01 PM PDT 24
Peak memory 206272 kb
Host smart-27a98a8b-8b0b-4bb3-9d7b-961ad59f9714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149829586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3149829586
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.372823300
Short name T975
Test name
Test status
Simulation time 24637269804 ps
CPU time 25.36 seconds
Started Aug 03 05:03:53 PM PDT 24
Finished Aug 03 05:04:18 PM PDT 24
Peak memory 235276 kb
Host smart-7d252f55-3711-43d7-b9de-f58523d7a4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372823300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.372823300
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3928136433
Short name T572
Test name
Test status
Simulation time 63045363 ps
CPU time 0.74 seconds
Started Aug 03 05:03:55 PM PDT 24
Finished Aug 03 05:03:56 PM PDT 24
Peak memory 205844 kb
Host smart-3a249997-0838-4572-a973-b8946dd6674c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928136433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3928136433
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1199841276
Short name T674
Test name
Test status
Simulation time 7937722378 ps
CPU time 9.81 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:04:03 PM PDT 24
Peak memory 224736 kb
Host smart-bce10e27-cf0f-43d7-bf1d-9acdc6d4fe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199841276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1199841276
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1486758935
Short name T956
Test name
Test status
Simulation time 28579693 ps
CPU time 0.82 seconds
Started Aug 03 05:03:55 PM PDT 24
Finished Aug 03 05:03:56 PM PDT 24
Peak memory 206944 kb
Host smart-105e824f-7f3f-41ec-b662-fb10a349dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486758935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1486758935
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.882512231
Short name T691
Test name
Test status
Simulation time 15185976996 ps
CPU time 44.73 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:04:39 PM PDT 24
Peak memory 249916 kb
Host smart-08c9e3ac-ff39-4efd-910b-1de32b0c5bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882512231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.882512231
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.440347551
Short name T498
Test name
Test status
Simulation time 104412673068 ps
CPU time 259.51 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:08:14 PM PDT 24
Peak memory 269588 kb
Host smart-f6b0f8cc-25bc-4aeb-9db0-52573c549007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440347551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.440347551
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.247625526
Short name T789
Test name
Test status
Simulation time 14985903803 ps
CPU time 120.79 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:05:55 PM PDT 24
Peak memory 257200 kb
Host smart-e225aefa-44cc-4f3d-a76c-e49aaf0071ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247625526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.247625526
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1696214838
Short name T853
Test name
Test status
Simulation time 1184292310 ps
CPU time 7.37 seconds
Started Aug 03 05:04:01 PM PDT 24
Finished Aug 03 05:04:09 PM PDT 24
Peak memory 233244 kb
Host smart-c87f39ea-212e-4f62-9e4c-de07d008b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696214838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1696214838
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1153820065
Short name T211
Test name
Test status
Simulation time 102815124827 ps
CPU time 143.35 seconds
Started Aug 03 05:03:57 PM PDT 24
Finished Aug 03 05:06:20 PM PDT 24
Peak memory 249548 kb
Host smart-06f75fdb-2cf0-4035-9e2c-4296e6643ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153820065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1153820065
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3282406450
Short name T874
Test name
Test status
Simulation time 63217497 ps
CPU time 2.42 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 232784 kb
Host smart-240b0a1e-ea35-4e3b-9e49-b1fcbe5ee22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282406450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3282406450
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4086673781
Short name T520
Test name
Test status
Simulation time 590517850 ps
CPU time 7.14 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:04:03 PM PDT 24
Peak memory 224904 kb
Host smart-b2c07cde-2d2f-4a57-81be-e5e4a0a04b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086673781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4086673781
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.421680515
Short name T248
Test name
Test status
Simulation time 1293095248 ps
CPU time 7.21 seconds
Started Aug 03 05:03:55 PM PDT 24
Finished Aug 03 05:04:02 PM PDT 24
Peak memory 240660 kb
Host smart-00dc278e-0fad-4222-871e-e0af5f714f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421680515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.421680515
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4176571081
Short name T700
Test name
Test status
Simulation time 7664669608 ps
CPU time 7.89 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:04:03 PM PDT 24
Peak memory 224904 kb
Host smart-3269d680-34a7-4d04-bb1c-32ee41942c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176571081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4176571081
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2403163897
Short name T412
Test name
Test status
Simulation time 23876784987 ps
CPU time 12.7 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:04:09 PM PDT 24
Peak memory 219316 kb
Host smart-5ab9076a-3482-4e19-9ea4-9a00fc550148
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2403163897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2403163897
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.319118848
Short name T768
Test name
Test status
Simulation time 2343050516 ps
CPU time 5.6 seconds
Started Aug 03 05:03:53 PM PDT 24
Finished Aug 03 05:03:59 PM PDT 24
Peak memory 216680 kb
Host smart-23090798-9cd4-44d9-a23c-9884221a34af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319118848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.319118848
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1956373359
Short name T327
Test name
Test status
Simulation time 4802412573 ps
CPU time 8.71 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:04:05 PM PDT 24
Peak memory 216656 kb
Host smart-0eb016db-5729-414e-9b4b-3f6e1124c105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956373359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1956373359
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3424726671
Short name T942
Test name
Test status
Simulation time 28314471 ps
CPU time 1.06 seconds
Started Aug 03 05:03:54 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 216472 kb
Host smart-453b7f4b-c86b-4ce6-b3ae-fe1c76b0a1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424726671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3424726671
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2952893048
Short name T780
Test name
Test status
Simulation time 18989770 ps
CPU time 0.68 seconds
Started Aug 03 05:03:52 PM PDT 24
Finished Aug 03 05:03:53 PM PDT 24
Peak memory 205972 kb
Host smart-bdc493ac-05a0-4d98-8fad-82f293a0a446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952893048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2952893048
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2301591275
Short name T440
Test name
Test status
Simulation time 8418778410 ps
CPU time 13.05 seconds
Started Aug 03 05:03:56 PM PDT 24
Finished Aug 03 05:04:09 PM PDT 24
Peak memory 233172 kb
Host smart-a3652d9b-8b58-44b8-ae1a-75f52d6dc2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301591275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2301591275
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.357244561
Short name T58
Test name
Test status
Simulation time 50678949 ps
CPU time 0.75 seconds
Started Aug 03 05:01:50 PM PDT 24
Finished Aug 03 05:01:51 PM PDT 24
Peak memory 206092 kb
Host smart-c8cebc51-07d9-4096-a57d-e0ffa2a435b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357244561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.357244561
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2693041250
Short name T852
Test name
Test status
Simulation time 55391749 ps
CPU time 3.16 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:01:54 PM PDT 24
Peak memory 233108 kb
Host smart-cdd3c148-3f69-485b-9c26-29d32e0a5cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693041250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2693041250
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.521394114
Short name T790
Test name
Test status
Simulation time 23201607 ps
CPU time 0.72 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:01:52 PM PDT 24
Peak memory 206996 kb
Host smart-8de4b254-732d-42c4-9b85-4e578df00dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521394114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.521394114
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3402421119
Short name T201
Test name
Test status
Simulation time 9998451974 ps
CPU time 141.46 seconds
Started Aug 03 05:01:54 PM PDT 24
Finished Aug 03 05:04:15 PM PDT 24
Peak memory 273324 kb
Host smart-e0e25a1e-cbb1-4094-b2b7-e2151b85050a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402421119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3402421119
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3357577911
Short name T969
Test name
Test status
Simulation time 4297218291 ps
CPU time 118.91 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:03:50 PM PDT 24
Peak memory 261808 kb
Host smart-78e144ef-ec94-4888-be2d-2a967ab17760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357577911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3357577911
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1985393021
Short name T77
Test name
Test status
Simulation time 25686436504 ps
CPU time 217.71 seconds
Started Aug 03 05:01:41 PM PDT 24
Finished Aug 03 05:05:18 PM PDT 24
Peak memory 256632 kb
Host smart-6bf6df6b-2848-4021-8b2b-96d878188733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985393021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1985393021
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3913319451
Short name T393
Test name
Test status
Simulation time 126649883 ps
CPU time 2.66 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:01:54 PM PDT 24
Peak memory 233120 kb
Host smart-2d5abfa5-98f5-4810-9429-634c4f50cbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913319451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3913319451
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3086197599
Short name T601
Test name
Test status
Simulation time 3674265079 ps
CPU time 30.38 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:02:21 PM PDT 24
Peak memory 235656 kb
Host smart-359bf889-ec18-4e23-9731-e6593d8437ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086197599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3086197599
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1534659317
Short name T221
Test name
Test status
Simulation time 5207517686 ps
CPU time 18.04 seconds
Started Aug 03 05:01:50 PM PDT 24
Finished Aug 03 05:02:08 PM PDT 24
Peak memory 224996 kb
Host smart-e21ff07c-48f3-4885-9ba8-a589013f0bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534659317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1534659317
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2545922910
Short name T687
Test name
Test status
Simulation time 11759153340 ps
CPU time 99.36 seconds
Started Aug 03 05:01:52 PM PDT 24
Finished Aug 03 05:03:32 PM PDT 24
Peak memory 233184 kb
Host smart-da3f15f5-a3a9-4ce5-bb16-21a50cf72391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545922910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2545922910
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1154639693
Short name T534
Test name
Test status
Simulation time 1420068426 ps
CPU time 6.97 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:01:58 PM PDT 24
Peak memory 233124 kb
Host smart-ebb35639-c060-4496-9778-2378c477905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154639693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1154639693
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3430851267
Short name T69
Test name
Test status
Simulation time 1948350037 ps
CPU time 9.93 seconds
Started Aug 03 05:01:54 PM PDT 24
Finished Aug 03 05:02:04 PM PDT 24
Peak memory 224948 kb
Host smart-a29af478-5c06-453d-86c0-3b37b6974cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430851267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3430851267
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2132468806
Short name T785
Test name
Test status
Simulation time 471367195 ps
CPU time 6 seconds
Started Aug 03 05:01:52 PM PDT 24
Finished Aug 03 05:01:58 PM PDT 24
Peak memory 221292 kb
Host smart-8c8e5767-abe2-4fb3-a6c4-a18f018e6bce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2132468806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2132468806
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2193715199
Short name T839
Test name
Test status
Simulation time 18824961431 ps
CPU time 18.42 seconds
Started Aug 03 05:01:42 PM PDT 24
Finished Aug 03 05:02:01 PM PDT 24
Peak memory 223564 kb
Host smart-3a74b28d-d81d-4490-8f1b-d44996419526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193715199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2193715199
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2881513494
Short name T606
Test name
Test status
Simulation time 7322469269 ps
CPU time 16.02 seconds
Started Aug 03 05:01:53 PM PDT 24
Finished Aug 03 05:02:09 PM PDT 24
Peak memory 216800 kb
Host smart-20f44288-da1f-4903-b504-bd89f119a780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881513494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2881513494
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1271018859
Short name T931
Test name
Test status
Simulation time 1336914355 ps
CPU time 1.93 seconds
Started Aug 03 05:01:52 PM PDT 24
Finished Aug 03 05:01:54 PM PDT 24
Peak memory 208124 kb
Host smart-12d6d0b5-0957-483b-8092-f0cdb35b3dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271018859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1271018859
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2882342332
Short name T9
Test name
Test status
Simulation time 82428837 ps
CPU time 0.92 seconds
Started Aug 03 05:01:50 PM PDT 24
Finished Aug 03 05:01:51 PM PDT 24
Peak memory 207116 kb
Host smart-1e00651c-de34-405f-88d5-f10bb35a9c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882342332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2882342332
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2188003830
Short name T343
Test name
Test status
Simulation time 37597650 ps
CPU time 0.74 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:01:52 PM PDT 24
Peak memory 206376 kb
Host smart-b85a391e-9187-42f7-9295-3812f81b6fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188003830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2188003830
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.606617866
Short name T265
Test name
Test status
Simulation time 207086791 ps
CPU time 3.76 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:01:55 PM PDT 24
Peak memory 224828 kb
Host smart-95fb0f2f-db27-43ef-8dbf-11589b7e4e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606617866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.606617866
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3552886139
Short name T968
Test name
Test status
Simulation time 25195744 ps
CPU time 0.74 seconds
Started Aug 03 05:01:54 PM PDT 24
Finished Aug 03 05:01:54 PM PDT 24
Peak memory 205788 kb
Host smart-dc142e98-f6af-424c-b6fb-88063be0ef72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552886139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
552886139
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.4009125570
Short name T910
Test name
Test status
Simulation time 455279539 ps
CPU time 4.03 seconds
Started Aug 03 05:01:59 PM PDT 24
Finished Aug 03 05:02:04 PM PDT 24
Peak memory 233128 kb
Host smart-8121382a-84d6-4f6a-b64a-3fff9862214b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009125570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4009125570
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2746350042
Short name T351
Test name
Test status
Simulation time 53131386 ps
CPU time 0.79 seconds
Started Aug 03 05:01:43 PM PDT 24
Finished Aug 03 05:01:44 PM PDT 24
Peak memory 206996 kb
Host smart-660eebcd-087b-4f17-8921-8c5207db417a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746350042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2746350042
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1573588518
Short name T173
Test name
Test status
Simulation time 24931375720 ps
CPU time 208.92 seconds
Started Aug 03 05:01:44 PM PDT 24
Finished Aug 03 05:05:13 PM PDT 24
Peak memory 257168 kb
Host smart-a6443793-3f26-459a-95b9-3c835c3216ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573588518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1573588518
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.430531036
Short name T656
Test name
Test status
Simulation time 16019628579 ps
CPU time 32.7 seconds
Started Aug 03 05:01:54 PM PDT 24
Finished Aug 03 05:02:27 PM PDT 24
Peak memory 218076 kb
Host smart-721025b7-84a7-4a8f-a32d-ee09a0c7f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430531036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.430531036
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4119356402
Short name T944
Test name
Test status
Simulation time 31639987440 ps
CPU time 130.5 seconds
Started Aug 03 05:01:49 PM PDT 24
Finished Aug 03 05:04:00 PM PDT 24
Peak memory 249640 kb
Host smart-d2284f3b-590e-4279-b749-a2532d7de94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119356402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4119356402
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2216373929
Short name T300
Test name
Test status
Simulation time 418920314 ps
CPU time 6.61 seconds
Started Aug 03 05:01:41 PM PDT 24
Finished Aug 03 05:01:48 PM PDT 24
Peak memory 241332 kb
Host smart-2d6a8f75-a53f-44cb-9c8f-c6bc19081988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216373929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2216373929
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2718217355
Short name T715
Test name
Test status
Simulation time 10119533948 ps
CPU time 82.55 seconds
Started Aug 03 05:02:03 PM PDT 24
Finished Aug 03 05:03:26 PM PDT 24
Peak memory 239236 kb
Host smart-58e8c933-af5d-4a1d-a63e-1dd70eec9415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718217355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2718217355
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3955631289
Short name T941
Test name
Test status
Simulation time 388583763 ps
CPU time 6.41 seconds
Started Aug 03 05:01:44 PM PDT 24
Finished Aug 03 05:01:50 PM PDT 24
Peak memory 224960 kb
Host smart-53aa4d83-c7c9-4b99-9558-fed355aa25e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955631289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3955631289
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.642336483
Short name T132
Test name
Test status
Simulation time 6937471693 ps
CPU time 19.48 seconds
Started Aug 03 05:01:41 PM PDT 24
Finished Aug 03 05:02:01 PM PDT 24
Peak memory 233172 kb
Host smart-42aec1b8-ce34-4648-87bb-4736f6102130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642336483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.642336483
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4065745720
Short name T493
Test name
Test status
Simulation time 4300130473 ps
CPU time 4.71 seconds
Started Aug 03 05:01:43 PM PDT 24
Finished Aug 03 05:01:48 PM PDT 24
Peak memory 224984 kb
Host smart-81fa7bae-e304-47a0-8930-ee923fdd4c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065745720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4065745720
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2738542582
Short name T915
Test name
Test status
Simulation time 13938786644 ps
CPU time 23.42 seconds
Started Aug 03 05:01:54 PM PDT 24
Finished Aug 03 05:02:18 PM PDT 24
Peak memory 224892 kb
Host smart-6f9fea17-295a-4af8-b24c-2282936c116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738542582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2738542582
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2188008409
Short name T720
Test name
Test status
Simulation time 2215113980 ps
CPU time 6.9 seconds
Started Aug 03 05:01:54 PM PDT 24
Finished Aug 03 05:02:01 PM PDT 24
Peak memory 222892 kb
Host smart-19b4aff0-d510-4cc8-a378-17114818a924
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2188008409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2188008409
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1207842150
Short name T137
Test name
Test status
Simulation time 692788863553 ps
CPU time 979.51 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:18:11 PM PDT 24
Peak memory 282400 kb
Host smart-5ae50be3-e0f2-463d-88fc-cbecc7c13fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207842150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1207842150
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4276891820
Short name T11
Test name
Test status
Simulation time 5436243424 ps
CPU time 27.31 seconds
Started Aug 03 05:01:53 PM PDT 24
Finished Aug 03 05:02:21 PM PDT 24
Peak memory 220584 kb
Host smart-a9a9b4cd-43dc-4a3f-8b55-6c702488218c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276891820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4276891820
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2856874156
Short name T415
Test name
Test status
Simulation time 12183049603 ps
CPU time 8.47 seconds
Started Aug 03 05:01:50 PM PDT 24
Finished Aug 03 05:01:58 PM PDT 24
Peak memory 216708 kb
Host smart-3b774ee9-7615-4df3-8bbc-183cea396f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856874156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2856874156
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3170261878
Short name T737
Test name
Test status
Simulation time 45626271 ps
CPU time 0.91 seconds
Started Aug 03 05:01:50 PM PDT 24
Finished Aug 03 05:01:51 PM PDT 24
Peak memory 207444 kb
Host smart-5126fb5a-e3fa-4953-bb58-08903bf83c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170261878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3170261878
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.4222638066
Short name T518
Test name
Test status
Simulation time 99396771 ps
CPU time 0.9 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:01:52 PM PDT 24
Peak memory 206312 kb
Host smart-72054e22-a9c7-4025-89c0-55bb78b477e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222638066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4222638066
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2850745200
Short name T962
Test name
Test status
Simulation time 10834892080 ps
CPU time 11.37 seconds
Started Aug 03 05:01:49 PM PDT 24
Finished Aug 03 05:02:01 PM PDT 24
Peak memory 239644 kb
Host smart-74c0c9bb-d6e8-472c-910b-ed65eda3b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850745200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2850745200
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1316872522
Short name T471
Test name
Test status
Simulation time 107645908 ps
CPU time 0.72 seconds
Started Aug 03 05:01:53 PM PDT 24
Finished Aug 03 05:01:54 PM PDT 24
Peak memory 205232 kb
Host smart-87e05494-3ead-4775-80c3-0e859eb6ca3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316872522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
316872522
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.427211472
Short name T496
Test name
Test status
Simulation time 41477417 ps
CPU time 2.39 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:01:54 PM PDT 24
Peak memory 233036 kb
Host smart-2bbd0fa0-c1f6-4d43-9732-9bf428b0f04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427211472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.427211472
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4235651347
Short name T495
Test name
Test status
Simulation time 32151451 ps
CPU time 0.79 seconds
Started Aug 03 05:01:50 PM PDT 24
Finished Aug 03 05:01:51 PM PDT 24
Peak memory 206968 kb
Host smart-36c0344c-3b94-4427-8ec6-affc231923f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235651347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4235651347
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2850009780
Short name T459
Test name
Test status
Simulation time 107108567 ps
CPU time 0.94 seconds
Started Aug 03 05:01:49 PM PDT 24
Finished Aug 03 05:01:50 PM PDT 24
Peak memory 216356 kb
Host smart-89d7ed35-1655-42da-bf30-1aeaaba0b97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850009780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2850009780
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3656451990
Short name T556
Test name
Test status
Simulation time 6714999534 ps
CPU time 77.49 seconds
Started Aug 03 05:01:48 PM PDT 24
Finished Aug 03 05:03:06 PM PDT 24
Peak memory 251596 kb
Host smart-2cbbc060-320c-401b-8549-5b2ee64edf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656451990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3656451990
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.897026220
Short name T585
Test name
Test status
Simulation time 2366244000 ps
CPU time 22.11 seconds
Started Aug 03 05:01:53 PM PDT 24
Finished Aug 03 05:02:15 PM PDT 24
Peak memory 233160 kb
Host smart-aec0f27e-ae8f-4211-9c78-d53e2f5cd1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897026220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.897026220
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.531083832
Short name T212
Test name
Test status
Simulation time 14168705774 ps
CPU time 69.25 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:03:00 PM PDT 24
Peak memory 256096 kb
Host smart-7a0ab48f-2bd7-4a18-802a-63d111f6b299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531083832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
531083832
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.495582232
Short name T729
Test name
Test status
Simulation time 109728131 ps
CPU time 2.47 seconds
Started Aug 03 05:01:48 PM PDT 24
Finished Aug 03 05:01:51 PM PDT 24
Peak memory 232728 kb
Host smart-cca90f7f-beb3-4219-b880-d9231d6eb684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495582232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.495582232
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3957634813
Short name T894
Test name
Test status
Simulation time 14073932699 ps
CPU time 31.46 seconds
Started Aug 03 05:01:52 PM PDT 24
Finished Aug 03 05:02:24 PM PDT 24
Peak memory 241148 kb
Host smart-ea77e495-701e-4713-a246-ab51a06732d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957634813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3957634813
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2618903633
Short name T256
Test name
Test status
Simulation time 460075564 ps
CPU time 3 seconds
Started Aug 03 05:01:52 PM PDT 24
Finished Aug 03 05:01:55 PM PDT 24
Peak memory 224776 kb
Host smart-78197341-bfe8-4822-81f1-cc2c7dadd751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618903633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2618903633
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2889373842
Short name T421
Test name
Test status
Simulation time 17758895573 ps
CPU time 8.68 seconds
Started Aug 03 05:01:48 PM PDT 24
Finished Aug 03 05:01:56 PM PDT 24
Peak memory 224968 kb
Host smart-a5793d3f-2a24-4241-8613-530b4efa553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889373842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2889373842
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.793676756
Short name T859
Test name
Test status
Simulation time 881792557 ps
CPU time 4.14 seconds
Started Aug 03 05:01:51 PM PDT 24
Finished Aug 03 05:01:55 PM PDT 24
Peak memory 223476 kb
Host smart-192e5ae7-2b00-4d54-9762-900f404dd749
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=793676756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.793676756
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.180402184
Short name T884
Test name
Test status
Simulation time 40931622181 ps
CPU time 54.03 seconds
Started Aug 03 05:01:55 PM PDT 24
Finished Aug 03 05:02:50 PM PDT 24
Peak memory 216744 kb
Host smart-9b4607d1-4378-4ff1-96dc-058c7b344f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180402184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.180402184
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2142552249
Short name T758
Test name
Test status
Simulation time 2571107646 ps
CPU time 2.25 seconds
Started Aug 03 05:01:54 PM PDT 24
Finished Aug 03 05:01:57 PM PDT 24
Peak memory 216480 kb
Host smart-dafc6c0b-122a-40d2-ace4-52d373e66bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142552249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2142552249
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.186853057
Short name T24
Test name
Test status
Simulation time 23967858 ps
CPU time 1 seconds
Started Aug 03 05:01:46 PM PDT 24
Finished Aug 03 05:01:47 PM PDT 24
Peak memory 207672 kb
Host smart-fee738ce-4f5b-4199-b753-e901de6867ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186853057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.186853057
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3487035380
Short name T735
Test name
Test status
Simulation time 25808981 ps
CPU time 0.69 seconds
Started Aug 03 05:01:52 PM PDT 24
Finished Aug 03 05:01:53 PM PDT 24
Peak memory 206012 kb
Host smart-f42342ce-1f51-43cb-9b2b-365e4b50d5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487035380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3487035380
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2838825202
Short name T579
Test name
Test status
Simulation time 697218006 ps
CPU time 5 seconds
Started Aug 03 05:01:47 PM PDT 24
Finished Aug 03 05:01:52 PM PDT 24
Peak memory 233080 kb
Host smart-a846469d-835c-4bed-9db9-ba698c3b6ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838825202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2838825202
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2886169246
Short name T849
Test name
Test status
Simulation time 34989649 ps
CPU time 0.71 seconds
Started Aug 03 05:02:05 PM PDT 24
Finished Aug 03 05:02:06 PM PDT 24
Peak memory 206160 kb
Host smart-b2753eaf-b086-47b0-b743-dd881cf3166c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886169246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
886169246
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2487897472
Short name T260
Test name
Test status
Simulation time 174075523 ps
CPU time 3.3 seconds
Started Aug 03 05:02:03 PM PDT 24
Finished Aug 03 05:02:06 PM PDT 24
Peak memory 224964 kb
Host smart-ff32ef50-71ef-4f5c-ba9d-829f3fd35954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487897472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2487897472
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2033762183
Short name T376
Test name
Test status
Simulation time 15537726 ps
CPU time 0.81 seconds
Started Aug 03 05:01:54 PM PDT 24
Finished Aug 03 05:01:55 PM PDT 24
Peak memory 206932 kb
Host smart-8b247572-7f90-4c40-b43b-06d406496d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033762183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2033762183
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1002790828
Short name T775
Test name
Test status
Simulation time 13577798583 ps
CPU time 125.5 seconds
Started Aug 03 05:02:07 PM PDT 24
Finished Aug 03 05:04:13 PM PDT 24
Peak memory 251464 kb
Host smart-8d9fb336-b6e9-4716-9ed0-c5cec8a80c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002790828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1002790828
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1504373359
Short name T387
Test name
Test status
Simulation time 7241320655 ps
CPU time 35.22 seconds
Started Aug 03 05:02:03 PM PDT 24
Finished Aug 03 05:02:38 PM PDT 24
Peak memory 217772 kb
Host smart-772f0d6d-11cc-46ed-b67d-7d60382f4829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504373359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1504373359
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4105635064
Short name T303
Test name
Test status
Simulation time 9288900755 ps
CPU time 23.66 seconds
Started Aug 03 05:01:56 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 233188 kb
Host smart-ad1b4572-f276-43fb-865b-e463d28c3f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105635064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4105635064
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.894718062
Short name T744
Test name
Test status
Simulation time 182045568889 ps
CPU time 96.69 seconds
Started Aug 03 05:01:54 PM PDT 24
Finished Aug 03 05:03:31 PM PDT 24
Peak memory 249588 kb
Host smart-92b6a926-0ab5-4161-a075-d10d629eec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894718062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
894718062
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2125053188
Short name T985
Test name
Test status
Simulation time 4853595550 ps
CPU time 12.44 seconds
Started Aug 03 05:02:02 PM PDT 24
Finished Aug 03 05:02:14 PM PDT 24
Peak memory 224932 kb
Host smart-3573492d-1b04-43cc-bd46-3045b24ab3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125053188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2125053188
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2669750300
Short name T483
Test name
Test status
Simulation time 11243470075 ps
CPU time 11.27 seconds
Started Aug 03 05:02:06 PM PDT 24
Finished Aug 03 05:02:17 PM PDT 24
Peak memory 238248 kb
Host smart-850b9748-5480-4dc0-9154-bd32314507f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669750300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2669750300
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1866285097
Short name T573
Test name
Test status
Simulation time 991364148 ps
CPU time 3.73 seconds
Started Aug 03 05:02:00 PM PDT 24
Finished Aug 03 05:02:04 PM PDT 24
Peak memory 233112 kb
Host smart-aaf88eed-b812-4440-8bf8-fce5fd0144af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866285097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1866285097
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1906691229
Short name T609
Test name
Test status
Simulation time 50419508796 ps
CPU time 19.87 seconds
Started Aug 03 05:01:54 PM PDT 24
Finished Aug 03 05:02:14 PM PDT 24
Peak memory 241236 kb
Host smart-a57dcda1-e10c-4ef4-b8ac-85c5c7b9f14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906691229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1906691229
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.691450350
Short name T143
Test name
Test status
Simulation time 208845003 ps
CPU time 5.22 seconds
Started Aug 03 05:01:52 PM PDT 24
Finished Aug 03 05:01:57 PM PDT 24
Peak memory 220940 kb
Host smart-e248263d-beaf-4f28-959f-911ddfff9575
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=691450350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.691450350
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3761309708
Short name T25
Test name
Test status
Simulation time 39971057 ps
CPU time 0.93 seconds
Started Aug 03 05:02:06 PM PDT 24
Finished Aug 03 05:02:07 PM PDT 24
Peak memory 205960 kb
Host smart-31215a4a-6a40-49a0-9979-9069d7791278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761309708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3761309708
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2003753348
Short name T325
Test name
Test status
Simulation time 713281132 ps
CPU time 3.8 seconds
Started Aug 03 05:02:07 PM PDT 24
Finished Aug 03 05:02:11 PM PDT 24
Peak memory 216644 kb
Host smart-1c4a651f-b7ca-4d5b-a5c7-d85d7cc1e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003753348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2003753348
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1292542879
Short name T355
Test name
Test status
Simulation time 161854564 ps
CPU time 1.09 seconds
Started Aug 03 05:02:04 PM PDT 24
Finished Aug 03 05:02:05 PM PDT 24
Peak memory 207468 kb
Host smart-716c7776-1b1c-4bbf-ac42-74239f3ece97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292542879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1292542879
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2266862141
Short name T335
Test name
Test status
Simulation time 686132626 ps
CPU time 4.16 seconds
Started Aug 03 05:01:56 PM PDT 24
Finished Aug 03 05:02:01 PM PDT 24
Peak memory 216592 kb
Host smart-8c92ba8b-5a65-4526-a57f-a7af07577b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266862141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2266862141
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3288615740
Short name T499
Test name
Test status
Simulation time 140054698 ps
CPU time 1.02 seconds
Started Aug 03 05:01:52 PM PDT 24
Finished Aug 03 05:01:54 PM PDT 24
Peak memory 207344 kb
Host smart-718cf6fd-b03a-4175-a65e-0b96c1b4f35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288615740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3288615740
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3460884043
Short name T813
Test name
Test status
Simulation time 34867434 ps
CPU time 2.33 seconds
Started Aug 03 05:01:55 PM PDT 24
Finished Aug 03 05:01:58 PM PDT 24
Peak memory 232808 kb
Host smart-695f29bf-04f3-4d37-a239-d6d8352d762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460884043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3460884043
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1996060748
Short name T903
Test name
Test status
Simulation time 13501418 ps
CPU time 0.71 seconds
Started Aug 03 05:02:00 PM PDT 24
Finished Aug 03 05:02:00 PM PDT 24
Peak memory 205184 kb
Host smart-a74594ac-744d-40e0-9121-61805cd9bb38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996060748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
996060748
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2702059582
Short name T543
Test name
Test status
Simulation time 118264194 ps
CPU time 2.46 seconds
Started Aug 03 05:02:03 PM PDT 24
Finished Aug 03 05:02:06 PM PDT 24
Peak memory 233028 kb
Host smart-5de2a20e-2665-42df-bb20-cc432b45841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702059582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2702059582
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1911707173
Short name T832
Test name
Test status
Simulation time 19862736 ps
CPU time 0.87 seconds
Started Aug 03 05:02:03 PM PDT 24
Finished Aug 03 05:02:04 PM PDT 24
Peak memory 207124 kb
Host smart-f2cc6b00-fcd2-4b28-a1d4-20af8a4c8992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911707173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1911707173
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1132795324
Short name T392
Test name
Test status
Simulation time 2278085346 ps
CPU time 9.85 seconds
Started Aug 03 05:02:04 PM PDT 24
Finished Aug 03 05:02:14 PM PDT 24
Peak memory 234364 kb
Host smart-6267aa34-3b92-4a6d-bea2-2a1e8f6eae46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132795324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1132795324
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.937745145
Short name T208
Test name
Test status
Simulation time 65537701386 ps
CPU time 200.99 seconds
Started Aug 03 05:02:06 PM PDT 24
Finished Aug 03 05:05:27 PM PDT 24
Peak memory 249812 kb
Host smart-b0b96ea8-9e88-4ef5-8939-a8fafd0b0beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937745145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.937745145
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2030736109
Short name T46
Test name
Test status
Simulation time 14501851518 ps
CPU time 142.59 seconds
Started Aug 03 05:02:07 PM PDT 24
Finished Aug 03 05:04:30 PM PDT 24
Peak memory 249580 kb
Host smart-8471fd20-1643-4084-af49-8894f910c311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030736109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2030736109
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1892211310
Short name T517
Test name
Test status
Simulation time 2804867797 ps
CPU time 39.62 seconds
Started Aug 03 05:02:03 PM PDT 24
Finished Aug 03 05:02:43 PM PDT 24
Peak memory 249508 kb
Host smart-681ef8a8-de7b-4fa8-bf0b-929485e9d8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892211310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1892211310
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1386028019
Short name T410
Test name
Test status
Simulation time 5494900150 ps
CPU time 32.33 seconds
Started Aug 03 05:02:08 PM PDT 24
Finished Aug 03 05:02:41 PM PDT 24
Peak memory 251944 kb
Host smart-d191ba7f-91e3-4e52-94cc-63aad0594f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386028019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1386028019
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.278934794
Short name T718
Test name
Test status
Simulation time 153778379 ps
CPU time 4.87 seconds
Started Aug 03 05:02:01 PM PDT 24
Finished Aug 03 05:02:06 PM PDT 24
Peak memory 233116 kb
Host smart-406ecde7-b847-420b-90db-a927b6db59b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278934794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.278934794
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2843374983
Short name T270
Test name
Test status
Simulation time 35505201892 ps
CPU time 49.77 seconds
Started Aug 03 05:02:09 PM PDT 24
Finished Aug 03 05:02:59 PM PDT 24
Peak memory 237220 kb
Host smart-d54f9e90-20e1-42d6-a6b0-62502368eebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843374983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2843374983
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4167357674
Short name T251
Test name
Test status
Simulation time 9128722250 ps
CPU time 26.16 seconds
Started Aug 03 05:02:07 PM PDT 24
Finished Aug 03 05:02:33 PM PDT 24
Peak memory 233148 kb
Host smart-a187351b-1248-47a0-8ea6-3d04e508269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167357674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4167357674
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3678090977
Short name T28
Test name
Test status
Simulation time 2211873005 ps
CPU time 7.15 seconds
Started Aug 03 05:02:02 PM PDT 24
Finished Aug 03 05:02:09 PM PDT 24
Peak memory 224972 kb
Host smart-65dd8d30-f1cb-42e3-8e2c-b5fa53567a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678090977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3678090977
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1531745239
Short name T991
Test name
Test status
Simulation time 425729032 ps
CPU time 4.16 seconds
Started Aug 03 05:02:03 PM PDT 24
Finished Aug 03 05:02:07 PM PDT 24
Peak memory 219736 kb
Host smart-8541cd49-df03-48f5-a6a4-cae6a1da6ba3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1531745239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1531745239
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2616288712
Short name T893
Test name
Test status
Simulation time 51566843529 ps
CPU time 198.49 seconds
Started Aug 03 05:01:59 PM PDT 24
Finished Aug 03 05:05:18 PM PDT 24
Peak memory 257804 kb
Host smart-0445a249-b460-4c97-9d89-b94cb4e770e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616288712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2616288712
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.640437179
Short name T582
Test name
Test status
Simulation time 7236329217 ps
CPU time 36.93 seconds
Started Aug 03 05:02:03 PM PDT 24
Finished Aug 03 05:02:41 PM PDT 24
Peak memory 216728 kb
Host smart-86874706-7544-4e6e-aebd-8727f3104931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640437179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.640437179
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1968475483
Short name T719
Test name
Test status
Simulation time 6105943209 ps
CPU time 9.31 seconds
Started Aug 03 05:02:08 PM PDT 24
Finished Aug 03 05:02:17 PM PDT 24
Peak memory 216672 kb
Host smart-5656d758-4d77-4880-883c-8e7677dc36bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968475483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1968475483
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2348017587
Short name T934
Test name
Test status
Simulation time 333983824 ps
CPU time 4.15 seconds
Started Aug 03 05:02:07 PM PDT 24
Finished Aug 03 05:02:12 PM PDT 24
Peak memory 216788 kb
Host smart-3523fe02-a939-4a7b-801c-08ab468fd628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348017587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2348017587
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.537819837
Short name T2
Test name
Test status
Simulation time 21798905 ps
CPU time 0.8 seconds
Started Aug 03 05:02:01 PM PDT 24
Finished Aug 03 05:02:02 PM PDT 24
Peak memory 206272 kb
Host smart-36a79946-f54d-4cd6-a807-334b121add2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537819837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.537819837
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.844409500
Short name T634
Test name
Test status
Simulation time 3227222798 ps
CPU time 10.15 seconds
Started Aug 03 05:02:03 PM PDT 24
Finished Aug 03 05:02:14 PM PDT 24
Peak memory 224956 kb
Host smart-f1654242-5972-4cba-ae20-73bcc77f40d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844409500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.844409500
Directory /workspace/9.spi_device_upload/latest
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