Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2991405	1			T1	1		T2	1		T3	9454
all_values[1]	2991405	1			T1	1		T2	1		T3	9454
all_values[2]	2991405	1			T1	1		T2	1		T3	9454
all_values[3]	2991405	1			T1	1		T2	1		T3	9454
all_values[4]	2991405	1			T1	1		T2	1		T3	9454
all_values[5]	2991405	1			T1	1		T2	1		T3	9454
all_values[6]	2991405	1			T1	1		T2	1		T3	9454
all_values[7]	2991405	1			T1	1		T2	1		T3	9454

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23270051

1

T1

8

T2

8

T3

75632

auto[1]

661189

1

T5

92

T15

17

T16

12928

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23904279

1

T1

8

T2

8

T3

75211

auto[1]

26961

1

T3

421

T5

62

T8

90

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2947626	1			T1	1		T2	1		T3	9235
all_values[0]	auto[0]	auto[1]	12631	1			T3	219		T5	1		T8	45
all_values[0]	auto[1]	auto[0]	30577	1			T5	9		T15	1		T16	1838
all_values[0]	auto[1]	auto[1]	571	1			T5	4		T16	9		T17	3
all_values[1]	auto[0]	auto[0]	2866994	1			T1	1		T2	1		T3	9310
all_values[1]	auto[0]	auto[1]	8060	1			T3	144		T5	7		T8	45
all_values[1]	auto[1]	auto[0]	115876	1			T5	8		T16	1841		T17	8
all_values[1]	auto[1]	auto[1]	475	1			T5	3		T15	2		T16	7
all_values[2]	auto[0]	auto[0]	2866961	1			T1	1		T2	1		T3	9396
all_values[2]	auto[0]	auto[1]	3023	1			T3	58		T5	3		T26	37
all_values[2]	auto[1]	auto[0]	121104	1			T5	7		T15	1		T16	1846
all_values[2]	auto[1]	auto[1]	317	1			T5	7		T15	3		T17	6
all_values[3]	auto[0]	auto[0]	2955026	1			T1	1		T2	1		T3	9454
all_values[3]	auto[0]	auto[1]	188	1			T17	3		T18	5		T19	3
all_values[3]	auto[1]	auto[0]	35992	1			T5	8		T15	2		T16	1844
all_values[3]	auto[1]	auto[1]	199	1			T5	4		T15	3		T16	2
all_values[4]	auto[0]	auto[0]	2960722	1			T1	1		T2	1		T3	9454
all_values[4]	auto[0]	auto[1]	216	1			T5	5		T15	2		T16	2
all_values[4]	auto[1]	auto[0]	30261	1			T5	4		T15	1		T17	1
all_values[4]	auto[1]	auto[1]	206	1			T5	8		T16	2		T17	3
all_values[5]	auto[0]	auto[0]	2973187	1			T1	1		T2	1		T3	9454
all_values[5]	auto[0]	auto[1]	165	1			T5	3		T15	1		T17	4
all_values[5]	auto[1]	auto[0]	17883	1			T5	9		T16	1845		T17	2
all_values[5]	auto[1]	auto[1]	170	1			T5	3		T16	2		T17	6
all_values[6]	auto[0]	auto[0]	2823116	1			T1	1		T2	1		T3	9454
all_values[6]	auto[0]	auto[1]	185	1			T5	4		T15	1		T16	1
all_values[6]	auto[1]	auto[0]	167914	1			T5	7		T15	3		T16	1844
all_values[6]	auto[1]	auto[1]	190	1			T5	4		T15	1		T16	2
all_values[7]	auto[0]	auto[0]	2851775	1			T1	1		T2	1		T3	9454
all_values[7]	auto[0]	auto[1]	176	1			T5	5		T16	1		T17	6
all_values[7]	auto[1]	auto[0]	139265	1			T5	6		T16	1844		T17	2
all_values[7]	auto[1]	auto[1]	189	1			T5	1		T16	2		T17	4