Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35127	1			T2	18		T3	246		T4	20
auto[SpiFlashAddrCfg]	8251	1			T1	6		T3	39		T7	37
auto[SpiFlashAddr3b]	9864	1			T3	78		T7	50		T8	11
auto[SpiFlashAddr4b]	8524	1			T1	4		T3	51		T7	76

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35395

1

T1

10

T2

18

T3

174

auto[1]

26371

1

T3

240

T7

223

T8

23

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32718

1

T1

10

T2

18

T3

259

auto[1]

29048

1

T3

155

T7

248

T8

30

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40120	1			T1	4		T2	18		T3	282
values[1]	1199	1			T3	8		T7	2		T8	4
values[2]	1627	1			T3	10		T7	12		T8	6
values[3]	1574	1			T3	7		T7	6		T8	3
values[4]	1559	1			T3	8		T7	10		T8	7
values[5]	1591	1			T1	2		T3	8		T7	7
values[6]	1618	1			T3	11		T7	17		T8	3
values[7]	1597	1			T3	6		T7	6		T8	3
values[8]	10881	1			T1	4		T3	74		T7	71

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34719

1

T1

10

T2

18

T3

414

auto[1]

27047

1

T26

197

T27

70

T34

160

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58330

1

T1

10

T2

18

T3

395

write

3436

1

T3

19

T7

19

T8

1

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

21085

1

T1

6

T2

18

T3

135

valids[0x1]

40681

1

T1

4

T3

279

T7

342

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1756	1			T3	17		T7	7		T8	4
internal_process_ops[0x5a]	1681	1			T3	15		T7	7		T8	1
internal_process_ops[0x05]	20038	1			T3	160		T7	240		T8	9
internal_process_ops[0x35]	1656	1			T3	4		T7	10		T8	4
internal_process_ops[0x15]	1736	1			T3	8		T7	6		T8	1
internal_process_ops[0x03]	1195	1			T3	13		T7	7		T8	1
internal_process_ops[0x0b]	1210	1			T1	4		T3	10		T7	9
internal_process_ops[0x3b]	1163	1			T1	2		T3	8		T7	8
internal_process_ops[0x6b]	1223	1			T1	4		T3	11		T7	13
internal_process_ops[0xbb]	1211	1			T3	7		T7	13		T12	2
internal_process_ops[0xeb]	1145	1			T3	10		T7	13		T8	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60119

1

T1

10

T2

18

T3

405

auto[1]

1647

1

T3

9

T7

9

T8

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59290

1

T1

10

T2

18

T3

390

auto[1]

2476

1

T3

24

T7

16

T8

1

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11533

1

T2

18

T3

100

T4

20

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6991

1

T3

141

T7

143

T8

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2339

1

T1

6

T3

17

T7

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2092

1

T3

17

T7

22

T8

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2845

1

T3

34

T7

21

T8

7

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2569

1

T3

37

T7

24

T8

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2534

1

T1

4

T3

18

T7

48

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2065

1

T3

31

T7

22

T8

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

118

1

T7

1

T13

3

T16

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

102

1

T3

1

T13

1

T39

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

119

1

T3

4

T7

2

T13

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

91

1

T13

6

T41

1

T39

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

127

1

T41

4

T39

3

T16

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

111

1

T7

2

T13

7

T41

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

80

1

T3

1

T7

1

T13

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

128

1

T3

4

T7

2

T13

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

109

1

T3

1

T7

1

T13

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

114

1

T3

1

T41

1

T42

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

99

1

T3

4

T7

2

T13

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

94

1

T3

1

T7

2

T13

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

130

1

T7

1

T13

1

T39

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

96

1

T3

2

T7

2

T8

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

129

1

T7

2

T13

3

T35

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

104

1

T7

1

T41

2

T42

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9503

1

T26

83

T27

33

T34

47

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6221

1

T26

23

T27

11

T34

17

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1528

1

T26

8

T27

1

T34

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1416

1

T26

17

T27

7

T34

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1845

1

T26

12

T27

5

T34

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1823

1

T26

11

T27

4

T34

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1520

1

T26

15

T27

5

T34

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1506

1

T26

11

T27

2

T34

14

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

108

1

T26

2

T15

5

T45

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

99

1

T34

1

T15

1

T45

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

126

1

T26

4

T15

3

T45

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

116

1

T26

1

T45

4

T165

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

120

1

T26

1

T27

1

T34

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

105

1

T15

1

T75

3

T165

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

103

1

T26

1

T34

1

T75

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

102

1

T26

1

T34

3

T15

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

92

1

T15

2

T75

1

T166

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T75

1

T165

1

T159

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

90

1

T26

2

T34

1

T75

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

86

1

T75

1

T165

1

T16

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

124

1

T26

2

T34

1

T15

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

95

1

T15

2

T165

1

T159

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

115

1

T26

2

T27

1

T34

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

106

1

T26

1

T15

3

T165

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4520	1			T2	18		T3	53		T4	20
auto[0]	values[0]	valids[0x1]	17292	1			T1	4		T3	229		T7	302
auto[0]	values[1]	valids[0x1]	643	1			T3	8		T7	2		T8	4
auto[0]	values[2]	valids[0x0]	669	1			T3	9		T7	9		T8	4
auto[0]	values[2]	valids[0x1]	337	1			T3	1		T7	3		T8	2
auto[0]	values[3]	valids[0x0]	619	1			T3	4		T7	4		T8	3
auto[0]	values[3]	valids[0x1]	355	1			T3	3		T7	2		T13	1
auto[0]	values[4]	valids[0x0]	647	1			T3	5		T7	9		T8	6
auto[0]	values[4]	valids[0x1]	306	1			T3	3		T7	1		T8	1
auto[0]	values[5]	valids[0x0]	612	1			T1	2		T3	5		T7	3
auto[0]	values[5]	valids[0x1]	316	1			T3	3		T7	4		T8	2
auto[0]	values[6]	valids[0x0]	633	1			T3	9		T7	14		T8	1
auto[0]	values[6]	valids[0x1]	336	1			T3	2		T7	3		T8	2
auto[0]	values[7]	valids[0x0]	637	1			T3	2		T7	5		T8	1
auto[0]	values[7]	valids[0x1]	297	1			T3	4		T7	1		T8	2
auto[0]	values[8]	valids[0x0]	4053	1			T1	4		T3	48		T7	47
auto[0]	values[8]	valids[0x1]	2447	1			T3	26		T7	24		T8	2
auto[1]	values[0]	valids[0x0]	3859	1			T26	40		T27	16		T34	20
auto[1]	values[0]	valids[0x1]	14449	1			T26	97		T27	32		T34	59
auto[1]	values[1]	valids[0x1]	556	1			T26	2		T27	3		T34	8
auto[1]	values[2]	valids[0x0]	382	1			T26	1		T27	2		T34	2
auto[1]	values[2]	valids[0x1]	239	1			T26	1		T15	6		T45	2
auto[1]	values[3]	valids[0x0]	358	1			T26	5		T27	1		T34	5
auto[1]	values[3]	valids[0x1]	242	1			T26	1		T27	1		T34	1
auto[1]	values[4]	valids[0x0]	355	1			T26	2		T34	2		T15	4
auto[1]	values[4]	valids[0x1]	251	1			T34	6		T45	2		T75	8
auto[1]	values[5]	valids[0x0]	399	1			T26	5		T27	1		T34	1
auto[1]	values[5]	valids[0x1]	264	1			T34	4		T15	1		T45	4
auto[1]	values[6]	valids[0x0]	405	1			T26	2		T34	2		T15	5
auto[1]	values[6]	valids[0x1]	244	1			T27	2		T34	1		T15	2
auto[1]	values[7]	valids[0x0]	391	1			T26	6		T27	2		T34	7
auto[1]	values[7]	valids[0x1]	272	1			T26	1		T34	3		T15	4
auto[1]	values[8]	valids[0x0]	2546	1			T26	21		T27	8		T34	26
auto[1]	values[8]	valids[0x1]	1835	1			T26	13		T27	2		T34	13