Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3711598

1

T1

2613

T2

239

T3

14985

auto[1]

28666

1

T3

154

T7

225

T8

6

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

992883

1

T1

2613

T2

239

T3

104

auto[1]

2747381

1

T3

15035

T7

15662

T8

6744

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	701468	1			T1	1056		T2	7		T3	277
auto[524288:1048575]	439686	1			T1	179		T2	124		T3	260
auto[1048576:1572863]	385970	1			T3	782		T7	1465		T8	259
auto[1572864:2097151]	466501	1			T2	99		T3	3941		T4	2
auto[2097152:2621439]	448935	1			T1	831		T3	30		T4	7
auto[2621440:3145727]	428668	1			T1	12		T3	5304		T7	262
auto[3145728:3670015]	396565	1			T1	522		T2	3		T3	4269
auto[3670016:4194303]	472471	1			T1	13		T2	6		T3	276

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2785716

1

T1

22

T2

20

T3

15132

auto[1]

954548

1

T1

2591

T2

219

T3

7

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3194758

1

T1

2613

T2

231

T3

14597

auto[1]

545506

1

T2

8

T3

542

T4

13

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	187648	1			T1	1056		T2	2		T3	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	421608	1			T3	258		T7	769		T8	265
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	137024	1			T1	179		T2	124		T3	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	225300	1			T3	256		T7	3728		T35	897
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	96359	1			T3	4		T7	4		T8	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	226882	1			T3	769		T7	513		T8	256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	148081	1			T2	99		T3	10		T4	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	264578	1			T3	3394		T13	5313		T35	512
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	102240	1			T1	831		T3	10		T4	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	280094	1			T3	5		T7	526		T13	512
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	105275	1			T1	12		T3	14		T7	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	247515	1			T3	5253		T7	257		T13	2103
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	92296	1			T1	522		T2	2		T3	15
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	225400	1			T3	4196		T7	1161		T8	1644
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	110309	1			T1	13		T2	4		T3	6
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	301365	1			T3	258		T7	2786		T13	2102
auto[0]	auto[1]	auto[0:524287]	auto[0]	2536	1			T2	5		T3	1		T7	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	84310	1			T7	4288		T27	1		T15	1280
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	878	1			T7	1		T26	6		T27	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	72893	1			T35	1806		T26	514		T15	388
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1405	1			T3	2		T7	4		T8	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	58220	1			T3	1		T7	906		T13	640
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	732	1			T3	5		T13	7		T26	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	49939	1			T3	515		T13	4		T26	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1018	1			T4	3		T7	3		T26	8
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	62308	1			T7	258		T26	516		T15	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1030	1			T3	3		T13	2		T26	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	71398	1			T26	514		T15	516		T45	3734
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1124	1			T2	1		T4	8		T7	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	74066	1			T7	256		T15	516		T75	69
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	723	1			T2	2		T3	1		T4	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	57044	1			T7	5		T8	4574		T27	385
auto[1]	auto[0]	auto[0:524287]	auto[0]	597	1			T3	2		T7	1		T13	13
auto[1]	auto[0]	auto[0:524287]	auto[1]	3693	1			T3	11		T7	15		T15	4
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	406	1			T7	1		T35	1		T26	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2579	1			T7	17		T35	27		T26	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	368	1			T3	1		T7	1		T13	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2096	1			T3	4		T7	6		T35	38
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	383	1			T3	1		T13	19		T33	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2295	1			T3	3		T13	1		T15	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	438	1			T3	5		T7	4		T13	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2134	1			T3	10		T7	48		T26	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	425	1			T3	4		T7	1		T13	17
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2336	1			T3	30		T7	1		T35	16
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	398	1			T3	5		T13	4		T35	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1937	1			T3	53		T35	4		T26	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	379	1			T3	2		T7	1		T13	15
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2320	1			T3	9		T7	17		T113	20
auto[1]	auto[1]	auto[0:524287]	auto[0]	132	1			T7	1		T75	2		T166	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	944	1			T7	34		T75	39		T166	12
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	118	1			T26	2		T185	1		T17	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	488	1			T26	3		T185	59		T40	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	62	1			T3	1		T7	2		T26	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	578	1			T7	29		T26	3		T15	45
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	109	1			T3	3		T26	1		T15	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	384	1			T3	10		T15	34		T39	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	99	1			T7	2		T26	2		T75	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	604	1			T7	20		T26	6		T75	24
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	109	1			T26	2		T15	1		T45	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	580	1			T26	1		T15	7		T39	36
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	104	1			T15	1		T75	2		T42	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1240	1			T15	1		T75	5		T42	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	78	1			T7	2		T8	1		T13	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	253	1			T7	22		T8	5		T27	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2221761	1			T1	22		T2	13		T3	14456
auto[0]	auto[0]	auto[1]	950213	1			T1	2591		T2	218		T3	1
auto[0]	auto[1]	auto[0]	536060	1			T2	7		T3	528		T4	11
auto[0]	auto[1]	auto[1]	3564	1			T2	1		T4	2		T7	5
auto[1]	auto[0]	auto[0]	22154	1			T3	135		T7	109		T13	59
auto[1]	auto[0]	auto[1]	630	1			T3	5		T7	4		T13	17
auto[1]	auto[1]	auto[0]	5741	1			T3	13		T7	107		T8	6
auto[1]	auto[1]	auto[1]	141	1			T3	1		T7	5		T13	1