Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2991405	1			T1	1		T2	1		T3	9454
all_pins[1]	2991405	1			T1	1		T2	1		T3	9454
all_pins[2]	2991405	1			T1	1		T2	1		T3	9454
all_pins[3]	2991405	1			T1	1		T2	1		T3	9454
all_pins[4]	2991405	1			T1	1		T2	1		T3	9454
all_pins[5]	2991405	1			T1	1		T2	1		T3	9454
all_pins[6]	2991405	1			T1	1		T2	1		T3	9454
all_pins[7]	2991405	1			T1	1		T2	1		T3	9454

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23760847	1			T1	8		T2	8		T3	75632
values[0x1]	170393	1			T5	34		T15	9		T16	2069
transitions[0x0=>0x1]	168927	1			T5	25		T15	5		T16	1851
transitions[0x1=>0x0]	168938	1			T5	25		T15	5		T16	1851

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2990799	1			T1	1		T2	1		T3	9454
all_pins[0]	values[0x1]	606	1			T5	4		T16	11		T17	3
all_pins[0]	transitions[0x0=>0x1]	536	1			T5	3		T16	2		T17	2
all_pins[0]	transitions[0x1=>0x0]	444	1			T5	2		T15	2		T17	2
all_pins[1]	values[0x0]	2990891	1			T1	1		T2	1		T3	9454
all_pins[1]	values[0x1]	514	1			T5	3		T15	2		T16	9
all_pins[1]	transitions[0x0=>0x1]	350	1			T5	1		T15	1		T16	9
all_pins[1]	transitions[0x1=>0x0]	162	1			T5	5		T15	2		T17	5
all_pins[2]	values[0x0]	2991079	1			T1	1		T2	1		T3	9454
all_pins[2]	values[0x1]	326	1			T5	7		T15	3		T17	6
all_pins[2]	transitions[0x0=>0x1]	273	1			T5	5		T17	4		T18	2
all_pins[2]	transitions[0x1=>0x0]	146	1			T5	2		T16	2		T17	1
all_pins[3]	values[0x0]	2991206	1			T1	1		T2	1		T3	9454
all_pins[3]	values[0x1]	199	1			T5	4		T15	3		T16	2
all_pins[3]	transitions[0x0=>0x1]	136	1			T5	3		T15	3		T16	2
all_pins[3]	transitions[0x1=>0x0]	143	1			T5	7		T16	2		T17	2
all_pins[4]	values[0x0]	2991199	1			T1	1		T2	1		T3	9454
all_pins[4]	values[0x1]	206	1			T5	8		T16	2		T17	3
all_pins[4]	transitions[0x0=>0x1]	167	1			T5	7		T16	1		T17	2
all_pins[4]	transitions[0x1=>0x0]	1068	1			T5	2		T16	207		T17	5
all_pins[5]	values[0x0]	2990298	1			T1	1		T2	1		T3	9454
all_pins[5]	values[0x1]	1107	1			T5	3		T16	208		T17	6
all_pins[5]	transitions[0x0=>0x1]	132	1			T5	2		T16	3		T17	5
all_pins[5]	transitions[0x1=>0x0]	166271	1			T5	3		T15	1		T16	1630
all_pins[6]	values[0x0]	2824159	1			T1	1		T2	1		T3	9454
all_pins[6]	values[0x1]	167246	1			T5	4		T15	1		T16	1835
all_pins[6]	transitions[0x0=>0x1]	167197	1			T5	3		T15	1		T16	1833
all_pins[6]	transitions[0x1=>0x0]	140	1			T17	3		T18	1		T20	9
all_pins[7]	values[0x0]	2991216	1			T1	1		T2	1		T3	9454
all_pins[7]	values[0x1]	189	1			T5	1		T16	2		T17	4
all_pins[7]	transitions[0x0=>0x1]	136	1			T5	1		T16	1		T17	4
all_pins[7]	transitions[0x1=>0x0]	564	1			T5	4		T16	10		T17	3