Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20158

1

T1

10

T2

18

T3

174

auto[1]

14561

1

T3

240

T7

223

T8

23

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3932	1			T3	128		T7	41		T8	26
values[1]	4406	1			T3	24		T13	60		T35	45
values[2]	5043	1			T1	10		T3	30		T4	20
values[3]	4723	1			T7	64		T33	20		T41	20
values[4]	4250	1			T2	18		T3	21		T7	99
values[5]	4078	1			T3	166		T7	69		T8	20
values[6]	4164	1			T3	25		T7	82		T12	2
values[7]	4123	1			T3	20		T7	76		T10	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4562	1			T3	84		T7	96		T13	40
values[1]	3570	1			T3	30		T7	44		T12	2
values[2]	3735	1			T3	73		T7	98		T13	40
values[3]	3905	1			T2	18		T4	20		T7	20
values[4]	4194	1			T1	10		T7	20		T13	40
values[5]	4631	1			T3	48		T7	69		T8	20
values[6]	4567	1			T3	159		T7	118		T13	20
values[7]	5555	1			T3	20		T7	20		T8	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	440	1			T3	48		T7	10		T39	88
auto[0]	values[0]	values[1]	208	1			T129	20		T200	15		T227	12
auto[0]	values[0]	values[2]	147	1			T7	19		T87	2		T183	13
auto[0]	values[0]	values[3]	184	1			T8	19		T40	11		T187	11
auto[0]	values[0]	values[4]	256	1			T41	7		T215	12		T29	83
auto[0]	values[0]	values[5]	260	1			T3	12		T228	20		T187	34
auto[0]	values[0]	values[6]	391	1			T3	15		T41	26		T229	4
auto[0]	values[0]	values[7]	295	1			T42	11		T157	6		T188	48
auto[0]	values[1]	values[0]	349	1			T41	8		T178	10		T58	78
auto[0]	values[1]	values[1]	285	1			T230	8		T41	11		T39	81
auto[0]	values[1]	values[2]	318	1			T42	16		T231	6		T200	12
auto[0]	values[1]	values[3]	377	1			T13	9		T187	43		T222	4
auto[0]	values[1]	values[4]	346	1			T13	10		T35	12		T39	22
auto[0]	values[1]	values[5]	312	1			T16	12		T29	15		T202	7
auto[0]	values[1]	values[6]	329	1			T3	9		T42	7		T161	16
auto[0]	values[1]	values[7]	423	1			T13	13		T35	18		T232	10
auto[0]	values[2]	values[0]	324	1			T7	11		T163	38		T40	16
auto[0]	values[2]	values[1]	476	1			T3	10		T40	10		T58	55
auto[0]	values[2]	values[2]	267	1			T233	4		T204	9		T186	12
auto[0]	values[2]	values[3]	432	1			T4	20		T35	47		T16	11
auto[0]	values[2]	values[4]	284	1			T1	10		T44	7		T31	9
auto[0]	values[2]	values[5]	414	1			T41	9		T16	100		T44	11
auto[0]	values[2]	values[6]	344	1			T13	9		T208	20		T187	13
auto[0]	values[2]	values[7]	427	1			T43	14		T221	10		T182	13
auto[0]	values[3]	values[0]	454	1			T188	14		T58	103		T195	12
auto[0]	values[3]	values[1]	328	1			T7	35		T40	38		T187	41
auto[0]	values[3]	values[2]	244	1			T44	16		T18	8		T178	16
auto[0]	values[3]	values[3]	320	1			T39	11		T162	4		T188	8
auto[0]	values[3]	values[4]	392	1			T7	12		T129	6		T195	21
auto[0]	values[3]	values[5]	453	1			T41	7		T186	9		T29	13
auto[0]	values[3]	values[6]	183	1			T16	15		T234	6		T235	14
auto[0]	values[3]	values[7]	304	1			T33	13		T187	10		T58	23
auto[0]	values[4]	values[0]	235	1			T7	16		T13	13		T129	14
auto[0]	values[4]	values[1]	300	1			T40	5		T61	8		T236	6
auto[0]	values[4]	values[2]	216	1			T3	10		T7	11		T13	17
auto[0]	values[4]	values[3]	228	1			T2	18		T187	12		T85	16
auto[0]	values[4]	values[4]	318	1			T204	8		T205	11		T201	101
auto[0]	values[4]	values[5]	277	1			T113	12		T41	7		T16	8
auto[0]	values[4]	values[6]	348	1			T197	29		T237	40		T202	8
auto[0]	values[4]	values[7]	342	1			T7	13		T8	12		T13	6
auto[0]	values[5]	values[0]	322	1			T211	10		T42	15		T129	17
auto[0]	values[5]	values[1]	170	1			T35	10		T129	14		T205	13
auto[0]	values[5]	values[2]	244	1			T3	11		T43	13		T182	11
auto[0]	values[5]	values[3]	249	1			T238	14		T40	11		T18	16
auto[0]	values[5]	values[4]	181	1			T39	6		T239	10		T240	17
auto[0]	values[5]	values[5]	261	1			T3	15		T7	12		T8	12
auto[0]	values[5]	values[6]	439	1			T3	25		T39	9		T241	10
auto[0]	values[5]	values[7]	428	1			T35	13		T41	13		T129	13
auto[0]	values[6]	values[0]	413	1			T13	16		T187	50		T206	6
auto[0]	values[6]	values[1]	151	1			T12	2		T13	7		T242	16
auto[0]	values[6]	values[2]	341	1			T3	9		T7	11		T39	12
auto[0]	values[6]	values[3]	158	1			T7	13		T90	4		T16	12
auto[0]	values[6]	values[4]	292	1			T41	9		T42	10		T18	14
auto[0]	values[6]	values[5]	337	1			T35	14		T74	2		T39	10
auto[0]	values[6]	values[6]	407	1			T7	31		T41	12		T243	16
auto[0]	values[6]	values[7]	498	1			T13	13		T40	17		T187	87
auto[0]	values[7]	values[0]	249	1			T91	8		T43	12		T187	31
auto[0]	values[7]	values[1]	261	1			T39	56		T244	9		T245	16
auto[0]	values[7]	values[2]	317	1			T35	13		T40	32		T182	13
auto[0]	values[7]	values[3]	320	1			T209	10		T31	12		T181	25
auto[0]	values[7]	values[4]	324	1			T13	12		T182	7		T18	13
auto[0]	values[7]	values[5]	209	1			T10	2		T43	14		T246	14
auto[0]	values[7]	values[6]	280	1			T7	68		T42	17		T16	9
auto[0]	values[7]	values[7]	477	1			T3	10		T35	24		T39	15
auto[1]	values[0]	values[0]	245	1			T3	36		T7	10		T39	8
auto[1]	values[0]	values[1]	106	1			T129	4		T200	5		T247	7
auto[1]	values[0]	values[2]	95	1			T7	2		T183	15		T200	4
auto[1]	values[0]	values[3]	158	1			T8	7		T40	9		T187	61
auto[1]	values[0]	values[4]	431	1			T41	13		T29	11		T248	8
auto[1]	values[0]	values[5]	201	1			T3	12		T187	8		T31	15
auto[1]	values[0]	values[6]	254	1			T3	5		T41	14		T187	3
auto[1]	values[0]	values[7]	261	1			T42	14		T188	3		T18	4
auto[1]	values[1]	values[0]	190	1			T36	12		T41	12		T178	11
auto[1]	values[1]	values[1]	198	1			T41	9		T39	17		T31	16
auto[1]	values[1]	values[2]	176	1			T42	7		T249	2		T200	8
auto[1]	values[1]	values[3]	165	1			T13	11		T187	10		T200	6
auto[1]	values[1]	values[4]	212	1			T13	10		T35	8		T39	18
auto[1]	values[1]	values[5]	229	1			T16	10		T29	43		T202	19
auto[1]	values[1]	values[6]	315	1			T3	15		T42	13		T44	10
auto[1]	values[1]	values[7]	182	1			T13	7		T35	7		T16	9
auto[1]	values[2]	values[0]	176	1			T7	43		T40	10		T204	4
auto[1]	values[2]	values[1]	281	1			T3	20		T40	10		T58	14
auto[1]	values[2]	values[2]	304	1			T204	11		T186	8		T192	10
auto[1]	values[2]	values[3]	160	1			T35	12		T16	11		T250	6
auto[1]	values[2]	values[4]	186	1			T44	15		T31	23		T251	9
auto[1]	values[2]	values[5]	359	1			T41	11		T16	17		T44	9
auto[1]	values[2]	values[6]	200	1			T13	11		T187	7		T18	11
auto[1]	values[2]	values[7]	409	1			T43	6		T182	7		T129	12
auto[1]	values[3]	values[0]	212	1			T188	6		T58	6		T195	8
auto[1]	values[3]	values[1]	219	1			T7	9		T40	16		T187	10
auto[1]	values[3]	values[2]	127	1			T44	9		T18	18		T178	7
auto[1]	values[3]	values[3]	247	1			T39	36		T188	12		T58	6
auto[1]	values[3]	values[4]	264	1			T7	8		T252	2		T129	14
auto[1]	values[3]	values[5]	455	1			T41	13		T253	6		T186	11
auto[1]	values[3]	values[6]	188	1			T16	24		T204	9		T31	16
auto[1]	values[3]	values[7]	333	1			T33	7		T187	53		T58	71
auto[1]	values[4]	values[0]	183	1			T7	6		T13	7		T129	6
auto[1]	values[4]	values[1]	213	1			T40	62		T205	8		T29	11
auto[1]	values[4]	values[2]	239	1			T3	11		T7	46		T13	23
auto[1]	values[4]	values[3]	279	1			T187	14		T31	9		T180	6
auto[1]	values[4]	values[4]	319	1			T225	4		T204	12		T205	9
auto[1]	values[4]	values[5]	221	1			T113	46		T41	13		T16	30
auto[1]	values[4]	values[6]	188	1			T197	5		T237	7		T202	48
auto[1]	values[4]	values[7]	344	1			T7	7		T8	8		T13	14
auto[1]	values[5]	values[0]	342	1			T42	5		T129	3		T200	7
auto[1]	values[5]	values[1]	144	1			T35	10		T129	6		T205	7
auto[1]	values[5]	values[2]	211	1			T3	16		T43	76		T182	9
auto[1]	values[5]	values[3]	292	1			T40	9		T18	9		T201	6
auto[1]	values[5]	values[4]	109	1			T39	14		T239	10		T240	3
auto[1]	values[5]	values[5]	254	1			T3	9		T7	57		T8	8
auto[1]	values[5]	values[6]	195	1			T3	90		T39	11		T241	10
auto[1]	values[5]	values[7]	237	1			T35	7		T41	7		T129	15
auto[1]	values[6]	values[0]	188	1			T13	4		T187	17		T200	13
auto[1]	values[6]	values[1]	112	1			T13	13		T58	13		T195	10
auto[1]	values[6]	values[2]	311	1			T3	16		T7	9		T39	11
auto[1]	values[6]	values[3]	97	1			T7	7		T16	8		T213	9
auto[1]	values[6]	values[4]	151	1			T41	11		T42	11		T18	9
auto[1]	values[6]	values[5]	239	1			T35	6		T39	20		T42	17
auto[1]	values[6]	values[6]	232	1			T7	11		T41	8		T178	10
auto[1]	values[6]	values[7]	237	1			T13	7		T40	37		T187	8
auto[1]	values[7]	values[0]	240	1			T43	12		T187	7		T204	11
auto[1]	values[7]	values[1]	118	1			T39	10		T244	25		T245	4
auto[1]	values[7]	values[2]	178	1			T35	35		T40	11		T182	7
auto[1]	values[7]	values[3]	239	1			T254	4		T209	14		T31	75
auto[1]	values[7]	values[4]	129	1			T13	8		T182	13		T18	10
auto[1]	values[7]	values[5]	150	1			T43	6		T220	22		T246	6
auto[1]	values[7]	values[6]	274	1			T7	8		T42	3		T16	11
auto[1]	values[7]	values[7]	358	1			T3	10		T35	13		T39	5