Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	481	1			T3	2		T7	3		T8	1
auto[ReadAddrCrossIntoMailbox]	371	1			T1	2		T7	3		T35	2
auto[ReadAddrCrossOutOfMailbox]	369	1			T1	4		T3	1		T7	5
auto[ReadAddrCrossAllMailbox]	302	1			T3	3		T7	2		T8	1
auto[ReadAddrOutsideMailbox]	4046	1			T1	4		T3	53		T7	50

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2768

1

T1

5

T3

33

T7

28

auto[1]

2801

1

T1

5

T3

26

T7

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	929	1			T3	13		T7	7		T8	1
read_ops[0x0b]	942	1			T1	4		T3	10		T7	9
read_ops[0x3b]	905	1			T1	2		T3	8		T7	8
read_ops[0x6b]	926	1			T1	4		T3	11		T7	13
read_ops[0xbb]	946	1			T3	7		T7	13		T12	2
read_ops[0xeb]	921	1			T3	10		T7	13		T8	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T13	1		T161	1		T129	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T113	1		T161	1		T187	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	39	1			T35	1		T16	1		T58	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T7	1		T40	1		T187	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T129	1		T209	1		T217	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T7	2		T42	2		T40	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T3	2		T42	1		T16	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T13	1		T16	1		T58	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	331	1			T3	8		T7	2		T8	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	359	1			T3	3		T7	2		T13	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	48	1			T3	1		T161	3		T44	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	49	1			T13	1		T41	1		T16	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T211	1		T39	2		T16	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T211	1		T16	1		T208	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	39	1			T1	1		T35	1		T39	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T1	1		T35	1		T187	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T8	1		T39	1		T42	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T42	1		T208	2		T200	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	332	1			T1	1		T3	8		T7	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T1	1		T3	1		T7	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T35	2		T255	1		T58	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T33	1		T39	1		T44	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T1	1		T40	1		T182	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	41	1			T1	1		T35	1		T16	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T13	1		T35	2		T40	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T7	1		T13	1		T16	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T7	1		T35	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T39	1		T18	1		T58	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	329	1			T7	3		T13	3		T35	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	332	1			T3	8		T7	3		T8	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T8	1		T211	1		T195	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T211	1		T41	1		T39	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T129	1		T255	1		T58	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T187	1		T182	1		T18	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T1	1		T3	1		T7	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T1	1		T35	1		T39	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T33	1		T113	1		T58	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T3	1		T39	1		T42	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	349	1			T1	1		T3	4		T7	5
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	339	1			T1	1		T3	5		T7	7
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T3	1		T42	2		T16	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T7	1		T161	1		T40	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T44	1		T40	1		T187	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T39	1		T44	1		T182	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T42	1		T40	1		T243	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T35	1		T16	1		T243	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T211	1		T16	1		T243	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	31	1			T211	1		T243	1		T186	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	369	1			T3	5		T7	7		T12	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	337	1			T3	1		T7	5		T12	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T7	1		T13	1		T41	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	50	1			T7	1		T41	1		T16	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T7	1		T211	1		T39	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T7	1		T211	1		T16	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T35	2		T42	1		T16	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T7	1		T8	1		T35	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T7	1		T35	1		T16	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	29	1			T35	1		T41	1		T208	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	312	1			T3	3		T7	1		T13	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	340	1			T3	7		T7	6		T13	1