Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5422	1			T2	18		T3	175		T7	174
values[1]	4626	1			T3	55		T4	20		T12	2
values[2]	3968	1			T3	94		T7	57		T13	40
values[3]	4208	1			T3	24		T7	80		T13	20
values[4]	4905	1			T1	10		T3	20		T8	26
values[5]	3527	1			T7	105		T13	40		T35	20
values[6]	4094	1			T7	69		T13	40		T35	59
values[7]	3969	1			T3	46		T10	2		T13	60

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4551	1			T3	136		T7	140		T13	20
values[1]	4431	1			T3	24		T7	22		T13	40
values[2]	4360	1			T2	18		T3	68		T8	26
values[3]	4749	1			T3	23		T7	44		T12	2
values[4]	4672	1			T1	10		T3	21		T4	20
values[5]	3623	1			T3	97		T7	20		T10	2
values[6]	3842	1			T3	20		T8	20		T13	40
values[7]	4491	1			T3	25		T7	40		T13	40

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33879

1

T1

10

T2

18

T3

405

auto[1]

840

1

T3

9

T7

9

T8

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	591	1			T3	92		T35	19		T58	20
auto[0]	values[0]	values[1]	461	1			T18	63		T61	8		T209	24
auto[0]	values[0]	values[2]	651	1			T2	18		T3	36		T16	20
auto[0]	values[0]	values[3]	887	1			T7	44		T41	20		T161	16
auto[0]	values[0]	values[4]	878	1			T3	21		T7	127		T8	20
auto[0]	values[0]	values[5]	418	1			T3	23		T41	35		T42	19
auto[0]	values[0]	values[6]	705	1			T8	20		T44	23		T40	69
auto[0]	values[0]	values[7]	729	1			T42	18		T242	16		T40	67
auto[0]	values[1]	values[0]	481	1			T18	26		T29	130		T256	16
auto[0]	values[1]	values[1]	540	1			T39	20		T244	34		T257	51
auto[0]	values[1]	values[2]	578	1			T3	30		T16	18		T18	69
auto[0]	values[1]	values[3]	752	1			T12	2		T39	21		T40	34
auto[0]	values[1]	values[4]	610	1			T4	20		T57	10		T189	14
auto[0]	values[1]	values[5]	347	1			T13	20		T187	41		T182	20
auto[0]	values[1]	values[6]	519	1			T13	20		T40	20		T187	93
auto[0]	values[1]	values[7]	694	1			T3	25		T33	18		T58	84
auto[0]	values[2]	values[0]	481	1			T7	54		T13	18		T16	21
auto[0]	values[2]	values[1]	840	1			T3	24		T13	18		T16	39
auto[0]	values[2]	values[2]	336	1			T41	20		T188	20		T247	20
auto[0]	values[2]	values[3]	488	1			T3	23		T41	19		T186	20
auto[0]	values[2]	values[4]	469	1			T225	4		T42	18		T16	23
auto[0]	values[2]	values[5]	494	1			T3	23		T35	37		T43	88
auto[0]	values[2]	values[6]	369	1			T3	19		T16	19		T40	20
auto[0]	values[2]	values[7]	369	1			T182	20		T129	20		T18	25
auto[0]	values[3]	values[0]	499	1			T3	24		T208	20		T187	25
auto[0]	values[3]	values[1]	456	1			T35	25		T43	22		T40	20
auto[0]	values[3]	values[2]	630	1			T186	18		T180	20		T214	103
auto[0]	values[3]	values[3]	419	1			T13	20		T39	46		T241	20
auto[0]	values[3]	values[4]	449	1			T7	20		T195	27		T29	24
auto[0]	values[3]	values[5]	602	1			T7	20		T129	40		T18	19
auto[0]	values[3]	values[6]	436	1			T39	78		T42	20		T157	6
auto[0]	values[3]	values[7]	606	1			T7	38		T187	51		T206	6
auto[0]	values[4]	values[0]	698	1			T3	20		T39	20		T187	51
auto[0]	values[4]	values[1]	663	1			T232	10		T41	20		T39	20
auto[0]	values[4]	values[2]	895	1			T8	25		T39	30		T16	20
auto[0]	values[4]	values[3]	357	1			T238	14		T258	4		T259	18
auto[0]	values[4]	values[4]	680	1			T1	10		T13	17		T44	20
auto[0]	values[4]	values[5]	412	1			T35	48		T199	4		T18	23
auto[0]	values[4]	values[6]	469	1			T113	58		T89	4		T260	20
auto[0]	values[4]	values[7]	627	1			T41	20		T39	63		T163	38
auto[0]	values[5]	values[0]	573	1			T7	82		T39	46		T221	10
auto[0]	values[5]	values[1]	342	1			T7	22		T261	16		T186	19
auto[0]	values[5]	values[2]	439	1			T211	10		T41	19		T43	19
auto[0]	values[5]	values[3]	459	1			T13	17		T129	19		T204	20
auto[0]	values[5]	values[4]	365	1			T247	20		T180	20		T248	20
auto[0]	values[5]	values[5]	419	1			T40	27		T129	24		T58	20
auto[0]	values[5]	values[6]	376	1			T35	20		T16	20		T262	8
auto[0]	values[5]	values[7]	454	1			T13	20		T90	4		T18	23
auto[0]	values[6]	values[0]	514	1			T41	38		T18	24		T183	26
auto[0]	values[6]	values[1]	465	1			T13	19		T42	24		T16	22
auto[0]	values[6]	values[2]	311	1			T129	20		T58	34		T183	25
auto[0]	values[6]	values[3]	773	1			T35	59		T42	26		T178	19
auto[0]	values[6]	values[4]	748	1			T7	69		T222	4		T58	60
auto[0]	values[6]	values[5]	458	1			T42	20		T263	2		T16	38
auto[0]	values[6]	values[6]	253	1			T74	2		T18	23		T58	48
auto[0]	values[6]	values[7]	463	1			T13	18		T36	12		T44	21
auto[0]	values[7]	values[0]	606	1			T230	8		T39	95		T40	29
auto[0]	values[7]	values[1]	568	1			T41	18		T39	20		T250	42
auto[0]	values[7]	values[2]	386	1			T13	19		T178	24		T253	4
auto[0]	values[7]	values[3]	509	1			T13	18		T220	14		T31	50
auto[0]	values[7]	values[4]	353	1			T35	20		T87	2		T42	21
auto[0]	values[7]	values[5]	380	1			T3	45		T10	2		T35	20
auto[0]	values[7]	values[6]	630	1			T13	20		T210	8		T217	20
auto[0]	values[7]	values[7]	450	1			T264	4		T205	17		T213	23
auto[1]	values[0]	values[0]	12	1			T35	1		T265	1		T266	1
auto[1]	values[0]	values[1]	7	1			T267	1		T268	1		T269	2
auto[1]	values[0]	values[2]	15	1			T3	2		T200	1		T245	1
auto[1]	values[0]	values[3]	4	1			T58	2		T195	1		T270	1
auto[1]	values[0]	values[4]	21	1			T7	3		T39	2		T186	1
auto[1]	values[0]	values[5]	14	1			T3	1		T41	5		T42	1
auto[1]	values[0]	values[6]	14	1			T44	2		T40	2		T183	3
auto[1]	values[0]	values[7]	15	1			T42	2		T18	3		T217	1
auto[1]	values[1]	values[0]	5	1			T247	3		T237	1		T271	1
auto[1]	values[1]	values[1]	12	1			T251	1		T272	3		T156	3
auto[1]	values[1]	values[2]	21	1			T16	4		T18	1		T58	1
auto[1]	values[1]	values[3]	11	1			T39	2		T187	2		T197	3
auto[1]	values[1]	values[4]	16	1			T29	1		T192	2		T273	4
auto[1]	values[1]	values[5]	5	1			T187	1		T205	1		T251	2
auto[1]	values[1]	values[6]	11	1			T187	2		T192	2		T248	1
auto[1]	values[1]	values[7]	24	1			T33	2		T58	3		T204	2
auto[1]	values[2]	values[0]	27	1			T7	3		T13	2		T209	3
auto[1]	values[2]	values[1]	17	1			T13	2		T259	1		T192	4
auto[1]	values[2]	values[2]	12	1			T247	1		T181	3		T274	2
auto[1]	values[2]	values[3]	18	1			T41	1		T209	3		T217	2
auto[1]	values[2]	values[4]	11	1			T42	2		T16	2		T187	1
auto[1]	values[2]	values[5]	20	1			T3	4		T43	1		T187	2
auto[1]	values[2]	values[6]	13	1			T3	1		T16	1		T187	1
auto[1]	values[2]	values[7]	4	1			T204	1		T194	2		T275	1
auto[1]	values[3]	values[0]	10	1			T187	1		T244	3		T246	2
auto[1]	values[3]	values[1]	12	1			T43	2		T187	2		T276	1
auto[1]	values[3]	values[2]	29	1			T186	2		T214	5		T181	3
auto[1]	values[3]	values[3]	8	1			T18	1		T209	1		T29	1
auto[1]	values[3]	values[4]	16	1			T195	2		T29	2		T260	1
auto[1]	values[3]	values[5]	13	1			T18	1		T277	6		T278	1
auto[1]	values[3]	values[6]	9	1			T42	1		T213	3		T239	2
auto[1]	values[3]	values[7]	14	1			T7	2		T200	1		T181	1
auto[1]	values[4]	values[0]	10	1			T187	2		T217	1		T192	1
auto[1]	values[4]	values[1]	7	1			T40	1		T200	1		T271	1
auto[1]	values[4]	values[2]	18	1			T8	1		T188	3		T204	3
auto[1]	values[4]	values[3]	11	1			T259	2		T203	2		T265	3
auto[1]	values[4]	values[4]	19	1			T13	3		T182	2		T200	1
auto[1]	values[4]	values[5]	12	1			T31	3		T197	2		T248	4
auto[1]	values[4]	values[6]	17	1			T260	3		T31	4		T180	1
auto[1]	values[4]	values[7]	10	1			T39	3		T18	2		T202	2
auto[1]	values[5]	values[0]	18	1			T7	1		T39	1		T129	1
auto[1]	values[5]	values[1]	3	1			T186	1		T279	1		T280	1
auto[1]	values[5]	values[2]	19	1			T41	1		T43	1		T40	3
auto[1]	values[5]	values[3]	12	1			T13	3		T129	1		T203	3
auto[1]	values[5]	values[4]	16	1			T247	2		T240	1		T281	2
auto[1]	values[5]	values[5]	16	1			T40	1		T129	1		T240	1
auto[1]	values[5]	values[6]	3	1			T271	3		-	-		-	-
auto[1]	values[5]	values[7]	13	1			T204	1		T203	1		T201	2
auto[1]	values[6]	values[0]	16	1			T41	2		T18	1		T200	1
auto[1]	values[6]	values[1]	24	1			T13	1		T42	1		T40	1
auto[1]	values[6]	values[2]	13	1			T58	2		T207	6		T181	1
auto[1]	values[6]	values[3]	23	1			T42	1		T178	2		T58	2
auto[1]	values[6]	values[4]	14	1			T58	3		T209	1		T29	2
auto[1]	values[6]	values[5]	4	1			T265	1		T270	2		T282	1
auto[1]	values[6]	values[6]	4	1			T58	1		T239	1		T251	2
auto[1]	values[6]	values[7]	11	1			T13	2		T44	1		T187	3
auto[1]	values[7]	values[0]	10	1			T39	1		T260	2		T217	1
auto[1]	values[7]	values[1]	14	1			T41	2		T250	2		T204	4
auto[1]	values[7]	values[2]	7	1			T13	1		T178	1		T253	2
auto[1]	values[7]	values[3]	18	1			T13	2		T220	8		T31	2
auto[1]	values[7]	values[4]	7	1			T42	2		T201	3		T268	1
auto[1]	values[7]	values[5]	9	1			T3	1		T272	4		T268	4
auto[1]	values[7]	values[6]	14	1			T267	3		T283	3		T284	1
auto[1]	values[7]	values[7]	8	1			T205	3		T192	1		T251	1