Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	773	1			T5	17		T15	4		T16	4
all_values[1]	773	1			T5	17		T15	4		T16	4
all_values[2]	773	1			T5	17		T15	4		T16	4
all_values[3]	773	1			T5	17		T15	4		T16	4
all_values[4]	773	1			T5	17		T15	4		T16	4
all_values[5]	773	1			T5	17		T15	4		T16	4
all_values[6]	773	1			T5	17		T15	4		T16	4
all_values[7]	773	1			T5	17		T15	4		T16	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3223

1

T5

64

T15

21

T16

14

auto[1]

2961

1

T5

72

T15

11

T16

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2485

1

T5

48

T15

15

T16

13

auto[1]

3699

1

T5

88

T15

17

T16

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3537

1

T5

71

T15

20

T16

21

auto[1]

2647

1

T5

65

T15

12

T16

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	157	1			T5	4		T15	1		T17	1
all_values[0]	auto[0]	auto[0]	auto[1]	62	1			T15	1		T16	1		T17	4
all_values[0]	auto[0]	auto[1]	auto[0]	146	1			T5	5		T17	2		T18	3
all_values[0]	auto[0]	auto[1]	auto[1]	74	1			T5	3		T16	1		T17	2
all_values[0]	auto[1]	auto[0]	auto[1]	178	1			T5	2		T15	2		T16	1
all_values[0]	auto[1]	auto[1]	auto[1]	156	1			T5	3		T16	1		T17	3
all_values[1]	auto[0]	auto[0]	auto[0]	162	1			T5	2		T15	1		T17	2
all_values[1]	auto[0]	auto[0]	auto[1]	69	1			T5	2		T17	3		T18	4
all_values[1]	auto[0]	auto[1]	auto[0]	167	1			T5	2		T15	1		T16	4
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T5	3		T17	2		T20	1
all_values[1]	auto[1]	auto[0]	auto[1]	168	1			T5	5		T15	1		T17	2
all_values[1]	auto[1]	auto[1]	auto[1]	134	1			T5	3		T15	1		T17	2
all_values[2]	auto[0]	auto[0]	auto[0]	171	1			T5	1		T16	2		T17	4
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T5	1		T17	1		T18	2
all_values[2]	auto[0]	auto[1]	auto[0]	120	1			T5	1		T16	2		T17	2
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T5	1		T15	1		T17	3
all_values[2]	auto[1]	auto[0]	auto[1]	161	1			T5	5		T15	1		T17	2
all_values[2]	auto[1]	auto[1]	auto[1]	166	1			T5	8		T15	2		T17	5
all_values[3]	auto[0]	auto[0]	auto[0]	161	1			T5	6		T15	1		T16	2
all_values[3]	auto[0]	auto[0]	auto[1]	66	1			T17	3		T18	4		T19	1
all_values[3]	auto[0]	auto[1]	auto[0]	125	1			T5	2		T17	3		T20	6
all_values[3]	auto[0]	auto[1]	auto[1]	89	1			T5	1		T15	1		T16	1
all_values[3]	auto[1]	auto[0]	auto[1]	182	1			T5	2		T17	2		T18	1
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T5	6		T15	2		T16	1
all_values[4]	auto[0]	auto[0]	auto[0]	147	1			T15	2		T17	2		T18	2
all_values[4]	auto[0]	auto[0]	auto[1]	71	1			T5	3		T15	1		T16	1
all_values[4]	auto[0]	auto[1]	auto[0]	101	1			T5	2		T18	1		T20	4
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T5	3		T17	1		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	202	1			T5	2		T15	1		T16	1
all_values[4]	auto[1]	auto[1]	auto[1]	171	1			T5	7		T16	2		T17	3
all_values[5]	auto[0]	auto[0]	auto[0]	220	1			T5	4		T15	3		T16	1
all_values[5]	auto[0]	auto[1]	auto[0]	218	1			T5	7		T16	1		T17	2
all_values[5]	auto[1]	auto[0]	auto[1]	179	1			T5	4		T15	1		T16	1
all_values[5]	auto[1]	auto[1]	auto[1]	156	1			T5	2		T16	1		T17	6
all_values[6]	auto[0]	auto[0]	auto[0]	151	1			T5	1		T16	1		T17	1
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T5	2		T17	3		T18	2
all_values[6]	auto[0]	auto[1]	auto[0]	129	1			T5	2		T15	2		T17	1
all_values[6]	auto[0]	auto[1]	auto[1]	87	1			T5	1		T15	1		T16	2
all_values[6]	auto[1]	auto[0]	auto[1]	176	1			T5	5		T15	1		T16	1
all_values[6]	auto[1]	auto[1]	auto[1]	159	1			T5	6		T17	6		T19	4
all_values[7]	auto[0]	auto[0]	auto[0]	165	1			T5	6		T15	4		T17	5
all_values[7]	auto[0]	auto[0]	auto[1]	69	1			T5	2		T16	1		T17	2
all_values[7]	auto[0]	auto[1]	auto[0]	145	1			T5	3		T18	3		T19	6
all_values[7]	auto[0]	auto[1]	auto[1]	85	1			T5	1		T16	1		T17	1
all_values[7]	auto[1]	auto[0]	auto[1]	157	1			T5	5		T16	1		T17	7
all_values[7]	auto[1]	auto[1]	auto[1]	152	1			T16	1		T17	2		T18	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal