Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1777

1

T3

6

T8

5

T9

7

auto[1]

1805

1

T3

10

T8

4

T9

17

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1875

1

T3

10

T8

9

T23

2

auto[1]

1707

1

T3

6

T9

24

T11

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2884

1

T3

11

T8

5

T9

24

auto[1]

698

1

T3

5

T8

4

T23

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	734	1			T3	3		T8	1		T9	3
valid[1]	676	1			T3	1		T8	3		T9	1
valid[2]	722	1			T3	4		T8	2		T9	6
valid[3]	752	1			T3	5		T8	1		T9	5
valid[4]	698	1			T3	3		T8	2		T9	9

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T3	1		T26	2		T27	1
auto[0]	auto[0]	valid[0]	auto[1]	191	1			T9	1		T11	2		T25	3
auto[0]	auto[0]	valid[1]	auto[0]	102	1			T8	2		T26	2		T27	1
auto[0]	auto[0]	valid[1]	auto[1]	161	1			T3	1		T25	2		T28	3
auto[0]	auto[0]	valid[2]	auto[0]	114	1			T3	1		T8	1		T27	1
auto[0]	auto[0]	valid[2]	auto[1]	167	1			T9	3		T11	1		T25	6
auto[0]	auto[0]	valid[3]	auto[0]	130	1			T8	1		T15	1		T46	4
auto[0]	auto[0]	valid[3]	auto[1]	165	1			T3	2		T9	1		T11	1
auto[0]	auto[0]	valid[4]	auto[0]	117	1			T27	1		T299	4		T298	1
auto[0]	auto[0]	valid[4]	auto[1]	165	1			T9	2		T11	2		T25	3
auto[0]	auto[1]	valid[0]	auto[0]	107	1			T8	1		T26	1		T46	1
auto[0]	auto[1]	valid[0]	auto[1]	164	1			T3	1		T9	2		T25	4
auto[0]	auto[1]	valid[1]	auto[0]	121	1			T27	2		T46	2		T299	1
auto[0]	auto[1]	valid[1]	auto[1]	160	1			T9	1		T11	2		T25	3
auto[0]	auto[1]	valid[2]	auto[0]	126	1			T3	1		T26	1		T27	1
auto[0]	auto[1]	valid[2]	auto[1]	167	1			T9	3		T11	4		T28	3
auto[0]	auto[1]	valid[3]	auto[0]	127	1			T26	2		T27	1		T46	2
auto[0]	auto[1]	valid[3]	auto[1]	190	1			T3	1		T9	4		T11	1
auto[0]	auto[1]	valid[4]	auto[0]	110	1			T3	2		T26	4		T15	1
auto[0]	auto[1]	valid[4]	auto[1]	177	1			T3	1		T9	7		T25	5
auto[1]	auto[0]	valid[0]	auto[0]	73	1			T23	1		T26	1		T15	1
auto[1]	auto[0]	valid[1]	auto[0]	70	1			T8	1		T27	1		T298	1
auto[1]	auto[0]	valid[2]	auto[0]	67	1			T3	1		T26	1		T27	2
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T23	1		T46	1		T42	2
auto[1]	auto[0]	valid[4]	auto[0]	58	1			T26	1		T27	1		T165	1
auto[1]	auto[1]	valid[0]	auto[0]	76	1			T3	1		T26	3		T47	1
auto[1]	auto[1]	valid[1]	auto[0]	62	1			T15	1		T298	1		T16	1
auto[1]	auto[1]	valid[2]	auto[0]	81	1			T3	1		T8	1		T26	2
auto[1]	auto[1]	valid[3]	auto[0]	66	1			T3	2		T27	1		T165	1
auto[1]	auto[1]	valid[4]	auto[0]	71	1			T8	2		T26	1		T27	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal