Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47777

1

T3

307

T8

386

T23

14

auto[1]

18524

1

T3

67

T9

258

T11

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48852

1

T3

235

T8

262

T9

258

auto[1]

17449

1

T3

139

T8

124

T23

7

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34169	1			T3	208		T8	212		T9	132
others[1]	5598	1			T3	35		T8	29		T9	18
others[2]	5572	1			T3	22		T8	36		T9	20
others[3]	6404	1			T3	33		T8	32		T9	29
interest[1]	3692	1			T3	21		T8	16		T9	16
interest[4]	22347	1			T3	142		T8	140		T9	88
interest[64]	10866	1			T3	55		T8	61		T9	43

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15497	1			T3	97		T8	148		T23	2
auto[0]	auto[0]	others[1]	2555	1			T3	11		T8	20		T26	27
auto[0]	auto[0]	others[2]	2574	1			T3	6		T8	23		T23	1
auto[0]	auto[0]	others[3]	3002	1			T3	17		T8	24		T23	1
auto[0]	auto[0]	interest[1]	1682	1			T3	9		T8	8		T23	2
auto[0]	auto[0]	interest[4]	10131	1			T3	62		T8	100		T23	1
auto[0]	auto[0]	interest[64]	5018	1			T3	28		T8	39		T23	1
auto[0]	auto[1]	others[0]	9679	1			T3	36		T9	132		T11	13
auto[0]	auto[1]	others[1]	1534	1			T3	11		T9	18		T25	24
auto[0]	auto[1]	others[2]	1539	1			T3	2		T9	20		T25	24
auto[0]	auto[1]	others[3]	1717	1			T3	6		T9	29		T25	26
auto[0]	auto[1]	interest[1]	1029	1			T3	5		T9	16		T25	15
auto[0]	auto[1]	interest[4]	6391	1			T3	27		T9	88		T11	13
auto[0]	auto[1]	interest[64]	3026	1			T3	7		T9	43		T25	34
auto[1]	auto[0]	others[0]	8993	1			T3	75		T8	64		T23	7
auto[1]	auto[0]	others[1]	1509	1			T3	13		T8	9		T26	11
auto[1]	auto[0]	others[2]	1459	1			T3	14		T8	13		T26	5
auto[1]	auto[0]	others[3]	1685	1			T3	10		T8	8		T26	7
auto[1]	auto[0]	interest[1]	981	1			T3	7		T8	8		T26	12
auto[1]	auto[0]	interest[4]	5825	1			T3	53		T8	40		T23	4
auto[1]	auto[0]	interest[64]	2822	1			T3	20		T8	22		T26	17

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal