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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1129
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T1030 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1377218902 Aug 04 04:32:51 PM PDT 24 Aug 04 04:32:53 PM PDT 24 145773520 ps
T109 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4162006897 Aug 04 04:33:07 PM PDT 24 Aug 04 04:33:10 PM PDT 24 121590375 ps
T1031 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3571255842 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:12 PM PDT 24 764196910 ps
T1032 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1057121727 Aug 04 04:33:13 PM PDT 24 Aug 04 04:33:14 PM PDT 24 225394395 ps
T117 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3597183704 Aug 04 04:33:02 PM PDT 24 Aug 04 04:33:05 PM PDT 24 112427857 ps
T1033 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4046260857 Aug 04 04:33:03 PM PDT 24 Aug 04 04:33:08 PM PDT 24 192988750 ps
T172 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.614742461 Aug 04 04:33:12 PM PDT 24 Aug 04 04:33:28 PM PDT 24 2950594456 ps
T168 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1123285594 Aug 04 04:32:58 PM PDT 24 Aug 04 04:33:07 PM PDT 24 754856637 ps
T1034 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1863665570 Aug 04 04:33:20 PM PDT 24 Aug 04 04:33:22 PM PDT 24 1358354049 ps
T169 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2483868593 Aug 04 04:33:10 PM PDT 24 Aug 04 04:33:31 PM PDT 24 3338900665 ps
T170 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3542720417 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:16 PM PDT 24 1441758584 ps
T98 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2926803410 Aug 04 04:33:07 PM PDT 24 Aug 04 04:33:09 PM PDT 24 215737267 ps
T1035 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2487095615 Aug 04 04:33:18 PM PDT 24 Aug 04 04:33:21 PM PDT 24 876926759 ps
T1036 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1296086933 Aug 04 04:33:02 PM PDT 24 Aug 04 04:33:03 PM PDT 24 66073916 ps
T118 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2669379947 Aug 04 04:33:00 PM PDT 24 Aug 04 04:33:01 PM PDT 24 63254153 ps
T1037 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1413517958 Aug 04 04:33:14 PM PDT 24 Aug 04 04:33:15 PM PDT 24 24518316 ps
T1038 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2856313753 Aug 04 04:33:04 PM PDT 24 Aug 04 04:33:05 PM PDT 24 16476156 ps
T1039 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2431265084 Aug 04 04:33:14 PM PDT 24 Aug 04 04:33:15 PM PDT 24 13354918 ps
T1040 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2285514960 Aug 04 04:32:53 PM PDT 24 Aug 04 04:32:56 PM PDT 24 94767196 ps
T1041 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2281416742 Aug 04 04:33:18 PM PDT 24 Aug 04 04:33:18 PM PDT 24 118801879 ps
T1042 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.751036460 Aug 04 04:33:15 PM PDT 24 Aug 04 04:33:16 PM PDT 24 40557500 ps
T1043 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2927942375 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:09 PM PDT 24 46287594 ps
T167 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1043930209 Aug 04 04:33:22 PM PDT 24 Aug 04 04:33:40 PM PDT 24 2033772971 ps
T1044 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4040336506 Aug 04 04:33:14 PM PDT 24 Aug 04 04:33:16 PM PDT 24 29847655 ps
T1045 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1916440628 Aug 04 04:33:10 PM PDT 24 Aug 04 04:33:11 PM PDT 24 20640336 ps
T1046 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2937691802 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:08 PM PDT 24 11873619 ps
T99 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.394338309 Aug 04 04:33:05 PM PDT 24 Aug 04 04:33:07 PM PDT 24 83620652 ps
T100 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3402056810 Aug 04 04:33:10 PM PDT 24 Aug 04 04:33:14 PM PDT 24 63217753 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.623823115 Aug 04 04:33:03 PM PDT 24 Aug 04 04:33:04 PM PDT 24 15594612 ps
T1048 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1001120635 Aug 04 04:33:06 PM PDT 24 Aug 04 04:33:08 PM PDT 24 408681144 ps
T103 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.136881611 Aug 04 04:33:05 PM PDT 24 Aug 04 04:33:09 PM PDT 24 236404755 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2345694336 Aug 04 04:33:03 PM PDT 24 Aug 04 04:33:03 PM PDT 24 23080160 ps
T107 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1852882436 Aug 04 04:33:07 PM PDT 24 Aug 04 04:33:09 PM PDT 24 93946804 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2899018636 Aug 04 04:33:05 PM PDT 24 Aug 04 04:33:06 PM PDT 24 126347232 ps
T1051 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2205907994 Aug 04 04:33:07 PM PDT 24 Aug 04 04:33:09 PM PDT 24 180767736 ps
T1052 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4141333424 Aug 04 04:33:14 PM PDT 24 Aug 04 04:33:17 PM PDT 24 45945960 ps
T1053 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1460435266 Aug 04 04:33:12 PM PDT 24 Aug 04 04:33:12 PM PDT 24 72200431 ps
T1054 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4112181371 Aug 04 04:33:18 PM PDT 24 Aug 04 04:33:21 PM PDT 24 127645147 ps
T1055 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4251480379 Aug 04 04:33:14 PM PDT 24 Aug 04 04:33:15 PM PDT 24 36055711 ps
T1056 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2369223658 Aug 04 04:33:03 PM PDT 24 Aug 04 04:33:04 PM PDT 24 90213611 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1487705292 Aug 04 04:33:09 PM PDT 24 Aug 04 04:33:11 PM PDT 24 94623290 ps
T104 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4197022464 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:12 PM PDT 24 68240966 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2679204377 Aug 04 04:33:03 PM PDT 24 Aug 04 04:33:05 PM PDT 24 213149749 ps
T1058 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.146338129 Aug 04 04:33:13 PM PDT 24 Aug 04 04:33:16 PM PDT 24 194822985 ps
T120 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3676641241 Aug 04 04:32:48 PM PDT 24 Aug 04 04:33:04 PM PDT 24 879509776 ps
T121 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1530631233 Aug 04 04:33:06 PM PDT 24 Aug 04 04:33:08 PM PDT 24 1128239403 ps
T1059 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1740855183 Aug 04 04:33:04 PM PDT 24 Aug 04 04:33:16 PM PDT 24 414569520 ps
T1060 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2276221758 Aug 04 04:32:59 PM PDT 24 Aug 04 04:33:00 PM PDT 24 73325031 ps
T1061 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1781025258 Aug 04 04:33:18 PM PDT 24 Aug 04 04:33:21 PM PDT 24 141487613 ps
T79 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3080263722 Aug 04 04:33:03 PM PDT 24 Aug 04 04:33:04 PM PDT 24 22867626 ps
T1062 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3226554932 Aug 04 04:33:11 PM PDT 24 Aug 04 04:33:13 PM PDT 24 29957701 ps
T122 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.831332282 Aug 04 04:33:05 PM PDT 24 Aug 04 04:33:31 PM PDT 24 8184479815 ps
T105 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1453704200 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:12 PM PDT 24 329085656 ps
T1063 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2023203274 Aug 04 04:33:38 PM PDT 24 Aug 04 04:33:39 PM PDT 24 30711671 ps
T106 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2865860054 Aug 04 04:33:14 PM PDT 24 Aug 04 04:33:17 PM PDT 24 556910440 ps
T1064 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1994872963 Aug 04 04:32:57 PM PDT 24 Aug 04 04:32:59 PM PDT 24 129756478 ps
T123 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1073321325 Aug 04 04:33:17 PM PDT 24 Aug 04 04:33:19 PM PDT 24 37759147 ps
T1065 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1829363148 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:09 PM PDT 24 122393679 ps
T101 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.551407611 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:13 PM PDT 24 76329083 ps
T1066 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2352229918 Aug 04 04:33:04 PM PDT 24 Aug 04 04:33:06 PM PDT 24 1066711893 ps
T1067 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2539303303 Aug 04 04:32:57 PM PDT 24 Aug 04 04:33:12 PM PDT 24 535913699 ps
T1068 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2866806807 Aug 04 04:33:11 PM PDT 24 Aug 04 04:33:13 PM PDT 24 80245453 ps
T127 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2529181826 Aug 04 04:33:03 PM PDT 24 Aug 04 04:33:05 PM PDT 24 48327395 ps
T125 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2910125160 Aug 04 04:33:26 PM PDT 24 Aug 04 04:33:27 PM PDT 24 87290663 ps
T1069 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3049031711 Aug 04 04:33:21 PM PDT 24 Aug 04 04:33:21 PM PDT 24 50408968 ps
T126 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2840229421 Aug 04 04:32:57 PM PDT 24 Aug 04 04:33:13 PM PDT 24 614695093 ps
T1070 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.25534738 Aug 04 04:33:07 PM PDT 24 Aug 04 04:33:12 PM PDT 24 213227546 ps
T128 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1170305430 Aug 04 04:33:12 PM PDT 24 Aug 04 04:33:26 PM PDT 24 2870029262 ps
T1071 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.860801634 Aug 04 04:33:32 PM PDT 24 Aug 04 04:33:33 PM PDT 24 157481926 ps
T102 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1457139680 Aug 04 04:32:57 PM PDT 24 Aug 04 04:32:59 PM PDT 24 67861070 ps
T1072 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3705988026 Aug 04 04:33:03 PM PDT 24 Aug 04 04:33:15 PM PDT 24 1219143943 ps
T1073 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1148025200 Aug 04 04:33:09 PM PDT 24 Aug 04 04:33:12 PM PDT 24 44809220 ps
T1074 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3228307317 Aug 04 04:33:17 PM PDT 24 Aug 04 04:33:19 PM PDT 24 39155773 ps
T1075 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2384998381 Aug 04 04:33:01 PM PDT 24 Aug 04 04:33:05 PM PDT 24 153687459 ps
T1076 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1233142084 Aug 04 04:33:02 PM PDT 24 Aug 04 04:33:06 PM PDT 24 49894907 ps
T1077 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.119803639 Aug 04 04:33:04 PM PDT 24 Aug 04 04:33:07 PM PDT 24 195345579 ps
T1078 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2573893814 Aug 04 04:33:22 PM PDT 24 Aug 04 04:33:24 PM PDT 24 45520079 ps
T80 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1769075046 Aug 04 04:33:11 PM PDT 24 Aug 04 04:33:13 PM PDT 24 20957640 ps
T1079 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1183388474 Aug 04 04:33:25 PM PDT 24 Aug 04 04:33:31 PM PDT 24 936921297 ps
T1080 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.178291264 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:09 PM PDT 24 15117774 ps
T1081 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2447221505 Aug 04 04:33:07 PM PDT 24 Aug 04 04:33:20 PM PDT 24 734725677 ps
T1082 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.24392887 Aug 04 04:33:02 PM PDT 24 Aug 04 04:33:06 PM PDT 24 649464233 ps
T1083 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1967907598 Aug 04 04:33:12 PM PDT 24 Aug 04 04:33:14 PM PDT 24 188762108 ps
T1084 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1898898904 Aug 04 04:33:13 PM PDT 24 Aug 04 04:33:13 PM PDT 24 37747438 ps
T1085 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3306560894 Aug 04 04:33:02 PM PDT 24 Aug 04 04:33:10 PM PDT 24 2297752735 ps
T1086 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1598786526 Aug 04 04:33:23 PM PDT 24 Aug 04 04:33:24 PM PDT 24 79887374 ps
T1087 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4000314764 Aug 04 04:33:34 PM PDT 24 Aug 04 04:33:40 PM PDT 24 373479738 ps
T1088 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.467675824 Aug 04 04:33:13 PM PDT 24 Aug 04 04:33:15 PM PDT 24 302137078 ps
T1089 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1534514886 Aug 04 04:33:10 PM PDT 24 Aug 04 04:33:12 PM PDT 24 60299439 ps
T1090 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3136601176 Aug 04 04:33:25 PM PDT 24 Aug 04 04:33:29 PM PDT 24 751789880 ps
T1091 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3941489508 Aug 04 04:33:24 PM PDT 24 Aug 04 04:33:28 PM PDT 24 150713051 ps
T1092 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.141191500 Aug 04 04:33:10 PM PDT 24 Aug 04 04:33:29 PM PDT 24 1243552065 ps
T1093 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1658030027 Aug 04 04:33:09 PM PDT 24 Aug 04 04:33:12 PM PDT 24 254844023 ps
T1094 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2951843514 Aug 04 04:33:17 PM PDT 24 Aug 04 04:33:21 PM PDT 24 53039280 ps
T1095 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3341638817 Aug 04 04:33:37 PM PDT 24 Aug 04 04:33:38 PM PDT 24 38545670 ps
T1096 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2023846635 Aug 04 04:33:11 PM PDT 24 Aug 04 04:33:13 PM PDT 24 242165020 ps
T1097 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1349173445 Aug 04 04:33:14 PM PDT 24 Aug 04 04:33:22 PM PDT 24 211156963 ps
T1098 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1923488957 Aug 04 04:33:09 PM PDT 24 Aug 04 04:33:12 PM PDT 24 94546459 ps
T1099 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.516493495 Aug 04 04:32:53 PM PDT 24 Aug 04 04:32:54 PM PDT 24 103014181 ps
T1100 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.70483221 Aug 04 04:33:05 PM PDT 24 Aug 04 04:33:08 PM PDT 24 45660874 ps
T1101 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3213490857 Aug 04 04:32:54 PM PDT 24 Aug 04 04:32:55 PM PDT 24 34960145 ps
T1102 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1744555801 Aug 04 04:33:14 PM PDT 24 Aug 04 04:33:16 PM PDT 24 247469606 ps
T1103 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2202752972 Aug 04 04:33:17 PM PDT 24 Aug 04 04:33:18 PM PDT 24 11853835 ps
T1104 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.34430914 Aug 04 04:33:15 PM PDT 24 Aug 04 04:33:22 PM PDT 24 208010524 ps
T1105 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1048548814 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:19 PM PDT 24 1641186162 ps
T1106 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1990607737 Aug 04 04:33:03 PM PDT 24 Aug 04 04:33:11 PM PDT 24 1644638258 ps
T1107 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2929890663 Aug 04 04:32:56 PM PDT 24 Aug 04 04:32:58 PM PDT 24 31736166 ps
T1108 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1839847129 Aug 04 04:33:09 PM PDT 24 Aug 04 04:33:10 PM PDT 24 27968655 ps
T1109 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1934629181 Aug 04 04:33:07 PM PDT 24 Aug 04 04:33:10 PM PDT 24 41529786 ps
T1110 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.592627279 Aug 04 04:33:10 PM PDT 24 Aug 04 04:33:12 PM PDT 24 137991315 ps
T1111 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.591050126 Aug 04 04:33:22 PM PDT 24 Aug 04 04:33:23 PM PDT 24 26134979 ps
T1112 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2232865934 Aug 04 04:33:17 PM PDT 24 Aug 04 04:33:22 PM PDT 24 858017502 ps
T1113 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2333103457 Aug 04 04:33:14 PM PDT 24 Aug 04 04:33:14 PM PDT 24 19926398 ps
T1114 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1420765421 Aug 04 04:33:09 PM PDT 24 Aug 04 04:33:17 PM PDT 24 1526019155 ps
T1115 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2911242204 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:10 PM PDT 24 43688135 ps
T1116 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.175885844 Aug 04 04:33:09 PM PDT 24 Aug 04 04:33:10 PM PDT 24 20696198 ps
T1117 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1292127064 Aug 04 04:33:22 PM PDT 24 Aug 04 04:33:22 PM PDT 24 49185786 ps
T1118 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3619738083 Aug 04 04:33:05 PM PDT 24 Aug 04 04:33:08 PM PDT 24 100823779 ps
T1119 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4177782028 Aug 04 04:33:10 PM PDT 24 Aug 04 04:33:12 PM PDT 24 72731255 ps
T1120 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3417257474 Aug 04 04:33:36 PM PDT 24 Aug 04 04:33:37 PM PDT 24 15078362 ps
T1121 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1553642754 Aug 04 04:33:15 PM PDT 24 Aug 04 04:33:15 PM PDT 24 11433855 ps
T1122 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1947102814 Aug 04 04:32:52 PM PDT 24 Aug 04 04:32:55 PM PDT 24 105658952 ps
T1123 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1840331106 Aug 04 04:33:39 PM PDT 24 Aug 04 04:33:59 PM PDT 24 4381565431 ps
T1124 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3482494818 Aug 04 04:33:13 PM PDT 24 Aug 04 04:33:14 PM PDT 24 52646370 ps
T1125 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.646284092 Aug 04 04:33:08 PM PDT 24 Aug 04 04:33:09 PM PDT 24 13256695 ps
T1126 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.127223846 Aug 04 04:33:04 PM PDT 24 Aug 04 04:33:09 PM PDT 24 473894949 ps
T1127 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2013537221 Aug 04 04:32:57 PM PDT 24 Aug 04 04:32:59 PM PDT 24 140130102 ps
T1128 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3359188963 Aug 04 04:33:18 PM PDT 24 Aug 04 04:33:18 PM PDT 24 16547821 ps
T1129 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.263646700 Aug 04 04:33:34 PM PDT 24 Aug 04 04:33:50 PM PDT 24 703689775 ps

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.457700666
Short name T3
Test name
Test status
Simulation time 44308445921 ps
CPU time 175.47 seconds
Started Aug 04 05:21:18 PM PDT 24
Finished Aug 04 05:24:13 PM PDT 24
Peak memory 253076 kb
Host smart-bc42df1a-4cd3-4735-a63d-7a27fbe7b42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457700666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.457700666
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.462380592
Short name T16
Test name
Test status
Simulation time 250746588388 ps
CPU time 548.06 seconds
Started Aug 04 05:21:17 PM PDT 24
Finished Aug 04 05:30:25 PM PDT 24
Peak memory 269852 kb
Host smart-62011e0f-015a-4dda-84e4-9d30f81b4fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462380592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.462380592
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2766405258
Short name T96
Test name
Test status
Simulation time 940755781 ps
CPU time 14.4 seconds
Started Aug 04 04:33:13 PM PDT 24
Finished Aug 04 04:33:27 PM PDT 24
Peak memory 215300 kb
Host smart-827c0928-7c81-4276-9167-f2f1f4821477
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766405258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2766405258
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3502044599
Short name T18
Test name
Test status
Simulation time 70326600207 ps
CPU time 750.9 seconds
Started Aug 04 05:21:28 PM PDT 24
Finished Aug 04 05:33:59 PM PDT 24
Peak memory 290496 kb
Host smart-1ad7be46-fddb-469b-8660-0b5d84477e65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502044599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3502044599
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4007322533
Short name T129
Test name
Test status
Simulation time 5556349854 ps
CPU time 130.74 seconds
Started Aug 04 05:21:24 PM PDT 24
Finished Aug 04 05:23:35 PM PDT 24
Peak memory 251980 kb
Host smart-caa66451-9039-40a8-bb41-07698c477c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007322533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4007322533
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1326633995
Short name T69
Test name
Test status
Simulation time 97261984 ps
CPU time 0.72 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 216384 kb
Host smart-f6afb436-a3a1-4960-9338-c1e4faad3e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326633995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1326633995
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1393282443
Short name T15
Test name
Test status
Simulation time 113789777008 ps
CPU time 226.45 seconds
Started Aug 04 05:21:29 PM PDT 24
Finished Aug 04 05:25:16 PM PDT 24
Peak memory 254292 kb
Host smart-1dd911df-8bc3-44f9-a0f6-12136901704f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393282443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1393282443
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4255719986
Short name T31
Test name
Test status
Simulation time 37532922295 ps
CPU time 470.45 seconds
Started Aug 04 05:19:48 PM PDT 24
Finished Aug 04 05:27:39 PM PDT 24
Peak memory 284664 kb
Host smart-3d6f5080-9653-487c-b422-4fdb53cee525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255719986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4255719986
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1650126811
Short name T42
Test name
Test status
Simulation time 9222069140 ps
CPU time 147.03 seconds
Started Aug 04 05:19:47 PM PDT 24
Finished Aug 04 05:22:14 PM PDT 24
Peak memory 255656 kb
Host smart-8ba6cef1-00cf-4186-8bc5-2b46587096b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650126811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1650126811
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4291506300
Short name T29
Test name
Test status
Simulation time 340600669248 ps
CPU time 629.24 seconds
Started Aug 04 05:21:40 PM PDT 24
Finished Aug 04 05:32:10 PM PDT 24
Peak memory 274080 kb
Host smart-6ccf645c-76a7-41b3-8a44-cf8dc320fe21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291506300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4291506300
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2154444040
Short name T94
Test name
Test status
Simulation time 158875266 ps
CPU time 3.86 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:13 PM PDT 24
Peak memory 215184 kb
Host smart-50bc1fca-284d-42a7-9d24-74fcbc737c48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154444040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2154444040
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3561264241
Short name T14
Test name
Test status
Simulation time 690740317 ps
CPU time 1.11 seconds
Started Aug 04 05:19:36 PM PDT 24
Finished Aug 04 05:19:37 PM PDT 24
Peak memory 236436 kb
Host smart-a0ccf5b8-c487-46a2-8c63-051efc77d7a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561264241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3561264241
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2899082961
Short name T13
Test name
Test status
Simulation time 68763610094 ps
CPU time 502.35 seconds
Started Aug 04 05:21:35 PM PDT 24
Finished Aug 04 05:29:58 PM PDT 24
Peak memory 253236 kb
Host smart-ab98f2d8-314a-43e5-a72d-c3403cdc7f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899082961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2899082961
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2506015955
Short name T142
Test name
Test status
Simulation time 424119480 ps
CPU time 10.08 seconds
Started Aug 04 05:20:57 PM PDT 24
Finished Aug 04 05:21:07 PM PDT 24
Peak memory 233128 kb
Host smart-2d66844f-a4d0-49ee-8f26-fecff341732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506015955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2506015955
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3788037157
Short name T204
Test name
Test status
Simulation time 20836489073 ps
CPU time 162.03 seconds
Started Aug 04 05:21:26 PM PDT 24
Finished Aug 04 05:24:08 PM PDT 24
Peak memory 265944 kb
Host smart-a7626cfb-9857-4625-89fe-8499e5a8e523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788037157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3788037157
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3683822425
Short name T115
Test name
Test status
Simulation time 81291545 ps
CPU time 1.31 seconds
Started Aug 04 04:33:02 PM PDT 24
Finished Aug 04 04:33:04 PM PDT 24
Peak memory 207060 kb
Host smart-07b3b5ea-a148-4110-8aa3-a767cbacda80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683822425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
683822425
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1746149871
Short name T213
Test name
Test status
Simulation time 58527226322 ps
CPU time 461.74 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:27:39 PM PDT 24
Peak memory 271576 kb
Host smart-6e5b45d5-6b83-44f4-aa4e-b0612ba56ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746149871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1746149871
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2239686042
Short name T165
Test name
Test status
Simulation time 37186223569 ps
CPU time 168.57 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:23:34 PM PDT 24
Peak memory 254564 kb
Host smart-a90b19ed-a73d-49cf-a540-91a085adc503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239686042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2239686042
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1862903908
Short name T133
Test name
Test status
Simulation time 123404419247 ps
CPU time 292.74 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:24:44 PM PDT 24
Peak memory 283436 kb
Host smart-9e254d7a-af02-405d-a468-e0f15bb806c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862903908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1862903908
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2582727960
Short name T270
Test name
Test status
Simulation time 103874105062 ps
CPU time 285.93 seconds
Started Aug 04 05:21:37 PM PDT 24
Finished Aug 04 05:26:23 PM PDT 24
Peak memory 265964 kb
Host smart-2b9bda0e-6f34-44a0-9178-74946e44a86f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582727960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2582727960
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.101025156
Short name T209
Test name
Test status
Simulation time 8436241074 ps
CPU time 134.36 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:22:08 PM PDT 24
Peak memory 257772 kb
Host smart-90d0c845-ff71-4358-9fb5-ff80ba2f472f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101025156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.101025156
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3386704412
Short name T200
Test name
Test status
Simulation time 53000159515 ps
CPU time 285.4 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:25:29 PM PDT 24
Peak memory 250640 kb
Host smart-0e6c91ab-7173-4bf6-9852-ca369870329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386704412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3386704412
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.551407611
Short name T101
Test name
Test status
Simulation time 76329083 ps
CPU time 4.54 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:13 PM PDT 24
Peak memory 216292 kb
Host smart-10ca5d47-f50b-4878-80d9-fdb3ad0da516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551407611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.551407611
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1516938317
Short name T442
Test name
Test status
Simulation time 11578470344 ps
CPU time 26.92 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:35 PM PDT 24
Peak memory 216752 kb
Host smart-03e4aca3-a079-47de-a4c6-fae8436151cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516938317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1516938317
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1155282697
Short name T380
Test name
Test status
Simulation time 16510975 ps
CPU time 0.74 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:19:52 PM PDT 24
Peak memory 206064 kb
Host smart-f6bb5792-7775-4e25-9cdc-9172cbd7f3d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155282697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1155282697
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1043930209
Short name T167
Test name
Test status
Simulation time 2033772971 ps
CPU time 17.63 seconds
Started Aug 04 04:33:22 PM PDT 24
Finished Aug 04 04:33:40 PM PDT 24
Peak memory 215096 kb
Host smart-003ea140-29b5-4400-ac2f-c330204c6a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043930209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1043930209
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.583917908
Short name T251
Test name
Test status
Simulation time 194518870095 ps
CPU time 362.02 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:26:01 PM PDT 24
Peak memory 266520 kb
Host smart-027a8475-a83f-4726-a40d-b4e93e83c33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583917908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.583917908
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2261289903
Short name T186
Test name
Test status
Simulation time 61799840865 ps
CPU time 270.49 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:24:22 PM PDT 24
Peak memory 255336 kb
Host smart-9e491cae-cdee-4dba-ba5b-bff2718e76b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261289903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2261289903
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.517684895
Short name T52
Test name
Test status
Simulation time 31012241172 ps
CPU time 168.76 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:22:44 PM PDT 24
Peak memory 267856 kb
Host smart-b045b7a3-aff5-4ca9-85db-d09a550eebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517684895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.517684895
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1887886033
Short name T35
Test name
Test status
Simulation time 2024653949 ps
CPU time 47.19 seconds
Started Aug 04 05:20:40 PM PDT 24
Finished Aug 04 05:21:28 PM PDT 24
Peak memory 244612 kb
Host smart-1dbd0eea-3514-4621-9a40-ee44451952b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887886033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1887886033
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3060234067
Short name T183
Test name
Test status
Simulation time 3434043193 ps
CPU time 73.63 seconds
Started Aug 04 05:20:38 PM PDT 24
Finished Aug 04 05:21:52 PM PDT 24
Peak memory 256224 kb
Host smart-052e14ea-ab45-4ba4-94d9-8fff375149d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060234067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3060234067
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.4177055042
Short name T203
Test name
Test status
Simulation time 12375045204 ps
CPU time 120.49 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:21:53 PM PDT 24
Peak memory 271500 kb
Host smart-76ce68b3-5cd2-4cf3-a4ce-3d29613c22c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177055042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.4177055042
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1756880408
Short name T159
Test name
Test status
Simulation time 81579647333 ps
CPU time 151.18 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:22:24 PM PDT 24
Peak memory 254028 kb
Host smart-baf4289f-236b-41d1-93c7-115cb1952a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756880408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1756880408
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3455295695
Short name T959
Test name
Test status
Simulation time 253200565 ps
CPU time 6.59 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:19:57 PM PDT 24
Peak memory 233064 kb
Host smart-d920072a-2033-438f-b7c6-58ab27f1b1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455295695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3455295695
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2114780507
Short name T88
Test name
Test status
Simulation time 1599782843 ps
CPU time 41.06 seconds
Started Aug 04 05:19:56 PM PDT 24
Finished Aug 04 05:20:37 PM PDT 24
Peak memory 250896 kb
Host smart-91968a09-360c-4a97-83ee-afbe4f2ccda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114780507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2114780507
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.343889871
Short name T144
Test name
Test status
Simulation time 6335232822 ps
CPU time 22.48 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:21:13 PM PDT 24
Peak memory 233144 kb
Host smart-298a9536-688b-4432-afab-e8ea0b8a9fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343889871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.343889871
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.960677309
Short name T28
Test name
Test status
Simulation time 950039621 ps
CPU time 4.58 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:19:56 PM PDT 24
Peak memory 216652 kb
Host smart-907a2bf3-ad0b-4258-8b87-88f7acd58405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960677309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.960677309
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3203066220
Short name T992
Test name
Test status
Simulation time 1222130700 ps
CPU time 7.35 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:20:05 PM PDT 24
Peak memory 233072 kb
Host smart-8798442f-9a40-4e5d-815e-a65a09a50839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203066220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3203066220
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3387508823
Short name T880
Test name
Test status
Simulation time 131732343721 ps
CPU time 437.23 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:27:07 PM PDT 24
Peak memory 265452 kb
Host smart-7714215d-f37d-4b98-9ea7-0f338cd6f522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387508823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3387508823
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2340605817
Short name T271
Test name
Test status
Simulation time 85335089670 ps
CPU time 428.68 seconds
Started Aug 04 05:20:26 PM PDT 24
Finished Aug 04 05:27:35 PM PDT 24
Peak memory 255588 kb
Host smart-4897051d-c358-4c7a-9ee3-c3d6856e79de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340605817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2340605817
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1918366917
Short name T181
Test name
Test status
Simulation time 318438963336 ps
CPU time 598.16 seconds
Started Aug 04 05:21:17 PM PDT 24
Finished Aug 04 05:31:15 PM PDT 24
Peak memory 268800 kb
Host smart-6032874b-f6fe-4fa3-b195-23a05933d2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918366917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1918366917
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1630906831
Short name T54
Test name
Test status
Simulation time 57285400508 ps
CPU time 331.11 seconds
Started Aug 04 05:20:05 PM PDT 24
Finished Aug 04 05:25:36 PM PDT 24
Peak memory 266372 kb
Host smart-0aa2dccd-8d82-4ec8-a8e7-196d6f68ee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630906831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1630906831
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.136881611
Short name T103
Test name
Test status
Simulation time 236404755 ps
CPU time 3.82 seconds
Started Aug 04 04:33:05 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 215328 kb
Host smart-2113e5c5-611c-42e2-8fd2-98e81700b08b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136881611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.136881611
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1123285594
Short name T168
Test name
Test status
Simulation time 754856637 ps
CPU time 8.66 seconds
Started Aug 04 04:32:58 PM PDT 24
Finished Aug 04 04:33:07 PM PDT 24
Peak memory 215300 kb
Host smart-5a61577e-fbe2-4ff9-a0c3-09b9add1a4a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123285594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1123285594
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3914710859
Short name T175
Test name
Test status
Simulation time 394217970 ps
CPU time 4.49 seconds
Started Aug 04 05:19:29 PM PDT 24
Finished Aug 04 05:19:34 PM PDT 24
Peak memory 224892 kb
Host smart-5cc2a7d6-f592-48c8-a6a3-c8a62367cd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914710859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3914710859
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1581547308
Short name T900
Test name
Test status
Simulation time 939819100 ps
CPU time 27.61 seconds
Started Aug 04 05:19:17 PM PDT 24
Finished Aug 04 05:19:45 PM PDT 24
Peak memory 240172 kb
Host smart-7b0f68a7-63a3-4ac3-b888-fd9dec747625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581547308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1581547308
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1702963616
Short name T27
Test name
Test status
Simulation time 8877928307 ps
CPU time 73.23 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:21:12 PM PDT 24
Peak memory 249432 kb
Host smart-70b7673d-f4b7-46e7-bdff-a9f86402298b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702963616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1702963616
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4149344692
Short name T267
Test name
Test status
Simulation time 3316603336 ps
CPU time 42.85 seconds
Started Aug 04 05:20:17 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 249556 kb
Host smart-8d0b0d96-f41c-4982-bdb3-7b3f7808d0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149344692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4149344692
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3404805993
Short name T90
Test name
Test status
Simulation time 1243094311 ps
CPU time 14.4 seconds
Started Aug 04 05:20:07 PM PDT 24
Finished Aug 04 05:20:21 PM PDT 24
Peak memory 233040 kb
Host smart-ad859521-da4e-4f11-8e94-62893a7c22e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404805993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3404805993
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.371756245
Short name T78
Test name
Test status
Simulation time 217682091 ps
CPU time 1.44 seconds
Started Aug 04 04:32:53 PM PDT 24
Finished Aug 04 04:32:54 PM PDT 24
Peak memory 206860 kb
Host smart-9676dee9-80f0-4715-95f3-cf187b902748
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371756245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.371756245
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1457139680
Short name T102
Test name
Test status
Simulation time 67861070 ps
CPU time 2.08 seconds
Started Aug 04 04:32:57 PM PDT 24
Finished Aug 04 04:32:59 PM PDT 24
Peak memory 215252 kb
Host smart-20393f6d-0ab2-4c44-b190-2124e29e6adb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457139680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
457139680
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2840229421
Short name T126
Test name
Test status
Simulation time 614695093 ps
CPU time 15.63 seconds
Started Aug 04 04:32:57 PM PDT 24
Finished Aug 04 04:33:13 PM PDT 24
Peak memory 215064 kb
Host smart-40a7f0f1-ad8c-4957-b441-756804787005
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840229421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2840229421
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1048548814
Short name T1105
Test name
Test status
Simulation time 1641186162 ps
CPU time 11.43 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:19 PM PDT 24
Peak memory 206828 kb
Host smart-f6a37e45-e631-43b9-bbc2-a3046e672df6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048548814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1048548814
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3080263722
Short name T79
Test name
Test status
Simulation time 22867626 ps
CPU time 0.97 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:04 PM PDT 24
Peak memory 206572 kb
Host smart-2df86e74-16cb-4155-9995-4b9f87ec4dc2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080263722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3080263722
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1233142084
Short name T1076
Test name
Test status
Simulation time 49894907 ps
CPU time 3.29 seconds
Started Aug 04 04:33:02 PM PDT 24
Finished Aug 04 04:33:06 PM PDT 24
Peak memory 216864 kb
Host smart-ede9f034-a22d-4911-a825-901d27d1ab74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233142084 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1233142084
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1296086933
Short name T1036
Test name
Test status
Simulation time 66073916 ps
CPU time 1.16 seconds
Started Aug 04 04:33:02 PM PDT 24
Finished Aug 04 04:33:03 PM PDT 24
Peak memory 206848 kb
Host smart-93b3b8a5-dcfa-4067-bdb7-6882489335e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296086933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
296086933
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2276221758
Short name T1060
Test name
Test status
Simulation time 73325031 ps
CPU time 0.74 seconds
Started Aug 04 04:32:59 PM PDT 24
Finished Aug 04 04:33:00 PM PDT 24
Peak memory 203512 kb
Host smart-eec58787-75a2-45f9-b878-f3caa053d660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276221758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
276221758
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2013537221
Short name T1127
Test name
Test status
Simulation time 140130102 ps
CPU time 2.07 seconds
Started Aug 04 04:32:57 PM PDT 24
Finished Aug 04 04:32:59 PM PDT 24
Peak memory 215000 kb
Host smart-3b30618d-3b19-4e29-a1bd-a817c5fe5bc9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013537221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2013537221
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1514345819
Short name T1027
Test name
Test status
Simulation time 17733699 ps
CPU time 0.66 seconds
Started Aug 04 04:32:46 PM PDT 24
Finished Aug 04 04:32:47 PM PDT 24
Peak memory 203776 kb
Host smart-ca30b386-1071-4d72-9945-8a47a7058d40
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514345819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1514345819
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3571255842
Short name T1031
Test name
Test status
Simulation time 764196910 ps
CPU time 4 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 215080 kb
Host smart-e77de6c1-5b9c-47be-a460-94014e8ce2e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571255842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3571255842
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1990607737
Short name T1106
Test name
Test status
Simulation time 1644638258 ps
CPU time 8.3 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:11 PM PDT 24
Peak memory 215056 kb
Host smart-68571b94-3437-4636-a95e-95e466c51967
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990607737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1990607737
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3676641241
Short name T120
Test name
Test status
Simulation time 879509776 ps
CPU time 15.34 seconds
Started Aug 04 04:32:48 PM PDT 24
Finished Aug 04 04:33:04 PM PDT 24
Peak memory 206752 kb
Host smart-d2087892-c03f-4be3-8f5f-14148d27b877
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676641241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3676641241
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3705988026
Short name T1072
Test name
Test status
Simulation time 1219143943 ps
CPU time 12.01 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:15 PM PDT 24
Peak memory 206816 kb
Host smart-b58a61d4-40cc-4569-8e80-67f6134600d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705988026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3705988026
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2384998381
Short name T1075
Test name
Test status
Simulation time 153687459 ps
CPU time 3.61 seconds
Started Aug 04 04:33:01 PM PDT 24
Finished Aug 04 04:33:05 PM PDT 24
Peak memory 217148 kb
Host smart-d949e5fb-c269-4c01-94c2-013865255873
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384998381 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2384998381
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.646284092
Short name T1125
Test name
Test status
Simulation time 13256695 ps
CPU time 0.67 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 203532 kb
Host smart-4d30c25d-2108-4ac5-8492-b7784f278969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646284092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.646284092
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2529181826
Short name T127
Test name
Test status
Simulation time 48327395 ps
CPU time 1.54 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:05 PM PDT 24
Peak memory 214968 kb
Host smart-b1652e1a-3d21-4e45-ac96-e5d614d94b22
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529181826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2529181826
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.347915050
Short name T1021
Test name
Test status
Simulation time 19775044 ps
CPU time 0.65 seconds
Started Aug 04 04:32:49 PM PDT 24
Finished Aug 04 04:32:50 PM PDT 24
Peak memory 203476 kb
Host smart-1330673c-ff13-4fdb-8c52-3076069fdf9e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347915050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.347915050
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2285514960
Short name T1040
Test name
Test status
Simulation time 94767196 ps
CPU time 2.75 seconds
Started Aug 04 04:32:53 PM PDT 24
Finished Aug 04 04:32:56 PM PDT 24
Peak memory 215144 kb
Host smart-2ddc8751-5e2c-4969-b276-092fb5300613
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285514960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2285514960
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4155635518
Short name T66
Test name
Test status
Simulation time 302593996 ps
CPU time 3.54 seconds
Started Aug 04 04:33:11 PM PDT 24
Finished Aug 04 04:33:15 PM PDT 24
Peak memory 217880 kb
Host smart-34f1f7a9-b83d-4f4d-83cc-78e33ed1e632
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155635518 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.4155635518
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2023846635
Short name T1096
Test name
Test status
Simulation time 242165020 ps
CPU time 2.38 seconds
Started Aug 04 04:33:11 PM PDT 24
Finished Aug 04 04:33:13 PM PDT 24
Peak memory 215020 kb
Host smart-59d35ea3-e92e-49b2-bc6b-0d9edd09abaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023846635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2023846635
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1292127064
Short name T1117
Test name
Test status
Simulation time 49185786 ps
CPU time 0.73 seconds
Started Aug 04 04:33:22 PM PDT 24
Finished Aug 04 04:33:22 PM PDT 24
Peak memory 203560 kb
Host smart-baaf7ae3-b5fd-4ef5-9d28-ab9e41bc6368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292127064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1292127064
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4112181371
Short name T1054
Test name
Test status
Simulation time 127645147 ps
CPU time 2.8 seconds
Started Aug 04 04:33:18 PM PDT 24
Finished Aug 04 04:33:21 PM PDT 24
Peak memory 215076 kb
Host smart-b4c8b7da-dd49-40c4-8b34-679838b71885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112181371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4112181371
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1852882436
Short name T107
Test name
Test status
Simulation time 93946804 ps
CPU time 1.9 seconds
Started Aug 04 04:33:07 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 215312 kb
Host smart-5236ac44-42b8-4421-95ae-88bf2b3a46f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852882436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1852882436
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1740855183
Short name T1059
Test name
Test status
Simulation time 414569520 ps
CPU time 12.34 seconds
Started Aug 04 04:33:04 PM PDT 24
Finished Aug 04 04:33:16 PM PDT 24
Peak memory 215064 kb
Host smart-f88a1075-3a8f-41ab-a84c-be68867d0a76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740855183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1740855183
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.908184644
Short name T108
Test name
Test status
Simulation time 1220923832 ps
CPU time 2.67 seconds
Started Aug 04 04:33:15 PM PDT 24
Finished Aug 04 04:33:18 PM PDT 24
Peak memory 217240 kb
Host smart-45eb6b77-99d5-4d7d-8951-2f27648d426e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908184644 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.908184644
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1073321325
Short name T123
Test name
Test status
Simulation time 37759147 ps
CPU time 2.25 seconds
Started Aug 04 04:33:17 PM PDT 24
Finished Aug 04 04:33:19 PM PDT 24
Peak memory 215076 kb
Host smart-9d1102d3-a832-4d73-ad24-485e6ebd9969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073321325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1073321325
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1229790887
Short name T1009
Test name
Test status
Simulation time 12929139 ps
CPU time 0.68 seconds
Started Aug 04 04:33:37 PM PDT 24
Finished Aug 04 04:33:38 PM PDT 24
Peak memory 203564 kb
Host smart-8c7cffef-d700-4bbc-95c4-a8369444aaf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229790887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1229790887
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1923488957
Short name T1098
Test name
Test status
Simulation time 94546459 ps
CPU time 2.88 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 215068 kb
Host smart-b195d7f8-25fb-4fed-99c5-324630366862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923488957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1923488957
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3402056810
Short name T100
Test name
Test status
Simulation time 63217753 ps
CPU time 3.84 seconds
Started Aug 04 04:33:10 PM PDT 24
Finished Aug 04 04:33:14 PM PDT 24
Peak memory 215280 kb
Host smart-aabb9d03-1129-4eec-818e-63779a26bc8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402056810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3402056810
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.591763226
Short name T110
Test name
Test status
Simulation time 555673823 ps
CPU time 18.18 seconds
Started Aug 04 04:33:15 PM PDT 24
Finished Aug 04 04:33:33 PM PDT 24
Peak memory 215436 kb
Host smart-ded2a12d-a7fb-4e3b-b06f-125af0e0de78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591763226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.591763226
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2487095615
Short name T1035
Test name
Test status
Simulation time 876926759 ps
CPU time 2.78 seconds
Started Aug 04 04:33:18 PM PDT 24
Finished Aug 04 04:33:21 PM PDT 24
Peak memory 217724 kb
Host smart-5be115ec-4507-472d-a885-0d1a603c8f17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487095615 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2487095615
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2352229918
Short name T1066
Test name
Test status
Simulation time 1066711893 ps
CPU time 2.61 seconds
Started Aug 04 04:33:04 PM PDT 24
Finished Aug 04 04:33:06 PM PDT 24
Peak memory 214976 kb
Host smart-1c5933ca-d06d-4a8f-9865-82fb21b8fed4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352229918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2352229918
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.89196808
Short name T1016
Test name
Test status
Simulation time 19023974 ps
CPU time 0.79 seconds
Started Aug 04 04:32:55 PM PDT 24
Finished Aug 04 04:32:56 PM PDT 24
Peak memory 203556 kb
Host smart-805fa745-87bc-41fc-a60a-9fb7a7fa5041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89196808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.89196808
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4141333424
Short name T1052
Test name
Test status
Simulation time 45945960 ps
CPU time 2.55 seconds
Started Aug 04 04:33:14 PM PDT 24
Finished Aug 04 04:33:17 PM PDT 24
Peak memory 215020 kb
Host smart-d8dd254a-24b7-4b35-ad65-5b10e46170e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141333424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4141333424
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4000314764
Short name T1087
Test name
Test status
Simulation time 373479738 ps
CPU time 6.24 seconds
Started Aug 04 04:33:34 PM PDT 24
Finished Aug 04 04:33:40 PM PDT 24
Peak memory 215224 kb
Host smart-5aa6cb43-8461-47de-b29a-1a2f6ae4e59f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000314764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4000314764
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1183388474
Short name T1079
Test name
Test status
Simulation time 936921297 ps
CPU time 6.54 seconds
Started Aug 04 04:33:25 PM PDT 24
Finished Aug 04 04:33:31 PM PDT 24
Peak memory 215516 kb
Host smart-9ef103ff-7292-435f-9946-de09f9484d3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183388474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1183388474
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1863665570
Short name T1034
Test name
Test status
Simulation time 1358354049 ps
CPU time 2.49 seconds
Started Aug 04 04:33:20 PM PDT 24
Finished Aug 04 04:33:22 PM PDT 24
Peak memory 217288 kb
Host smart-b88f66ae-018e-442a-b14d-ccb890098235
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863665570 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1863665570
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4040336506
Short name T1044
Test name
Test status
Simulation time 29847655 ps
CPU time 1.91 seconds
Started Aug 04 04:33:14 PM PDT 24
Finished Aug 04 04:33:16 PM PDT 24
Peak memory 215060 kb
Host smart-6b324f3a-c08a-4396-bb31-5c1d5bf0b22f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040336506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
4040336506
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2023203274
Short name T1063
Test name
Test status
Simulation time 30711671 ps
CPU time 0.69 seconds
Started Aug 04 04:33:38 PM PDT 24
Finished Aug 04 04:33:39 PM PDT 24
Peak memory 203552 kb
Host smart-4b2de807-5661-4944-a4ed-efc2195f7d6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023203274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2023203274
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.146338129
Short name T1058
Test name
Test status
Simulation time 194822985 ps
CPU time 3.89 seconds
Started Aug 04 04:33:13 PM PDT 24
Finished Aug 04 04:33:16 PM PDT 24
Peak memory 215004 kb
Host smart-28f8a1e4-933f-469d-88ca-b3a4c4b64c3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146338129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.146338129
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1453704200
Short name T105
Test name
Test status
Simulation time 329085656 ps
CPU time 3.79 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 215120 kb
Host smart-8715a44d-cbb0-49b7-9a36-3bc8e104ed9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453704200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1453704200
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.263646700
Short name T1129
Test name
Test status
Simulation time 703689775 ps
CPU time 15.27 seconds
Started Aug 04 04:33:34 PM PDT 24
Finished Aug 04 04:33:50 PM PDT 24
Peak memory 214996 kb
Host smart-d93e98c4-bfe4-4209-bb78-609081482973
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263646700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.263646700
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1967907598
Short name T1083
Test name
Test status
Simulation time 188762108 ps
CPU time 1.45 seconds
Started Aug 04 04:33:12 PM PDT 24
Finished Aug 04 04:33:14 PM PDT 24
Peak memory 214980 kb
Host smart-27314447-2870-4cc9-9141-7931219c492a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967907598 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1967907598
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2573893814
Short name T1078
Test name
Test status
Simulation time 45520079 ps
CPU time 1.41 seconds
Started Aug 04 04:33:22 PM PDT 24
Finished Aug 04 04:33:24 PM PDT 24
Peak memory 206816 kb
Host smart-f533c08a-f4f8-45b8-8d6d-6ee44565686e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573893814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2573893814
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.558795693
Short name T1022
Test name
Test status
Simulation time 23883689 ps
CPU time 0.7 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:15 PM PDT 24
Peak memory 203564 kb
Host smart-185ae3d7-054f-4c60-908e-9094d290a684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558795693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.558795693
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.467675824
Short name T1088
Test name
Test status
Simulation time 302137078 ps
CPU time 1.9 seconds
Started Aug 04 04:33:13 PM PDT 24
Finished Aug 04 04:33:15 PM PDT 24
Peak memory 215000 kb
Host smart-7e9a6aa3-137e-4623-a128-37eb93d9c23a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467675824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.467675824
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.141191500
Short name T1092
Test name
Test status
Simulation time 1243552065 ps
CPU time 18.22 seconds
Started Aug 04 04:33:10 PM PDT 24
Finished Aug 04 04:33:29 PM PDT 24
Peak memory 215072 kb
Host smart-928dcb1c-4fa4-4008-871f-b448872d2ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141191500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.141191500
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1534514886
Short name T1089
Test name
Test status
Simulation time 60299439 ps
CPU time 1.7 seconds
Started Aug 04 04:33:10 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 216104 kb
Host smart-85ef64e0-3d24-481e-a201-2d1b2b941250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534514886 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1534514886
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3226554932
Short name T1062
Test name
Test status
Simulation time 29957701 ps
CPU time 1.94 seconds
Started Aug 04 04:33:11 PM PDT 24
Finished Aug 04 04:33:13 PM PDT 24
Peak memory 215112 kb
Host smart-97bc87d2-7134-4b7a-bd2f-d73fc5419036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226554932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3226554932
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3341638817
Short name T1095
Test name
Test status
Simulation time 38545670 ps
CPU time 0.76 seconds
Started Aug 04 04:33:37 PM PDT 24
Finished Aug 04 04:33:38 PM PDT 24
Peak memory 203520 kb
Host smart-2a108a3e-e84c-4b53-9b70-76d172650e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341638817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3341638817
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3941489508
Short name T1091
Test name
Test status
Simulation time 150713051 ps
CPU time 3.81 seconds
Started Aug 04 04:33:24 PM PDT 24
Finished Aug 04 04:33:28 PM PDT 24
Peak memory 215000 kb
Host smart-c522ed4d-8d97-44d3-8cd4-93e76986bbdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941489508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3941489508
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3136601176
Short name T1090
Test name
Test status
Simulation time 751789880 ps
CPU time 4.16 seconds
Started Aug 04 04:33:25 PM PDT 24
Finished Aug 04 04:33:29 PM PDT 24
Peak memory 219600 kb
Host smart-a155bfbe-4320-433d-b83e-0674e5b2d654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136601176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3136601176
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2447221505
Short name T1081
Test name
Test status
Simulation time 734725677 ps
CPU time 8.18 seconds
Started Aug 04 04:33:07 PM PDT 24
Finished Aug 04 04:33:20 PM PDT 24
Peak memory 215472 kb
Host smart-a469c5de-1c27-4cff-bd9b-4dda776562da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447221505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2447221505
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.119803639
Short name T1077
Test name
Test status
Simulation time 195345579 ps
CPU time 2.48 seconds
Started Aug 04 04:33:04 PM PDT 24
Finished Aug 04 04:33:07 PM PDT 24
Peak memory 216064 kb
Host smart-189ed99f-7f23-4056-a526-d8be4a5455d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119803639 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.119803639
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2910125160
Short name T125
Test name
Test status
Simulation time 87290663 ps
CPU time 1.68 seconds
Started Aug 04 04:33:26 PM PDT 24
Finished Aug 04 04:33:27 PM PDT 24
Peak memory 214992 kb
Host smart-8263c5b0-bfd6-44de-9cdb-2a8e29912949
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910125160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2910125160
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1095650964
Short name T1015
Test name
Test status
Simulation time 72659258 ps
CPU time 0.76 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:10 PM PDT 24
Peak memory 203520 kb
Host smart-b383f1cf-c730-4a71-931d-34625d9b85fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095650964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1095650964
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.851761920
Short name T147
Test name
Test status
Simulation time 205713293 ps
CPU time 4.13 seconds
Started Aug 04 04:33:30 PM PDT 24
Finished Aug 04 04:33:35 PM PDT 24
Peak memory 215160 kb
Host smart-fe80510d-6549-4ba2-9c51-b91a930dadc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851761920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.851761920
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4197022464
Short name T104
Test name
Test status
Simulation time 68240966 ps
CPU time 4.38 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 215324 kb
Host smart-df375750-0c48-4e4b-85fe-b3b54e80d3cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197022464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4197022464
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3046008844
Short name T171
Test name
Test status
Simulation time 291410083 ps
CPU time 6.48 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:15 PM PDT 24
Peak memory 214888 kb
Host smart-1d3c7e39-4933-481d-a88e-1a4810ad2ddd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046008844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3046008844
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1781025258
Short name T1061
Test name
Test status
Simulation time 141487613 ps
CPU time 3.37 seconds
Started Aug 04 04:33:18 PM PDT 24
Finished Aug 04 04:33:21 PM PDT 24
Peak memory 217092 kb
Host smart-04cfc810-db13-4702-8b85-f7dcd810a7ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781025258 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1781025258
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.592627279
Short name T1110
Test name
Test status
Simulation time 137991315 ps
CPU time 2.44 seconds
Started Aug 04 04:33:10 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 215040 kb
Host smart-c353a1f9-f730-457b-9ea1-3e45b8c1b161
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592627279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.592627279
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.175885844
Short name T1116
Test name
Test status
Simulation time 20696198 ps
CPU time 0.73 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:10 PM PDT 24
Peak memory 203560 kb
Host smart-81522f31-5be7-4d4a-aac8-c63a2391d798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175885844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.175885844
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1744555801
Short name T1102
Test name
Test status
Simulation time 247469606 ps
CPU time 1.73 seconds
Started Aug 04 04:33:14 PM PDT 24
Finished Aug 04 04:33:16 PM PDT 24
Peak memory 215048 kb
Host smart-5924d1b2-b3e4-4d85-b2e1-e3a9aafb011a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744555801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1744555801
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2951843514
Short name T1094
Test name
Test status
Simulation time 53039280 ps
CPU time 3.34 seconds
Started Aug 04 04:33:17 PM PDT 24
Finished Aug 04 04:33:21 PM PDT 24
Peak memory 217116 kb
Host smart-e29f1669-9bcf-43c5-855b-5cb04f79f1c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951843514 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2951843514
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1057121727
Short name T1032
Test name
Test status
Simulation time 225394395 ps
CPU time 1.4 seconds
Started Aug 04 04:33:13 PM PDT 24
Finished Aug 04 04:33:14 PM PDT 24
Peak memory 215084 kb
Host smart-77cb7edd-7f0b-4f14-821b-0320cea8d8ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057121727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1057121727
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2670518707
Short name T1026
Test name
Test status
Simulation time 22706870 ps
CPU time 0.74 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 203540 kb
Host smart-569f454d-a948-4f38-a149-82027ceedf54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670518707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2670518707
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2462240232
Short name T145
Test name
Test status
Simulation time 231136862 ps
CPU time 1.7 seconds
Started Aug 04 04:33:13 PM PDT 24
Finished Aug 04 04:33:14 PM PDT 24
Peak memory 215100 kb
Host smart-20baf0a2-6a7c-479b-9c22-1adf781e1c37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462240232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2462240232
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1197394329
Short name T92
Test name
Test status
Simulation time 266479935 ps
CPU time 2.03 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:11 PM PDT 24
Peak memory 215072 kb
Host smart-622d0c8d-ac1f-439c-9401-f4643b5a4448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197394329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1197394329
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.475744889
Short name T95
Test name
Test status
Simulation time 1006943408 ps
CPU time 22.12 seconds
Started Aug 04 04:33:27 PM PDT 24
Finished Aug 04 04:33:50 PM PDT 24
Peak memory 215440 kb
Host smart-0ba2435e-3f79-4691-9d6d-715fff475575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475744889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.475744889
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1658030027
Short name T1093
Test name
Test status
Simulation time 254844023 ps
CPU time 2.8 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 216344 kb
Host smart-797b283c-78b8-4c89-8224-93b70023542b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658030027 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1658030027
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3228307317
Short name T1074
Test name
Test status
Simulation time 39155773 ps
CPU time 2.31 seconds
Started Aug 04 04:33:17 PM PDT 24
Finished Aug 04 04:33:19 PM PDT 24
Peak memory 214940 kb
Host smart-11b9c5f7-1b76-4b4e-a47b-cd06325e2f93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228307317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3228307317
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.386567460
Short name T1012
Test name
Test status
Simulation time 20907523 ps
CPU time 0.7 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 203892 kb
Host smart-8f4c459a-649c-4c6c-96eb-5c4dca0bda1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386567460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.386567460
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4144783721
Short name T149
Test name
Test status
Simulation time 388673653 ps
CPU time 3.9 seconds
Started Aug 04 04:33:22 PM PDT 24
Finished Aug 04 04:33:26 PM PDT 24
Peak memory 215028 kb
Host smart-402b6586-85c7-4ade-8e86-049682e9ec7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144783721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4144783721
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2232865934
Short name T1112
Test name
Test status
Simulation time 858017502 ps
CPU time 5.06 seconds
Started Aug 04 04:33:17 PM PDT 24
Finished Aug 04 04:33:22 PM PDT 24
Peak memory 215052 kb
Host smart-87fff4ad-ad7f-48b8-a1c0-a38144d8eaef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232865934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2232865934
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.614742461
Short name T172
Test name
Test status
Simulation time 2950594456 ps
CPU time 15.59 seconds
Started Aug 04 04:33:12 PM PDT 24
Finished Aug 04 04:33:28 PM PDT 24
Peak memory 215744 kb
Host smart-302ae950-6dd3-4334-9848-40ed46fc1647
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614742461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.614742461
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1420765421
Short name T1114
Test name
Test status
Simulation time 1526019155 ps
CPU time 7.99 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:17 PM PDT 24
Peak memory 206764 kb
Host smart-b98f1e78-014f-40b8-ac19-ec180d239d7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420765421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1420765421
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3417957641
Short name T148
Test name
Test status
Simulation time 822811882 ps
CPU time 12.19 seconds
Started Aug 04 04:32:58 PM PDT 24
Finished Aug 04 04:33:10 PM PDT 24
Peak memory 206788 kb
Host smart-c0615087-e9f0-40e1-9615-3513df6b4f81
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417957641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3417957641
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1487705292
Short name T1057
Test name
Test status
Simulation time 94623290 ps
CPU time 0.94 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:11 PM PDT 24
Peak memory 206640 kb
Host smart-4f0036d2-cc00-4226-8c5a-c06de0ff18a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487705292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1487705292
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4162006897
Short name T109
Test name
Test status
Simulation time 121590375 ps
CPU time 3.41 seconds
Started Aug 04 04:33:07 PM PDT 24
Finished Aug 04 04:33:10 PM PDT 24
Peak memory 217244 kb
Host smart-2483de09-f774-406f-a847-8f0611e765c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162006897 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.4162006897
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1934629181
Short name T1109
Test name
Test status
Simulation time 41529786 ps
CPU time 2.47 seconds
Started Aug 04 04:33:07 PM PDT 24
Finished Aug 04 04:33:10 PM PDT 24
Peak memory 215080 kb
Host smart-e1002c50-64fc-441d-9536-bd6cdbcbf4fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934629181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
934629181
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2431265084
Short name T1039
Test name
Test status
Simulation time 13354918 ps
CPU time 0.7 seconds
Started Aug 04 04:33:14 PM PDT 24
Finished Aug 04 04:33:15 PM PDT 24
Peak memory 203548 kb
Host smart-5a166da0-5827-4d55-93ed-ca76180f943a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431265084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
431265084
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1947102814
Short name T1122
Test name
Test status
Simulation time 105658952 ps
CPU time 2.31 seconds
Started Aug 04 04:32:52 PM PDT 24
Finished Aug 04 04:32:55 PM PDT 24
Peak memory 214964 kb
Host smart-b9d70ae4-2879-4ac6-8b65-8541d91690ff
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947102814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1947102814
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3213490857
Short name T1101
Test name
Test status
Simulation time 34960145 ps
CPU time 0.65 seconds
Started Aug 04 04:32:54 PM PDT 24
Finished Aug 04 04:32:55 PM PDT 24
Peak memory 203488 kb
Host smart-411c1093-4df9-4824-b36d-f5e7c08481bf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213490857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3213490857
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1377218902
Short name T1030
Test name
Test status
Simulation time 145773520 ps
CPU time 1.88 seconds
Started Aug 04 04:32:51 PM PDT 24
Finished Aug 04 04:32:53 PM PDT 24
Peak memory 215668 kb
Host smart-21e5d42b-401d-4c4e-9c0d-fca2fd7deb26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377218902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1377218902
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3479989343
Short name T93
Test name
Test status
Simulation time 60201512 ps
CPU time 3.36 seconds
Started Aug 04 04:32:54 PM PDT 24
Finished Aug 04 04:32:57 PM PDT 24
Peak memory 215132 kb
Host smart-d5675a87-0498-44b3-8fe5-84751a29873b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479989343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
479989343
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2539303303
Short name T1067
Test name
Test status
Simulation time 535913699 ps
CPU time 14 seconds
Started Aug 04 04:32:57 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 215084 kb
Host smart-0211e2d0-7aac-45f2-a028-5ad80f2850ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539303303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2539303303
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1553642754
Short name T1121
Test name
Test status
Simulation time 11433855 ps
CPU time 0.72 seconds
Started Aug 04 04:33:15 PM PDT 24
Finished Aug 04 04:33:15 PM PDT 24
Peak memory 203824 kb
Host smart-06df8c8f-3360-4f5f-a94e-84a8e788357b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553642754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1553642754
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1460435266
Short name T1053
Test name
Test status
Simulation time 72200431 ps
CPU time 0.73 seconds
Started Aug 04 04:33:12 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 203524 kb
Host smart-5ab50722-3509-4a54-818b-97791b1cb048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460435266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1460435266
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2202752972
Short name T1103
Test name
Test status
Simulation time 11853835 ps
CPU time 0.71 seconds
Started Aug 04 04:33:17 PM PDT 24
Finished Aug 04 04:33:18 PM PDT 24
Peak memory 203872 kb
Host smart-8e92fb65-a110-43da-bf56-3e4b11fc945b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202752972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2202752972
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1727001272
Short name T1011
Test name
Test status
Simulation time 14201594 ps
CPU time 0.73 seconds
Started Aug 04 04:33:21 PM PDT 24
Finished Aug 04 04:33:22 PM PDT 24
Peak memory 203848 kb
Host smart-33ee9191-2ef4-495c-a5ab-67ef1719f691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727001272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1727001272
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3359188963
Short name T1128
Test name
Test status
Simulation time 16547821 ps
CPU time 0.71 seconds
Started Aug 04 04:33:18 PM PDT 24
Finished Aug 04 04:33:18 PM PDT 24
Peak memory 203816 kb
Host smart-3f5eca56-8c00-45b4-a0b0-e1258e292af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359188963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3359188963
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2281416742
Short name T1041
Test name
Test status
Simulation time 118801879 ps
CPU time 0.73 seconds
Started Aug 04 04:33:18 PM PDT 24
Finished Aug 04 04:33:18 PM PDT 24
Peak memory 203504 kb
Host smart-8c813464-636f-41e2-b756-a6180428b5f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281416742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2281416742
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.860801634
Short name T1071
Test name
Test status
Simulation time 157481926 ps
CPU time 0.7 seconds
Started Aug 04 04:33:32 PM PDT 24
Finished Aug 04 04:33:33 PM PDT 24
Peak memory 203816 kb
Host smart-78fe8b53-6b77-4583-b6e8-2bca8d8e08c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860801634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.860801634
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3152603523
Short name T1029
Test name
Test status
Simulation time 13255961 ps
CPU time 0.73 seconds
Started Aug 04 04:33:11 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 203164 kb
Host smart-38947541-b4f3-4cba-ba55-6750d12811bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152603523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3152603523
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1839847129
Short name T1108
Test name
Test status
Simulation time 27968655 ps
CPU time 0.77 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:10 PM PDT 24
Peak memory 203516 kb
Host smart-67fd4b20-8998-49c0-9970-80574d227660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839847129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1839847129
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3482494818
Short name T1124
Test name
Test status
Simulation time 52646370 ps
CPU time 0.71 seconds
Started Aug 04 04:33:13 PM PDT 24
Finished Aug 04 04:33:14 PM PDT 24
Peak memory 203880 kb
Host smart-b8eb2f54-1a12-448f-8733-804bc2ef17ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482494818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3482494818
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1170305430
Short name T128
Test name
Test status
Simulation time 2870029262 ps
CPU time 13.81 seconds
Started Aug 04 04:33:12 PM PDT 24
Finished Aug 04 04:33:26 PM PDT 24
Peak memory 215088 kb
Host smart-2cc2d2c4-bee2-4f60-97b4-e55b2b11da9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170305430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1170305430
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.831332282
Short name T122
Test name
Test status
Simulation time 8184479815 ps
CPU time 25.72 seconds
Started Aug 04 04:33:05 PM PDT 24
Finished Aug 04 04:33:31 PM PDT 24
Peak memory 215116 kb
Host smart-62cbe545-2995-41a1-8b6d-af52444e62e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831332282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.831332282
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1316680354
Short name T77
Test name
Test status
Simulation time 31258644 ps
CPU time 1.15 seconds
Started Aug 04 04:33:07 PM PDT 24
Finished Aug 04 04:33:08 PM PDT 24
Peak memory 206816 kb
Host smart-338df256-6c0d-442a-af7a-f33d5b46ce12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316680354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1316680354
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1279843799
Short name T111
Test name
Test status
Simulation time 57156668 ps
CPU time 1.8 seconds
Started Aug 04 04:33:07 PM PDT 24
Finished Aug 04 04:33:08 PM PDT 24
Peak memory 216068 kb
Host smart-5f13ae5f-4af8-4270-bad4-56927b6a5257
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279843799 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1279843799
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3597183704
Short name T117
Test name
Test status
Simulation time 112427857 ps
CPU time 2.68 seconds
Started Aug 04 04:33:02 PM PDT 24
Finished Aug 04 04:33:05 PM PDT 24
Peak memory 215012 kb
Host smart-117f0c28-9ea9-45b9-852d-87653c40d202
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597183704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
597183704
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2345694336
Short name T1049
Test name
Test status
Simulation time 23080160 ps
CPU time 0.7 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:03 PM PDT 24
Peak memory 203548 kb
Host smart-3ca2aee7-37c4-4530-aa87-14cd3040fa58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345694336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
345694336
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3441756822
Short name T116
Test name
Test status
Simulation time 57282269 ps
CPU time 1.74 seconds
Started Aug 04 04:33:07 PM PDT 24
Finished Aug 04 04:33:19 PM PDT 24
Peak memory 215044 kb
Host smart-737ec490-2725-4f97-8a7c-f1054f456be0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441756822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3441756822
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.623823115
Short name T1047
Test name
Test status
Simulation time 15594612 ps
CPU time 0.66 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:04 PM PDT 24
Peak memory 203816 kb
Host smart-5293173e-9f6f-440f-9859-77ad587498fa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623823115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.623823115
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2956969582
Short name T146
Test name
Test status
Simulation time 171822118 ps
CPU time 1.83 seconds
Started Aug 04 04:33:10 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 215108 kb
Host smart-f201c5f5-e07a-463b-913d-a1dc9b38885b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956969582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2956969582
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.394338309
Short name T99
Test name
Test status
Simulation time 83620652 ps
CPU time 2.5 seconds
Started Aug 04 04:33:05 PM PDT 24
Finished Aug 04 04:33:07 PM PDT 24
Peak memory 215136 kb
Host smart-d858de0f-e41f-46ad-be7d-ad018fe00243
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394338309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.394338309
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1446809759
Short name T112
Test name
Test status
Simulation time 644891262 ps
CPU time 14.22 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:17 PM PDT 24
Peak memory 215132 kb
Host smart-7675fcf4-9644-4401-80e7-db2ce761dd28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446809759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1446809759
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2854317658
Short name T1010
Test name
Test status
Simulation time 11997756 ps
CPU time 0.68 seconds
Started Aug 04 04:33:05 PM PDT 24
Finished Aug 04 04:33:05 PM PDT 24
Peak memory 203860 kb
Host smart-3b4ba5fc-e2a6-4030-b34b-dbb8ed372c58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854317658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2854317658
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3417257474
Short name T1120
Test name
Test status
Simulation time 15078362 ps
CPU time 0.76 seconds
Started Aug 04 04:33:36 PM PDT 24
Finished Aug 04 04:33:37 PM PDT 24
Peak memory 203488 kb
Host smart-102f260b-4767-43e0-9c53-db849f73b787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417257474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3417257474
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.591050126
Short name T1111
Test name
Test status
Simulation time 26134979 ps
CPU time 0.74 seconds
Started Aug 04 04:33:22 PM PDT 24
Finished Aug 04 04:33:23 PM PDT 24
Peak memory 203840 kb
Host smart-9d83c03f-fa87-44ae-9c0e-d4faebc09b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591050126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.591050126
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2937691802
Short name T1046
Test name
Test status
Simulation time 11873619 ps
CPU time 0.68 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:08 PM PDT 24
Peak memory 203548 kb
Host smart-71f9ae6a-6fdf-44f1-abdc-4759a6f9256c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937691802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2937691802
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.178291264
Short name T1080
Test name
Test status
Simulation time 15117774 ps
CPU time 0.75 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 203852 kb
Host smart-e7b7e96b-dd22-4843-be0f-7064ec68e4df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178291264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.178291264
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.496533198
Short name T1028
Test name
Test status
Simulation time 29676460 ps
CPU time 0.72 seconds
Started Aug 04 04:33:12 PM PDT 24
Finished Aug 04 04:33:13 PM PDT 24
Peak memory 203524 kb
Host smart-70b84f47-41c9-479c-872e-91ffa64f1d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496533198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.496533198
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1916440628
Short name T1045
Test name
Test status
Simulation time 20640336 ps
CPU time 0.69 seconds
Started Aug 04 04:33:10 PM PDT 24
Finished Aug 04 04:33:11 PM PDT 24
Peak memory 203556 kb
Host smart-7d5209a6-a0a6-4da9-8ee4-be08ef0a4169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916440628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1916440628
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1298837598
Short name T1018
Test name
Test status
Simulation time 11062545 ps
CPU time 0.68 seconds
Started Aug 04 04:33:18 PM PDT 24
Finished Aug 04 04:33:18 PM PDT 24
Peak memory 203504 kb
Host smart-1f1d65ae-ac7c-48c0-8ba3-4ca410e0c949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298837598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1298837598
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3049031711
Short name T1069
Test name
Test status
Simulation time 50408968 ps
CPU time 0.72 seconds
Started Aug 04 04:33:21 PM PDT 24
Finished Aug 04 04:33:21 PM PDT 24
Peak memory 203848 kb
Host smart-11a48db6-afe0-4df2-bfd7-a56c1ad7c187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049031711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3049031711
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1598786526
Short name T1086
Test name
Test status
Simulation time 79887374 ps
CPU time 0.67 seconds
Started Aug 04 04:33:23 PM PDT 24
Finished Aug 04 04:33:24 PM PDT 24
Peak memory 203508 kb
Host smart-734b8316-6d67-40e7-8561-20328da65e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598786526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1598786526
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3306560894
Short name T1085
Test name
Test status
Simulation time 2297752735 ps
CPU time 7.65 seconds
Started Aug 04 04:33:02 PM PDT 24
Finished Aug 04 04:33:10 PM PDT 24
Peak memory 206808 kb
Host smart-be22b779-3959-40f8-bb1a-8e153c8d0761
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306560894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3306560894
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1693343019
Short name T124
Test name
Test status
Simulation time 9766586296 ps
CPU time 34.78 seconds
Started Aug 04 04:32:59 PM PDT 24
Finished Aug 04 04:33:34 PM PDT 24
Peak memory 206880 kb
Host smart-ee812cd2-0051-4375-9b53-4795d1dc9414
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693343019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1693343019
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1769075046
Short name T80
Test name
Test status
Simulation time 20957640 ps
CPU time 1.09 seconds
Started Aug 04 04:33:11 PM PDT 24
Finished Aug 04 04:33:13 PM PDT 24
Peak memory 216044 kb
Host smart-0ce37027-cc69-45f8-adfe-c180c05e1240
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769075046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1769075046
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1374796131
Short name T68
Test name
Test status
Simulation time 84104405 ps
CPU time 1.61 seconds
Started Aug 04 04:32:59 PM PDT 24
Finished Aug 04 04:33:02 PM PDT 24
Peak memory 215212 kb
Host smart-6ecdfa5f-7a99-4900-80fb-ee32bb4dcfb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374796131 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1374796131
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2927942375
Short name T1043
Test name
Test status
Simulation time 46287594 ps
CPU time 1.34 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 206800 kb
Host smart-4bf39946-bae9-4eed-ba1b-a6ef3d99406a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927942375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
927942375
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2899018636
Short name T1050
Test name
Test status
Simulation time 126347232 ps
CPU time 0.65 seconds
Started Aug 04 04:33:05 PM PDT 24
Finished Aug 04 04:33:06 PM PDT 24
Peak memory 203908 kb
Host smart-c57af02c-b222-43c9-9a35-1cd0c8982475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899018636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
899018636
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2679204377
Short name T119
Test name
Test status
Simulation time 213149749 ps
CPU time 2.12 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:05 PM PDT 24
Peak memory 215088 kb
Host smart-16e434fa-3c3a-45ab-a2f6-c5444209cdfd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679204377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2679204377
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3054120025
Short name T1023
Test name
Test status
Simulation time 13238364 ps
CPU time 0.67 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:08 PM PDT 24
Peak memory 203480 kb
Host smart-d71e97d7-d25a-4e97-8843-d790775d7a44
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054120025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3054120025
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.70483221
Short name T1100
Test name
Test status
Simulation time 45660874 ps
CPU time 2.78 seconds
Started Aug 04 04:33:05 PM PDT 24
Finished Aug 04 04:33:08 PM PDT 24
Peak memory 216320 kb
Host smart-adb8e195-c231-46f1-a524-314d407588b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70483221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_same_csr_outstanding.70483221
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2926803410
Short name T98
Test name
Test status
Simulation time 215737267 ps
CPU time 2.7 seconds
Started Aug 04 04:33:07 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 216176 kb
Host smart-4f77d420-d192-43f7-b6f2-39b351501c09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926803410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
926803410
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3542720417
Short name T170
Test name
Test status
Simulation time 1441758584 ps
CPU time 7.64 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:16 PM PDT 24
Peak memory 215032 kb
Host smart-8a1b5958-3b0b-4ad8-9195-6e2f02eb9624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542720417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3542720417
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3845738747
Short name T1014
Test name
Test status
Simulation time 12647254 ps
CPU time 0.73 seconds
Started Aug 04 04:33:00 PM PDT 24
Finished Aug 04 04:33:01 PM PDT 24
Peak memory 203524 kb
Host smart-59b753b7-c12b-44fb-ad58-d7b90fe60d2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845738747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3845738747
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2333103457
Short name T1113
Test name
Test status
Simulation time 19926398 ps
CPU time 0.7 seconds
Started Aug 04 04:33:14 PM PDT 24
Finished Aug 04 04:33:14 PM PDT 24
Peak memory 203568 kb
Host smart-2e8ed576-6930-457e-af39-4347c4e1c07c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333103457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2333103457
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.751036460
Short name T1042
Test name
Test status
Simulation time 40557500 ps
CPU time 0.69 seconds
Started Aug 04 04:33:15 PM PDT 24
Finished Aug 04 04:33:16 PM PDT 24
Peak memory 203860 kb
Host smart-d94496e7-087c-4880-add3-d3d0564e8cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751036460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.751036460
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1768278623
Short name T1025
Test name
Test status
Simulation time 162635084 ps
CPU time 0.76 seconds
Started Aug 04 04:33:07 PM PDT 24
Finished Aug 04 04:33:08 PM PDT 24
Peak memory 203532 kb
Host smart-56b6deda-6385-479f-a5f4-c494a7218245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768278623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1768278623
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1829363148
Short name T1065
Test name
Test status
Simulation time 122393679 ps
CPU time 0.8 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 203532 kb
Host smart-20b983db-d04b-4804-9d3c-a7f16f9a76a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829363148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1829363148
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1413517958
Short name T1037
Test name
Test status
Simulation time 24518316 ps
CPU time 0.69 seconds
Started Aug 04 04:33:14 PM PDT 24
Finished Aug 04 04:33:15 PM PDT 24
Peak memory 203872 kb
Host smart-c71efc31-0857-451b-9a10-6c93ea53cac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413517958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1413517958
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2399198139
Short name T1019
Test name
Test status
Simulation time 10626356 ps
CPU time 0.69 seconds
Started Aug 04 04:33:18 PM PDT 24
Finished Aug 04 04:33:18 PM PDT 24
Peak memory 203500 kb
Host smart-a45c905d-781b-403d-9f20-9fc8b24800c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399198139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2399198139
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2534158812
Short name T1013
Test name
Test status
Simulation time 48026748 ps
CPU time 0.84 seconds
Started Aug 04 04:33:29 PM PDT 24
Finished Aug 04 04:33:30 PM PDT 24
Peak memory 203544 kb
Host smart-82fa3c1a-38e9-49d7-90c3-2622eacb5b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534158812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2534158812
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2843228603
Short name T1024
Test name
Test status
Simulation time 25293345 ps
CPU time 0.69 seconds
Started Aug 04 04:33:14 PM PDT 24
Finished Aug 04 04:33:15 PM PDT 24
Peak memory 203836 kb
Host smart-63203a74-22af-4993-a9b9-1db14448ba84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843228603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2843228603
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1898898904
Short name T1084
Test name
Test status
Simulation time 37747438 ps
CPU time 0.73 seconds
Started Aug 04 04:33:13 PM PDT 24
Finished Aug 04 04:33:13 PM PDT 24
Peak memory 203512 kb
Host smart-18e8fe63-e911-4cc7-bcd8-3a43d03b8f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898898904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1898898904
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1349173445
Short name T1097
Test name
Test status
Simulation time 211156963 ps
CPU time 2.65 seconds
Started Aug 04 04:33:14 PM PDT 24
Finished Aug 04 04:33:22 PM PDT 24
Peak memory 216256 kb
Host smart-0279c9a2-0fa9-41a8-8eb3-d7169d87c418
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349173445 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1349173445
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4177782028
Short name T1119
Test name
Test status
Simulation time 72731255 ps
CPU time 2.22 seconds
Started Aug 04 04:33:10 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 215100 kb
Host smart-169564d0-9270-422b-ad86-758aec365b89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177782028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4
177782028
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2227194562
Short name T1017
Test name
Test status
Simulation time 15998013 ps
CPU time 0.79 seconds
Started Aug 04 04:33:13 PM PDT 24
Finished Aug 04 04:33:14 PM PDT 24
Peak memory 203832 kb
Host smart-6955a034-73a3-4687-80fb-b753bb3d87d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227194562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
227194562
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.737765756
Short name T1020
Test name
Test status
Simulation time 488720947 ps
CPU time 1.8 seconds
Started Aug 04 04:33:05 PM PDT 24
Finished Aug 04 04:33:07 PM PDT 24
Peak memory 215080 kb
Host smart-2486952f-933e-4308-814c-8ba2607a8f05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737765756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.737765756
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.24392887
Short name T1082
Test name
Test status
Simulation time 649464233 ps
CPU time 3.99 seconds
Started Aug 04 04:33:02 PM PDT 24
Finished Aug 04 04:33:06 PM PDT 24
Peak memory 215472 kb
Host smart-a0989c28-8c09-452d-a5dc-97a8607ea6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24392887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.24392887
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2929890663
Short name T1107
Test name
Test status
Simulation time 31736166 ps
CPU time 1.67 seconds
Started Aug 04 04:32:56 PM PDT 24
Finished Aug 04 04:32:58 PM PDT 24
Peak memory 216168 kb
Host smart-37236586-1b6c-45b1-8e50-9990a37c4af5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929890663 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2929890663
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1530631233
Short name T121
Test name
Test status
Simulation time 1128239403 ps
CPU time 2.48 seconds
Started Aug 04 04:33:06 PM PDT 24
Finished Aug 04 04:33:08 PM PDT 24
Peak memory 206812 kb
Host smart-30c5063a-1aa8-49d3-91c6-9d51035d66e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530631233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
530631233
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4251480379
Short name T1055
Test name
Test status
Simulation time 36055711 ps
CPU time 0.69 seconds
Started Aug 04 04:33:14 PM PDT 24
Finished Aug 04 04:33:15 PM PDT 24
Peak memory 203548 kb
Host smart-86412aae-6133-4306-9926-d7de2d5336b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251480379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
251480379
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2911242204
Short name T1115
Test name
Test status
Simulation time 43688135 ps
CPU time 2.65 seconds
Started Aug 04 04:33:08 PM PDT 24
Finished Aug 04 04:33:10 PM PDT 24
Peak memory 215036 kb
Host smart-35ab1f67-3e8e-4862-a25a-93f204ff3106
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911242204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2911242204
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3619738083
Short name T1118
Test name
Test status
Simulation time 100823779 ps
CPU time 2.77 seconds
Started Aug 04 04:33:05 PM PDT 24
Finished Aug 04 04:33:08 PM PDT 24
Peak memory 215236 kb
Host smart-46821787-289f-46c3-9224-bda707541112
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619738083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
619738083
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.34430914
Short name T1104
Test name
Test status
Simulation time 208010524 ps
CPU time 6.21 seconds
Started Aug 04 04:33:15 PM PDT 24
Finished Aug 04 04:33:22 PM PDT 24
Peak memory 215736 kb
Host smart-d7fdf2d0-9e85-413f-b5b8-22ac61c3c300
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34430914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_t
l_intg_err.34430914
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2205907994
Short name T1051
Test name
Test status
Simulation time 180767736 ps
CPU time 1.58 seconds
Started Aug 04 04:33:07 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 215068 kb
Host smart-dbafd977-0982-471b-be78-d42ff720cbd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205907994 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2205907994
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1190462703
Short name T114
Test name
Test status
Simulation time 53557748 ps
CPU time 1.71 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:11 PM PDT 24
Peak memory 215068 kb
Host smart-f461753b-e451-4963-ab17-c4733b3e6f7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190462703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
190462703
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2369223658
Short name T1056
Test name
Test status
Simulation time 90213611 ps
CPU time 0.66 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:04 PM PDT 24
Peak memory 203548 kb
Host smart-14cdb321-5d32-49e3-a5a8-595a2934ee78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369223658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
369223658
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4046260857
Short name T1033
Test name
Test status
Simulation time 192988750 ps
CPU time 4.08 seconds
Started Aug 04 04:33:03 PM PDT 24
Finished Aug 04 04:33:08 PM PDT 24
Peak memory 215020 kb
Host smart-dd3c3d23-e197-4d65-a7d4-f40de831c0e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046260857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4046260857
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.127223846
Short name T1126
Test name
Test status
Simulation time 473894949 ps
CPU time 4.1 seconds
Started Aug 04 04:33:04 PM PDT 24
Finished Aug 04 04:33:09 PM PDT 24
Peak memory 215204 kb
Host smart-8cc8088d-1f4f-49cb-a965-174668ee68dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127223846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.127223846
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2477051749
Short name T97
Test name
Test status
Simulation time 1972987439 ps
CPU time 12.17 seconds
Started Aug 04 04:33:14 PM PDT 24
Finished Aug 04 04:33:27 PM PDT 24
Peak memory 215012 kb
Host smart-4d2c0710-9d1e-4536-af78-260ec561a535
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477051749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2477051749
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1437814238
Short name T67
Test name
Test status
Simulation time 92580750 ps
CPU time 1.61 seconds
Started Aug 04 04:33:13 PM PDT 24
Finished Aug 04 04:33:15 PM PDT 24
Peak memory 215152 kb
Host smart-0d03e559-03ce-47ce-8ef3-eb13bf4202d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437814238 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1437814238
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2669379947
Short name T118
Test name
Test status
Simulation time 63254153 ps
CPU time 1.16 seconds
Started Aug 04 04:33:00 PM PDT 24
Finished Aug 04 04:33:01 PM PDT 24
Peak memory 206780 kb
Host smart-01633ef8-112c-46d5-9c66-4d933b69a696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669379947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
669379947
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.516493495
Short name T1099
Test name
Test status
Simulation time 103014181 ps
CPU time 0.7 seconds
Started Aug 04 04:32:53 PM PDT 24
Finished Aug 04 04:32:54 PM PDT 24
Peak memory 203508 kb
Host smart-2662505e-b2f7-4959-8ba8-5c6fc40a314f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516493495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.516493495
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1148025200
Short name T1073
Test name
Test status
Simulation time 44809220 ps
CPU time 2.58 seconds
Started Aug 04 04:33:09 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 215100 kb
Host smart-18225e18-d352-491a-829b-1d7fcfd57b87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148025200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1148025200
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2866806807
Short name T1068
Test name
Test status
Simulation time 80245453 ps
CPU time 2.05 seconds
Started Aug 04 04:33:11 PM PDT 24
Finished Aug 04 04:33:13 PM PDT 24
Peak memory 215196 kb
Host smart-af570691-b90a-4554-a684-b182ab5bd697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866806807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
866806807
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2483868593
Short name T169
Test name
Test status
Simulation time 3338900665 ps
CPU time 20.75 seconds
Started Aug 04 04:33:10 PM PDT 24
Finished Aug 04 04:33:31 PM PDT 24
Peak memory 215096 kb
Host smart-29baac4e-86fa-4abb-a52f-befa04e3c149
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483868593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2483868593
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1001120635
Short name T1048
Test name
Test status
Simulation time 408681144 ps
CPU time 2.59 seconds
Started Aug 04 04:33:06 PM PDT 24
Finished Aug 04 04:33:08 PM PDT 24
Peak memory 216876 kb
Host smart-462aa6f6-6bc6-405d-a75b-2db0630a4416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001120635 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1001120635
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1994872963
Short name T1064
Test name
Test status
Simulation time 129756478 ps
CPU time 1.21 seconds
Started Aug 04 04:32:57 PM PDT 24
Finished Aug 04 04:32:59 PM PDT 24
Peak memory 215020 kb
Host smart-ccba2d87-1d8e-4553-b1da-8976db7fc28f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994872963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
994872963
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2856313753
Short name T1038
Test name
Test status
Simulation time 16476156 ps
CPU time 0.78 seconds
Started Aug 04 04:33:04 PM PDT 24
Finished Aug 04 04:33:05 PM PDT 24
Peak memory 203876 kb
Host smart-50144c16-52b1-476c-855b-ce1c241a2e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856313753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
856313753
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.25534738
Short name T1070
Test name
Test status
Simulation time 213227546 ps
CPU time 4.14 seconds
Started Aug 04 04:33:07 PM PDT 24
Finished Aug 04 04:33:12 PM PDT 24
Peak memory 215200 kb
Host smart-af88d92c-3a10-4580-9809-b7d607248820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25534738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi
_device_same_csr_outstanding.25534738
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2865860054
Short name T106
Test name
Test status
Simulation time 556910440 ps
CPU time 3.31 seconds
Started Aug 04 04:33:14 PM PDT 24
Finished Aug 04 04:33:17 PM PDT 24
Peak memory 215124 kb
Host smart-56721251-47af-470a-bebe-312a04c7fa44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865860054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
865860054
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1840331106
Short name T1123
Test name
Test status
Simulation time 4381565431 ps
CPU time 20.7 seconds
Started Aug 04 04:33:39 PM PDT 24
Finished Aug 04 04:33:59 PM PDT 24
Peak memory 215156 kb
Host smart-3d1ea161-4647-4c8a-881a-bbc25843eebc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840331106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1840331106
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1351794889
Short name T990
Test name
Test status
Simulation time 14796751 ps
CPU time 0.74 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 205240 kb
Host smart-635225c9-b803-4073-9de7-3e56b16c0399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351794889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
351794889
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1323141651
Short name T641
Test name
Test status
Simulation time 108870378 ps
CPU time 2.23 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 224500 kb
Host smart-160a51a6-e471-4dff-9502-7dfb693e0c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323141651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1323141651
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1769117295
Short name T424
Test name
Test status
Simulation time 28478349 ps
CPU time 0.78 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 207004 kb
Host smart-2cf1c786-7582-42ff-a238-23d73630e417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769117295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1769117295
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2596872356
Short name T933
Test name
Test status
Simulation time 60225390 ps
CPU time 0.78 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 216100 kb
Host smart-8e0255bd-240f-4ade-b83e-e0747a2888ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596872356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2596872356
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3364589799
Short name T967
Test name
Test status
Simulation time 414790587505 ps
CPU time 430.54 seconds
Started Aug 04 05:19:11 PM PDT 24
Finished Aug 04 05:26:22 PM PDT 24
Peak memory 269820 kb
Host smart-206f5c3a-804a-4716-ba43-4e0e548c6ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364589799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3364589799
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2294586401
Short name T830
Test name
Test status
Simulation time 54539979399 ps
CPU time 333.5 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:24:37 PM PDT 24
Peak memory 257284 kb
Host smart-bfc9075c-770a-4a36-98cc-661360c24925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294586401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2294586401
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2495460593
Short name T287
Test name
Test status
Simulation time 493420451 ps
CPU time 8.2 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:13 PM PDT 24
Peak memory 233136 kb
Host smart-8f37a623-f1aa-4743-9ba2-cba0eaff8797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495460593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2495460593
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.4101565030
Short name T821
Test name
Test status
Simulation time 20656053381 ps
CPU time 118.41 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:21:08 PM PDT 24
Peak memory 265864 kb
Host smart-b60e4101-a7a0-46db-998c-9cd811f99bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101565030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.4101565030
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1008864016
Short name T931
Test name
Test status
Simulation time 415402239 ps
CPU time 4.34 seconds
Started Aug 04 05:19:04 PM PDT 24
Finished Aug 04 05:19:08 PM PDT 24
Peak memory 224908 kb
Host smart-9f68a95e-eded-446d-8bf1-c72582cba583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008864016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1008864016
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.940684919
Short name T211
Test name
Test status
Simulation time 4673953589 ps
CPU time 24.2 seconds
Started Aug 04 05:19:12 PM PDT 24
Finished Aug 04 05:19:37 PM PDT 24
Peak memory 224792 kb
Host smart-e1b61294-f53d-4399-9862-557b7182c426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940684919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.940684919
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3320908929
Short name T991
Test name
Test status
Simulation time 367917424 ps
CPU time 6.06 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 240956 kb
Host smart-268c5384-fb96-49fe-8370-14a667c5a607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320908929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3320908929
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.456776667
Short name T406
Test name
Test status
Simulation time 18978536657 ps
CPU time 17.38 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:16 PM PDT 24
Peak memory 224988 kb
Host smart-12c24342-1d82-4530-9297-bf5211ab277b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456776667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.456776667
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3488614986
Short name T788
Test name
Test status
Simulation time 370940110 ps
CPU time 4.98 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 219784 kb
Host smart-62ff6be0-1e18-46db-aac2-9dab3b0003f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3488614986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3488614986
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2840818578
Short name T70
Test name
Test status
Simulation time 32317432 ps
CPU time 0.92 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:09 PM PDT 24
Peak memory 236740 kb
Host smart-69049d3e-222d-4ef3-b24a-03757285cc5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840818578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2840818578
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4261689499
Short name T942
Test name
Test status
Simulation time 31699245 ps
CPU time 0.89 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 206200 kb
Host smart-383b6b86-d09f-42a1-b1aa-1db4532b12b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261689499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4261689499
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2219659835
Short name T905
Test name
Test status
Simulation time 1494528493 ps
CPU time 4.16 seconds
Started Aug 04 05:19:33 PM PDT 24
Finished Aug 04 05:19:38 PM PDT 24
Peak memory 216748 kb
Host smart-180daa90-bab9-4c11-9ba6-f9da5a1e833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219659835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2219659835
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4056843866
Short name T409
Test name
Test status
Simulation time 142287467 ps
CPU time 1.7 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 216716 kb
Host smart-c2fcb0ac-eefa-4f40-af65-d3387574f999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056843866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4056843866
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1469463907
Short name T858
Test name
Test status
Simulation time 13971800 ps
CPU time 0.7 seconds
Started Aug 04 05:19:15 PM PDT 24
Finished Aug 04 05:19:15 PM PDT 24
Peak memory 206384 kb
Host smart-dc1a6045-c70f-41f8-8609-18f54b4eeddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469463907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1469463907
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.103192452
Short name T163
Test name
Test status
Simulation time 736253119 ps
CPU time 7.37 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:15 PM PDT 24
Peak memory 233132 kb
Host smart-9af6fccb-6cc9-495b-b702-b8adf549f188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103192452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.103192452
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1486832022
Short name T781
Test name
Test status
Simulation time 58449119 ps
CPU time 0.72 seconds
Started Aug 04 05:19:30 PM PDT 24
Finished Aug 04 05:19:31 PM PDT 24
Peak memory 205236 kb
Host smart-6e96e761-b2fd-4203-9296-45635f87ac3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486832022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
486832022
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1257732029
Short name T508
Test name
Test status
Simulation time 61294583 ps
CPU time 0.78 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 206908 kb
Host smart-c63017c6-ea06-43cd-b285-b1a0250115f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257732029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1257732029
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1079745320
Short name T685
Test name
Test status
Simulation time 41121297332 ps
CPU time 172.97 seconds
Started Aug 04 05:19:13 PM PDT 24
Finished Aug 04 05:22:06 PM PDT 24
Peak memory 255776 kb
Host smart-32748182-63c1-4f9d-b3e6-004f6aa87939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079745320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1079745320
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1857749976
Short name T299
Test name
Test status
Simulation time 5849802680 ps
CPU time 20.07 seconds
Started Aug 04 05:19:31 PM PDT 24
Finished Aug 04 05:19:51 PM PDT 24
Peak memory 225028 kb
Host smart-be2a266c-c7ac-452a-923c-2abac6c979d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857749976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1857749976
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.390039787
Short name T164
Test name
Test status
Simulation time 3578743654 ps
CPU time 23.73 seconds
Started Aug 04 05:19:13 PM PDT 24
Finished Aug 04 05:19:37 PM PDT 24
Peak memory 241300 kb
Host smart-da907dd5-9268-4dcf-982d-7db6a1625849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390039787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.390039787
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3818989899
Short name T780
Test name
Test status
Simulation time 2759446479 ps
CPU time 58.69 seconds
Started Aug 04 05:19:40 PM PDT 24
Finished Aug 04 05:20:39 PM PDT 24
Peak memory 259084 kb
Host smart-07992767-2929-4e0f-8a6c-64068d0a53dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818989899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3818989899
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1570033242
Short name T179
Test name
Test status
Simulation time 826067778 ps
CPU time 6.46 seconds
Started Aug 04 05:19:25 PM PDT 24
Finished Aug 04 05:19:32 PM PDT 24
Peak memory 224944 kb
Host smart-22746477-163d-485a-bd34-0bec7fcfe490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570033242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1570033242
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2577444688
Short name T978
Test name
Test status
Simulation time 747112352 ps
CPU time 3.15 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 233172 kb
Host smart-ce4a946e-3615-45a4-be39-cd38a3f6e63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577444688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2577444688
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3524198247
Short name T725
Test name
Test status
Simulation time 5826402419 ps
CPU time 5.41 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:15 PM PDT 24
Peak memory 224796 kb
Host smart-3909eee2-078a-4357-8954-4ffc13f27ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524198247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3524198247
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1189340439
Short name T392
Test name
Test status
Simulation time 27877797686 ps
CPU time 24.8 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:34 PM PDT 24
Peak memory 235316 kb
Host smart-e4d78a26-7283-4589-85b0-2ebc3af499f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189340439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1189340439
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2034409570
Short name T388
Test name
Test status
Simulation time 1561702846 ps
CPU time 9.47 seconds
Started Aug 04 05:19:13 PM PDT 24
Finished Aug 04 05:19:23 PM PDT 24
Peak memory 222372 kb
Host smart-464238b8-9b9f-4655-b0a8-8a7187598871
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2034409570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2034409570
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1439298660
Short name T73
Test name
Test status
Simulation time 198035340 ps
CPU time 1.16 seconds
Started Aug 04 05:19:17 PM PDT 24
Finished Aug 04 05:19:18 PM PDT 24
Peak memory 237948 kb
Host smart-930494a1-b588-4662-a945-3742704e8f1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439298660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1439298660
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.684729225
Short name T513
Test name
Test status
Simulation time 235001712187 ps
CPU time 1083.79 seconds
Started Aug 04 05:19:26 PM PDT 24
Finished Aug 04 05:37:30 PM PDT 24
Peak memory 281824 kb
Host smart-ee58b0fc-5248-4201-bd53-69e4fc81750e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684729225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.684729225
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.732008958
Short name T993
Test name
Test status
Simulation time 14110669712 ps
CPU time 27.06 seconds
Started Aug 04 05:19:35 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 216792 kb
Host smart-f5eac761-dd0c-474d-9def-e31786e33a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732008958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.732008958
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1435941823
Short name T360
Test name
Test status
Simulation time 6775361698 ps
CPU time 19.3 seconds
Started Aug 04 05:19:12 PM PDT 24
Finished Aug 04 05:19:31 PM PDT 24
Peak memory 216720 kb
Host smart-09258a80-6a39-4f61-99fc-ba0a60aa2d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435941823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1435941823
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1457853487
Short name T569
Test name
Test status
Simulation time 43072791 ps
CPU time 1.13 seconds
Started Aug 04 05:19:14 PM PDT 24
Finished Aug 04 05:19:15 PM PDT 24
Peak memory 207724 kb
Host smart-695f6b59-1028-4623-b91c-491af7339410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457853487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1457853487
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2711549211
Short name T696
Test name
Test status
Simulation time 17515572 ps
CPU time 0.78 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 206244 kb
Host smart-c01bd462-6a3e-4553-a933-7e137065d39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711549211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2711549211
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1618238949
Short name T885
Test name
Test status
Simulation time 881348616 ps
CPU time 11.02 seconds
Started Aug 04 05:19:35 PM PDT 24
Finished Aug 04 05:19:47 PM PDT 24
Peak memory 233104 kb
Host smart-130323ad-19fb-4ee0-813e-079080c70eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618238949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1618238949
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4121770166
Short name T619
Test name
Test status
Simulation time 248736368 ps
CPU time 3.22 seconds
Started Aug 04 05:19:45 PM PDT 24
Finished Aug 04 05:19:48 PM PDT 24
Peak memory 233136 kb
Host smart-83d01eb5-8f7c-4ceb-b621-aead67bcc795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121770166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4121770166
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.456174384
Short name T361
Test name
Test status
Simulation time 125897041 ps
CPU time 0.78 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:19:52 PM PDT 24
Peak memory 205988 kb
Host smart-91b6f09a-702a-4b73-a678-bcba5cd908e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456174384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.456174384
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3430069745
Short name T647
Test name
Test status
Simulation time 103767789643 ps
CPU time 193.2 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:23:05 PM PDT 24
Peak memory 261660 kb
Host smart-f1b7db47-7b64-4fb2-a7e2-d928f3dfbb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430069745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3430069745
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3590422765
Short name T531
Test name
Test status
Simulation time 4186064674 ps
CPU time 42 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:36 PM PDT 24
Peak memory 233232 kb
Host smart-568db4c4-fdd8-4383-8975-3cc86e210c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590422765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3590422765
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3762850210
Short name T194
Test name
Test status
Simulation time 36807698714 ps
CPU time 160.28 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:22:42 PM PDT 24
Peak memory 257500 kb
Host smart-6faef128-1361-48b5-8e96-f4d78f695a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762850210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3762850210
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3028215528
Short name T286
Test name
Test status
Simulation time 2513443326 ps
CPU time 22.3 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:20:12 PM PDT 24
Peak memory 233212 kb
Host smart-25c03347-6376-4b0e-ae0f-999c7c59ed17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028215528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3028215528
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.4114436195
Short name T173
Test name
Test status
Simulation time 4220103386 ps
CPU time 52 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 251320 kb
Host smart-950f17b4-065d-4d2b-b05f-9050cdb536bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114436195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.4114436195
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1430302621
Short name T762
Test name
Test status
Simulation time 267061486 ps
CPU time 2.72 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 224740 kb
Host smart-342d5d2e-9eb1-4323-9894-08b3d664cfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430302621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1430302621
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.8070724
Short name T882
Test name
Test status
Simulation time 1477202353 ps
CPU time 20.25 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:20:15 PM PDT 24
Peak memory 232520 kb
Host smart-e3c3544f-3788-4e7b-89cc-04e0aa44697d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8070724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.8070724
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2116820466
Short name T612
Test name
Test status
Simulation time 8053415958 ps
CPU time 12.39 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:12 PM PDT 24
Peak memory 233144 kb
Host smart-81b4f665-ddab-4e2c-95f8-245e204de190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116820466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2116820466
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.293126583
Short name T468
Test name
Test status
Simulation time 493559311 ps
CPU time 9.84 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:04 PM PDT 24
Peak memory 240988 kb
Host smart-9f83406c-7365-404b-9159-69af64f96574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293126583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.293126583
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1882578478
Short name T585
Test name
Test status
Simulation time 5285897779 ps
CPU time 9.95 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 223704 kb
Host smart-2fcb93fe-be86-4bc8-9a66-441595a53dd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1882578478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1882578478
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1475571793
Short name T875
Test name
Test status
Simulation time 4424952509 ps
CPU time 46.34 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:39 PM PDT 24
Peak memory 249632 kb
Host smart-a1fe64c8-235a-470c-b342-dc991f255fba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475571793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1475571793
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.938431328
Short name T47
Test name
Test status
Simulation time 680753266 ps
CPU time 6.12 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:19:57 PM PDT 24
Peak memory 219380 kb
Host smart-f649147a-976b-40f6-84c5-8165c4decfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938431328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.938431328
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2099943809
Short name T987
Test name
Test status
Simulation time 1792584728 ps
CPU time 6.51 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:20:04 PM PDT 24
Peak memory 216708 kb
Host smart-72f460b1-37b9-4eb2-8645-1d295a2f5279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099943809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2099943809
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2821495137
Short name T48
Test name
Test status
Simulation time 31581868 ps
CPU time 1.01 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:19:51 PM PDT 24
Peak memory 207616 kb
Host smart-58854d32-75dd-4b8d-8e38-5555fc417619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821495137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2821495137
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4234881995
Short name T820
Test name
Test status
Simulation time 527112520 ps
CPU time 0.85 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 206388 kb
Host smart-5d157cc0-e657-43ea-b7a5-85e59fb83841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234881995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4234881995
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1693923672
Short name T422
Test name
Test status
Simulation time 259904230 ps
CPU time 2.87 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 224792 kb
Host smart-d3409f9e-01dc-41bd-a142-ae4952fa1c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693923672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1693923672
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.485503432
Short name T635
Test name
Test status
Simulation time 11605879 ps
CPU time 0.72 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:50 PM PDT 24
Peak memory 206056 kb
Host smart-5a9f3b92-8a75-4fae-9c4d-83bef9f89801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485503432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.485503432
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4282169819
Short name T812
Test name
Test status
Simulation time 192296864 ps
CPU time 4.69 seconds
Started Aug 04 05:19:56 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 232912 kb
Host smart-4eea9109-3798-43ad-9b94-c2191f3cfef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282169819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4282169819
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.129985948
Short name T487
Test name
Test status
Simulation time 58167824 ps
CPU time 0.76 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 206188 kb
Host smart-9e8da7c5-3526-435b-8617-81ff4341b738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129985948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.129985948
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3268739981
Short name T716
Test name
Test status
Simulation time 3922304476 ps
CPU time 13.9 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:20:03 PM PDT 24
Peak memory 233148 kb
Host smart-bddc21e6-5ac4-4c56-b09d-90282b38ccd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268739981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3268739981
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.12613556
Short name T49
Test name
Test status
Simulation time 2616745602 ps
CPU time 59.59 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:53 PM PDT 24
Peak memory 250300 kb
Host smart-75f21e13-f905-44c5-b619-2a7bf03c3d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12613556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.12613556
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2770255377
Short name T423
Test name
Test status
Simulation time 2809582887 ps
CPU time 7.58 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 233508 kb
Host smart-21cf8f1f-e591-459c-aa9d-a3a74b154096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770255377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2770255377
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3957118994
Short name T598
Test name
Test status
Simulation time 17062824 ps
CPU time 0.74 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:19:58 PM PDT 24
Peak memory 215996 kb
Host smart-846b9e7e-db84-4131-b12a-13a585a0102b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957118994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3957118994
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.119381980
Short name T584
Test name
Test status
Simulation time 141896755 ps
CPU time 2.32 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:51 PM PDT 24
Peak memory 224900 kb
Host smart-94adb7af-bded-48c3-88af-7b831ccc9ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119381980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.119381980
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1073889348
Short name T221
Test name
Test status
Simulation time 3248148355 ps
CPU time 33.81 seconds
Started Aug 04 05:19:56 PM PDT 24
Finished Aug 04 05:20:30 PM PDT 24
Peak memory 250496 kb
Host smart-bc1dc89a-eabf-4961-8ae4-ed6dc7c5d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073889348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1073889348
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2937266450
Short name T849
Test name
Test status
Simulation time 1783887128 ps
CPU time 4.66 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:20:00 PM PDT 24
Peak memory 224788 kb
Host smart-8bd37849-27c4-4551-93b5-2364ecb22c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937266450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2937266450
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2807225208
Short name T316
Test name
Test status
Simulation time 36146923 ps
CPU time 2.15 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:19:53 PM PDT 24
Peak memory 224120 kb
Host smart-ebe5537d-c0eb-453e-b0db-c75ded2e8514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807225208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2807225208
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1280576892
Short name T6
Test name
Test status
Simulation time 395475890 ps
CPU time 3.86 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:19:56 PM PDT 24
Peak memory 223060 kb
Host smart-f4c6cb87-4ac1-4ae9-8d7f-9e8df7335c24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1280576892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1280576892
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2614170575
Short name T20
Test name
Test status
Simulation time 69309445 ps
CPU time 1.25 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:19:53 PM PDT 24
Peak memory 207532 kb
Host smart-eadf76a6-fe2d-4ed0-980f-f397ab635b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614170575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2614170575
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1243485800
Short name T730
Test name
Test status
Simulation time 13456889772 ps
CPU time 19.46 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:13 PM PDT 24
Peak memory 216708 kb
Host smart-f202d6b0-e8a8-44c3-aa3f-e500d3055cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243485800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1243485800
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1241965464
Short name T718
Test name
Test status
Simulation time 76415270 ps
CPU time 1.25 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:51 PM PDT 24
Peak memory 208456 kb
Host smart-a17c2ab5-974a-4e48-96da-7b4432cc2efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241965464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1241965464
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.627976383
Short name T719
Test name
Test status
Simulation time 34394248 ps
CPU time 0.78 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:19:52 PM PDT 24
Peak memory 206308 kb
Host smart-531da1b3-2793-400c-80e0-68e4d862bc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627976383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.627976383
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3386632110
Short name T794
Test name
Test status
Simulation time 25955528717 ps
CPU time 22.68 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:16 PM PDT 24
Peak memory 233096 kb
Host smart-427725c3-33fd-4852-a818-55f69fff3a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386632110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3386632110
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.430867280
Short name T917
Test name
Test status
Simulation time 35380362 ps
CPU time 0.72 seconds
Started Aug 04 05:20:04 PM PDT 24
Finished Aug 04 05:20:05 PM PDT 24
Peak memory 205792 kb
Host smart-a8307114-54da-4703-bb95-f58da90c86ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430867280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.430867280
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.218942638
Short name T4
Test name
Test status
Simulation time 42425382 ps
CPU time 2.72 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:19:58 PM PDT 24
Peak memory 232400 kb
Host smart-3259e266-d150-4f81-97b8-222f29ceb2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218942638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.218942638
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1456598880
Short name T337
Test name
Test status
Simulation time 42140081 ps
CPU time 0.74 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:19:55 PM PDT 24
Peak memory 206932 kb
Host smart-fd615131-d2c1-43b2-a4ea-3d803810a703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456598880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1456598880
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2967623343
Short name T878
Test name
Test status
Simulation time 3534207768 ps
CPU time 12.29 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:13 PM PDT 24
Peak memory 236252 kb
Host smart-90a9f2ce-497f-44cf-bb05-ac3a1153bf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967623343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2967623343
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2204519437
Short name T226
Test name
Test status
Simulation time 168548357363 ps
CPU time 374.46 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:26:10 PM PDT 24
Peak memory 249580 kb
Host smart-e4c717e4-c56c-434b-9cf0-36d6ea50eb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204519437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2204519437
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3354266502
Short name T76
Test name
Test status
Simulation time 23649141030 ps
CPU time 227.78 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:23:48 PM PDT 24
Peak memory 271348 kb
Host smart-9882226d-c52d-463f-9ded-4a5472cb1cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354266502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3354266502
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3052544459
Short name T903
Test name
Test status
Simulation time 1627221836 ps
CPU time 29.14 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:20:20 PM PDT 24
Peak memory 233180 kb
Host smart-d497696d-db43-424a-8af3-8b2c49dc6b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052544459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3052544459
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1328839428
Short name T779
Test name
Test status
Simulation time 656112216 ps
CPU time 4.07 seconds
Started Aug 04 05:20:04 PM PDT 24
Finished Aug 04 05:20:08 PM PDT 24
Peak memory 233092 kb
Host smart-19e45ef0-1540-4469-8124-d6d0e1f2445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328839428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1328839428
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4233526493
Short name T243
Test name
Test status
Simulation time 2555497083 ps
CPU time 33.53 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:20:31 PM PDT 24
Peak memory 233044 kb
Host smart-5c677f0f-20bb-4554-b169-1869b4afc4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233526493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4233526493
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2461678255
Short name T463
Test name
Test status
Simulation time 18552153840 ps
CPU time 16.74 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:10 PM PDT 24
Peak memory 233168 kb
Host smart-fe71c77f-3aba-4a1b-b849-d16b162d5609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461678255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2461678255
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.911337585
Short name T242
Test name
Test status
Simulation time 10626174693 ps
CPU time 10.63 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:20:00 PM PDT 24
Peak memory 233168 kb
Host smart-f5fd685f-d59a-4ba5-841f-81b30710c116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911337585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.911337585
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3512839383
Short name T528
Test name
Test status
Simulation time 7239737020 ps
CPU time 8.15 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 221708 kb
Host smart-d8c0c6c0-7d30-4e98-be7e-ef938c887105
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3512839383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3512839383
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3349665421
Short name T155
Test name
Test status
Simulation time 14210382196 ps
CPU time 118.85 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:21:53 PM PDT 24
Peak memory 257840 kb
Host smart-5a3ec28f-6661-4ae0-98df-bc1445315318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349665421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3349665421
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.758080403
Short name T985
Test name
Test status
Simulation time 4474131433 ps
CPU time 18.1 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:20:13 PM PDT 24
Peak memory 216548 kb
Host smart-92448bc8-18d7-421e-8ab5-2ad843624775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758080403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.758080403
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1610117963
Short name T410
Test name
Test status
Simulation time 2268622316 ps
CPU time 4.43 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 216716 kb
Host smart-478236c2-719c-49af-b343-15292f8d61a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610117963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1610117963
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1985693501
Short name T726
Test name
Test status
Simulation time 160333024 ps
CPU time 1.08 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 208220 kb
Host smart-447971cb-c5a7-478c-9713-ff5cf4cf7147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985693501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1985693501
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.753998538
Short name T751
Test name
Test status
Simulation time 53252163 ps
CPU time 0.88 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 206272 kb
Host smart-3171fee1-49f0-4181-a470-add9c30bfc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753998538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.753998538
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1296973949
Short name T588
Test name
Test status
Simulation time 29314518663 ps
CPU time 22.52 seconds
Started Aug 04 05:20:03 PM PDT 24
Finished Aug 04 05:20:26 PM PDT 24
Peak memory 224860 kb
Host smart-0c52c90a-2200-45ea-9b39-b02c53079565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296973949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1296973949
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1601729722
Short name T525
Test name
Test status
Simulation time 13405047 ps
CPU time 0.73 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:06 PM PDT 24
Peak memory 205144 kb
Host smart-5a9f34eb-dd08-4724-aba1-d7668348978e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601729722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1601729722
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1254090064
Short name T238
Test name
Test status
Simulation time 96834111 ps
CPU time 2.42 seconds
Started Aug 04 05:20:03 PM PDT 24
Finished Aug 04 05:20:05 PM PDT 24
Peak memory 224840 kb
Host smart-2819e36f-83c2-4c52-b6e5-3faeb631cb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254090064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1254090064
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.587838558
Short name T929
Test name
Test status
Simulation time 37405963 ps
CPU time 0.7 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:19:55 PM PDT 24
Peak memory 205944 kb
Host smart-cb4fd22c-b522-4f74-b004-ea5c3ed4c715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587838558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.587838558
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3371543260
Short name T312
Test name
Test status
Simulation time 38974894 ps
CPU time 0.86 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:19:58 PM PDT 24
Peak memory 216124 kb
Host smart-d98e7fae-b8c0-4bfe-b921-c333eb3738f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371543260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3371543260
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3787069954
Short name T778
Test name
Test status
Simulation time 8352057028 ps
CPU time 50.54 seconds
Started Aug 04 05:19:56 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 224972 kb
Host smart-60b86199-3946-4729-a419-7a41e20f2d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787069954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3787069954
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4065627936
Short name T699
Test name
Test status
Simulation time 533066094 ps
CPU time 6.34 seconds
Started Aug 04 05:20:02 PM PDT 24
Finished Aug 04 05:20:09 PM PDT 24
Peak memory 233044 kb
Host smart-9d5f67a3-49fa-4113-8d5b-46ff9f0c3ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065627936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4065627936
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2728554686
Short name T276
Test name
Test status
Simulation time 10455771534 ps
CPU time 33.24 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:20:28 PM PDT 24
Peak memory 236752 kb
Host smart-64a64783-c1fc-4ee7-a331-cb411b1b8855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728554686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2728554686
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1221941621
Short name T206
Test name
Test status
Simulation time 338677536 ps
CPU time 3.14 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 224736 kb
Host smart-fca7dee7-6d3e-4de3-98ed-fdf5762ebf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221941621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1221941621
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.438670759
Short name T258
Test name
Test status
Simulation time 509940299 ps
CPU time 7.96 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:20:03 PM PDT 24
Peak memory 224852 kb
Host smart-197ce649-081c-40b9-ad8c-b0c1eefdd41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438670759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.438670759
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2245997845
Short name T373
Test name
Test status
Simulation time 876605161 ps
CPU time 5.1 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:20:03 PM PDT 24
Peak memory 240848 kb
Host smart-f1754cb5-cec1-4599-90ee-0cce11ee3692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245997845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2245997845
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1397675844
Short name T689
Test name
Test status
Simulation time 2667141959 ps
CPU time 8.86 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:08 PM PDT 24
Peak memory 234024 kb
Host smart-d6d198a5-5b6c-4661-8cf3-53f4ec43a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397675844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1397675844
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1410119640
Short name T482
Test name
Test status
Simulation time 2157835981 ps
CPU time 6.16 seconds
Started Aug 04 05:20:03 PM PDT 24
Finished Aug 04 05:20:10 PM PDT 24
Peak memory 220140 kb
Host smart-70012438-4380-44c4-aa72-1f37fdebc46a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1410119640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1410119640
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.849568002
Short name T594
Test name
Test status
Simulation time 14332645824 ps
CPU time 22.54 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:16 PM PDT 24
Peak memory 216720 kb
Host smart-2b97eca8-9bed-4bf9-83df-2ef9366e07d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849568002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.849568002
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3606193568
Short name T357
Test name
Test status
Simulation time 4921344049 ps
CPU time 3.67 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 216656 kb
Host smart-acc57f24-898b-40c7-bf37-82bc7f93ab40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606193568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3606193568
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2615215957
Short name T412
Test name
Test status
Simulation time 17792978 ps
CPU time 0.67 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:50 PM PDT 24
Peak memory 205996 kb
Host smart-f8b5f6f5-7343-452c-93a0-04aace2a6d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615215957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2615215957
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2255224505
Short name T904
Test name
Test status
Simulation time 57097312 ps
CPU time 0.73 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:19:58 PM PDT 24
Peak memory 206336 kb
Host smart-affe244b-9f30-4493-89e4-58445390fb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255224505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2255224505
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.69736723
Short name T432
Test name
Test status
Simulation time 15094935485 ps
CPU time 18.02 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:20:15 PM PDT 24
Peak memory 233076 kb
Host smart-33a7f9ae-81db-4224-938b-fbf5eb4c7459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69736723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.69736723
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3705318310
Short name T364
Test name
Test status
Simulation time 43066920 ps
CPU time 0.74 seconds
Started Aug 04 05:20:02 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 205496 kb
Host smart-ff231d2e-5c7d-4274-bc30-b8a01bc65a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705318310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3705318310
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.197607898
Short name T947
Test name
Test status
Simulation time 51143842 ps
CPU time 2.58 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:20:00 PM PDT 24
Peak memory 233100 kb
Host smart-e23cb978-3bd9-41ff-9f3a-bddaa410db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197607898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.197607898
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3280864020
Short name T783
Test name
Test status
Simulation time 79167907 ps
CPU time 0.81 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 206868 kb
Host smart-bda14e19-f77a-4ad0-99a3-96808f6fe975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280864020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3280864020
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3666890002
Short name T58
Test name
Test status
Simulation time 48248527213 ps
CPU time 153.67 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:22:24 PM PDT 24
Peak memory 254720 kb
Host smart-b575d9ee-71fc-4bb4-8764-d54e405a3bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666890002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3666890002
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3663658978
Short name T30
Test name
Test status
Simulation time 10140374454 ps
CPU time 60.53 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:20:52 PM PDT 24
Peak memory 257064 kb
Host smart-fe662f03-ba5e-419e-9392-60c3fe8acc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663658978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3663658978
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.4209147956
Short name T807
Test name
Test status
Simulation time 15297754539 ps
CPU time 159.94 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:22:35 PM PDT 24
Peak memory 250944 kb
Host smart-08938b0c-a7ac-45d9-ba9b-1f614091f970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209147956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.4209147956
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3248364037
Short name T433
Test name
Test status
Simulation time 221748891 ps
CPU time 6.67 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:20:05 PM PDT 24
Peak memory 233348 kb
Host smart-6475348f-1f55-4d91-ba25-7d790abc5a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248364037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3248364037
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3206075422
Short name T524
Test name
Test status
Simulation time 701944608 ps
CPU time 8.48 seconds
Started Aug 04 05:20:05 PM PDT 24
Finished Aug 04 05:20:13 PM PDT 24
Peak memory 224840 kb
Host smart-94dc56e9-6cc6-4000-b9dc-68d39788a85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206075422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3206075422
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2874458507
Short name T951
Test name
Test status
Simulation time 5792649442 ps
CPU time 6.62 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 233152 kb
Host smart-2ffd3937-72f6-4458-8215-ba9989533a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874458507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2874458507
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2588659729
Short name T709
Test name
Test status
Simulation time 4159592376 ps
CPU time 9.37 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:10 PM PDT 24
Peak memory 233128 kb
Host smart-b60a27bf-f717-47c0-8176-0b825998ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588659729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2588659729
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1777712730
Short name T526
Test name
Test status
Simulation time 4164392373 ps
CPU time 10.78 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 223032 kb
Host smart-98ea9170-1793-40d2-80e1-37a7f92406b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1777712730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1777712730
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1568387069
Short name T260
Test name
Test status
Simulation time 36979938423 ps
CPU time 128.38 seconds
Started Aug 04 05:19:56 PM PDT 24
Finished Aug 04 05:22:05 PM PDT 24
Peak memory 257832 kb
Host smart-e1487467-ee52-49bc-84bc-30963d2c82cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568387069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1568387069
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2407331161
Short name T1007
Test name
Test status
Simulation time 1167531955 ps
CPU time 6.21 seconds
Started Aug 04 05:19:56 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 219868 kb
Host smart-c89766dc-aab2-453f-a813-110228b119b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407331161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2407331161
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3912922685
Short name T436
Test name
Test status
Simulation time 1396740280 ps
CPU time 3.96 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 216708 kb
Host smart-3c0dadf1-d2d9-4e74-81a7-ab230fa7ef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912922685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3912922685
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3781342983
Short name T888
Test name
Test status
Simulation time 168555768 ps
CPU time 2.02 seconds
Started Aug 04 05:19:48 PM PDT 24
Finished Aug 04 05:19:50 PM PDT 24
Peak memory 216652 kb
Host smart-1da43585-93ff-4be4-8b09-603900957c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781342983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3781342983
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4161177874
Short name T324
Test name
Test status
Simulation time 53205057 ps
CPU time 0.75 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 206240 kb
Host smart-8d11c90d-2c83-4134-8271-8a14724a2287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161177874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4161177874
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1331012980
Short name T189
Test name
Test status
Simulation time 11442195839 ps
CPU time 14.34 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:20:05 PM PDT 24
Peak memory 224988 kb
Host smart-13586ebf-d0f7-4bca-a52a-bf524bf12120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331012980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1331012980
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1117450106
Short name T784
Test name
Test status
Simulation time 11854782 ps
CPU time 0.74 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 205828 kb
Host smart-b912a0d5-2c30-4bd6-b6e0-83629a881de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117450106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1117450106
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2805610807
Short name T177
Test name
Test status
Simulation time 145024046 ps
CPU time 2.64 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:19:58 PM PDT 24
Peak memory 224812 kb
Host smart-c64d855c-5f1c-4313-ac50-048f60d4843b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805610807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2805610807
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2286846391
Short name T773
Test name
Test status
Simulation time 120020765 ps
CPU time 0.75 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 206904 kb
Host smart-169ed9c4-54c5-4f1f-802d-cfcdd9a5bd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286846391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2286846391
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2157203721
Short name T702
Test name
Test status
Simulation time 1273667332 ps
CPU time 7.57 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 236012 kb
Host smart-cbf9f7a1-00ea-4c09-8424-684a8f36a44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157203721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2157203721
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.13069173
Short name T657
Test name
Test status
Simulation time 1727895531 ps
CPU time 39.03 seconds
Started Aug 04 05:20:05 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 241328 kb
Host smart-0e4669be-baf7-4529-99e3-068509d0f903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13069173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.13069173
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3647508709
Short name T134
Test name
Test status
Simulation time 336986294462 ps
CPU time 354.31 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:25:52 PM PDT 24
Peak memory 264024 kb
Host smart-12365569-5f6a-43de-b92f-e964c6984339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647508709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3647508709
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.285351973
Short name T293
Test name
Test status
Simulation time 112659141 ps
CPU time 4.12 seconds
Started Aug 04 05:19:56 PM PDT 24
Finished Aug 04 05:20:00 PM PDT 24
Peak memory 233008 kb
Host smart-09011ac0-1172-4dc7-b2ad-1a2dbff03b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285351973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.285351973
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2568358620
Short name T387
Test name
Test status
Simulation time 61423380 ps
CPU time 1.01 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 216292 kb
Host smart-82a9d9cb-0792-4b30-91d4-00f8c5d9c83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568358620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2568358620
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.322127075
Short name T398
Test name
Test status
Simulation time 318743568 ps
CPU time 2.21 seconds
Started Aug 04 05:19:56 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 224176 kb
Host smart-157fbc75-2f2a-4a43-be94-dbbf1d9db533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322127075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.322127075
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4212930751
Short name T582
Test name
Test status
Simulation time 8502495441 ps
CPU time 70.55 seconds
Started Aug 04 05:19:56 PM PDT 24
Finished Aug 04 05:21:07 PM PDT 24
Peak memory 234464 kb
Host smart-d9559a7b-3174-4e6a-bc44-698901d97c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212930751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4212930751
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1998620730
Short name T625
Test name
Test status
Simulation time 2076811035 ps
CPU time 11.63 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:20:13 PM PDT 24
Peak memory 237064 kb
Host smart-d254398e-dc81-4b27-a41c-7c12f34d51ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998620730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1998620730
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.768145406
Short name T519
Test name
Test status
Simulation time 1676913794 ps
CPU time 10.6 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 249516 kb
Host smart-c336ce2d-7552-4b74-8f2a-630f454f1079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768145406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.768145406
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1846288596
Short name T451
Test name
Test status
Simulation time 1817991590 ps
CPU time 12.6 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:20:05 PM PDT 24
Peak memory 221020 kb
Host smart-4cef3033-96c3-4cc4-9245-68451eb1e4bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1846288596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1846288596
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3603993690
Short name T694
Test name
Test status
Simulation time 49928193934 ps
CPU time 182.62 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:23:02 PM PDT 24
Peak memory 272948 kb
Host smart-fba5a6aa-9340-4284-a5b9-8f979179e765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603993690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3603993690
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3225938540
Short name T707
Test name
Test status
Simulation time 5279117150 ps
CPU time 30.42 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:20:25 PM PDT 24
Peak memory 216688 kb
Host smart-78612362-032f-473f-9565-5b58dc700ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225938540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3225938540
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2388398209
Short name T9
Test name
Test status
Simulation time 2023892941 ps
CPU time 7.21 seconds
Started Aug 04 05:20:05 PM PDT 24
Finished Aug 04 05:20:12 PM PDT 24
Peak memory 216644 kb
Host smart-ee796c58-0b3e-454b-9bff-7154ad611476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388398209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2388398209
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2640896343
Short name T305
Test name
Test status
Simulation time 310235187 ps
CPU time 4.2 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:03 PM PDT 24
Peak memory 216508 kb
Host smart-6750dd08-b1ff-41a2-88b2-b22be45ffbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640896343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2640896343
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.4136125827
Short name T464
Test name
Test status
Simulation time 72694713 ps
CPU time 0.78 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:19:53 PM PDT 24
Peak memory 206288 kb
Host smart-46e45c5c-6af5-4de4-b7d7-64518913ff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136125827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4136125827
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.394488352
Short name T731
Test name
Test status
Simulation time 621669103 ps
CPU time 5.73 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:20:07 PM PDT 24
Peak memory 218564 kb
Host smart-d54ff488-28f6-4e5e-8b22-04378fd5a78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394488352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.394488352
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1740776137
Short name T638
Test name
Test status
Simulation time 10487967 ps
CPU time 0.68 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 205732 kb
Host smart-72e4a387-ea1f-4a38-a0ec-21dbe0fcb407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740776137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1740776137
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4082177699
Short name T701
Test name
Test status
Simulation time 159716208 ps
CPU time 3.98 seconds
Started Aug 04 05:20:07 PM PDT 24
Finished Aug 04 05:20:11 PM PDT 24
Peak memory 233036 kb
Host smart-d85f12ed-0eb9-4220-98a7-345dc27f37fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082177699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4082177699
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3353305497
Short name T886
Test name
Test status
Simulation time 307230183 ps
CPU time 0.78 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 207332 kb
Host smart-2bab45dc-13de-4270-b636-bcf6b299a1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353305497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3353305497
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2592095963
Short name T520
Test name
Test status
Simulation time 5488024598 ps
CPU time 19.55 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:20:17 PM PDT 24
Peak memory 241308 kb
Host smart-74862136-48de-4c09-96da-269c66b8f25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592095963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2592095963
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1016532759
Short name T283
Test name
Test status
Simulation time 219152642004 ps
CPU time 468.98 seconds
Started Aug 04 05:20:05 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 273724 kb
Host smart-bac62567-25e1-41c7-980e-ebae614509c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016532759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1016532759
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1381848718
Short name T279
Test name
Test status
Simulation time 2844165596 ps
CPU time 57.26 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:20:55 PM PDT 24
Peak memory 239256 kb
Host smart-596b59fe-522d-409f-88a1-21095cdec3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381848718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1381848718
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2683954003
Short name T336
Test name
Test status
Simulation time 566830774 ps
CPU time 9.03 seconds
Started Aug 04 05:20:05 PM PDT 24
Finished Aug 04 05:20:14 PM PDT 24
Peak memory 224896 kb
Host smart-34c067cd-8c00-4770-b117-c9f50b0e4826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683954003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2683954003
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1833551464
Short name T182
Test name
Test status
Simulation time 27971930127 ps
CPU time 195.82 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:23:08 PM PDT 24
Peak memory 255680 kb
Host smart-6fb22c5c-aca6-4f15-9635-56b8c574ded1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833551464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1833551464
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1220624201
Short name T215
Test name
Test status
Simulation time 7810141799 ps
CPU time 19.18 seconds
Started Aug 04 05:19:47 PM PDT 24
Finished Aug 04 05:20:07 PM PDT 24
Peak memory 233128 kb
Host smart-29c5e375-2861-4eb6-b3d9-40814c5f7a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220624201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1220624201
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.217580051
Short name T986
Test name
Test status
Simulation time 5025351658 ps
CPU time 17.11 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:17 PM PDT 24
Peak memory 241316 kb
Host smart-a94f16bb-b6b3-4bf6-9250-b0a1ad3cedec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217580051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.217580051
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2987167695
Short name T1004
Test name
Test status
Simulation time 1116222481 ps
CPU time 9.08 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 233024 kb
Host smart-40257c95-0853-4391-b9f0-d06190930909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987167695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2987167695
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3766522454
Short name T639
Test name
Test status
Simulation time 28623907168 ps
CPU time 21.54 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:20:12 PM PDT 24
Peak memory 225040 kb
Host smart-9183fbaf-3b21-40f8-a381-c6c11d81ac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766522454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3766522454
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1805492677
Short name T636
Test name
Test status
Simulation time 391644188 ps
CPU time 6.06 seconds
Started Aug 04 05:20:06 PM PDT 24
Finished Aug 04 05:20:12 PM PDT 24
Peak memory 223184 kb
Host smart-1fff070e-de53-4238-a5f6-cfa396a3da8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1805492677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1805492677
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2113007113
Short name T5
Test name
Test status
Simulation time 210811608 ps
CPU time 1.2 seconds
Started Aug 04 05:19:48 PM PDT 24
Finished Aug 04 05:19:49 PM PDT 24
Peak memory 207284 kb
Host smart-5cb2c296-6eb1-46cb-81e1-0927e7e906bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113007113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2113007113
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1992245699
Short name T431
Test name
Test status
Simulation time 2844048073 ps
CPU time 14.31 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:20:15 PM PDT 24
Peak memory 216708 kb
Host smart-5586e52b-9775-4141-a5ae-b7bb13390bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992245699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1992245699
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1778240467
Short name T592
Test name
Test status
Simulation time 9116362061 ps
CPU time 8.92 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 216656 kb
Host smart-9456226f-f065-45b5-9d80-bf0a6bdf83fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778240467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1778240467
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3341864911
Short name T339
Test name
Test status
Simulation time 220406207 ps
CPU time 5.57 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:06 PM PDT 24
Peak memory 216612 kb
Host smart-71193fba-027f-43a8-80a4-a577bbaf3517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341864911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3341864911
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.898964995
Short name T315
Test name
Test status
Simulation time 67507228 ps
CPU time 0.85 seconds
Started Aug 04 05:20:08 PM PDT 24
Finished Aug 04 05:20:09 PM PDT 24
Peak memory 206268 kb
Host smart-b0934a41-3d50-4fa8-a272-a475016f2020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898964995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.898964995
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4132757626
Short name T682
Test name
Test status
Simulation time 10982456584 ps
CPU time 9.45 seconds
Started Aug 04 05:20:07 PM PDT 24
Finished Aug 04 05:20:16 PM PDT 24
Peak memory 233104 kb
Host smart-b4ee942c-da41-4b84-881c-3258a183ac77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132757626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4132757626
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1361228338
Short name T808
Test name
Test status
Simulation time 31452332 ps
CPU time 0.68 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 205768 kb
Host smart-5eedc6ba-50c7-4161-9e3e-26cdff978466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361228338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1361228338
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1357694929
Short name T263
Test name
Test status
Simulation time 32754692 ps
CPU time 2.03 seconds
Started Aug 04 05:20:02 PM PDT 24
Finished Aug 04 05:20:04 PM PDT 24
Peak memory 224912 kb
Host smart-51d67760-4ed8-441b-bc7a-9be23e21eabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357694929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1357694929
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3965805337
Short name T675
Test name
Test status
Simulation time 68193478 ps
CPU time 0.79 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:50 PM PDT 24
Peak memory 206988 kb
Host smart-f708d8df-b0b9-408a-9c76-f3365cca2753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965805337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3965805337
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1764445579
Short name T555
Test name
Test status
Simulation time 34089904036 ps
CPU time 254.35 seconds
Started Aug 04 05:20:02 PM PDT 24
Finished Aug 04 05:24:16 PM PDT 24
Peak memory 261936 kb
Host smart-833ad7c4-1f54-43fe-95b4-891ece6ca1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764445579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1764445579
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3193239025
Short name T190
Test name
Test status
Simulation time 25873184435 ps
CPU time 104.94 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:21:46 PM PDT 24
Peak memory 250608 kb
Host smart-437510b8-601b-47d1-bae3-607ac576d378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193239025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3193239025
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2450327549
Short name T665
Test name
Test status
Simulation time 8954763265 ps
CPU time 26.46 seconds
Started Aug 04 05:20:07 PM PDT 24
Finished Aug 04 05:20:34 PM PDT 24
Peak memory 239352 kb
Host smart-816f9442-8e93-4e89-966f-0038d8fd325e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450327549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2450327549
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3697280427
Short name T33
Test name
Test status
Simulation time 3401240208 ps
CPU time 28.17 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:28 PM PDT 24
Peak memory 237512 kb
Host smart-008a6dc8-0841-4cf1-935c-f69e16d5dd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697280427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3697280427
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.251811769
Short name T444
Test name
Test status
Simulation time 771411485 ps
CPU time 2.68 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:03 PM PDT 24
Peak memory 233048 kb
Host smart-c0955955-bef5-4ac5-96e2-f1b067a825f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251811769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.251811769
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4180307098
Short name T74
Test name
Test status
Simulation time 20620422589 ps
CPU time 42.67 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:20:41 PM PDT 24
Peak memory 233240 kb
Host smart-e55df929-caf8-40d3-9f0a-51fa472fc1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180307098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4180307098
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1196129038
Short name T753
Test name
Test status
Simulation time 4940829670 ps
CPU time 8.46 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 233084 kb
Host smart-aca58d90-476c-4fbe-a287-6a0a28e57e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196129038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1196129038
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1359624172
Short name T928
Test name
Test status
Simulation time 1496178959 ps
CPU time 5.33 seconds
Started Aug 04 05:20:02 PM PDT 24
Finished Aug 04 05:20:07 PM PDT 24
Peak memory 225128 kb
Host smart-099a152b-73e5-4eb4-8edc-ee244f50c91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359624172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1359624172
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.140657707
Short name T741
Test name
Test status
Simulation time 131232654 ps
CPU time 3.79 seconds
Started Aug 04 05:20:02 PM PDT 24
Finished Aug 04 05:20:06 PM PDT 24
Peak memory 223512 kb
Host smart-5217cab9-3293-4a59-9057-0d17f68de3e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=140657707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.140657707
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.293847320
Short name T150
Test name
Test status
Simulation time 188280754 ps
CPU time 1.02 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:19:56 PM PDT 24
Peak memory 207872 kb
Host smart-dd035306-6903-48d0-835a-8ff12e7d52d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293847320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.293847320
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.775975093
Short name T574
Test name
Test status
Simulation time 3732009612 ps
CPU time 10.57 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:04 PM PDT 24
Peak memory 216768 kb
Host smart-a9010bc4-b690-463b-8d58-e4dc255df036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775975093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.775975093
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.576375534
Short name T568
Test name
Test status
Simulation time 5570837128 ps
CPU time 16.15 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:20:06 PM PDT 24
Peak memory 216652 kb
Host smart-385d16e3-001d-4dcd-b2bd-14bf37337d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576375534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.576375534
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.624263894
Short name T744
Test name
Test status
Simulation time 305930057 ps
CPU time 2.37 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:03 PM PDT 24
Peak memory 216476 kb
Host smart-393e8139-5348-4a18-ba0c-06c6721e56bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624263894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.624263894
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2950052970
Short name T981
Test name
Test status
Simulation time 99090088 ps
CPU time 0.71 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:00 PM PDT 24
Peak memory 206216 kb
Host smart-3d6e6154-419f-4a3c-943e-14bc2b9757d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950052970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2950052970
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2991779510
Short name T218
Test name
Test status
Simulation time 34046529165 ps
CPU time 29.07 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:28 PM PDT 24
Peak memory 252468 kb
Host smart-ef2edc3a-ea1f-4d78-9007-605cbb4b8be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991779510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2991779510
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1492087419
Short name T681
Test name
Test status
Simulation time 58931965 ps
CPU time 0.71 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 205204 kb
Host smart-4104da14-125a-4b24-9950-a91deaa9634f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492087419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1492087419
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2558715393
Short name T983
Test name
Test status
Simulation time 2204093507 ps
CPU time 8.71 seconds
Started Aug 04 05:19:44 PM PDT 24
Finished Aug 04 05:19:53 PM PDT 24
Peak memory 233156 kb
Host smart-87427c52-23d1-46ca-b105-bf90a10ed7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558715393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2558715393
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.116191474
Short name T441
Test name
Test status
Simulation time 50456956 ps
CPU time 0.71 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:19:53 PM PDT 24
Peak memory 205964 kb
Host smart-cec773a4-87c7-4ef9-aa11-e75ff338231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116191474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.116191474
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3833661246
Short name T195
Test name
Test status
Simulation time 255348540350 ps
CPU time 322.66 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:25:17 PM PDT 24
Peak memory 257276 kb
Host smart-d2da8e03-9a5f-4b55-af82-7d9b47161beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833661246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3833661246
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4261529057
Short name T281
Test name
Test status
Simulation time 13754597141 ps
CPU time 101.74 seconds
Started Aug 04 05:20:07 PM PDT 24
Finished Aug 04 05:21:49 PM PDT 24
Peak memory 265340 kb
Host smart-a1285fae-0b2e-4614-9d99-85771c7ebb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261529057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4261529057
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3241636931
Short name T259
Test name
Test status
Simulation time 28689464297 ps
CPU time 146.95 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:22:24 PM PDT 24
Peak memory 255680 kb
Host smart-53162b90-f46d-4378-aea0-654511f3dd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241636931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3241636931
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3987156958
Short name T974
Test name
Test status
Simulation time 124079276 ps
CPU time 2.39 seconds
Started Aug 04 05:20:08 PM PDT 24
Finished Aug 04 05:20:10 PM PDT 24
Peak memory 227128 kb
Host smart-b1f267e7-f391-438a-a10c-445bf2a13338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987156958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3987156958
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3559305982
Short name T255
Test name
Test status
Simulation time 5097984459 ps
CPU time 39.16 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:20:37 PM PDT 24
Peak memory 250408 kb
Host smart-a886b8d1-b251-496b-b49d-ce8722bb7262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559305982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3559305982
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3266808516
Short name T669
Test name
Test status
Simulation time 8268039131 ps
CPU time 6.42 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:06 PM PDT 24
Peak memory 233048 kb
Host smart-f83673e9-5767-428c-aff3-9f918b2d6be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266808516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3266808516
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3095810266
Short name T515
Test name
Test status
Simulation time 8372797003 ps
CPU time 13.69 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:20:05 PM PDT 24
Peak memory 233208 kb
Host smart-97e288dc-b394-4367-888a-a83a7e774424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095810266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3095810266
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1330981645
Short name T37
Test name
Test status
Simulation time 206161769 ps
CPU time 3.93 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:19:56 PM PDT 24
Peak memory 223660 kb
Host smart-6a4c149e-db0b-4128-a57d-98e77b70363b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1330981645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1330981645
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3461579425
Short name T390
Test name
Test status
Simulation time 32908683 ps
CPU time 0.72 seconds
Started Aug 04 05:20:03 PM PDT 24
Finished Aug 04 05:20:04 PM PDT 24
Peak memory 205956 kb
Host smart-bd658943-3a81-465f-8c4d-dbc26bbcf3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461579425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3461579425
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3791289704
Short name T56
Test name
Test status
Simulation time 9328959069 ps
CPU time 3.82 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 216696 kb
Host smart-defd1445-d4ea-4a2b-8130-27a95e50610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791289704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3791289704
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2420336223
Short name T445
Test name
Test status
Simulation time 66639805 ps
CPU time 2.13 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 216576 kb
Host smart-744b86f7-600e-41dc-af8f-baf85c198aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420336223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2420336223
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3338548974
Short name T363
Test name
Test status
Simulation time 146364541 ps
CPU time 1.05 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:19:56 PM PDT 24
Peak memory 207328 kb
Host smart-d7fc61a3-73e5-40e6-abe8-69e33957aaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338548974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3338548974
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.577437497
Short name T989
Test name
Test status
Simulation time 2120657670 ps
CPU time 7.04 seconds
Started Aug 04 05:20:04 PM PDT 24
Finished Aug 04 05:20:12 PM PDT 24
Peak memory 233068 kb
Host smart-2d06cae7-cbbd-4856-b2de-314bdec823da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577437497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.577437497
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3240828539
Short name T877
Test name
Test status
Simulation time 36779532 ps
CPU time 0.69 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:19:55 PM PDT 24
Peak memory 205304 kb
Host smart-14136789-8e2b-4582-85ee-82184925517d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240828539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3240828539
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2080272466
Short name T916
Test name
Test status
Simulation time 3146333109 ps
CPU time 16.39 seconds
Started Aug 04 05:20:07 PM PDT 24
Finished Aug 04 05:20:29 PM PDT 24
Peak memory 233056 kb
Host smart-55b2badf-2533-4f8e-a46a-5914b39cf96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080272466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2080272466
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1078387879
Short name T671
Test name
Test status
Simulation time 90850942 ps
CPU time 0.84 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:19:55 PM PDT 24
Peak memory 206944 kb
Host smart-d12081c0-eeb0-4cf7-ac38-da2cc9f5fa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078387879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1078387879
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2179867492
Short name T601
Test name
Test status
Simulation time 24727882211 ps
CPU time 21.78 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:20:16 PM PDT 24
Peak memory 249256 kb
Host smart-89ba433f-31df-42cc-af2b-054386ddd8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179867492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2179867492
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3858251243
Short name T599
Test name
Test status
Simulation time 3164074928 ps
CPU time 27.85 seconds
Started Aug 04 05:20:06 PM PDT 24
Finished Aug 04 05:20:34 PM PDT 24
Peak memory 224852 kb
Host smart-60d05017-8f4f-4f8b-af5c-c3789be0adaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858251243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3858251243
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1846132032
Short name T550
Test name
Test status
Simulation time 60755705713 ps
CPU time 199.44 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:23:13 PM PDT 24
Peak memory 249512 kb
Host smart-c82be3b2-286f-49fd-9b19-bb910c28f66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846132032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1846132032
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2002564351
Short name T614
Test name
Test status
Simulation time 331066472 ps
CPU time 4.66 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:20:06 PM PDT 24
Peak memory 224908 kb
Host smart-17c036a4-f4f1-4f9d-9956-ab7095ec5a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002564351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2002564351
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3501058728
Short name T736
Test name
Test status
Simulation time 11128848714 ps
CPU time 91.19 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:21:30 PM PDT 24
Peak memory 240492 kb
Host smart-ab438086-8220-499c-b8f6-5bfb9f554596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501058728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3501058728
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2540574086
Short name T460
Test name
Test status
Simulation time 26742699835 ps
CPU time 29.53 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:23 PM PDT 24
Peak memory 240824 kb
Host smart-7777ba88-e16e-4d63-88de-ed5c120d52b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540574086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2540574086
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3227291789
Short name T714
Test name
Test status
Simulation time 5731810045 ps
CPU time 16.87 seconds
Started Aug 04 05:20:09 PM PDT 24
Finished Aug 04 05:20:26 PM PDT 24
Peak memory 233028 kb
Host smart-25a75252-d910-4e5a-b38c-1e537229072e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227291789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3227291789
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3450143281
Short name T684
Test name
Test status
Simulation time 216497608 ps
CPU time 3.81 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:03 PM PDT 24
Peak memory 223296 kb
Host smart-9348c08e-6291-4754-8974-c00c98097eb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3450143281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3450143281
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.261884177
Short name T979
Test name
Test status
Simulation time 12936368750 ps
CPU time 106.22 seconds
Started Aug 04 05:20:07 PM PDT 24
Finished Aug 04 05:21:53 PM PDT 24
Peak memory 241316 kb
Host smart-ee1d27ca-d178-470c-bad7-a573ca5609c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261884177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.261884177
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3829328788
Short name T300
Test name
Test status
Simulation time 9212929021 ps
CPU time 30.15 seconds
Started Aug 04 05:20:02 PM PDT 24
Finished Aug 04 05:20:32 PM PDT 24
Peak memory 220936 kb
Host smart-2c90a28a-0cd7-458b-b8f0-a2d7814a0c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829328788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3829328788
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2839815537
Short name T777
Test name
Test status
Simulation time 6321040804 ps
CPU time 11.62 seconds
Started Aug 04 05:20:02 PM PDT 24
Finished Aug 04 05:20:14 PM PDT 24
Peak memory 216572 kb
Host smart-be88da71-f25a-4111-8562-e294f4d7a66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839815537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2839815537
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.229178616
Short name T500
Test name
Test status
Simulation time 33181919 ps
CPU time 0.67 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:20:07 PM PDT 24
Peak memory 206016 kb
Host smart-ba2d5fa1-14e8-45f6-9341-270c50eff2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229178616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.229178616
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.346731994
Short name T772
Test name
Test status
Simulation time 34934491 ps
CPU time 0.67 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 206048 kb
Host smart-bfd0638e-a6b8-4e89-a5dc-27ca0214b1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346731994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.346731994
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.985404633
Short name T764
Test name
Test status
Simulation time 429447998 ps
CPU time 3.36 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 233060 kb
Host smart-fec85260-34d0-4e8e-9ee0-d526e4f7733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985404633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.985404633
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3222977150
Short name T867
Test name
Test status
Simulation time 23314319 ps
CPU time 0.78 seconds
Started Aug 04 05:19:35 PM PDT 24
Finished Aug 04 05:19:36 PM PDT 24
Peak memory 205308 kb
Host smart-8fb3532d-520d-4fd8-8041-bb176dd8ff5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222977150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
222977150
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.853616251
Short name T85
Test name
Test status
Simulation time 878798822 ps
CPU time 4.22 seconds
Started Aug 04 05:19:29 PM PDT 24
Finished Aug 04 05:19:33 PM PDT 24
Peak memory 224876 kb
Host smart-a9354bc3-e243-4aa2-b12b-9f02b15fe208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853616251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.853616251
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2696944561
Short name T485
Test name
Test status
Simulation time 12296386 ps
CPU time 0.73 seconds
Started Aug 04 05:19:31 PM PDT 24
Finished Aug 04 05:19:32 PM PDT 24
Peak memory 205948 kb
Host smart-73d9ab8e-fe5d-4208-885e-c5c6d6dd14f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696944561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2696944561
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2893142373
Short name T332
Test name
Test status
Simulation time 4712434186 ps
CPU time 28.74 seconds
Started Aug 04 05:19:32 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 249920 kb
Host smart-bf5778e6-ef2e-4154-8726-1bccf7545e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893142373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2893142373
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3299835315
Short name T679
Test name
Test status
Simulation time 260419415211 ps
CPU time 377.68 seconds
Started Aug 04 05:19:36 PM PDT 24
Finished Aug 04 05:25:54 PM PDT 24
Peak memory 266020 kb
Host smart-38df62f7-a1a7-4f17-b7f4-91afe8dbc247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299835315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3299835315
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2709289959
Short name T971
Test name
Test status
Simulation time 104178434375 ps
CPU time 139.25 seconds
Started Aug 04 05:19:30 PM PDT 24
Finished Aug 04 05:21:49 PM PDT 24
Peak memory 250408 kb
Host smart-d8fb9054-6a61-423d-b1d6-f1cef7d37588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709289959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2709289959
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2936624605
Short name T472
Test name
Test status
Simulation time 3186624505 ps
CPU time 9.23 seconds
Started Aug 04 05:19:34 PM PDT 24
Finished Aug 04 05:19:44 PM PDT 24
Peak memory 233120 kb
Host smart-6dcd67a0-cbab-4b57-bf99-3d9699a4fe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936624605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2936624605
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3136074358
Short name T954
Test name
Test status
Simulation time 12264386717 ps
CPU time 47.8 seconds
Started Aug 04 05:19:32 PM PDT 24
Finished Aug 04 05:20:20 PM PDT 24
Peak memory 241668 kb
Host smart-bba564e9-9792-4c90-bf9e-c3912ff99848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136074358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3136074358
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3168366415
Short name T652
Test name
Test status
Simulation time 295797635 ps
CPU time 3.57 seconds
Started Aug 04 05:19:30 PM PDT 24
Finished Aug 04 05:19:33 PM PDT 24
Peak memory 233080 kb
Host smart-ba24c640-4664-4eba-9f85-21060b25634a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168366415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3168366415
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1594759433
Short name T547
Test name
Test status
Simulation time 7302521251 ps
CPU time 46.95 seconds
Started Aug 04 05:19:30 PM PDT 24
Finished Aug 04 05:20:17 PM PDT 24
Peak memory 234144 kb
Host smart-090b844a-a37e-45ad-8ca5-2634bd01cb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594759433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1594759433
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2519667779
Short name T420
Test name
Test status
Simulation time 88227093 ps
CPU time 3.04 seconds
Started Aug 04 05:19:43 PM PDT 24
Finished Aug 04 05:19:46 PM PDT 24
Peak memory 233068 kb
Host smart-28c7ab1d-672c-473e-b2ff-5a0fe7d76952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519667779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2519667779
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2899592711
Short name T848
Test name
Test status
Simulation time 686895645 ps
CPU time 10.11 seconds
Started Aug 04 05:19:23 PM PDT 24
Finished Aug 04 05:19:33 PM PDT 24
Peak memory 233156 kb
Host smart-a0bb82a2-091c-42b9-b0c3-1acf71e36e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899592711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2899592711
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3427570637
Short name T138
Test name
Test status
Simulation time 1161876499 ps
CPU time 4.54 seconds
Started Aug 04 05:19:35 PM PDT 24
Finished Aug 04 05:19:39 PM PDT 24
Peak memory 223436 kb
Host smart-14df798c-48ff-490d-ad69-f01d5a1bc704
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3427570637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3427570637
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1667227666
Short name T71
Test name
Test status
Simulation time 36720136 ps
CPU time 1.11 seconds
Started Aug 04 05:19:46 PM PDT 24
Finished Aug 04 05:19:47 PM PDT 24
Peak memory 236084 kb
Host smart-e34aed33-3598-4de0-8bef-9bdc2588758c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667227666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1667227666
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2828162711
Short name T984
Test name
Test status
Simulation time 387671483598 ps
CPU time 961.89 seconds
Started Aug 04 05:19:27 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 282420 kb
Host smart-a39de469-80dc-4d22-92ed-7c0beb2b04ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828162711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2828162711
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2273742670
Short name T742
Test name
Test status
Simulation time 13906658 ps
CPU time 0.74 seconds
Started Aug 04 05:19:30 PM PDT 24
Finished Aug 04 05:19:31 PM PDT 24
Peak memory 206040 kb
Host smart-4fd76540-f660-4c41-b166-931dbb541c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273742670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2273742670
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2880894155
Short name T341
Test name
Test status
Simulation time 12906141918 ps
CPU time 9.06 seconds
Started Aug 04 05:19:37 PM PDT 24
Finished Aug 04 05:19:47 PM PDT 24
Peak memory 216696 kb
Host smart-425e809b-0206-4301-a168-1f251fbfea79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880894155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2880894155
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2829236503
Short name T763
Test name
Test status
Simulation time 73366657 ps
CPU time 2.83 seconds
Started Aug 04 05:19:36 PM PDT 24
Finished Aug 04 05:19:39 PM PDT 24
Peak memory 216600 kb
Host smart-58d4403d-cb5b-4fb4-bfce-009557dcf812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829236503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2829236503
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1060658567
Short name T322
Test name
Test status
Simulation time 24217539 ps
CPU time 0.72 seconds
Started Aug 04 05:19:43 PM PDT 24
Finished Aug 04 05:19:43 PM PDT 24
Peak memory 206220 kb
Host smart-eb62eb90-7b71-4a4b-a7df-69f9b83fee23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060658567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1060658567
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3066623934
Short name T863
Test name
Test status
Simulation time 5509909901 ps
CPU time 8.78 seconds
Started Aug 04 05:19:20 PM PDT 24
Finished Aug 04 05:19:29 PM PDT 24
Peak memory 224948 kb
Host smart-7b29ed0c-6609-47c6-befb-6dcda7931346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066623934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3066623934
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2059894840
Short name T63
Test name
Test status
Simulation time 16579802 ps
CPU time 0.69 seconds
Started Aug 04 05:20:03 PM PDT 24
Finished Aug 04 05:20:04 PM PDT 24
Peak memory 205856 kb
Host smart-55acbbd7-17c2-45e1-b724-84805cdfcbf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059894840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2059894840
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.254713634
Short name T771
Test name
Test status
Simulation time 573738624 ps
CPU time 3.34 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 224876 kb
Host smart-1ef6db80-c0e2-4be1-b9e8-d3f9b4e5d440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254713634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.254713634
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1168489323
Short name T715
Test name
Test status
Simulation time 32694583 ps
CPU time 0.8 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 206908 kb
Host smart-212d9ab4-278e-4b55-ab19-6b5528d35218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168489323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1168489323
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1276047835
Short name T201
Test name
Test status
Simulation time 139607865728 ps
CPU time 288.34 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:24:48 PM PDT 24
Peak memory 264292 kb
Host smart-656890ec-17b0-4a21-a0b3-e2b992197487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276047835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1276047835
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.248018128
Short name T597
Test name
Test status
Simulation time 16387476216 ps
CPU time 167.58 seconds
Started Aug 04 05:20:03 PM PDT 24
Finished Aug 04 05:22:51 PM PDT 24
Peak memory 249616 kb
Host smart-fb1eaa67-2443-4458-922b-1e5fc929e365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248018128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.248018128
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3910536955
Short name T51
Test name
Test status
Simulation time 11305407820 ps
CPU time 76.36 seconds
Started Aug 04 05:20:05 PM PDT 24
Finished Aug 04 05:21:22 PM PDT 24
Peak memory 251728 kb
Host smart-aabed967-d222-46ca-8fe6-aad20aefd64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910536955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3910536955
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2509013961
Short name T919
Test name
Test status
Simulation time 94329702 ps
CPU time 3.02 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:20:00 PM PDT 24
Peak memory 224836 kb
Host smart-7c40ef32-e23e-4805-9076-a13cdd391771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509013961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2509013961
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2125268061
Short name T918
Test name
Test status
Simulation time 8054910341 ps
CPU time 53.75 seconds
Started Aug 04 05:20:06 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 238304 kb
Host smart-365e7712-0f13-43b3-8316-26589aba681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125268061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2125268061
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3027125242
Short name T87
Test name
Test status
Simulation time 624021288 ps
CPU time 3.22 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:20:00 PM PDT 24
Peak memory 224836 kb
Host smart-53d6f97e-d72e-443b-9e4d-1d38cfd38757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027125242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3027125242
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3991433498
Short name T494
Test name
Test status
Simulation time 29441625 ps
CPU time 2.08 seconds
Started Aug 04 05:20:06 PM PDT 24
Finished Aug 04 05:20:09 PM PDT 24
Peak memory 224432 kb
Host smart-19bc2d1f-2eaf-4804-82b4-c5c6fab5367d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991433498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3991433498
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.921152841
Short name T912
Test name
Test status
Simulation time 1542166143 ps
CPU time 8.87 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:08 PM PDT 24
Peak memory 233088 kb
Host smart-ad8752d3-81cb-4116-9f8e-07758837f849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921152841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.921152841
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2097172899
Short name T700
Test name
Test status
Simulation time 586960164 ps
CPU time 5.44 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:05 PM PDT 24
Peak memory 233092 kb
Host smart-ec470db0-dff1-49de-931e-824bc100c499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097172899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2097172899
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1928551575
Short name T421
Test name
Test status
Simulation time 1420823236 ps
CPU time 4.2 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:20:05 PM PDT 24
Peak memory 219312 kb
Host smart-a65bfb92-3736-4fb5-8070-ac2ed14483ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1928551575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1928551575
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.202611183
Short name T841
Test name
Test status
Simulation time 1244063885582 ps
CPU time 707.31 seconds
Started Aug 04 05:20:04 PM PDT 24
Finished Aug 04 05:31:56 PM PDT 24
Peak memory 273752 kb
Host smart-789dedd8-7746-4006-8a30-e04775f7ec9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202611183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.202611183
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2541576556
Short name T310
Test name
Test status
Simulation time 11242510774 ps
CPU time 34.19 seconds
Started Aug 04 05:20:06 PM PDT 24
Finished Aug 04 05:20:40 PM PDT 24
Peak memory 216740 kb
Host smart-85c7d35b-01ee-4c64-94e6-1dcfda638414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541576556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2541576556
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3993425650
Short name T944
Test name
Test status
Simulation time 819035413 ps
CPU time 1.68 seconds
Started Aug 04 05:19:59 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 208140 kb
Host smart-d8a2ec24-76ca-497b-bc67-f6e632f3037b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993425650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3993425650
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3849253467
Short name T400
Test name
Test status
Simulation time 12023474 ps
CPU time 0.69 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 206052 kb
Host smart-13ce5bc6-81dd-4dd5-ae78-28c483db5e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849253467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3849253467
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1303533709
Short name T895
Test name
Test status
Simulation time 76968110 ps
CPU time 0.99 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:50 PM PDT 24
Peak memory 206360 kb
Host smart-19647cec-15fc-4c11-a2a5-567eb20f74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303533709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1303533709
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3240133392
Short name T448
Test name
Test status
Simulation time 74386487568 ps
CPU time 15.29 seconds
Started Aug 04 05:20:02 PM PDT 24
Finished Aug 04 05:20:17 PM PDT 24
Peak memory 240636 kb
Host smart-2b8cfe09-4566-4e6d-8ce6-0adb4c3820e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240133392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3240133392
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3551706877
Short name T22
Test name
Test status
Simulation time 33978480 ps
CPU time 0.68 seconds
Started Aug 04 05:20:10 PM PDT 24
Finished Aug 04 05:20:11 PM PDT 24
Peak memory 206084 kb
Host smart-9859e398-214a-4116-9674-557bb7891a9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551706877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3551706877
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1308651794
Short name T839
Test name
Test status
Simulation time 413353896 ps
CPU time 6.36 seconds
Started Aug 04 05:20:04 PM PDT 24
Finished Aug 04 05:20:10 PM PDT 24
Peak memory 233128 kb
Host smart-1073d1dc-7d8a-4eb7-a151-3f57fcc307c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308651794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1308651794
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3879095867
Short name T328
Test name
Test status
Simulation time 50130373 ps
CPU time 0.78 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 206316 kb
Host smart-e0c18a11-43d5-4dd7-bf28-005158985616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879095867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3879095867
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1485668374
Short name T530
Test name
Test status
Simulation time 21054244411 ps
CPU time 109.02 seconds
Started Aug 04 05:20:20 PM PDT 24
Finished Aug 04 05:22:09 PM PDT 24
Peak memory 252576 kb
Host smart-cca1c769-2ec4-4654-87b9-169fca65851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485668374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1485668374
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2006911692
Short name T862
Test name
Test status
Simulation time 17682437752 ps
CPU time 65.12 seconds
Started Aug 04 05:20:11 PM PDT 24
Finished Aug 04 05:21:16 PM PDT 24
Peak memory 241488 kb
Host smart-a2975759-026f-4a0a-a6d0-2a10e05c188e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006911692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2006911692
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.899886797
Short name T563
Test name
Test status
Simulation time 14508789063 ps
CPU time 64.04 seconds
Started Aug 04 05:20:07 PM PDT 24
Finished Aug 04 05:21:11 PM PDT 24
Peak memory 249984 kb
Host smart-ef430319-1bfa-45bc-b9a7-02c249abee24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899886797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.899886797
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2610058847
Short name T352
Test name
Test status
Simulation time 333649769 ps
CPU time 4.1 seconds
Started Aug 04 05:20:04 PM PDT 24
Finished Aug 04 05:20:08 PM PDT 24
Peak memory 224924 kb
Host smart-38972cf2-ed04-4175-9618-0daa0c0a3d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610058847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2610058847
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1796118924
Short name T419
Test name
Test status
Simulation time 343074214793 ps
CPU time 254.46 seconds
Started Aug 04 05:20:04 PM PDT 24
Finished Aug 04 05:24:24 PM PDT 24
Peak memory 257028 kb
Host smart-34b43e72-b8a2-42b7-9952-a50a1d3c5ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796118924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1796118924
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2760350037
Short name T879
Test name
Test status
Simulation time 106412123 ps
CPU time 2.35 seconds
Started Aug 04 05:20:08 PM PDT 24
Finished Aug 04 05:20:11 PM PDT 24
Peak memory 224900 kb
Host smart-0cf3509d-6710-49bd-ab01-dd41b47a8f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760350037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2760350037
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2827054304
Short name T624
Test name
Test status
Simulation time 35543218 ps
CPU time 2.18 seconds
Started Aug 04 05:20:08 PM PDT 24
Finished Aug 04 05:20:10 PM PDT 24
Peak memory 224800 kb
Host smart-c06e194c-64ee-4d6d-83fd-dce61887105c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827054304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2827054304
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3332141475
Short name T883
Test name
Test status
Simulation time 2622197641 ps
CPU time 11.24 seconds
Started Aug 04 05:20:04 PM PDT 24
Finished Aug 04 05:20:16 PM PDT 24
Peak memory 241216 kb
Host smart-5b4a9011-e405-4151-8d95-57e639561bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332141475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3332141475
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3662884984
Short name T890
Test name
Test status
Simulation time 835513056 ps
CPU time 5.81 seconds
Started Aug 04 05:20:04 PM PDT 24
Finished Aug 04 05:20:09 PM PDT 24
Peak memory 222396 kb
Host smart-d692e4d0-921f-47fa-b66c-a39321ff668b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3662884984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3662884984
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1578986823
Short name T949
Test name
Test status
Simulation time 4900839824 ps
CPU time 55.87 seconds
Started Aug 04 05:20:16 PM PDT 24
Finished Aug 04 05:21:12 PM PDT 24
Peak memory 249584 kb
Host smart-225164c4-4b1e-4f10-baae-ba1430a6993b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578986823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1578986823
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.27106116
Short name T838
Test name
Test status
Simulation time 2310872997 ps
CPU time 16.4 seconds
Started Aug 04 05:20:05 PM PDT 24
Finished Aug 04 05:20:21 PM PDT 24
Peak memory 220240 kb
Host smart-c735acae-9d00-4786-bf2a-0b54ed29eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27106116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.27106116
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1372004514
Short name T864
Test name
Test status
Simulation time 2679430728 ps
CPU time 12.67 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:13 PM PDT 24
Peak memory 216948 kb
Host smart-a752fdc4-2cd4-4f66-9a90-779391d2ae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372004514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1372004514
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3783951853
Short name T590
Test name
Test status
Simulation time 115343731 ps
CPU time 1.07 seconds
Started Aug 04 05:20:04 PM PDT 24
Finished Aug 04 05:20:05 PM PDT 24
Peak memory 208284 kb
Host smart-80c5469f-ec28-4890-b952-3a89339f2e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783951853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3783951853
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.353518809
Short name T60
Test name
Test status
Simulation time 66189484 ps
CPU time 0.95 seconds
Started Aug 04 05:20:03 PM PDT 24
Finished Aug 04 05:20:04 PM PDT 24
Peak memory 206752 kb
Host smart-f9420e29-718d-43ad-84a0-88bb8ad2a8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353518809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.353518809
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.192095968
Short name T697
Test name
Test status
Simulation time 621682012 ps
CPU time 3.65 seconds
Started Aug 04 05:20:05 PM PDT 24
Finished Aug 04 05:20:14 PM PDT 24
Peak memory 224964 kb
Host smart-07ade33d-dbf1-421a-9c8b-b0ab1436fec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192095968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.192095968
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.952142296
Short name T795
Test name
Test status
Simulation time 14177504 ps
CPU time 0.72 seconds
Started Aug 04 05:20:26 PM PDT 24
Finished Aug 04 05:20:26 PM PDT 24
Peak memory 205204 kb
Host smart-bb13c96d-93a7-4a39-b825-cdaeeeaaba27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952142296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.952142296
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1513344985
Short name T393
Test name
Test status
Simulation time 2465466829 ps
CPU time 4.4 seconds
Started Aug 04 05:20:08 PM PDT 24
Finished Aug 04 05:20:12 PM PDT 24
Peak memory 225032 kb
Host smart-5208a535-9837-4d01-835b-d70a943d7844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513344985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1513344985
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2193654199
Short name T884
Test name
Test status
Simulation time 23741181 ps
CPU time 0.77 seconds
Started Aug 04 05:20:10 PM PDT 24
Finished Aug 04 05:20:11 PM PDT 24
Peak memory 206008 kb
Host smart-0e7ba4be-5ace-441b-a269-546a6b3b4c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193654199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2193654199
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1922347688
Short name T405
Test name
Test status
Simulation time 212019240053 ps
CPU time 70.37 seconds
Started Aug 04 05:20:11 PM PDT 24
Finished Aug 04 05:21:22 PM PDT 24
Peak memory 238392 kb
Host smart-ae02d590-b78e-49ff-965a-457d04bd5aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922347688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1922347688
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2817302134
Short name T32
Test name
Test status
Simulation time 5946023171 ps
CPU time 37.07 seconds
Started Aug 04 05:20:12 PM PDT 24
Finished Aug 04 05:20:49 PM PDT 24
Peak memory 253828 kb
Host smart-b057538e-0852-4797-a84d-aad833e22e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817302134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2817302134
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2858313499
Short name T646
Test name
Test status
Simulation time 2309516250 ps
CPU time 22.99 seconds
Started Aug 04 05:20:10 PM PDT 24
Finished Aug 04 05:20:33 PM PDT 24
Peak memory 241348 kb
Host smart-1e222510-77cf-439d-a82c-397c46049979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858313499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2858313499
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.381232174
Short name T240
Test name
Test status
Simulation time 92239752897 ps
CPU time 163.32 seconds
Started Aug 04 05:20:10 PM PDT 24
Finished Aug 04 05:22:54 PM PDT 24
Peak memory 257032 kb
Host smart-f97ddc8f-162c-4a56-b4d1-33c8d19ea205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381232174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.381232174
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1760530893
Short name T233
Test name
Test status
Simulation time 4410392450 ps
CPU time 11.54 seconds
Started Aug 04 05:20:11 PM PDT 24
Finished Aug 04 05:20:23 PM PDT 24
Peak memory 224836 kb
Host smart-18cbe2c0-3ba3-4bc7-85e5-8ee8fd29433f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760530893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1760530893
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4006523738
Short name T721
Test name
Test status
Simulation time 9068332617 ps
CPU time 41.7 seconds
Started Aug 04 05:20:08 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 249568 kb
Host smart-7a493a5d-2b6f-4b5e-b770-5df2936aefb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006523738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4006523738
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4012305599
Short name T766
Test name
Test status
Simulation time 3471142706 ps
CPU time 7.98 seconds
Started Aug 04 05:20:12 PM PDT 24
Finished Aug 04 05:20:20 PM PDT 24
Peak memory 224884 kb
Host smart-8776abec-27ba-4abe-ba6a-6a5858f5c3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012305599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4012305599
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1242802972
Short name T452
Test name
Test status
Simulation time 10315691644 ps
CPU time 12.26 seconds
Started Aug 04 05:20:09 PM PDT 24
Finished Aug 04 05:20:21 PM PDT 24
Peak memory 233228 kb
Host smart-80766ceb-791e-4666-9a78-90de8043c823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242802972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1242802972
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2678520565
Short name T768
Test name
Test status
Simulation time 832683629 ps
CPU time 4.82 seconds
Started Aug 04 05:20:11 PM PDT 24
Finished Aug 04 05:20:16 PM PDT 24
Peak memory 220392 kb
Host smart-b8fa6ad3-62ed-49a0-95f1-bed84c86be31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2678520565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2678520565
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1410841002
Short name T53
Test name
Test status
Simulation time 323313816711 ps
CPU time 786.74 seconds
Started Aug 04 05:20:27 PM PDT 24
Finished Aug 04 05:33:34 PM PDT 24
Peak memory 269092 kb
Host smart-07fce149-27fa-4cde-a56e-fe4a8ab2ef59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410841002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1410841002
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2969329718
Short name T158
Test name
Test status
Simulation time 5233936080 ps
CPU time 16.64 seconds
Started Aug 04 05:20:14 PM PDT 24
Finished Aug 04 05:20:30 PM PDT 24
Peak memory 216672 kb
Host smart-f77ce2c5-1331-42fa-a76b-611e18b0abc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969329718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2969329718
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4035840444
Short name T492
Test name
Test status
Simulation time 12913981892 ps
CPU time 17.79 seconds
Started Aug 04 05:20:13 PM PDT 24
Finished Aug 04 05:20:31 PM PDT 24
Peak memory 216956 kb
Host smart-3b44dc8d-0205-4b55-8221-0975fcea764b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035840444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4035840444
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2287043454
Short name T596
Test name
Test status
Simulation time 108026723 ps
CPU time 1.78 seconds
Started Aug 04 05:20:10 PM PDT 24
Finished Aug 04 05:20:12 PM PDT 24
Peak memory 216740 kb
Host smart-1bee70d3-2673-4070-bcdb-ef86c0de03ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287043454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2287043454
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.4074450831
Short name T545
Test name
Test status
Simulation time 18282049 ps
CPU time 0.71 seconds
Started Aug 04 05:20:11 PM PDT 24
Finished Aug 04 05:20:12 PM PDT 24
Peak memory 206388 kb
Host smart-d38900f3-41f2-4dcf-9ce7-a58ddeb0fc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074450831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4074450831
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1335037142
Short name T493
Test name
Test status
Simulation time 4327109768 ps
CPU time 18.13 seconds
Started Aug 04 05:20:19 PM PDT 24
Finished Aug 04 05:20:37 PM PDT 24
Peak memory 241352 kb
Host smart-aabc6b26-63bf-49ed-8d3e-9d45313c1d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335037142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1335037142
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1566063249
Short name T860
Test name
Test status
Simulation time 25843803 ps
CPU time 0.75 seconds
Started Aug 04 05:20:29 PM PDT 24
Finished Aug 04 05:20:30 PM PDT 24
Peak memory 205868 kb
Host smart-f4948ea0-7903-4b1e-ae64-3de6b9492466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566063249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1566063249
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2758325601
Short name T1001
Test name
Test status
Simulation time 629305803 ps
CPU time 2.9 seconds
Started Aug 04 05:20:23 PM PDT 24
Finished Aug 04 05:20:26 PM PDT 24
Peak memory 224940 kb
Host smart-bfc4fa87-5cd2-4c47-abdb-68bc4d2c7034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758325601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2758325601
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.377014476
Short name T755
Test name
Test status
Simulation time 19986948 ps
CPU time 0.84 seconds
Started Aug 04 05:20:26 PM PDT 24
Finished Aug 04 05:20:27 PM PDT 24
Peak memory 206876 kb
Host smart-aa0aa84d-00b1-45b5-bc8c-a301fd1e4c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377014476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.377014476
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3588492497
Short name T188
Test name
Test status
Simulation time 60258351218 ps
CPU time 121.52 seconds
Started Aug 04 05:20:27 PM PDT 24
Finished Aug 04 05:22:29 PM PDT 24
Peak memory 250516 kb
Host smart-bf65ffe9-ec52-4ebf-8dd8-e82464618046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588492497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3588492497
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2129144654
Short name T219
Test name
Test status
Simulation time 141524496201 ps
CPU time 262.9 seconds
Started Aug 04 05:20:25 PM PDT 24
Finished Aug 04 05:24:48 PM PDT 24
Peak memory 255424 kb
Host smart-56602b9c-a227-4fe6-8585-8548d281d7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129144654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2129144654
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3884617614
Short name T562
Test name
Test status
Simulation time 5352735796 ps
CPU time 89.45 seconds
Started Aug 04 05:20:14 PM PDT 24
Finished Aug 04 05:21:43 PM PDT 24
Peak memory 250044 kb
Host smart-899a73bf-364d-4614-a0af-cd173c6bb1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884617614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3884617614
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3861398577
Short name T806
Test name
Test status
Simulation time 4243255189 ps
CPU time 27.97 seconds
Started Aug 04 05:20:17 PM PDT 24
Finished Aug 04 05:20:45 PM PDT 24
Peak memory 233200 kb
Host smart-02a6f272-6d97-4527-82ec-0935af704445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861398577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3861398577
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2769982037
Short name T370
Test name
Test status
Simulation time 3264915485 ps
CPU time 59.38 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:21:41 PM PDT 24
Peak memory 253648 kb
Host smart-c3befcee-9549-4264-86d5-e73bcb1987e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769982037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2769982037
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4037053768
Short name T743
Test name
Test status
Simulation time 4190450564 ps
CPU time 15.58 seconds
Started Aug 04 05:20:17 PM PDT 24
Finished Aug 04 05:20:32 PM PDT 24
Peak memory 224944 kb
Host smart-bfae3aa2-ac35-447c-807b-f9de73a6baff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037053768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4037053768
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2198581817
Short name T815
Test name
Test status
Simulation time 3000476891 ps
CPU time 32.57 seconds
Started Aug 04 05:20:22 PM PDT 24
Finished Aug 04 05:20:55 PM PDT 24
Peak memory 224904 kb
Host smart-efbd1b0b-d201-456f-8201-ed23f95eac50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198581817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2198581817
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1063220161
Short name T556
Test name
Test status
Simulation time 1359215513 ps
CPU time 5.17 seconds
Started Aug 04 05:20:22 PM PDT 24
Finished Aug 04 05:20:27 PM PDT 24
Peak memory 225092 kb
Host smart-13f58d03-ca41-4bbb-96bb-a4b7f4a6071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063220161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1063220161
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2029712247
Short name T961
Test name
Test status
Simulation time 9743363826 ps
CPU time 11.83 seconds
Started Aug 04 05:20:19 PM PDT 24
Finished Aug 04 05:20:30 PM PDT 24
Peak memory 225028 kb
Host smart-fa2929d2-20c9-4177-b2c1-c53bb78b1d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029712247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2029712247
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3649413846
Short name T354
Test name
Test status
Simulation time 222748519 ps
CPU time 4 seconds
Started Aug 04 05:20:23 PM PDT 24
Finished Aug 04 05:20:27 PM PDT 24
Peak memory 223616 kb
Host smart-d3f6fb73-3dbd-4b7e-95f7-96a1aea9c107
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3649413846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3649413846
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1726333135
Short name T197
Test name
Test status
Simulation time 156516578802 ps
CPU time 421.52 seconds
Started Aug 04 05:20:26 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 257832 kb
Host smart-beedfaa4-cf76-4e2c-ab5f-36cf213c9c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726333135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1726333135
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2508891677
Short name T483
Test name
Test status
Simulation time 29684644319 ps
CPU time 37.54 seconds
Started Aug 04 05:20:14 PM PDT 24
Finished Aug 04 05:20:51 PM PDT 24
Peak memory 216588 kb
Host smart-cf1c6fcb-6b7e-43cb-ba92-e18ffdb65da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508891677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2508891677
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2532996630
Short name T710
Test name
Test status
Simulation time 2507609839 ps
CPU time 5.88 seconds
Started Aug 04 05:20:18 PM PDT 24
Finished Aug 04 05:20:24 PM PDT 24
Peak memory 216596 kb
Host smart-975da622-2666-4db7-b5c2-77170b7e2693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532996630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2532996630
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1862123238
Short name T307
Test name
Test status
Simulation time 37277632 ps
CPU time 0.8 seconds
Started Aug 04 05:20:18 PM PDT 24
Finished Aug 04 05:20:19 PM PDT 24
Peak memory 207360 kb
Host smart-97111daf-d46d-49d2-9755-6105d63bac5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862123238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1862123238
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3703776128
Short name T415
Test name
Test status
Simulation time 39598818 ps
CPU time 0.86 seconds
Started Aug 04 05:20:13 PM PDT 24
Finished Aug 04 05:20:13 PM PDT 24
Peak memory 206252 kb
Host smart-5ea63c5b-a9ba-41e0-a2f5-53f0559e4857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703776128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3703776128
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.4274087552
Short name T802
Test name
Test status
Simulation time 255037549 ps
CPU time 5.46 seconds
Started Aug 04 05:20:21 PM PDT 24
Finished Aug 04 05:20:27 PM PDT 24
Peak memory 232492 kb
Host smart-1bd22f29-011d-427b-a7c6-9cc4b93ba0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274087552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4274087552
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2535166413
Short name T898
Test name
Test status
Simulation time 17389681 ps
CPU time 0.74 seconds
Started Aug 04 05:20:40 PM PDT 24
Finished Aug 04 05:20:41 PM PDT 24
Peak memory 205828 kb
Host smart-287427cb-deaf-47c8-80f3-9fee9169fa8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535166413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2535166413
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.670003900
Short name T504
Test name
Test status
Simulation time 414491025 ps
CPU time 5.56 seconds
Started Aug 04 05:20:20 PM PDT 24
Finished Aug 04 05:20:26 PM PDT 24
Peak memory 224888 kb
Host smart-445b9684-6eda-4a01-b366-912c2455852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670003900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.670003900
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1566566153
Short name T353
Test name
Test status
Simulation time 18394587 ps
CPU time 0.76 seconds
Started Aug 04 05:20:36 PM PDT 24
Finished Aug 04 05:20:37 PM PDT 24
Peak memory 207296 kb
Host smart-6c35861f-af86-47c4-8dc5-8ef07e771d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566566153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1566566153
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2306511189
Short name T853
Test name
Test status
Simulation time 5800892104 ps
CPU time 8.66 seconds
Started Aug 04 05:20:25 PM PDT 24
Finished Aug 04 05:20:34 PM PDT 24
Peak memory 219808 kb
Host smart-82f07930-2931-480a-b6ba-4ce4d3365a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306511189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2306511189
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.575517954
Short name T136
Test name
Test status
Simulation time 207221064949 ps
CPU time 528.74 seconds
Started Aug 04 05:20:31 PM PDT 24
Finished Aug 04 05:29:20 PM PDT 24
Peak memory 249532 kb
Host smart-23d1871b-9903-4f4c-9780-95d00d428f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575517954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.575517954
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1441698976
Short name T512
Test name
Test status
Simulation time 9248298046 ps
CPU time 33.59 seconds
Started Aug 04 05:20:23 PM PDT 24
Finished Aug 04 05:20:57 PM PDT 24
Peak memory 241280 kb
Host smart-2319224b-96dd-4564-bdf1-9dbe19a1b6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441698976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1441698976
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2962816575
Short name T59
Test name
Test status
Simulation time 942686168 ps
CPU time 20.56 seconds
Started Aug 04 05:20:25 PM PDT 24
Finished Aug 04 05:20:45 PM PDT 24
Peak memory 250812 kb
Host smart-fe29e66d-9503-42ca-9dcd-faf9b74ed68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962816575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2962816575
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2900920760
Short name T901
Test name
Test status
Simulation time 971744680 ps
CPU time 3.47 seconds
Started Aug 04 05:20:40 PM PDT 24
Finished Aug 04 05:20:43 PM PDT 24
Peak memory 224832 kb
Host smart-c9ac2bc2-637a-40ff-a862-68819a1cf3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900920760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2900920760
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2357477010
Short name T443
Test name
Test status
Simulation time 4477339782 ps
CPU time 29.88 seconds
Started Aug 04 05:20:26 PM PDT 24
Finished Aug 04 05:20:56 PM PDT 24
Peak memory 233116 kb
Host smart-3916f47d-e4e5-4f09-b4c7-6142fe88acf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357477010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2357477010
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1260778881
Short name T926
Test name
Test status
Simulation time 6602019636 ps
CPU time 20.84 seconds
Started Aug 04 05:20:27 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 234244 kb
Host smart-72428031-ac9f-43da-bb5e-cbd3be5d9424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260778881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1260778881
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1534886510
Short name T210
Test name
Test status
Simulation time 41715000628 ps
CPU time 11.33 seconds
Started Aug 04 05:20:29 PM PDT 24
Finished Aug 04 05:20:41 PM PDT 24
Peak memory 225036 kb
Host smart-3c4f33ff-0b34-45bd-b1e9-76d8fd63e4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534886510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1534886510
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1222196312
Short name T536
Test name
Test status
Simulation time 2366129013 ps
CPU time 13.66 seconds
Started Aug 04 05:20:30 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 219540 kb
Host smart-f1b9845a-3773-478f-af45-275d43664a2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1222196312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1222196312
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2970044936
Short name T131
Test name
Test status
Simulation time 2394364843 ps
CPU time 44.27 seconds
Started Aug 04 05:20:29 PM PDT 24
Finished Aug 04 05:21:14 PM PDT 24
Peak memory 241108 kb
Host smart-e6d92f66-f6fe-4994-8c59-dd22228653ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970044936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2970044936
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2771820354
Short name T796
Test name
Test status
Simulation time 7912156123 ps
CPU time 30.11 seconds
Started Aug 04 05:20:25 PM PDT 24
Finished Aug 04 05:20:55 PM PDT 24
Peak memory 216704 kb
Host smart-b71448bc-e102-428f-8be7-9daefb9ebc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771820354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2771820354
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1231064347
Short name T557
Test name
Test status
Simulation time 529915011 ps
CPU time 3.27 seconds
Started Aug 04 05:20:25 PM PDT 24
Finished Aug 04 05:20:28 PM PDT 24
Peak memory 216620 kb
Host smart-ab563b1d-40f3-4df7-89bb-d337a24a6b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231064347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1231064347
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2308186383
Short name T551
Test name
Test status
Simulation time 28790158 ps
CPU time 0.69 seconds
Started Aug 04 05:20:29 PM PDT 24
Finished Aug 04 05:20:30 PM PDT 24
Peak memory 205908 kb
Host smart-f50ed751-910a-4a73-b594-12ddf88fef4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308186383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2308186383
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1123459812
Short name T414
Test name
Test status
Simulation time 18892662 ps
CPU time 0.71 seconds
Started Aug 04 05:20:28 PM PDT 24
Finished Aug 04 05:20:28 PM PDT 24
Peak memory 206376 kb
Host smart-21fcc6c4-a1e9-4566-92c9-60b2711e4812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123459812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1123459812
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2725683881
Short name T975
Test name
Test status
Simulation time 609725216 ps
CPU time 8.01 seconds
Started Aug 04 05:20:24 PM PDT 24
Finished Aug 04 05:20:32 PM PDT 24
Peak memory 234208 kb
Host smart-2a831cf7-297e-4e3c-8e00-ae4ef2595e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725683881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2725683881
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.638474108
Short name T558
Test name
Test status
Simulation time 24686811 ps
CPU time 0.73 seconds
Started Aug 04 05:20:33 PM PDT 24
Finished Aug 04 05:20:34 PM PDT 24
Peak memory 205812 kb
Host smart-5fbfc581-e4ef-4bca-baf0-18283d5c4c12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638474108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.638474108
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2793736568
Short name T706
Test name
Test status
Simulation time 1410347988 ps
CPU time 11.99 seconds
Started Aug 04 05:20:32 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 224820 kb
Host smart-972d438a-ddce-498a-8f29-e4cdd2db9e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793736568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2793736568
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.106123678
Short name T516
Test name
Test status
Simulation time 20307810 ps
CPU time 0.77 seconds
Started Aug 04 05:20:25 PM PDT 24
Finished Aug 04 05:20:26 PM PDT 24
Peak memory 207356 kb
Host smart-5be6f884-62f3-4875-8978-b9fc3af98db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106123678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.106123678
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1736560512
Short name T178
Test name
Test status
Simulation time 20881948329 ps
CPU time 127.3 seconds
Started Aug 04 05:20:25 PM PDT 24
Finished Aug 04 05:22:33 PM PDT 24
Peak memory 254952 kb
Host smart-956425b4-d43f-4b6f-9f30-ceee4bc80d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736560512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1736560512
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.343375032
Short name T290
Test name
Test status
Simulation time 1827868917 ps
CPU time 28.7 seconds
Started Aug 04 05:20:34 PM PDT 24
Finished Aug 04 05:21:03 PM PDT 24
Peak memory 224860 kb
Host smart-d64154e7-3b67-4a43-9015-466f1e8d62dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343375032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.343375032
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2165050744
Short name T245
Test name
Test status
Simulation time 40626300301 ps
CPU time 43.48 seconds
Started Aug 04 05:20:33 PM PDT 24
Finished Aug 04 05:21:16 PM PDT 24
Peak memory 235548 kb
Host smart-4fc29fb9-bd3f-4508-8650-dd36eff4fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165050744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2165050744
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2773792950
Short name T932
Test name
Test status
Simulation time 792537438 ps
CPU time 9.53 seconds
Started Aug 04 05:20:40 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 233064 kb
Host smart-84f86ada-67a0-4b87-8b80-02f0c9835119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773792950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2773792950
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.975676950
Short name T790
Test name
Test status
Simulation time 74335836 ps
CPU time 2.73 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 233104 kb
Host smart-1116ebd8-cfe9-48de-a489-c9d167f7ee31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975676950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.975676950
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.886538943
Short name T564
Test name
Test status
Simulation time 1358286576 ps
CPU time 5.44 seconds
Started Aug 04 05:21:00 PM PDT 24
Finished Aug 04 05:21:05 PM PDT 24
Peak memory 224768 kb
Host smart-3b4caf29-dd73-420d-853a-15820c3d2c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886538943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.886538943
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2388598015
Short name T997
Test name
Test status
Simulation time 11286453118 ps
CPU time 6.3 seconds
Started Aug 04 05:20:39 PM PDT 24
Finished Aug 04 05:20:45 PM PDT 24
Peak memory 233120 kb
Host smart-1e0a6546-d5c8-4622-bf6a-52a29271d74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388598015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2388598015
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1445782375
Short name T969
Test name
Test status
Simulation time 4158205138 ps
CPU time 14.75 seconds
Started Aug 04 05:20:40 PM PDT 24
Finished Aug 04 05:20:55 PM PDT 24
Peak memory 223428 kb
Host smart-5eeb2fff-e07a-429e-a15b-37ccef37e52e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1445782375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1445782375
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3105181193
Short name T152
Test name
Test status
Simulation time 932794447 ps
CPU time 1.16 seconds
Started Aug 04 05:20:32 PM PDT 24
Finished Aug 04 05:20:33 PM PDT 24
Peak memory 207424 kb
Host smart-9e184f31-fa50-411d-b7d0-c184e213c9b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105181193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3105181193
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3521907281
Short name T964
Test name
Test status
Simulation time 1441954365 ps
CPU time 21.45 seconds
Started Aug 04 05:20:37 PM PDT 24
Finished Aug 04 05:20:58 PM PDT 24
Peak memory 216612 kb
Host smart-059b0eb1-3d81-4f59-84ac-db753541115b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521907281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3521907281
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.36806952
Short name T617
Test name
Test status
Simulation time 12501640 ps
CPU time 0.73 seconds
Started Aug 04 05:20:31 PM PDT 24
Finished Aug 04 05:20:31 PM PDT 24
Peak memory 206036 kb
Host smart-08b2a191-101d-4f94-a4d9-4068385390dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36806952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.36806952
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3993984380
Short name T471
Test name
Test status
Simulation time 795920598 ps
CPU time 4.16 seconds
Started Aug 04 05:20:26 PM PDT 24
Finished Aug 04 05:20:30 PM PDT 24
Peak memory 216548 kb
Host smart-91f57ff6-9316-4417-b046-eb6b52349164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993984380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3993984380
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.493278597
Short name T356
Test name
Test status
Simulation time 54997579 ps
CPU time 0.7 seconds
Started Aug 04 05:20:30 PM PDT 24
Finished Aug 04 05:20:30 PM PDT 24
Peak memory 206276 kb
Host smart-f2f83fe7-c166-4e00-ba3f-4d2cc687f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493278597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.493278597
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1943625583
Short name T399
Test name
Test status
Simulation time 1299752283 ps
CPU time 3.39 seconds
Started Aug 04 05:20:31 PM PDT 24
Finished Aug 04 05:20:34 PM PDT 24
Peak memory 224980 kb
Host smart-19b31f7f-8d15-4a17-9532-5287ec7e1966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943625583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1943625583
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.933019021
Short name T475
Test name
Test status
Simulation time 65278424 ps
CPU time 0.7 seconds
Started Aug 04 05:20:33 PM PDT 24
Finished Aug 04 05:20:34 PM PDT 24
Peak memory 206104 kb
Host smart-22547e5d-025d-43aa-9b8a-8fe927c67fbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933019021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.933019021
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.824261564
Short name T474
Test name
Test status
Simulation time 149814733 ps
CPU time 2.87 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 233100 kb
Host smart-1501c4d9-67dd-45c7-baf4-82a4e02ca07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824261564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.824261564
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2537993045
Short name T389
Test name
Test status
Simulation time 20254860 ps
CPU time 0.82 seconds
Started Aug 04 05:20:31 PM PDT 24
Finished Aug 04 05:20:32 PM PDT 24
Peak memory 206960 kb
Host smart-b1055062-5c28-4c6f-bba4-57c7f0a8eed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537993045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2537993045
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1738211619
Short name T362
Test name
Test status
Simulation time 15035311321 ps
CPU time 129.59 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:22:51 PM PDT 24
Peak memory 272836 kb
Host smart-70403055-8d00-405e-b583-4ab915ca300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738211619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1738211619
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1163683205
Short name T934
Test name
Test status
Simulation time 3654749396 ps
CPU time 98.73 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:22:23 PM PDT 24
Peak memory 255124 kb
Host smart-ba535607-8d54-4509-982e-9a51667fd13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163683205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1163683205
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1642341107
Short name T278
Test name
Test status
Simulation time 57129612961 ps
CPU time 501.33 seconds
Started Aug 04 05:20:38 PM PDT 24
Finished Aug 04 05:29:00 PM PDT 24
Peak memory 269996 kb
Host smart-c2638a6e-d5ec-4b0c-8404-6c82d293de98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642341107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1642341107
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.929396072
Short name T708
Test name
Test status
Simulation time 667408136 ps
CPU time 7.62 seconds
Started Aug 04 05:20:42 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 241664 kb
Host smart-e40fb411-1607-4d20-8796-2fe2da15cc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929396072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.929396072
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3925250707
Short name T913
Test name
Test status
Simulation time 4260334663 ps
CPU time 69.93 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:21:51 PM PDT 24
Peak memory 239608 kb
Host smart-3fc932c5-7464-49f6-8c77-5462a3fb0ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925250707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3925250707
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.929917329
Short name T507
Test name
Test status
Simulation time 2033075754 ps
CPU time 13.53 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:21:01 PM PDT 24
Peak memory 224880 kb
Host smart-d66956ec-912a-4e3e-ac2d-ed05ad7de4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929917329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.929917329
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.324755089
Short name T383
Test name
Test status
Simulation time 11842620562 ps
CPU time 33.71 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:21:15 PM PDT 24
Peak memory 233128 kb
Host smart-604f1bef-6f45-4804-873a-497597e98b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324755089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.324755089
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1448311579
Short name T225
Test name
Test status
Simulation time 870357424 ps
CPU time 2.45 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:20:43 PM PDT 24
Peak memory 224796 kb
Host smart-5122b11f-df1a-4e1b-a377-1bca9c3d739b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448311579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1448311579
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.121375341
Short name T610
Test name
Test status
Simulation time 630699413 ps
CPU time 5.79 seconds
Started Aug 04 05:20:42 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 239952 kb
Host smart-c712c5d6-5e28-415e-bb65-e172daf937a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121375341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.121375341
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2328455528
Short name T140
Test name
Test status
Simulation time 621361350 ps
CPU time 7.06 seconds
Started Aug 04 05:20:32 PM PDT 24
Finished Aug 04 05:20:39 PM PDT 24
Peak memory 219584 kb
Host smart-76da2d11-4a84-4736-ad30-6e10cc7ec2a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2328455528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2328455528
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3568698543
Short name T265
Test name
Test status
Simulation time 224383999778 ps
CPU time 630.92 seconds
Started Aug 04 05:20:32 PM PDT 24
Finished Aug 04 05:31:03 PM PDT 24
Peak memory 283092 kb
Host smart-803bac3c-28a7-4e4f-ad64-89bb7c88909e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568698543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3568698543
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2950186811
Short name T668
Test name
Test status
Simulation time 3558618141 ps
CPU time 25.73 seconds
Started Aug 04 05:20:42 PM PDT 24
Finished Aug 04 05:21:07 PM PDT 24
Peak memory 216660 kb
Host smart-7ebf3d03-d7a9-42b9-8c25-7832285934c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950186811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2950186811
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.419370881
Short name T401
Test name
Test status
Simulation time 1018105454 ps
CPU time 7.44 seconds
Started Aug 04 05:20:21 PM PDT 24
Finished Aug 04 05:20:28 PM PDT 24
Peak memory 216576 kb
Host smart-ce557953-331b-44cc-98c9-6afc8985b272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419370881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.419370881
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2836213517
Short name T379
Test name
Test status
Simulation time 35547651 ps
CPU time 0.71 seconds
Started Aug 04 05:20:40 PM PDT 24
Finished Aug 04 05:20:41 PM PDT 24
Peak memory 205992 kb
Host smart-24d15c87-2bbc-42a0-b5a2-9488085304a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836213517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2836213517
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.613158894
Short name T499
Test name
Test status
Simulation time 345106479 ps
CPU time 0.92 seconds
Started Aug 04 05:20:40 PM PDT 24
Finished Aug 04 05:20:41 PM PDT 24
Peak memory 207284 kb
Host smart-ea3023f1-0625-43f2-8ec2-eba0a165329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613158894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.613158894
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.403498398
Short name T232
Test name
Test status
Simulation time 2313797472 ps
CPU time 6.35 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 233208 kb
Host smart-80408e5e-7f53-4c44-bd93-3c8bd4002e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403498398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.403498398
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3341948995
Short name T958
Test name
Test status
Simulation time 126420275 ps
CPU time 0.7 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 206080 kb
Host smart-12ced0a1-62a5-4ed1-b17a-e28cfb702ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341948995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3341948995
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.481613946
Short name T580
Test name
Test status
Simulation time 88280899 ps
CPU time 3.74 seconds
Started Aug 04 05:20:40 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 233168 kb
Host smart-0f6fa4c1-2cb2-4d83-972c-3ff265d77b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481613946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.481613946
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3310279485
Short name T311
Test name
Test status
Simulation time 61528239 ps
CPU time 0.75 seconds
Started Aug 04 05:20:37 PM PDT 24
Finished Aug 04 05:20:37 PM PDT 24
Peak memory 206212 kb
Host smart-854b4c05-9ba3-454b-a788-a99be544ea10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310279485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3310279485
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2558308962
Short name T214
Test name
Test status
Simulation time 11138642219 ps
CPU time 106.96 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:22:28 PM PDT 24
Peak memory 249608 kb
Host smart-c5850cc2-a28d-411c-91d3-1e9134a6cbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558308962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2558308962
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1183902994
Short name T577
Test name
Test status
Simulation time 113990359077 ps
CPU time 235.38 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:24:37 PM PDT 24
Peak memory 266036 kb
Host smart-91352a8a-94e1-4add-a1b3-9670d0d7790a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183902994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1183902994
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3174761672
Short name T809
Test name
Test status
Simulation time 7446959589 ps
CPU time 94.82 seconds
Started Aug 04 05:20:37 PM PDT 24
Finished Aug 04 05:22:17 PM PDT 24
Peak memory 262564 kb
Host smart-45204926-52d7-46be-9402-e38dbcaef63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174761672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3174761672
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.345457410
Short name T650
Test name
Test status
Simulation time 5637660137 ps
CPU time 12.78 seconds
Started Aug 04 05:20:37 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 224868 kb
Host smart-08d5992a-594b-4892-809f-826bf9a1391f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345457410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.345457410
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3134482611
Short name T695
Test name
Test status
Simulation time 7869154986 ps
CPU time 27.42 seconds
Started Aug 04 05:20:34 PM PDT 24
Finished Aug 04 05:21:01 PM PDT 24
Peak memory 224940 kb
Host smart-84c6a287-837d-4f2d-99b8-eb503e0f52d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134482611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3134482611
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3436719741
Short name T435
Test name
Test status
Simulation time 544052629 ps
CPU time 3.03 seconds
Started Aug 04 05:20:34 PM PDT 24
Finished Aug 04 05:20:37 PM PDT 24
Peak memory 224832 kb
Host smart-8cb94677-abe6-43ae-9966-18520f8d697e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436719741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3436719741
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2275364615
Short name T162
Test name
Test status
Simulation time 6609775443 ps
CPU time 82.43 seconds
Started Aug 04 05:20:32 PM PDT 24
Finished Aug 04 05:21:54 PM PDT 24
Peak memory 233244 kb
Host smart-78a53bbb-6240-4acd-a0d6-63d05db686c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275364615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2275364615
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.552641454
Short name T36
Test name
Test status
Simulation time 15475602343 ps
CPU time 14.05 seconds
Started Aug 04 05:20:37 PM PDT 24
Finished Aug 04 05:20:51 PM PDT 24
Peak memory 233112 kb
Host smart-e882665f-252a-4fed-8f62-112b6b20129a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552641454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.552641454
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3191437101
Short name T955
Test name
Test status
Simulation time 638573844 ps
CPU time 4.1 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 233076 kb
Host smart-ca29c98b-3c3a-4237-b789-652ccbeb2efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191437101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3191437101
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1142408723
Short name T395
Test name
Test status
Simulation time 70094938 ps
CPU time 3.67 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:49 PM PDT 24
Peak memory 223564 kb
Host smart-7a8d55ef-f815-4512-9c2f-5fa091fe46cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1142408723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1142408723
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2536817856
Short name T50
Test name
Test status
Simulation time 44895489531 ps
CPU time 221.48 seconds
Started Aug 04 05:20:40 PM PDT 24
Finished Aug 04 05:24:22 PM PDT 24
Peak memory 254680 kb
Host smart-769b2298-5cf3-4cdc-82dd-5bda811b9864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536817856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2536817856
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4163290686
Short name T659
Test name
Test status
Simulation time 1024433170 ps
CPU time 16.48 seconds
Started Aug 04 05:20:33 PM PDT 24
Finished Aug 04 05:20:49 PM PDT 24
Peak memory 216652 kb
Host smart-2830a5dd-89e7-47fd-89ff-6c5404574764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163290686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4163290686
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2729837227
Short name T797
Test name
Test status
Simulation time 1007198958 ps
CPU time 3.58 seconds
Started Aug 04 05:20:39 PM PDT 24
Finished Aug 04 05:20:42 PM PDT 24
Peak memory 216628 kb
Host smart-d3f8fc0f-4c8c-4f7c-af7e-9e91d3c7a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729837227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2729837227
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1950059227
Short name T621
Test name
Test status
Simulation time 370835473 ps
CPU time 1.58 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 216644 kb
Host smart-a515b342-a611-4ba9-95fb-ad7870375dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950059227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1950059227
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.873745355
Short name T358
Test name
Test status
Simulation time 162037292 ps
CPU time 1.05 seconds
Started Aug 04 05:20:39 PM PDT 24
Finished Aug 04 05:20:40 PM PDT 24
Peak memory 206264 kb
Host smart-c4c3ed60-5806-4f1a-9342-81944496e99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873745355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.873745355
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1175925945
Short name T223
Test name
Test status
Simulation time 199150000 ps
CPU time 2.23 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:20:43 PM PDT 24
Peak memory 224920 kb
Host smart-48e78476-7fe3-4de4-9f9b-765ead4a9a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175925945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1175925945
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1046597209
Short name T677
Test name
Test status
Simulation time 13688529 ps
CPU time 0.68 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 205168 kb
Host smart-d406bab3-9135-4034-a833-d62e94e10bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046597209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1046597209
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2626431942
Short name T995
Test name
Test status
Simulation time 81232608 ps
CPU time 2.24 seconds
Started Aug 04 05:20:42 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 224968 kb
Host smart-e0d036f0-fd9b-4140-b61a-35a42edfa5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626431942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2626431942
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4062296217
Short name T833
Test name
Test status
Simulation time 16891991 ps
CPU time 0.75 seconds
Started Aug 04 05:20:37 PM PDT 24
Finished Aug 04 05:20:38 PM PDT 24
Peak memory 206448 kb
Host smart-ed530489-2dac-47a2-aa89-11405a5e9072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062296217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4062296217
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1926216426
Short name T113
Test name
Test status
Simulation time 2390363428 ps
CPU time 19.94 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:21:04 PM PDT 24
Peak memory 235980 kb
Host smart-250b1c8c-ca4c-4d45-ab2b-43b1a91ec116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926216426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1926216426
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2021602105
Short name T192
Test name
Test status
Simulation time 25598778892 ps
CPU time 116.7 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:22:44 PM PDT 24
Peak memory 256108 kb
Host smart-b67b78cb-1096-407f-830b-886c7569bb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021602105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2021602105
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3540414387
Short name T166
Test name
Test status
Simulation time 15487360819 ps
CPU time 136.55 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:23:00 PM PDT 24
Peak memory 249856 kb
Host smart-f63009fa-9889-4c58-a423-52e898d1a77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540414387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3540414387
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1883142494
Short name T326
Test name
Test status
Simulation time 1067510933 ps
CPU time 15.11 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:21:05 PM PDT 24
Peak memory 224884 kb
Host smart-31aacd4c-01ac-4089-b99c-0447d4e39246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883142494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1883142494
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2304755409
Short name T269
Test name
Test status
Simulation time 24788676313 ps
CPU time 96.01 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:22:25 PM PDT 24
Peak memory 249548 kb
Host smart-66006d19-3e5d-4032-ba36-e1a1e7aea44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304755409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2304755409
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2333438967
Short name T552
Test name
Test status
Simulation time 1183083345 ps
CPU time 3.38 seconds
Started Aug 04 05:20:34 PM PDT 24
Finished Aug 04 05:20:43 PM PDT 24
Peak memory 224784 kb
Host smart-2a079e0b-a589-45fd-b84f-7ded9c23a86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333438967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2333438967
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1579712996
Short name T698
Test name
Test status
Simulation time 4883190609 ps
CPU time 7.28 seconds
Started Aug 04 05:20:36 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 224816 kb
Host smart-46e62854-87c7-4783-8581-83b00420f5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579712996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1579712996
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.693098681
Short name T434
Test name
Test status
Simulation time 129226142 ps
CPU time 2.68 seconds
Started Aug 04 05:20:38 PM PDT 24
Finished Aug 04 05:20:41 PM PDT 24
Peak memory 233016 kb
Host smart-15a2b0ab-a760-4b42-b66a-1d1da3eba731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693098681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.693098681
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3862514909
Short name T856
Test name
Test status
Simulation time 2299622435 ps
CPU time 5.02 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 225008 kb
Host smart-4a94b3e1-aaf6-4e00-9db2-c95090aabcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862514909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3862514909
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3091693223
Short name T767
Test name
Test status
Simulation time 498540837 ps
CPU time 4.13 seconds
Started Aug 04 05:20:33 PM PDT 24
Finished Aug 04 05:20:37 PM PDT 24
Peak memory 223004 kb
Host smart-d302c5b9-77af-4754-a6cd-376c771eada8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3091693223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3091693223
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2407704560
Short name T553
Test name
Test status
Simulation time 17335134724 ps
CPU time 155.69 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:23:25 PM PDT 24
Peak memory 249600 kb
Host smart-3ebf1970-1fdc-45b7-8c44-cfbbea6b9dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407704560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2407704560
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2722082993
Short name T426
Test name
Test status
Simulation time 8652500091 ps
CPU time 13.14 seconds
Started Aug 04 05:20:40 PM PDT 24
Finished Aug 04 05:20:54 PM PDT 24
Peak memory 220212 kb
Host smart-5c3e2098-ba27-4bc6-bcc8-72d7df7a47cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722082993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2722082993
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3238045511
Short name T327
Test name
Test status
Simulation time 2134955307 ps
CPU time 6.61 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 216504 kb
Host smart-05b4b834-f5e6-4fee-820c-d520daa41642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238045511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3238045511
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1233743447
Short name T417
Test name
Test status
Simulation time 739364588 ps
CPU time 1.85 seconds
Started Aug 04 05:20:42 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 216632 kb
Host smart-05896cdf-9539-4478-acef-7a8b851923f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233743447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1233743447
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4283088223
Short name T785
Test name
Test status
Simulation time 147550387 ps
CPU time 0.84 seconds
Started Aug 04 05:20:29 PM PDT 24
Finished Aug 04 05:20:30 PM PDT 24
Peak memory 206376 kb
Host smart-0014332f-9c86-4afd-9198-a1c03b036ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283088223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4283088223
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3981641096
Short name T490
Test name
Test status
Simulation time 2294976856 ps
CPU time 6.63 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 224988 kb
Host smart-73d6afb6-ee16-4562-8494-ccd457948358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981641096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3981641096
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3348739237
Short name T384
Test name
Test status
Simulation time 36787879 ps
CPU time 0.71 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:20:45 PM PDT 24
Peak memory 205804 kb
Host smart-bd78d0b9-4bb7-42b2-9cc8-ccdfb842a383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348739237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3348739237
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1935740374
Short name T355
Test name
Test status
Simulation time 333300626 ps
CPU time 3.37 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 224896 kb
Host smart-97faeeeb-64f0-457b-b88b-0bef4db668b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935740374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1935740374
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1567207951
Short name T909
Test name
Test status
Simulation time 12368578 ps
CPU time 0.73 seconds
Started Aug 04 05:20:42 PM PDT 24
Finished Aug 04 05:20:43 PM PDT 24
Peak memory 205980 kb
Host smart-72abb33d-f6eb-4da4-9a95-28f2585850c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567207951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1567207951
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.570421326
Short name T787
Test name
Test status
Simulation time 14801287741 ps
CPU time 14.39 seconds
Started Aug 04 05:20:37 PM PDT 24
Finished Aug 04 05:20:51 PM PDT 24
Peak memory 224968 kb
Host smart-e3da7bc4-2a18-45f6-8ebf-8f6b3d8e497e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570421326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.570421326
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2282102401
Short name T937
Test name
Test status
Simulation time 63901910193 ps
CPU time 105.55 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:22:38 PM PDT 24
Peak memory 254208 kb
Host smart-9fc92ea5-4f90-43e5-ac6d-b727326810ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282102401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2282102401
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.949505971
Short name T615
Test name
Test status
Simulation time 32514518116 ps
CPU time 348.57 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:26:30 PM PDT 24
Peak memory 263068 kb
Host smart-dd64f70c-f7c5-49ea-bad8-c5fab0f2a775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949505971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.949505971
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3176352444
Short name T342
Test name
Test status
Simulation time 61223771 ps
CPU time 2.56 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:49 PM PDT 24
Peak memory 233080 kb
Host smart-2c87b2d8-a321-4942-9146-6f41b4a1247f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176352444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3176352444
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1799105244
Short name T161
Test name
Test status
Simulation time 7016803091 ps
CPU time 15.89 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:20:57 PM PDT 24
Peak memory 224968 kb
Host smart-cb72f45f-da2e-4a59-92cf-49a9bcdcfaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799105244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1799105244
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2812835969
Short name T976
Test name
Test status
Simulation time 8934558484 ps
CPU time 32.62 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:21:14 PM PDT 24
Peak memory 224972 kb
Host smart-7a08e810-ee17-48da-9ab2-e5163e9d7076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812835969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2812835969
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1403835742
Short name T220
Test name
Test status
Simulation time 7961881527 ps
CPU time 9.94 seconds
Started Aug 04 05:20:42 PM PDT 24
Finished Aug 04 05:20:52 PM PDT 24
Peak memory 225040 kb
Host smart-9d97f0e5-7882-4fe6-991d-aac00b30db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403835742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1403835742
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3165865182
Short name T637
Test name
Test status
Simulation time 4975289851 ps
CPU time 6.09 seconds
Started Aug 04 05:20:42 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 233144 kb
Host smart-c3472d60-f2f1-4550-a04a-409677d00017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165865182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3165865182
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.789109368
Short name T38
Test name
Test status
Simulation time 5196995643 ps
CPU time 7.4 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:20:51 PM PDT 24
Peak memory 223076 kb
Host smart-0198c67e-120c-4178-ac53-6b2481efe96c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=789109368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.789109368
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2399808954
Short name T151
Test name
Test status
Simulation time 62852032867 ps
CPU time 192.33 seconds
Started Aug 04 05:20:42 PM PDT 24
Finished Aug 04 05:23:54 PM PDT 24
Peak memory 255480 kb
Host smart-826b2c74-af5d-44a6-b31d-9138ccca9829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399808954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2399808954
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1084291825
Short name T844
Test name
Test status
Simulation time 174404651 ps
CPU time 2.46 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 216840 kb
Host smart-3447642d-e51d-4455-9ff4-d2a7f4b9caf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084291825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1084291825
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.371206968
Short name T540
Test name
Test status
Simulation time 8323051363 ps
CPU time 3.97 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 217536 kb
Host smart-e2d03daa-e11f-48cb-9b52-c4a8d0ed9b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371206968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.371206968
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3663132964
Short name T495
Test name
Test status
Simulation time 1206683898 ps
CPU time 2.32 seconds
Started Aug 04 05:20:40 PM PDT 24
Finished Aug 04 05:20:42 PM PDT 24
Peak memory 216600 kb
Host smart-85214577-b433-4937-95c8-dc8d146e14b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663132964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3663132964
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2876795433
Short name T623
Test name
Test status
Simulation time 11912035 ps
CPU time 0.69 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 206064 kb
Host smart-db892aa9-841e-4807-a47e-7a94a6d1443a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876795433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2876795433
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2065149728
Short name T609
Test name
Test status
Simulation time 143037964 ps
CPU time 3.33 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:20:53 PM PDT 24
Peak memory 217680 kb
Host smart-f45153a4-ff06-4957-baf3-dbe34e045807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065149728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2065149728
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3624751104
Short name T834
Test name
Test status
Simulation time 38581683 ps
CPU time 0.72 seconds
Started Aug 04 05:19:39 PM PDT 24
Finished Aug 04 05:19:40 PM PDT 24
Peak memory 205716 kb
Host smart-4d222233-c77d-4b16-89cf-bd26b6dc0cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624751104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
624751104
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3732841994
Short name T537
Test name
Test status
Simulation time 8212485022 ps
CPU time 16.35 seconds
Started Aug 04 05:19:39 PM PDT 24
Finished Aug 04 05:19:56 PM PDT 24
Peak memory 224948 kb
Host smart-6bebd507-fc6d-4f4e-91c8-4acdbf72f1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732841994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3732841994
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.493590119
Short name T896
Test name
Test status
Simulation time 25121867 ps
CPU time 0.78 seconds
Started Aug 04 05:19:23 PM PDT 24
Finished Aug 04 05:19:24 PM PDT 24
Peak memory 206200 kb
Host smart-8b63574b-6d99-464f-888d-a68e56b2705b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493590119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.493590119
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1160497418
Short name T246
Test name
Test status
Simulation time 5135642951 ps
CPU time 42.51 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:20:33 PM PDT 24
Peak memory 233212 kb
Host smart-bf9e6957-572b-41c2-81d5-0f6a5906f499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160497418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1160497418
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1552770591
Short name T819
Test name
Test status
Simulation time 48388816198 ps
CPU time 110.07 seconds
Started Aug 04 05:19:32 PM PDT 24
Finished Aug 04 05:21:22 PM PDT 24
Peak memory 249536 kb
Host smart-1e8cc0b6-5246-4f1d-948d-0f1bffa01db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552770591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1552770591
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2369564707
Short name T634
Test name
Test status
Simulation time 388221557 ps
CPU time 2.24 seconds
Started Aug 04 05:19:35 PM PDT 24
Finished Aug 04 05:19:37 PM PDT 24
Peak memory 218152 kb
Host smart-b4f2b65c-4945-4bcc-a4c1-fd25a08c4b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369564707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2369564707
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1732146079
Short name T295
Test name
Test status
Simulation time 688358292 ps
CPU time 6.91 seconds
Started Aug 04 05:19:39 PM PDT 24
Finished Aug 04 05:19:46 PM PDT 24
Peak memory 233144 kb
Host smart-9e557e69-6900-400e-a351-d8acdd29e83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732146079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1732146079
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1618923694
Short name T180
Test name
Test status
Simulation time 73284117870 ps
CPU time 517.36 seconds
Started Aug 04 05:19:33 PM PDT 24
Finished Aug 04 05:28:10 PM PDT 24
Peak memory 265884 kb
Host smart-a1482476-ecef-4714-a651-446cb8b8567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618923694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1618923694
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3077592204
Short name T321
Test name
Test status
Simulation time 204748465 ps
CPU time 2.24 seconds
Started Aug 04 05:19:25 PM PDT 24
Finished Aug 04 05:19:27 PM PDT 24
Peak memory 223552 kb
Host smart-5b9b2bd8-a13f-4af3-9f6e-9fbc00e5036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077592204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3077592204
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2419743886
Short name T193
Test name
Test status
Simulation time 6104747729 ps
CPU time 15.94 seconds
Started Aug 04 05:19:26 PM PDT 24
Finished Aug 04 05:19:42 PM PDT 24
Peak memory 225000 kb
Host smart-965e1706-1ddb-428a-a44b-152b675ac098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419743886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2419743886
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1414313257
Short name T249
Test name
Test status
Simulation time 80181351 ps
CPU time 2.09 seconds
Started Aug 04 05:19:33 PM PDT 24
Finished Aug 04 05:19:35 PM PDT 24
Peak memory 224812 kb
Host smart-d596d4db-b9a7-4fe8-9992-ae48cf146b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414313257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1414313257
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.975803076
Short name T10
Test name
Test status
Simulation time 2022476869 ps
CPU time 3.34 seconds
Started Aug 04 05:19:31 PM PDT 24
Finished Aug 04 05:19:34 PM PDT 24
Peak memory 224964 kb
Host smart-7b7ac1b6-5fed-4f58-b3b9-f2b17d307b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975803076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.975803076
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.541117447
Short name T662
Test name
Test status
Simulation time 104887314 ps
CPU time 4.11 seconds
Started Aug 04 05:19:34 PM PDT 24
Finished Aug 04 05:19:38 PM PDT 24
Peak memory 219656 kb
Host smart-2accf0c6-b22f-4871-8523-e840d22bcddf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=541117447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.541117447
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.384015449
Short name T137
Test name
Test status
Simulation time 14300908841 ps
CPU time 89.57 seconds
Started Aug 04 05:19:38 PM PDT 24
Finished Aug 04 05:21:07 PM PDT 24
Peak memory 257756 kb
Host smart-28cb2a9c-af8e-4ddc-8264-885eca9c2f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384015449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.384015449
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.934563475
Short name T302
Test name
Test status
Simulation time 1043725176 ps
CPU time 3.98 seconds
Started Aug 04 05:19:27 PM PDT 24
Finished Aug 04 05:19:32 PM PDT 24
Peak memory 216568 kb
Host smart-4632a5c8-a1fa-4e30-af60-4610f270fa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934563475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.934563475
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3580972786
Short name T529
Test name
Test status
Simulation time 3687835239 ps
CPU time 6.7 seconds
Started Aug 04 05:19:39 PM PDT 24
Finished Aug 04 05:19:46 PM PDT 24
Peak memory 216672 kb
Host smart-c24ee57d-8e72-4c51-980a-d4c3c860a838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580972786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3580972786
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3319559243
Short name T656
Test name
Test status
Simulation time 784399695 ps
CPU time 3.48 seconds
Started Aug 04 05:19:33 PM PDT 24
Finished Aug 04 05:19:37 PM PDT 24
Peak memory 216620 kb
Host smart-b639cd39-5ac6-4cd7-8ffb-68ad9c7bd88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319559243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3319559243
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3872183196
Short name T449
Test name
Test status
Simulation time 306781345 ps
CPU time 0.92 seconds
Started Aug 04 05:19:37 PM PDT 24
Finished Aug 04 05:19:38 PM PDT 24
Peak memory 207316 kb
Host smart-8a4b9309-e9a2-4449-9e3a-b7933cbfcd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872183196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3872183196
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.649082262
Short name T620
Test name
Test status
Simulation time 1318705065 ps
CPU time 5.11 seconds
Started Aug 04 05:19:46 PM PDT 24
Finished Aug 04 05:19:51 PM PDT 24
Peak memory 224172 kb
Host smart-bc907fd1-6b2d-436a-b627-f5585341f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649082262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.649082262
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1635512942
Short name T963
Test name
Test status
Simulation time 16521281 ps
CPU time 0.76 seconds
Started Aug 04 05:20:42 PM PDT 24
Finished Aug 04 05:20:43 PM PDT 24
Peak memory 205804 kb
Host smart-e919a1d2-a4ec-475b-ab9b-128f098e1836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635512942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1635512942
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1407549610
Short name T61
Test name
Test status
Simulation time 252272325 ps
CPU time 3.26 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:20:52 PM PDT 24
Peak memory 233080 kb
Host smart-807059f7-73cf-4313-b040-569d1f90576d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407549610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1407549610
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2303776109
Short name T810
Test name
Test status
Simulation time 21037509 ps
CPU time 0.77 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:20:49 PM PDT 24
Peak memory 207032 kb
Host smart-36f9d1e2-595a-4e12-9284-924205040915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303776109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2303776109
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2574054347
Short name T198
Test name
Test status
Simulation time 2293349074 ps
CPU time 32.26 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:21:22 PM PDT 24
Peak memory 249272 kb
Host smart-37fb99ae-670b-4380-9aa9-c18cd06a7119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574054347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2574054347
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.943056299
Short name T247
Test name
Test status
Simulation time 89583559240 ps
CPU time 561.39 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:30:02 PM PDT 24
Peak memory 257472 kb
Host smart-6265076c-281e-4464-bb72-7e49af84b834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943056299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.943056299
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3385173263
Short name T275
Test name
Test status
Simulation time 430929619885 ps
CPU time 620.67 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:31:08 PM PDT 24
Peak memory 256180 kb
Host smart-759a9221-690d-44e9-a045-2a95929e4ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385173263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3385173263
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3966846412
Short name T285
Test name
Test status
Simulation time 1049262586 ps
CPU time 12.28 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 249432 kb
Host smart-2a730ad6-7f9d-43a3-9f15-a86d66f9cccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966846412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3966846412
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.4017621380
Short name T606
Test name
Test status
Simulation time 1824781710 ps
CPU time 7.94 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:54 PM PDT 24
Peak memory 233096 kb
Host smart-faff301e-9682-4376-b14a-5bfc354ed5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017621380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.4017621380
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1473436137
Short name T953
Test name
Test status
Simulation time 6558235673 ps
CPU time 17.23 seconds
Started Aug 04 05:20:37 PM PDT 24
Finished Aug 04 05:20:54 PM PDT 24
Peak memory 233160 kb
Host smart-92873b60-1e9d-4d0c-bd12-115b8c14cabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473436137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1473436137
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3867612303
Short name T648
Test name
Test status
Simulation time 219373983 ps
CPU time 3.15 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 224964 kb
Host smart-e68b19ba-7dea-4541-99cf-db519c6b2103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867612303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3867612303
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.169492869
Short name T542
Test name
Test status
Simulation time 4768302783 ps
CPU time 17.47 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:21:02 PM PDT 24
Peak memory 233032 kb
Host smart-2dbb7443-590d-47d5-a8cc-4114e41b0e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169492869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.169492869
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.64769901
Short name T549
Test name
Test status
Simulation time 737894204 ps
CPU time 4.58 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:51 PM PDT 24
Peak memory 233132 kb
Host smart-e6cf3b2e-608e-4378-bf8e-82da75d87529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64769901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.64769901
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3315744691
Short name T143
Test name
Test status
Simulation time 2188994354 ps
CPU time 6.89 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:53 PM PDT 24
Peak memory 221996 kb
Host smart-f7c60b3a-6ae9-4b35-be96-ad61eee944de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3315744691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3315744691
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2108869930
Short name T17
Test name
Test status
Simulation time 61062955563 ps
CPU time 188.36 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:23:55 PM PDT 24
Peak memory 257380 kb
Host smart-27c0ad09-4c93-4d9d-a9d2-e83176b22a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108869930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2108869930
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1121622480
Short name T822
Test name
Test status
Simulation time 7843028092 ps
CPU time 20.63 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:21:04 PM PDT 24
Peak memory 216652 kb
Host smart-52b4ce05-7801-4740-aafe-a01615dad7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121622480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1121622480
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.918973096
Short name T683
Test name
Test status
Simulation time 1096700077 ps
CPU time 2.25 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 216612 kb
Host smart-1ec1604d-6301-483f-bf16-a8df3cd98c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918973096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.918973096
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.649115843
Short name T776
Test name
Test status
Simulation time 43557106 ps
CPU time 0.76 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 206352 kb
Host smart-6ecea9e9-6aaf-4816-b86f-de7975bad719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649115843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.649115843
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1047502502
Short name T631
Test name
Test status
Simulation time 84903919 ps
CPU time 0.79 seconds
Started Aug 04 05:20:37 PM PDT 24
Finished Aug 04 05:20:37 PM PDT 24
Peak memory 206276 kb
Host smart-6b95aadc-2717-455d-8ff9-25b0c4fad61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047502502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1047502502
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1417703625
Short name T600
Test name
Test status
Simulation time 30345019 ps
CPU time 2.46 seconds
Started Aug 04 05:20:37 PM PDT 24
Finished Aug 04 05:20:40 PM PDT 24
Peak memory 232828 kb
Host smart-704228c2-c04f-44dd-a6e1-6e5ac183fb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417703625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1417703625
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.211246693
Short name T658
Test name
Test status
Simulation time 96536833 ps
CPU time 0.74 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 205720 kb
Host smart-ea541536-d371-47e7-a14d-b2389d111991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211246693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.211246693
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2211988269
Short name T227
Test name
Test status
Simulation time 261127174 ps
CPU time 4.73 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:51 PM PDT 24
Peak memory 224880 kb
Host smart-3c8f30ed-9ea2-4f1d-af3c-85e20dbfc9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211988269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2211988269
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3995201446
Short name T343
Test name
Test status
Simulation time 44887976 ps
CPU time 0.79 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 206952 kb
Host smart-cf9b8bfa-9056-4727-b8a4-402af6496ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995201446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3995201446
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1294823008
Short name T823
Test name
Test status
Simulation time 6812822331 ps
CPU time 24.01 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:21:10 PM PDT 24
Peak memory 241344 kb
Host smart-732b1e6e-9cdf-4a91-bb36-78c4cd9cfa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294823008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1294823008
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3794126506
Short name T26
Test name
Test status
Simulation time 15249454700 ps
CPU time 170.7 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:23:36 PM PDT 24
Peak memory 249692 kb
Host smart-c53e97e3-bfb5-4195-9745-34e271da1a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794126506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3794126506
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.237701575
Short name T956
Test name
Test status
Simulation time 7862368187 ps
CPU time 65.69 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:21:54 PM PDT 24
Peak memory 224940 kb
Host smart-9a8eeb82-ac9d-4888-a115-6490cef3453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237701575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.237701575
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1624902305
Short name T816
Test name
Test status
Simulation time 41764537 ps
CPU time 3.1 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:49 PM PDT 24
Peak memory 233092 kb
Host smart-7e3f7fa2-07fb-4f50-b206-2887fed7306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624902305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1624902305
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3010591050
Short name T174
Test name
Test status
Simulation time 50129486711 ps
CPU time 103.66 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:22:28 PM PDT 24
Peak memory 249556 kb
Host smart-0da5cdba-c07d-4791-98f1-571da5528a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010591050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3010591050
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1099739872
Short name T586
Test name
Test status
Simulation time 8498690262 ps
CPU time 23.58 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:21:11 PM PDT 24
Peak memory 233220 kb
Host smart-1946eb16-90a0-49ee-a94a-559d1c4336f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099739872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1099739872
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2486479971
Short name T208
Test name
Test status
Simulation time 928541545 ps
CPU time 15.08 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:20:59 PM PDT 24
Peak memory 241124 kb
Host smart-c9643082-46a7-4b90-9abd-bdda5e1effc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486479971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2486479971
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1188239000
Short name T722
Test name
Test status
Simulation time 421315679 ps
CPU time 3.43 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 224836 kb
Host smart-01773b33-dd8d-477d-b988-f8428beacad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188239000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1188239000
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.841215369
Short name T640
Test name
Test status
Simulation time 48200166 ps
CPU time 2.59 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:49 PM PDT 24
Peak memory 233136 kb
Host smart-0f7bc5d4-acba-4823-8369-230a915f822e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841215369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.841215369
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1201065257
Short name T503
Test name
Test status
Simulation time 373185080 ps
CPU time 6.41 seconds
Started Aug 04 05:20:54 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 223484 kb
Host smart-c70beca1-e591-4f37-961a-9c61047c12fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1201065257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1201065257
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3371064929
Short name T156
Test name
Test status
Simulation time 210443928445 ps
CPU time 948.74 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:36:41 PM PDT 24
Peak memory 274192 kb
Host smart-a9f6565f-e7e8-46c4-8770-012474fb378b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371064929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3371064929
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2343999229
Short name T46
Test name
Test status
Simulation time 4073717531 ps
CPU time 30.07 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:21:18 PM PDT 24
Peak memory 216584 kb
Host smart-059580e2-a871-474a-a286-b3f2f95e7385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343999229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2343999229
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1165133896
Short name T923
Test name
Test status
Simulation time 24346528153 ps
CPU time 16.72 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:20:58 PM PDT 24
Peak memory 216716 kb
Host smart-4439570a-f24c-4cc8-8f52-6a33741ea32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165133896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1165133896
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1262069002
Short name T630
Test name
Test status
Simulation time 216615553 ps
CPU time 2.03 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:20:52 PM PDT 24
Peak memory 216652 kb
Host smart-35dd5430-8ed1-4bb3-b164-1c87f6a33922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262069002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1262069002
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.413413009
Short name T374
Test name
Test status
Simulation time 50134816 ps
CPU time 0.88 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 206296 kb
Host smart-ddd347e5-9483-49b2-8f92-7d331b7783d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413413009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.413413009
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2663367032
Short name T881
Test name
Test status
Simulation time 1011898667 ps
CPU time 4.42 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 224836 kb
Host smart-133ee414-d864-4783-a477-b204e08ccb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663367032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2663367032
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3479253996
Short name T527
Test name
Test status
Simulation time 13045830 ps
CPU time 0.73 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 205168 kb
Host smart-433d4ac8-986e-446e-a49b-0e27690b3801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479253996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3479253996
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3188349673
Short name T704
Test name
Test status
Simulation time 112396783 ps
CPU time 2.45 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 233052 kb
Host smart-cdfe6d98-3f61-4725-84b6-a5e3d91b971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188349673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3188349673
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.683491505
Short name T453
Test name
Test status
Simulation time 17226530 ps
CPU time 0.83 seconds
Started Aug 04 05:20:37 PM PDT 24
Finished Aug 04 05:20:38 PM PDT 24
Peak memory 206948 kb
Host smart-098becdc-a9c9-4e7b-a2ac-97e0ddc887fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683491505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.683491505
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1225661097
Short name T814
Test name
Test status
Simulation time 24062199776 ps
CPU time 112.49 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:22:37 PM PDT 24
Peak memory 263776 kb
Host smart-c37def92-e20d-4699-800c-af85fd2c15a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225661097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1225661097
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3554215042
Short name T613
Test name
Test status
Simulation time 21663820513 ps
CPU time 54.72 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:21:43 PM PDT 24
Peak memory 238916 kb
Host smart-8d064dba-7667-40e8-be4e-18dab394fb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554215042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3554215042
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2902857136
Short name T908
Test name
Test status
Simulation time 234163214388 ps
CPU time 241.81 seconds
Started Aug 04 05:20:55 PM PDT 24
Finished Aug 04 05:24:57 PM PDT 24
Peak memory 249476 kb
Host smart-58c70790-e8fc-4e4b-aeaf-c7be56f73871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902857136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2902857136
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.525732077
Short name T288
Test name
Test status
Simulation time 2911399762 ps
CPU time 6.26 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:20:54 PM PDT 24
Peak memory 233168 kb
Host smart-35561753-d4e4-406b-83a6-87b392e90727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525732077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.525732077
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1649142437
Short name T687
Test name
Test status
Simulation time 2911190608 ps
CPU time 51.15 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:21:35 PM PDT 24
Peak memory 256332 kb
Host smart-9e9c14d8-4e81-4c07-8c4b-a0b5275c14af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649142437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1649142437
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.91358536
Short name T505
Test name
Test status
Simulation time 1464829312 ps
CPU time 13.83 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:59 PM PDT 24
Peak memory 232992 kb
Host smart-e5f57619-b5ff-4ee7-ad84-f3847136cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91358536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.91358536
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3891783555
Short name T470
Test name
Test status
Simulation time 79469726846 ps
CPU time 72.76 seconds
Started Aug 04 05:20:54 PM PDT 24
Finished Aug 04 05:22:06 PM PDT 24
Peak memory 233232 kb
Host smart-6f474712-fd5f-440c-bb82-7d5ffa465471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891783555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3891783555
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1059044247
Short name T330
Test name
Test status
Simulation time 434184282 ps
CPU time 5.23 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:20:53 PM PDT 24
Peak memory 233128 kb
Host smart-16ad577f-25af-4daa-a507-6702de68c1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059044247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1059044247
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2182751542
Short name T235
Test name
Test status
Simulation time 3161213781 ps
CPU time 5.15 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:51 PM PDT 24
Peak memory 233160 kb
Host smart-13f14442-2826-4000-957c-6d170d59b0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182751542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2182751542
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2562012565
Short name T141
Test name
Test status
Simulation time 98193358 ps
CPU time 3.87 seconds
Started Aug 04 05:21:35 PM PDT 24
Finished Aug 04 05:21:39 PM PDT 24
Peak memory 219676 kb
Host smart-030031cb-a233-4762-ad90-92c76b1ca55f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2562012565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2562012565
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1158872541
Short name T840
Test name
Test status
Simulation time 129776939812 ps
CPU time 252.74 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:24:59 PM PDT 24
Peak memory 251484 kb
Host smart-65e853a1-7722-4829-acbb-1cf7daa03b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158872541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1158872541
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2420902385
Short name T456
Test name
Test status
Simulation time 785847123 ps
CPU time 3.31 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:20:53 PM PDT 24
Peak memory 216724 kb
Host smart-acc71441-3ab9-4ef6-b3d5-7522caedb88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420902385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2420902385
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.27471059
Short name T786
Test name
Test status
Simulation time 2707640774 ps
CPU time 6.07 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:20:54 PM PDT 24
Peak memory 216740 kb
Host smart-cb0341ea-360e-4f0d-ab51-3efcca2554ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27471059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.27471059
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2495815671
Short name T1006
Test name
Test status
Simulation time 1110727858 ps
CPU time 4.05 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 216572 kb
Host smart-5c80a705-d990-49ee-bb0f-85f65d6bad3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495815671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2495815671
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1703109885
Short name T567
Test name
Test status
Simulation time 66174083 ps
CPU time 0.88 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 206316 kb
Host smart-1636853c-98b9-4220-ae6e-e6a18cd1918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703109885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1703109885
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1425360319
Short name T608
Test name
Test status
Simulation time 2731353847 ps
CPU time 9.21 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:54 PM PDT 24
Peak memory 233240 kb
Host smart-7ceca48f-1284-4059-be68-7aa2c151c342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425360319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1425360319
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.162537470
Short name T988
Test name
Test status
Simulation time 12489343 ps
CPU time 0.72 seconds
Started Aug 04 05:20:58 PM PDT 24
Finished Aug 04 05:20:59 PM PDT 24
Peak memory 206184 kb
Host smart-81c5c8d4-1e01-4e7a-91ee-edf323140c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162537470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.162537470
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.576554948
Short name T968
Test name
Test status
Simulation time 10407067124 ps
CPU time 26.06 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:21:12 PM PDT 24
Peak memory 225032 kb
Host smart-9cc86268-8d62-4a0c-9d6c-60583caaf4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576554948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.576554948
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4164591102
Short name T314
Test name
Test status
Simulation time 18628892 ps
CPU time 0.73 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 205924 kb
Host smart-6e176e0c-8d8a-4e20-a31c-84d3305e4874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164591102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4164591102
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3341422229
Short name T187
Test name
Test status
Simulation time 23422404051 ps
CPU time 218.31 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:24:22 PM PDT 24
Peak memory 265352 kb
Host smart-87a9a74d-91c0-4f9e-bb60-01de92ae04e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341422229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3341422229
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3748795804
Short name T836
Test name
Test status
Simulation time 75889175379 ps
CPU time 388.89 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:27:16 PM PDT 24
Peak memory 264584 kb
Host smart-80f69eb2-1694-47aa-b7e2-76ea35e72db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748795804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3748795804
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1152638995
Short name T1000
Test name
Test status
Simulation time 891537678 ps
CPU time 3.37 seconds
Started Aug 04 05:20:53 PM PDT 24
Finished Aug 04 05:20:57 PM PDT 24
Peak memory 224968 kb
Host smart-b5d39c6d-760f-4a63-973a-c809da5e5d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152638995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1152638995
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3388270134
Short name T284
Test name
Test status
Simulation time 38459269683 ps
CPU time 135.43 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:23:02 PM PDT 24
Peak memory 255996 kb
Host smart-0ce962bf-83d0-4124-9fb6-a0e4e0c7a8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388270134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3388270134
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1999030858
Short name T375
Test name
Test status
Simulation time 178710092 ps
CPU time 3.41 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:49 PM PDT 24
Peak memory 224892 kb
Host smart-b915c024-354a-46af-ad1d-691ace4e2c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999030858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1999030858
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3789980269
Short name T450
Test name
Test status
Simulation time 43259609109 ps
CPU time 105.94 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:22:34 PM PDT 24
Peak memory 250684 kb
Host smart-5fd3e5cf-bef5-4254-9d85-2c2ca1fd5bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789980269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3789980269
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.939850701
Short name T973
Test name
Test status
Simulation time 1323175052 ps
CPU time 4.74 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 224788 kb
Host smart-93003935-26d3-4247-99f3-296a6957ffbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939850701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.939850701
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.841915851
Short name T644
Test name
Test status
Simulation time 2112571715 ps
CPU time 7.96 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:54 PM PDT 24
Peak memory 224752 kb
Host smart-e9de6412-63b2-4919-81a1-55fd5e6031ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841915851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.841915851
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2790351219
Short name T813
Test name
Test status
Simulation time 16372822668 ps
CPU time 17.2 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:21:05 PM PDT 24
Peak memory 223264 kb
Host smart-5da7883e-9822-4e85-bc3f-d9599e674a61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2790351219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2790351219
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.299783191
Short name T927
Test name
Test status
Simulation time 8833148928 ps
CPU time 83.73 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:22:08 PM PDT 24
Peak memory 266920 kb
Host smart-070e662d-0dae-461c-81ba-534c8568e161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299783191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.299783191
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3433648407
Short name T306
Test name
Test status
Simulation time 1004771058 ps
CPU time 5.75 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:20:54 PM PDT 24
Peak memory 216660 kb
Host smart-59888b4a-4dca-4156-a0c2-562152ef5196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433648407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3433648407
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.295619904
Short name T945
Test name
Test status
Simulation time 776891045 ps
CPU time 2.15 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 216712 kb
Host smart-76a0f800-d77f-469c-8c9b-444f8199bf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295619904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.295619904
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3276080271
Short name T801
Test name
Test status
Simulation time 73720618 ps
CPU time 1.18 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 208432 kb
Host smart-2bd682da-d2a0-4c3c-9889-729067858a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276080271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3276080271
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3961527909
Short name T965
Test name
Test status
Simulation time 44576051 ps
CPU time 0.9 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:20:45 PM PDT 24
Peak memory 206384 kb
Host smart-2d61066c-a4dd-4702-af46-ab9744af53cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961527909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3961527909
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3165559229
Short name T846
Test name
Test status
Simulation time 3491501745 ps
CPU time 11.77 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 233208 kb
Host smart-71ade79c-858d-4606-b339-7590e93b874f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165559229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3165559229
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.92505248
Short name T1003
Test name
Test status
Simulation time 20337133 ps
CPU time 0.71 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 205848 kb
Host smart-67dcea5e-079c-4cee-b9fc-da3518590de1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92505248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.92505248
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.25277519
Short name T616
Test name
Test status
Simulation time 717684055 ps
CPU time 4.17 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:20:45 PM PDT 24
Peak memory 233096 kb
Host smart-52cec1ca-a241-4974-9506-fcfb393efd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25277519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.25277519
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1132690903
Short name T539
Test name
Test status
Simulation time 19835998 ps
CPU time 0.79 seconds
Started Aug 04 05:20:53 PM PDT 24
Finished Aug 04 05:20:54 PM PDT 24
Peak memory 206908 kb
Host smart-b7e0188b-5b14-455d-ac65-d1d250456dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132690903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1132690903
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.698190373
Short name T581
Test name
Test status
Simulation time 4483999229 ps
CPU time 53.97 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:21:41 PM PDT 24
Peak memory 252076 kb
Host smart-1140c975-92fb-4609-bad3-ec70a84f4d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698190373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.698190373
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3556832648
Short name T304
Test name
Test status
Simulation time 3196776406 ps
CPU time 66.01 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:21:54 PM PDT 24
Peak memory 249612 kb
Host smart-d7315ce9-d20e-4397-8466-9a09a142124f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556832648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3556832648
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.641979606
Short name T750
Test name
Test status
Simulation time 36112604545 ps
CPU time 94.14 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:22:27 PM PDT 24
Peak memory 249552 kb
Host smart-b94eb015-ff81-4f94-8873-c8a1c9ed1b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641979606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.641979606
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2617278421
Short name T297
Test name
Test status
Simulation time 4041630828 ps
CPU time 5.7 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:52 PM PDT 24
Peak memory 224960 kb
Host smart-c4cc167d-74ef-448e-9f96-27320acfe45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617278421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2617278421
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1910048903
Short name T205
Test name
Test status
Simulation time 82714229481 ps
CPU time 291.11 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:25:36 PM PDT 24
Peak memory 271136 kb
Host smart-fb61a487-59e2-4d9a-9a58-5a6638b24bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910048903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1910048903
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4088204290
Short name T831
Test name
Test status
Simulation time 225773039 ps
CPU time 2.5 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 224708 kb
Host smart-002131c5-686c-42d2-bd0f-bdff7e507b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088204290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4088204290
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.61213651
Short name T589
Test name
Test status
Simulation time 2856835313 ps
CPU time 13.81 seconds
Started Aug 04 05:20:53 PM PDT 24
Finished Aug 04 05:21:07 PM PDT 24
Peak memory 231692 kb
Host smart-13d88d25-f74c-4280-9618-fd86678daeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61213651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.61213651
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3662902199
Short name T479
Test name
Test status
Simulation time 1145186388 ps
CPU time 3.45 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:20:51 PM PDT 24
Peak memory 224828 kb
Host smart-74ce24b7-e366-4794-9fef-0d17d11bfef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662902199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3662902199
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.233018465
Short name T660
Test name
Test status
Simulation time 5507581687 ps
CPU time 10.81 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:57 PM PDT 24
Peak memory 233144 kb
Host smart-485c6b76-87e3-4588-a264-aefb46b438c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233018465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.233018465
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.148543458
Short name T865
Test name
Test status
Simulation time 1089417984 ps
CPU time 5.06 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 220872 kb
Host smart-2a62feb7-05a7-449d-99ee-d86cf59ef24c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=148543458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.148543458
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1604059548
Short name T739
Test name
Test status
Simulation time 412436383 ps
CPU time 0.99 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:20:45 PM PDT 24
Peak memory 206980 kb
Host smart-e7ea5927-f737-48aa-bac0-b65181f38cff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604059548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1604059548
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2651382674
Short name T303
Test name
Test status
Simulation time 5053018321 ps
CPU time 36.9 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:21:24 PM PDT 24
Peak memory 216768 kb
Host smart-edd3e50f-cc11-488c-8389-513e3b1a34ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651382674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2651382674
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2330099802
Short name T344
Test name
Test status
Simulation time 125858198470 ps
CPU time 16.47 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 216840 kb
Host smart-c8ee715e-9544-411f-a84d-82093a8c0481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330099802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2330099802
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4038161228
Short name T994
Test name
Test status
Simulation time 106402501 ps
CPU time 1.17 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 207824 kb
Host smart-0b87075c-82c3-4ed0-b537-2330c8a0cb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038161228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4038161228
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1321863055
Short name T628
Test name
Test status
Simulation time 94656997 ps
CPU time 0.97 seconds
Started Aug 04 05:20:41 PM PDT 24
Finished Aug 04 05:20:42 PM PDT 24
Peak memory 206328 kb
Host smart-e42aecd6-b336-477e-ad9b-0f12965ccd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321863055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1321863055
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.625794043
Short name T734
Test name
Test status
Simulation time 1948230313 ps
CPU time 4.96 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:20:55 PM PDT 24
Peak memory 233012 kb
Host smart-fe9abde5-607c-4d9e-86f7-ca4b4e846b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625794043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.625794043
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1907025243
Short name T407
Test name
Test status
Simulation time 35256232 ps
CPU time 0.77 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 205136 kb
Host smart-c6baa796-f884-4fcc-b79b-8a23c6ffed94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907025243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1907025243
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2969046686
Short name T230
Test name
Test status
Simulation time 58661064 ps
CPU time 2.55 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:20:51 PM PDT 24
Peak memory 224908 kb
Host smart-acfab716-1f6c-4fe2-b2ee-795f93d297e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969046686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2969046686
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3037098667
Short name T397
Test name
Test status
Simulation time 27065119 ps
CPU time 0.75 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:47 PM PDT 24
Peak memory 205980 kb
Host smart-3f73d9f9-d002-43ba-8bb2-6ed254dbf61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037098667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3037098667
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2848472344
Short name T910
Test name
Test status
Simulation time 68623600280 ps
CPU time 189.29 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:23:56 PM PDT 24
Peak memory 249548 kb
Host smart-ed50af1a-9d95-42ad-a5d6-d06ca0e939e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848472344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2848472344
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1984140651
Short name T239
Test name
Test status
Simulation time 186604817142 ps
CPU time 403.79 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:27:37 PM PDT 24
Peak memory 251640 kb
Host smart-a3a528bc-db09-4baa-841f-481eff76ded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984140651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1984140651
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3371453521
Short name T514
Test name
Test status
Simulation time 82806251 ps
CPU time 3.68 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:20:53 PM PDT 24
Peak memory 233008 kb
Host smart-daed2ad7-3ace-4856-b4d4-70d53feba490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371453521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3371453521
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2730143244
Short name T674
Test name
Test status
Simulation time 30068286648 ps
CPU time 203.94 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:24:12 PM PDT 24
Peak memory 249540 kb
Host smart-d10910b4-25a1-4ba5-ad87-4b383764bb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730143244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2730143244
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1321501010
Short name T850
Test name
Test status
Simulation time 1339497903 ps
CPU time 6.84 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:20:57 PM PDT 24
Peak memory 233148 kb
Host smart-94a64624-b191-44c5-8536-6cad636fe998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321501010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1321501010
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1712761281
Short name T920
Test name
Test status
Simulation time 7174011625 ps
CPU time 49.16 seconds
Started Aug 04 05:20:39 PM PDT 24
Finished Aug 04 05:21:29 PM PDT 24
Peak memory 233060 kb
Host smart-0cebd54d-6fc1-4738-acd1-0a3cbf12dc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712761281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1712761281
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.710604655
Short name T261
Test name
Test status
Simulation time 320558138 ps
CPU time 4.87 seconds
Started Aug 04 05:20:43 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 224916 kb
Host smart-9d9b2236-b11f-4fbc-a5e3-7058f202c385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710604655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.710604655
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2681786187
Short name T893
Test name
Test status
Simulation time 2523924137 ps
CPU time 10.22 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:56 PM PDT 24
Peak memory 236552 kb
Host smart-bc21de5b-0e8b-4496-a8ad-5667c748068e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681786187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2681786187
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2402970026
Short name T139
Test name
Test status
Simulation time 1159132934 ps
CPU time 4.24 seconds
Started Aug 04 05:20:59 PM PDT 24
Finished Aug 04 05:21:03 PM PDT 24
Peak memory 220464 kb
Host smart-9ae2ffa6-6cdf-4cd8-bc14-a285b8a936f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2402970026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2402970026
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.732695282
Short name T925
Test name
Test status
Simulation time 32635840304 ps
CPU time 218.1 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:24:25 PM PDT 24
Peak memory 263172 kb
Host smart-0272fe34-8a16-488a-a2b9-b06b60b22807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732695282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.732695282
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4031414076
Short name T769
Test name
Test status
Simulation time 508937406 ps
CPU time 8.71 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:20:58 PM PDT 24
Peak memory 216696 kb
Host smart-0ebc6653-7287-44e5-b98b-cf2cb193e53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031414076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4031414076
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3639548153
Short name T957
Test name
Test status
Simulation time 20735093191 ps
CPU time 23.74 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:21:11 PM PDT 24
Peak memory 217040 kb
Host smart-a3a44fa3-17d9-46d7-8d9a-8be9de038c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639548153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3639548153
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.59092528
Short name T521
Test name
Test status
Simulation time 183157399 ps
CPU time 4.03 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:20:52 PM PDT 24
Peak memory 216604 kb
Host smart-1ffd789f-3a9b-44c6-a8cb-54f52291a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59092528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.59092528
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3496312733
Short name T566
Test name
Test status
Simulation time 77460203 ps
CPU time 0.88 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:20:50 PM PDT 24
Peak memory 206396 kb
Host smart-ee1cb3f1-7ae6-4734-9935-401d3132d075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496312733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3496312733
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3021226056
Short name T936
Test name
Test status
Simulation time 155837183 ps
CPU time 2.19 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:20:55 PM PDT 24
Peak memory 224840 kb
Host smart-721dddcc-f2e7-4c3e-9acf-740e0384ed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021226056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3021226056
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.529666976
Short name T64
Test name
Test status
Simulation time 55663523 ps
CPU time 0.72 seconds
Started Aug 04 05:20:53 PM PDT 24
Finished Aug 04 05:20:54 PM PDT 24
Peak memory 205752 kb
Host smart-ceac7ad6-81d8-465e-be6a-38ff552e8086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529666976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.529666976
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.744245604
Short name T264
Test name
Test status
Simulation time 93443896 ps
CPU time 3.19 seconds
Started Aug 04 05:20:58 PM PDT 24
Finished Aug 04 05:21:01 PM PDT 24
Peak memory 224896 kb
Host smart-38f922cb-5c58-425b-bd60-5b4f52ac761b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744245604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.744245604
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3433149818
Short name T972
Test name
Test status
Simulation time 26954955 ps
CPU time 0.74 seconds
Started Aug 04 05:20:44 PM PDT 24
Finished Aug 04 05:20:45 PM PDT 24
Peak memory 205876 kb
Host smart-1d63342e-b980-4484-9e48-fda5c08e61ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433149818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3433149818
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3039280419
Short name T250
Test name
Test status
Simulation time 3859694771 ps
CPU time 16.73 seconds
Started Aug 04 05:20:51 PM PDT 24
Finished Aug 04 05:21:08 PM PDT 24
Peak memory 235752 kb
Host smart-b2679d85-b756-4059-b60a-2618daef46dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039280419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3039280419
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.182523999
Short name T459
Test name
Test status
Simulation time 49029008599 ps
CPU time 219.35 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:24:26 PM PDT 24
Peak memory 265404 kb
Host smart-ce999610-a657-4aca-a190-43267b932ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182523999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.182523999
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1798154951
Short name T257
Test name
Test status
Simulation time 18303294034 ps
CPU time 243.63 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:24:54 PM PDT 24
Peak memory 251776 kb
Host smart-995e5e99-b82f-4c1c-8a92-8165cb9c03f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798154951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1798154951
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3052770245
Short name T212
Test name
Test status
Simulation time 53424651535 ps
CPU time 207.7 seconds
Started Aug 04 05:20:54 PM PDT 24
Finished Aug 04 05:24:22 PM PDT 24
Peak memory 254528 kb
Host smart-c9c82653-56a4-4608-800a-39a6ce4189c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052770245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3052770245
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2395982843
Short name T818
Test name
Test status
Simulation time 4613331109 ps
CPU time 11.64 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:21:01 PM PDT 24
Peak memory 224900 kb
Host smart-19465d88-7875-44fc-a8f7-4e33e29760bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395982843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2395982843
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4205222385
Short name T89
Test name
Test status
Simulation time 17098619525 ps
CPU time 44.97 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:21:36 PM PDT 24
Peak memory 233180 kb
Host smart-a4841422-7e27-4d3c-b85b-5ab4f98d3ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205222385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4205222385
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3911748581
Short name T404
Test name
Test status
Simulation time 3474176566 ps
CPU time 14.79 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:21:04 PM PDT 24
Peak memory 241372 kb
Host smart-0c38f1b4-5958-4480-b5ce-d8a576c34603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911748581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3911748581
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2946950993
Short name T256
Test name
Test status
Simulation time 16148983277 ps
CPU time 22.61 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:21:11 PM PDT 24
Peak memory 233088 kb
Host smart-3606775d-155d-4308-abc5-fef26e66f1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946950993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2946950993
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2622897427
Short name T754
Test name
Test status
Simulation time 80165227 ps
CPU time 3.52 seconds
Started Aug 04 05:20:57 PM PDT 24
Finished Aug 04 05:21:01 PM PDT 24
Peak memory 223592 kb
Host smart-27e6ce25-3197-4b62-9aba-7b00aa361161
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2622897427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2622897427
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3147188204
Short name T19
Test name
Test status
Simulation time 42459477 ps
CPU time 1.02 seconds
Started Aug 04 05:20:57 PM PDT 24
Finished Aug 04 05:20:58 PM PDT 24
Peak memory 207228 kb
Host smart-9e8e0849-7e9a-4cb6-83ce-72fe69776e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147188204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3147188204
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2056011294
Short name T670
Test name
Test status
Simulation time 843267738 ps
CPU time 13.34 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:21:04 PM PDT 24
Peak memory 216960 kb
Host smart-4825e031-294e-49b1-a12b-ad8e7516ae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056011294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2056011294
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3155953757
Short name T345
Test name
Test status
Simulation time 6422377226 ps
CPU time 11.68 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:21:04 PM PDT 24
Peak memory 216648 kb
Host smart-0b1277eb-31cd-4ed4-999e-a1076dccbc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155953757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3155953757
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2389015296
Short name T351
Test name
Test status
Simulation time 369413839 ps
CPU time 2.15 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:20:53 PM PDT 24
Peak memory 216680 kb
Host smart-4bdcc068-e097-492b-88bf-e2cd826d4cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389015296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2389015296
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1402224758
Short name T757
Test name
Test status
Simulation time 110278391 ps
CPU time 0.87 seconds
Started Aug 04 05:20:51 PM PDT 24
Finished Aug 04 05:20:52 PM PDT 24
Peak memory 206164 kb
Host smart-7b98c181-2dfa-46d6-a308-3dc00663d1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402224758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1402224758
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2030196370
Short name T236
Test name
Test status
Simulation time 346516197 ps
CPU time 2.81 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 224792 kb
Host smart-8f944522-ac1a-4b5f-a7a1-4f1ab88c0f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030196370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2030196370
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2554471647
Short name T418
Test name
Test status
Simulation time 35574953 ps
CPU time 0.72 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 205692 kb
Host smart-627207c0-6ab2-4b37-92c1-f9a703b765b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554471647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2554471647
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4171629189
Short name T607
Test name
Test status
Simulation time 2102627893 ps
CPU time 3.26 seconds
Started Aug 04 05:20:57 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 233048 kb
Host smart-40588a8f-6588-414f-848d-1de0ffedad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171629189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4171629189
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1707259572
Short name T372
Test name
Test status
Simulation time 81335670 ps
CPU time 0.75 seconds
Started Aug 04 05:21:00 PM PDT 24
Finished Aug 04 05:21:01 PM PDT 24
Peak memory 206172 kb
Host smart-358045f3-78a3-48c0-8358-d62fa59adb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707259572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1707259572
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.805435030
Short name T948
Test name
Test status
Simulation time 10044711867 ps
CPU time 71.17 seconds
Started Aug 04 05:20:53 PM PDT 24
Finished Aug 04 05:22:04 PM PDT 24
Peak memory 249444 kb
Host smart-4a113231-f067-49ba-9c35-8d629af2890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805435030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.805435030
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.612688284
Short name T805
Test name
Test status
Simulation time 14874044032 ps
CPU time 111.56 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:22:43 PM PDT 24
Peak memory 257160 kb
Host smart-4f991220-bde6-4fe6-8406-cd05f9d103c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612688284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.612688284
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2579296219
Short name T832
Test name
Test status
Simulation time 19916187770 ps
CPU time 153.38 seconds
Started Aug 04 05:20:51 PM PDT 24
Finished Aug 04 05:23:25 PM PDT 24
Peak memory 264384 kb
Host smart-d80d1338-f544-48ed-b6ca-1765297f8ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579296219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2579296219
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2625986106
Short name T921
Test name
Test status
Simulation time 591104390 ps
CPU time 12.56 seconds
Started Aug 04 05:20:59 PM PDT 24
Finished Aug 04 05:21:11 PM PDT 24
Peak memory 224908 kb
Host smart-0bda45e1-5c7b-4664-af36-ff5d6b591b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625986106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2625986106
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2061520982
Short name T855
Test name
Test status
Simulation time 4687034936 ps
CPU time 11.59 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:21:03 PM PDT 24
Peak memory 249612 kb
Host smart-090711e5-b9ca-4b24-bed7-60efefeda9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061520982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2061520982
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2781449684
Short name T234
Test name
Test status
Simulation time 229636827 ps
CPU time 5.24 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:20:55 PM PDT 24
Peak memory 224840 kb
Host smart-81de96a1-f518-4ee9-b96e-045d9fcef7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781449684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2781449684
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2330050279
Short name T1002
Test name
Test status
Simulation time 6837152607 ps
CPU time 45.28 seconds
Started Aug 04 05:20:55 PM PDT 24
Finished Aug 04 05:21:40 PM PDT 24
Peak memory 238764 kb
Host smart-7a549ccd-7673-4272-a130-40931e9d9efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330050279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2330050279
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3145536240
Short name T273
Test name
Test status
Simulation time 2768298131 ps
CPU time 6.01 seconds
Started Aug 04 05:20:54 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 233236 kb
Host smart-e3cb03cf-1a87-40aa-9d92-e2cc2f8b0a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145536240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3145536240
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1964238617
Short name T643
Test name
Test status
Simulation time 1971438046 ps
CPU time 5.9 seconds
Started Aug 04 05:20:54 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 225068 kb
Host smart-56491a00-81f5-47f7-8e02-1e13c402d792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964238617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1964238617
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2710167685
Short name T391
Test name
Test status
Simulation time 643933788 ps
CPU time 7.84 seconds
Started Aug 04 05:20:53 PM PDT 24
Finished Aug 04 05:21:01 PM PDT 24
Peak memory 220216 kb
Host smart-f54b57fa-3339-494f-bd46-eeca2726f464
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2710167685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2710167685
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3676892689
Short name T55
Test name
Test status
Simulation time 26223082461 ps
CPU time 216.38 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:24:28 PM PDT 24
Peak memory 251456 kb
Host smart-91d762c3-d86e-426d-8ebb-c49102d4404e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676892689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3676892689
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2136616854
Short name T654
Test name
Test status
Simulation time 12602416953 ps
CPU time 17.08 seconds
Started Aug 04 05:20:54 PM PDT 24
Finished Aug 04 05:21:11 PM PDT 24
Peak memory 216612 kb
Host smart-64fd10b2-6565-43e4-842c-3a3a9e018d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136616854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2136616854
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3808221874
Short name T317
Test name
Test status
Simulation time 4711426752 ps
CPU time 9.99 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:21:06 PM PDT 24
Peak memory 216512 kb
Host smart-9eff1d00-9c6e-4755-81f0-a0be7b58102f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808221874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3808221874
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2032896624
Short name T366
Test name
Test status
Simulation time 90420720 ps
CPU time 0.94 seconds
Started Aug 04 05:20:55 PM PDT 24
Finished Aug 04 05:20:56 PM PDT 24
Peak memory 206968 kb
Host smart-d7fecc9a-a140-4b1e-8650-4fe1841ef2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032896624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2032896624
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2098195507
Short name T570
Test name
Test status
Simulation time 68293727 ps
CPU time 0.93 seconds
Started Aug 04 05:20:57 PM PDT 24
Finished Aug 04 05:20:58 PM PDT 24
Peak memory 206384 kb
Host smart-36541d3b-063d-4007-9f79-05cd47bd5d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098195507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2098195507
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1899465846
Short name T394
Test name
Test status
Simulation time 74352784 ps
CPU time 2.27 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:20:58 PM PDT 24
Peak memory 232788 kb
Host smart-debc12f3-189d-472d-bc3b-cd66662fa389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899465846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1899465846
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.995954662
Short name T546
Test name
Test status
Simulation time 14368869 ps
CPU time 0.7 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:20:57 PM PDT 24
Peak memory 205824 kb
Host smart-bbf6dbc7-8e13-46cd-9ac5-62d1da94efa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995954662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.995954662
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2201147155
Short name T484
Test name
Test status
Simulation time 42659250 ps
CPU time 2.66 seconds
Started Aug 04 05:20:46 PM PDT 24
Finished Aug 04 05:20:49 PM PDT 24
Peak memory 233040 kb
Host smart-9d87c355-2466-4237-ab3f-a8c6c16d1358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201147155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2201147155
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3425928971
Short name T313
Test name
Test status
Simulation time 102419103 ps
CPU time 0.81 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:20:57 PM PDT 24
Peak memory 207004 kb
Host smart-fb102328-d78d-4d17-a8f9-99b3ed3c985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425928971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3425928971
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.116914873
Short name T75
Test name
Test status
Simulation time 124304717565 ps
CPU time 225.13 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:24:37 PM PDT 24
Peak memory 254156 kb
Host smart-d7a0d612-95b0-4ff8-96d4-4a83e299b951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116914873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.116914873
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3144631284
Short name T216
Test name
Test status
Simulation time 2778603739 ps
CPU time 65.19 seconds
Started Aug 04 05:20:53 PM PDT 24
Finished Aug 04 05:21:59 PM PDT 24
Peak memory 249652 kb
Host smart-e0a801d6-dc02-438b-a68f-6855b0aeddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144631284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3144631284
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.337428443
Short name T135
Test name
Test status
Simulation time 24408983188 ps
CPU time 57.16 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:21:54 PM PDT 24
Peak memory 249632 kb
Host smart-5b4b3f6d-ea52-4a2c-b21a-79468cee17b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337428443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.337428443
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3795826097
Short name T41
Test name
Test status
Simulation time 8738792578 ps
CPU time 123.15 seconds
Started Aug 04 05:20:53 PM PDT 24
Finished Aug 04 05:22:57 PM PDT 24
Peak memory 263432 kb
Host smart-967d6236-8658-4bb0-ba18-993fb0018f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795826097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3795826097
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2863984645
Short name T541
Test name
Test status
Simulation time 6917147912 ps
CPU time 17.62 seconds
Started Aug 04 05:20:51 PM PDT 24
Finished Aug 04 05:21:09 PM PDT 24
Peak memory 224856 kb
Host smart-0d2f51bf-25a9-45cd-86d1-5923f5db7015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863984645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2863984645
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3256209469
Short name T746
Test name
Test status
Simulation time 23245588470 ps
CPU time 53.51 seconds
Started Aug 04 05:20:47 PM PDT 24
Finished Aug 04 05:21:41 PM PDT 24
Peak memory 224920 kb
Host smart-d714b94a-e961-40de-b0a2-552090f69c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256209469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3256209469
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1668134872
Short name T748
Test name
Test status
Simulation time 15034431522 ps
CPU time 16.89 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:21:05 PM PDT 24
Peak memory 241276 kb
Host smart-25da449d-ed5f-47f1-ae48-f28432a362b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668134872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1668134872
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1534179575
Short name T711
Test name
Test status
Simulation time 7943589614 ps
CPU time 18.01 seconds
Started Aug 04 05:20:48 PM PDT 24
Finished Aug 04 05:21:06 PM PDT 24
Peak memory 233136 kb
Host smart-c17ee1cd-affd-4e4c-95c4-eaffa61d4f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534179575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1534179575
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.721823487
Short name T605
Test name
Test status
Simulation time 4077745148 ps
CPU time 12.08 seconds
Started Aug 04 05:20:54 PM PDT 24
Finished Aug 04 05:21:06 PM PDT 24
Peak memory 219240 kb
Host smart-aaf0f432-3324-4ef2-ba39-96e88204bfd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=721823487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.721823487
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1185669334
Short name T154
Test name
Test status
Simulation time 91342499911 ps
CPU time 154.11 seconds
Started Aug 04 05:20:55 PM PDT 24
Finished Aug 04 05:23:30 PM PDT 24
Peak memory 255256 kb
Host smart-a22b9d98-286a-4ea6-8e7a-805ee0a64d18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185669334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1185669334
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2381452539
Short name T655
Test name
Test status
Simulation time 10545967348 ps
CPU time 54.92 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:21:51 PM PDT 24
Peak memory 216780 kb
Host smart-b6890a5f-763d-4cf6-887f-ef32fbf9b3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381452539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2381452539
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2259385208
Short name T83
Test name
Test status
Simulation time 5732142036 ps
CPU time 9.93 seconds
Started Aug 04 05:20:50 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 216696 kb
Host smart-499451b7-980a-461c-8562-5ce006a315c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259385208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2259385208
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2175777427
Short name T723
Test name
Test status
Simulation time 96409896 ps
CPU time 1.33 seconds
Started Aug 04 05:20:49 PM PDT 24
Finished Aug 04 05:20:51 PM PDT 24
Peak memory 216652 kb
Host smart-699c0191-7abf-46d4-aee9-6dd882e67056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175777427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2175777427
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3409581522
Short name T11
Test name
Test status
Simulation time 117120433 ps
CPU time 0.88 seconds
Started Aug 04 05:20:45 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 207348 kb
Host smart-b5c574e7-d274-4648-a57d-774f8577bf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409581522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3409581522
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.266154584
Short name T664
Test name
Test status
Simulation time 939813462 ps
CPU time 4.41 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 241260 kb
Host smart-28fd6cbb-fddf-4958-8cc7-f067649b3bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266154584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.266154584
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1516388121
Short name T534
Test name
Test status
Simulation time 37077989 ps
CPU time 0.74 seconds
Started Aug 04 05:20:57 PM PDT 24
Finished Aug 04 05:20:58 PM PDT 24
Peak memory 206052 kb
Host smart-8715d255-fbc9-4312-bdce-fb7d8b94fd65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516388121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1516388121
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3863239008
Short name T548
Test name
Test status
Simulation time 3396222309 ps
CPU time 11.2 seconds
Started Aug 04 05:20:51 PM PDT 24
Finished Aug 04 05:21:03 PM PDT 24
Peak memory 224796 kb
Host smart-4a14bfbd-4a76-499e-94bc-4a07d4e05287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863239008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3863239008
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1970119938
Short name T800
Test name
Test status
Simulation time 20410755 ps
CPU time 0.8 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:20:56 PM PDT 24
Peak memory 207020 kb
Host smart-0a42a2ab-8eba-43c9-84c4-271fc9f666df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970119938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1970119938
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2575229032
Short name T184
Test name
Test status
Simulation time 15921857306 ps
CPU time 55.84 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:21:48 PM PDT 24
Peak memory 254292 kb
Host smart-b99fe847-69fa-4760-99da-7bb953becc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575229032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2575229032
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1801912201
Short name T770
Test name
Test status
Simulation time 3656303833 ps
CPU time 43.62 seconds
Started Aug 04 05:21:00 PM PDT 24
Finished Aug 04 05:21:43 PM PDT 24
Peak memory 237644 kb
Host smart-9d6c1aae-ee97-4b20-ad90-73e84a62ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801912201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1801912201
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.49360286
Short name T268
Test name
Test status
Simulation time 16975419977 ps
CPU time 124.95 seconds
Started Aug 04 05:20:58 PM PDT 24
Finished Aug 04 05:23:03 PM PDT 24
Peak memory 266932 kb
Host smart-e9406cdd-e6b0-447c-b56a-0ee9dcf5085c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49360286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.49360286
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1084112670
Short name T294
Test name
Test status
Simulation time 367304044 ps
CPU time 3.82 seconds
Started Aug 04 05:20:57 PM PDT 24
Finished Aug 04 05:21:01 PM PDT 24
Peak memory 224900 kb
Host smart-2d2c25eb-132e-447b-8d23-b76993b9f821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084112670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1084112670
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2741002111
Short name T488
Test name
Test status
Simulation time 24762508332 ps
CPU time 85.83 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:22:22 PM PDT 24
Peak memory 256676 kb
Host smart-1e8b9ad8-8001-4935-b21e-4921fd8abcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741002111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2741002111
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3704129256
Short name T86
Test name
Test status
Simulation time 238063549 ps
CPU time 5.09 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:21:02 PM PDT 24
Peak memory 233068 kb
Host smart-ae12bd20-9cdb-407d-b7b7-36f85dd7328c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704129256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3704129256
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1196343580
Short name T915
Test name
Test status
Simulation time 2082464511 ps
CPU time 28.38 seconds
Started Aug 04 05:20:57 PM PDT 24
Finished Aug 04 05:21:25 PM PDT 24
Peak memory 250284 kb
Host smart-f9cf7040-199d-4e91-96e1-220f545f5a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196343580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1196343580
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3965588037
Short name T476
Test name
Test status
Simulation time 49098643392 ps
CPU time 31.23 seconds
Started Aug 04 05:20:54 PM PDT 24
Finished Aug 04 05:21:26 PM PDT 24
Peak memory 233152 kb
Host smart-923c534c-2c7b-44b6-a61e-b78075c2df83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965588037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3965588037
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.931646155
Short name T653
Test name
Test status
Simulation time 10245728731 ps
CPU time 13.49 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:21:09 PM PDT 24
Peak memory 233084 kb
Host smart-6e5ec3a9-3bd2-492b-bd03-22775b9f674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931646155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.931646155
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1023881856
Short name T717
Test name
Test status
Simulation time 2015279637 ps
CPU time 17.17 seconds
Started Aug 04 05:20:57 PM PDT 24
Finished Aug 04 05:21:14 PM PDT 24
Peak memory 222544 kb
Host smart-79090bba-5a16-451a-b272-2fa574c23f40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1023881856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1023881856
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.362965833
Short name T130
Test name
Test status
Simulation time 15168413933 ps
CPU time 65.34 seconds
Started Aug 04 05:20:58 PM PDT 24
Finished Aug 04 05:22:03 PM PDT 24
Peak memory 249608 kb
Host smart-6f64c755-0e2d-4e1d-b92a-1ac067055c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362965833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.362965833
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.164896546
Short name T402
Test name
Test status
Simulation time 12233589650 ps
CPU time 37.1 seconds
Started Aug 04 05:20:52 PM PDT 24
Finished Aug 04 05:21:30 PM PDT 24
Peak memory 216628 kb
Host smart-81a0ee1f-e509-4967-800e-b2127e426c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164896546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.164896546
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4130434899
Short name T891
Test name
Test status
Simulation time 5715652726 ps
CPU time 2.39 seconds
Started Aug 04 05:20:58 PM PDT 24
Finished Aug 04 05:21:00 PM PDT 24
Peak memory 208276 kb
Host smart-249e3947-411b-40d6-97a2-32168d479f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130434899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4130434899
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3439773583
Short name T23
Test name
Test status
Simulation time 159816322 ps
CPU time 3.25 seconds
Started Aug 04 05:20:53 PM PDT 24
Finished Aug 04 05:20:56 PM PDT 24
Peak memory 216592 kb
Host smart-e60f1f3d-4a5d-4b35-899a-3ec77eb9af99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439773583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3439773583
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1668691631
Short name T591
Test name
Test status
Simulation time 48261226 ps
CPU time 0.82 seconds
Started Aug 04 05:20:55 PM PDT 24
Finished Aug 04 05:20:56 PM PDT 24
Peak memory 206556 kb
Host smart-16fd1ae5-4bab-499c-83e8-6cbdc4d6d500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668691631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1668691631
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2042871122
Short name T509
Test name
Test status
Simulation time 1289319497 ps
CPU time 3.36 seconds
Started Aug 04 05:20:53 PM PDT 24
Finished Aug 04 05:20:57 PM PDT 24
Peak memory 233184 kb
Host smart-5eda18cd-b2ed-4ee7-937c-2f2d632a2b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042871122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2042871122
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1280848365
Short name T376
Test name
Test status
Simulation time 11266507 ps
CPU time 0.68 seconds
Started Aug 04 05:19:39 PM PDT 24
Finished Aug 04 05:19:40 PM PDT 24
Peak memory 205164 kb
Host smart-9cdfb49c-a1a1-4bb0-8558-58937a9489ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280848365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
280848365
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1647372487
Short name T533
Test name
Test status
Simulation time 1666802917 ps
CPU time 8.1 seconds
Started Aug 04 05:19:48 PM PDT 24
Finished Aug 04 05:19:57 PM PDT 24
Peak memory 224956 kb
Host smart-ef6e33a3-2685-44b6-8c2c-b76c89a69b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647372487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1647372487
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1231828404
Short name T440
Test name
Test status
Simulation time 55434893 ps
CPU time 0.75 seconds
Started Aug 04 05:19:39 PM PDT 24
Finished Aug 04 05:19:40 PM PDT 24
Peak memory 205856 kb
Host smart-808fdd3b-bb8f-49de-90c1-699964c34545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231828404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1231828404
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1113925009
Short name T829
Test name
Test status
Simulation time 452877144280 ps
CPU time 305.17 seconds
Started Aug 04 05:19:38 PM PDT 24
Finished Aug 04 05:24:43 PM PDT 24
Peak memory 249440 kb
Host smart-afe1e0ef-d71b-4928-96d2-3275674f19ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113925009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1113925009
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2617722980
Short name T447
Test name
Test status
Simulation time 1285047716 ps
CPU time 32.63 seconds
Started Aug 04 05:19:31 PM PDT 24
Finished Aug 04 05:20:03 PM PDT 24
Peak memory 249452 kb
Host smart-e67da8de-1a58-4610-8b0b-ad07a292334e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617722980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2617722980
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3547050101
Short name T517
Test name
Test status
Simulation time 12223913103 ps
CPU time 111.68 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:21:42 PM PDT 24
Peak memory 249604 kb
Host smart-df27f6f3-b418-4723-a747-17a3e927c034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547050101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3547050101
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2925517284
Short name T292
Test name
Test status
Simulation time 1130587778 ps
CPU time 16 seconds
Started Aug 04 05:19:36 PM PDT 24
Finished Aug 04 05:19:52 PM PDT 24
Peak memory 241304 kb
Host smart-dafab9f2-e6f0-4965-bfa3-0d81cbeaad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925517284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2925517284
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2468432548
Short name T382
Test name
Test status
Simulation time 1137887334 ps
CPU time 9.73 seconds
Started Aug 04 05:19:38 PM PDT 24
Finished Aug 04 05:19:48 PM PDT 24
Peak memory 240552 kb
Host smart-4d8bcee7-8761-436f-889d-4722d6615108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468432548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2468432548
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3647490049
Short name T982
Test name
Test status
Simulation time 1352744371 ps
CPU time 6.55 seconds
Started Aug 04 05:19:34 PM PDT 24
Finished Aug 04 05:19:41 PM PDT 24
Peak memory 228296 kb
Host smart-3b661a46-af20-40f6-8fa0-c2d1a7572689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647490049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3647490049
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1025067603
Short name T765
Test name
Test status
Simulation time 4128982107 ps
CPU time 57.35 seconds
Started Aug 04 05:19:42 PM PDT 24
Finished Aug 04 05:20:39 PM PDT 24
Peak memory 233212 kb
Host smart-76fbe4b9-92c5-4cfc-b5cc-cb14da042861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025067603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1025067603
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.635272280
Short name T207
Test name
Test status
Simulation time 33733638462 ps
CPU time 15.62 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:20:07 PM PDT 24
Peak memory 233212 kb
Host smart-07d5b494-5002-4b56-b757-bdfdbf3ce937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635272280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
635272280
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.467102112
Short name T798
Test name
Test status
Simulation time 17858813501 ps
CPU time 48.51 seconds
Started Aug 04 05:19:36 PM PDT 24
Finished Aug 04 05:20:25 PM PDT 24
Peak memory 253988 kb
Host smart-300a1328-3514-45ea-840b-b975402bebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467102112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.467102112
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1941013333
Short name T458
Test name
Test status
Simulation time 1066376871 ps
CPU time 13.08 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:20:03 PM PDT 24
Peak memory 222232 kb
Host smart-aff4a0cb-0f7c-4f93-a722-adf80c0c9178
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1941013333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1941013333
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.273497528
Short name T72
Test name
Test status
Simulation time 71323958 ps
CPU time 1.08 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:51 PM PDT 24
Peak memory 236376 kb
Host smart-e0343ccf-0b9d-494f-9e50-794d39db60af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273497528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.273497528
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2192776682
Short name T272
Test name
Test status
Simulation time 22583076650 ps
CPU time 209.75 seconds
Started Aug 04 05:19:43 PM PDT 24
Finished Aug 04 05:23:13 PM PDT 24
Peak memory 268960 kb
Host smart-197d7707-54f9-481c-9c2e-80cb214770ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192776682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2192776682
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.75996058
Short name T902
Test name
Test status
Simulation time 332768955 ps
CPU time 2.53 seconds
Started Aug 04 05:19:35 PM PDT 24
Finished Aug 04 05:19:38 PM PDT 24
Peak memory 216532 kb
Host smart-62e1333f-bf72-4e28-9e19-1a5df54429b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75996058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.75996058
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2726420404
Short name T649
Test name
Test status
Simulation time 815549685 ps
CPU time 2.79 seconds
Started Aug 04 05:19:38 PM PDT 24
Finished Aug 04 05:19:41 PM PDT 24
Peak memory 208148 kb
Host smart-282974f0-9e55-4771-b0a6-710545e14bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726420404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2726420404
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1748958390
Short name T938
Test name
Test status
Simulation time 1517398473 ps
CPU time 7.58 seconds
Started Aug 04 05:19:34 PM PDT 24
Finished Aug 04 05:19:42 PM PDT 24
Peak memory 216696 kb
Host smart-c02cbc95-77e0-48d2-9054-0042cf261e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748958390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1748958390
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2733978066
Short name T970
Test name
Test status
Simulation time 29897053 ps
CPU time 0.78 seconds
Started Aug 04 05:19:34 PM PDT 24
Finished Aug 04 05:19:35 PM PDT 24
Peak memory 206220 kb
Host smart-b2d13cd9-8fea-4954-88de-65c9c208f3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733978066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2733978066
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2952626631
Short name T319
Test name
Test status
Simulation time 41447659 ps
CPU time 2.48 seconds
Started Aug 04 05:19:43 PM PDT 24
Finished Aug 04 05:19:45 PM PDT 24
Peak memory 232832 kb
Host smart-d95afecb-1de8-47e5-bc67-4bfa172e736f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952626631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2952626631
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2131725362
Short name T427
Test name
Test status
Simulation time 11935710 ps
CPU time 0.74 seconds
Started Aug 04 05:21:04 PM PDT 24
Finished Aug 04 05:21:05 PM PDT 24
Peak memory 205764 kb
Host smart-119cc9ed-0593-481a-8715-7b27fc8d77c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131725362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2131725362
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.567619981
Short name T899
Test name
Test status
Simulation time 1836838340 ps
CPU time 10.91 seconds
Started Aug 04 05:20:59 PM PDT 24
Finished Aug 04 05:21:10 PM PDT 24
Peak memory 233052 kb
Host smart-74b090f7-2180-4e87-8592-1af1ea627816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567619981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.567619981
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.566627471
Short name T334
Test name
Test status
Simulation time 48423306 ps
CPU time 0.74 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:20:57 PM PDT 24
Peak memory 205964 kb
Host smart-03b17c4b-b2d4-4065-a956-54f987616630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566627471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.566627471
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.508627164
Short name T473
Test name
Test status
Simulation time 14998729406 ps
CPU time 66.95 seconds
Started Aug 04 05:20:59 PM PDT 24
Finished Aug 04 05:22:06 PM PDT 24
Peak memory 255572 kb
Host smart-6cf2c17f-141b-4a4d-88ef-317ca1ca25ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508627164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.508627164
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1584969753
Short name T248
Test name
Test status
Simulation time 223897160378 ps
CPU time 398.74 seconds
Started Aug 04 05:21:02 PM PDT 24
Finished Aug 04 05:27:40 PM PDT 24
Peak memory 252708 kb
Host smart-e49ee1d7-6866-4715-b9d5-c42f5b0bfa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584969753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1584969753
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3060650250
Short name T672
Test name
Test status
Simulation time 15976316650 ps
CPU time 43.75 seconds
Started Aug 04 05:21:02 PM PDT 24
Finished Aug 04 05:21:46 PM PDT 24
Peak memory 234240 kb
Host smart-33d1b404-d6cd-49ab-b813-921535498a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060650250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3060650250
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2369084273
Short name T350
Test name
Test status
Simulation time 65012269 ps
CPU time 2.88 seconds
Started Aug 04 05:21:00 PM PDT 24
Finished Aug 04 05:21:03 PM PDT 24
Peak memory 232956 kb
Host smart-24d798d8-7a14-4033-98a7-b6664b9e945e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369084273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2369084273
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.954609891
Short name T280
Test name
Test status
Simulation time 79672268055 ps
CPU time 314.37 seconds
Started Aug 04 05:20:58 PM PDT 24
Finished Aug 04 05:26:13 PM PDT 24
Peak memory 252272 kb
Host smart-6fe2c20e-1c31-4260-baac-cbfa80c084ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954609891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.954609891
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1032767728
Short name T477
Test name
Test status
Simulation time 463402611 ps
CPU time 3.07 seconds
Started Aug 04 05:21:04 PM PDT 24
Finished Aug 04 05:21:08 PM PDT 24
Peak memory 224804 kb
Host smart-3ffd9d3d-95d7-4d30-9151-8de968a6de18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032767728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1032767728
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1348745139
Short name T732
Test name
Test status
Simulation time 3451355058 ps
CPU time 46.77 seconds
Started Aug 04 05:21:03 PM PDT 24
Finished Aug 04 05:21:50 PM PDT 24
Peak memory 225180 kb
Host smart-fca1fe6d-96c3-4d20-9fd6-1f736c392430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348745139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1348745139
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2618546942
Short name T277
Test name
Test status
Simulation time 386392244 ps
CPU time 7.7 seconds
Started Aug 04 05:20:59 PM PDT 24
Finished Aug 04 05:21:07 PM PDT 24
Peak memory 238260 kb
Host smart-49a9a510-181b-4468-adbf-46a8c3d4600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618546942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2618546942
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3792952606
Short name T887
Test name
Test status
Simulation time 798795067 ps
CPU time 7.65 seconds
Started Aug 04 05:21:04 PM PDT 24
Finished Aug 04 05:21:12 PM PDT 24
Peak memory 224828 kb
Host smart-5639018f-82d9-4283-940e-d40414e2aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792952606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3792952606
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2097484367
Short name T868
Test name
Test status
Simulation time 991551693 ps
CPU time 12.01 seconds
Started Aug 04 05:21:00 PM PDT 24
Finished Aug 04 05:21:13 PM PDT 24
Peak memory 220508 kb
Host smart-2f71062d-17fd-42a8-af36-cbfd334cceec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2097484367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2097484367
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4069160090
Short name T480
Test name
Test status
Simulation time 33116701904 ps
CPU time 15.42 seconds
Started Aug 04 05:21:04 PM PDT 24
Finished Aug 04 05:21:19 PM PDT 24
Peak memory 225012 kb
Host smart-38b2597b-4713-47a1-9038-2c9b8395a633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069160090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4069160090
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1758702502
Short name T446
Test name
Test status
Simulation time 799951015 ps
CPU time 11.7 seconds
Started Aug 04 05:20:55 PM PDT 24
Finished Aug 04 05:21:07 PM PDT 24
Peak memory 216592 kb
Host smart-b714e740-96da-478d-8dec-ffa86f4d6202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758702502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1758702502
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4281614690
Short name T329
Test name
Test status
Simulation time 9435305905 ps
CPU time 3.9 seconds
Started Aug 04 05:21:00 PM PDT 24
Finished Aug 04 05:21:04 PM PDT 24
Peak memory 216732 kb
Host smart-c172b03d-c31d-4202-a9d5-7add74f85a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281614690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4281614690
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.381831238
Short name T712
Test name
Test status
Simulation time 14100051 ps
CPU time 0.86 seconds
Started Aug 04 05:20:56 PM PDT 24
Finished Aug 04 05:20:57 PM PDT 24
Peak memory 206960 kb
Host smart-ec1580f0-3fd7-4e9f-9134-6f13b99bb481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381831238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.381831238
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3532823903
Short name T371
Test name
Test status
Simulation time 39191028 ps
CPU time 0.71 seconds
Started Aug 04 05:20:57 PM PDT 24
Finished Aug 04 05:20:58 PM PDT 24
Peak memory 206000 kb
Host smart-cb86a884-9ac1-4742-8e6d-ea1b1de62c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532823903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3532823903
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.4247089614
Short name T824
Test name
Test status
Simulation time 3985309939 ps
CPU time 6.43 seconds
Started Aug 04 05:21:00 PM PDT 24
Finished Aug 04 05:21:07 PM PDT 24
Peak memory 224956 kb
Host smart-7f3be6d4-d228-4009-8212-accbbb160ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247089614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.4247089614
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.810019771
Short name T571
Test name
Test status
Simulation time 28141915 ps
CPU time 0.69 seconds
Started Aug 04 05:21:14 PM PDT 24
Finished Aug 04 05:21:15 PM PDT 24
Peak memory 205852 kb
Host smart-93bce3cd-7a11-4da4-9dc9-5eaca45866e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810019771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.810019771
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.738202108
Short name T622
Test name
Test status
Simulation time 83976936 ps
CPU time 2.49 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:21:28 PM PDT 24
Peak memory 233148 kb
Host smart-efab9bc8-7846-4b23-ad9b-208ad6ee38cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738202108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.738202108
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3168997618
Short name T837
Test name
Test status
Simulation time 28127275 ps
CPU time 0.78 seconds
Started Aug 04 05:21:07 PM PDT 24
Finished Aug 04 05:21:07 PM PDT 24
Peak memory 207156 kb
Host smart-2deab83c-b35e-4221-9693-3962ec3abd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168997618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3168997618
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.612384465
Short name T347
Test name
Test status
Simulation time 744181513 ps
CPU time 13.24 seconds
Started Aug 04 05:21:15 PM PDT 24
Finished Aug 04 05:21:29 PM PDT 24
Peak memory 237588 kb
Host smart-37e4c8ad-b7f6-42c7-b89e-d7b5754de693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612384465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.612384465
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2072753262
Short name T8
Test name
Test status
Simulation time 31733037665 ps
CPU time 85.07 seconds
Started Aug 04 05:21:30 PM PDT 24
Finished Aug 04 05:22:55 PM PDT 24
Peak memory 233144 kb
Host smart-802b50f2-16ca-4ced-be2d-4de6f8614701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072753262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2072753262
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3933654369
Short name T703
Test name
Test status
Simulation time 4281234904 ps
CPU time 100.66 seconds
Started Aug 04 05:21:12 PM PDT 24
Finished Aug 04 05:22:53 PM PDT 24
Peak memory 265932 kb
Host smart-273e9d01-bd5c-410d-a6b3-8de33d851834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933654369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3933654369
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.4128095349
Short name T289
Test name
Test status
Simulation time 11444477248 ps
CPU time 152.55 seconds
Started Aug 04 05:21:15 PM PDT 24
Finished Aug 04 05:23:47 PM PDT 24
Peak memory 240848 kb
Host smart-961e6577-90cd-4d7f-aaa2-8e4bf0097815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128095349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4128095349
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3657034131
Short name T872
Test name
Test status
Simulation time 11649953836 ps
CPU time 50.8 seconds
Started Aug 04 05:21:24 PM PDT 24
Finished Aug 04 05:22:15 PM PDT 24
Peak memory 249492 kb
Host smart-4802553e-e208-4863-8880-bd63b1f6eb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657034131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3657034131
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3988874429
Short name T587
Test name
Test status
Simulation time 393990743 ps
CPU time 2.12 seconds
Started Aug 04 05:21:19 PM PDT 24
Finished Aug 04 05:21:21 PM PDT 24
Peak memory 224256 kb
Host smart-fc89c555-2d64-4f53-a41b-0e3559fd6c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988874429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3988874429
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3123477467
Short name T1
Test name
Test status
Simulation time 706417152 ps
CPU time 9.68 seconds
Started Aug 04 05:21:18 PM PDT 24
Finished Aug 04 05:21:28 PM PDT 24
Peak memory 233136 kb
Host smart-48500102-2fdc-4b47-8eca-196bb00a886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123477467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3123477467
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3008658262
Short name T866
Test name
Test status
Simulation time 3124540507 ps
CPU time 11.83 seconds
Started Aug 04 05:21:12 PM PDT 24
Finished Aug 04 05:21:24 PM PDT 24
Peak memory 234212 kb
Host smart-c467fe6a-c09c-42af-bf0d-86db42e0471e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008658262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3008658262
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2214875912
Short name T737
Test name
Test status
Simulation time 78001368760 ps
CPU time 20.89 seconds
Started Aug 04 05:21:13 PM PDT 24
Finished Aug 04 05:21:34 PM PDT 24
Peak memory 233088 kb
Host smart-3bd7f107-2f45-4d4a-93f7-0fc26aa04928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214875912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2214875912
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.861596838
Short name T593
Test name
Test status
Simulation time 180117487 ps
CPU time 4.39 seconds
Started Aug 04 05:21:29 PM PDT 24
Finished Aug 04 05:21:33 PM PDT 24
Peak memory 224376 kb
Host smart-82928994-736b-4f56-88c9-203f393a4671
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=861596838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.861596838
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1773206089
Short name T774
Test name
Test status
Simulation time 5528589736 ps
CPU time 95.08 seconds
Started Aug 04 05:21:21 PM PDT 24
Finished Aug 04 05:22:56 PM PDT 24
Peak memory 254672 kb
Host smart-51badb50-e7e4-429a-85a4-6654e904dd69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773206089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1773206089
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1561015951
Short name T713
Test name
Test status
Simulation time 3705421511 ps
CPU time 29.76 seconds
Started Aug 04 05:21:02 PM PDT 24
Finished Aug 04 05:21:32 PM PDT 24
Peak memory 216728 kb
Host smart-085942a6-e956-45b3-bdf8-1bae9baf158f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561015951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1561015951
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1597730719
Short name T396
Test name
Test status
Simulation time 1634412756 ps
CPU time 8.34 seconds
Started Aug 04 05:20:59 PM PDT 24
Finished Aug 04 05:21:07 PM PDT 24
Peak memory 216580 kb
Host smart-eec7d79b-c0f4-4357-9b47-a0d6c6c1d6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597730719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1597730719
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3271981553
Short name T873
Test name
Test status
Simulation time 85181777 ps
CPU time 1.1 seconds
Started Aug 04 05:21:02 PM PDT 24
Finished Aug 04 05:21:03 PM PDT 24
Peak memory 208416 kb
Host smart-73b27f97-3afe-47de-b6b6-d6ddfd5e765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271981553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3271981553
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3569153387
Short name T673
Test name
Test status
Simulation time 45854414 ps
CPU time 0.83 seconds
Started Aug 04 05:21:01 PM PDT 24
Finished Aug 04 05:21:02 PM PDT 24
Peak memory 206372 kb
Host smart-68994847-407a-4883-9da1-f5e9fa3eed41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569153387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3569153387
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.411534824
Short name T331
Test name
Test status
Simulation time 2272314227 ps
CPU time 10.56 seconds
Started Aug 04 05:21:13 PM PDT 24
Finished Aug 04 05:21:24 PM PDT 24
Peak memory 233124 kb
Host smart-e13d33ce-8a6b-4fbe-9cb6-74b92de416ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411534824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.411534824
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2310077358
Short name T826
Test name
Test status
Simulation time 11713247 ps
CPU time 0.74 seconds
Started Aug 04 05:21:35 PM PDT 24
Finished Aug 04 05:21:35 PM PDT 24
Peak memory 205856 kb
Host smart-84be6df9-7ec5-4ceb-9acd-e0bcac5aa0a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310077358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2310077358
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1233650959
Short name T906
Test name
Test status
Simulation time 697179247 ps
CPU time 4.2 seconds
Started Aug 04 05:21:30 PM PDT 24
Finished Aug 04 05:21:35 PM PDT 24
Peak memory 233152 kb
Host smart-650dfb92-55b2-41cd-a0c6-37143bb4fd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233650959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1233650959
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3515609200
Short name T438
Test name
Test status
Simulation time 14836080 ps
CPU time 0.79 seconds
Started Aug 04 05:21:20 PM PDT 24
Finished Aug 04 05:21:21 PM PDT 24
Peak memory 207016 kb
Host smart-b72d1cfd-3ce8-45b7-a34a-0d54573dcfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515609200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3515609200
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3341008001
Short name T892
Test name
Test status
Simulation time 4686406410 ps
CPU time 31.14 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:21:56 PM PDT 24
Peak memory 249552 kb
Host smart-8b38b50a-1b5f-4ef4-b02c-1c0f4aacacae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341008001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3341008001
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.237440205
Short name T455
Test name
Test status
Simulation time 47866417606 ps
CPU time 284.59 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:26:09 PM PDT 24
Peak memory 256416 kb
Host smart-2aad4c03-1bf8-4111-abac-a2031d9c6a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237440205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.237440205
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1480805989
Short name T43
Test name
Test status
Simulation time 2030419103 ps
CPU time 44.26 seconds
Started Aug 04 05:21:26 PM PDT 24
Finished Aug 04 05:22:10 PM PDT 24
Peak memory 249548 kb
Host smart-c65de24b-9689-4b0e-9b3c-8f3b4dfbf815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480805989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1480805989
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.210146973
Short name T749
Test name
Test status
Simulation time 1918483412 ps
CPU time 31.36 seconds
Started Aug 04 05:21:36 PM PDT 24
Finished Aug 04 05:22:08 PM PDT 24
Peak memory 224908 kb
Host smart-c02b6450-95cc-464e-9568-6225f2073601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210146973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.210146973
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2924253578
Short name T825
Test name
Test status
Simulation time 4906509629 ps
CPU time 68.36 seconds
Started Aug 04 05:21:13 PM PDT 24
Finished Aug 04 05:22:22 PM PDT 24
Peak memory 257696 kb
Host smart-f4775d17-7afc-4a9a-8bab-c7ed4db729aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924253578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2924253578
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1946227626
Short name T560
Test name
Test status
Simulation time 3991681581 ps
CPU time 15.82 seconds
Started Aug 04 05:21:15 PM PDT 24
Finished Aug 04 05:21:31 PM PDT 24
Peak memory 233160 kb
Host smart-e5250df1-a707-4df6-9932-9c45b3a4e059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946227626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1946227626
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.327248150
Short name T523
Test name
Test status
Simulation time 5009291397 ps
CPU time 45.45 seconds
Started Aug 04 05:21:16 PM PDT 24
Finished Aug 04 05:22:01 PM PDT 24
Peak memory 224616 kb
Host smart-9277be8a-ab6e-44bf-be0f-77ef68b5c882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327248150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.327248150
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.35991905
Short name T861
Test name
Test status
Simulation time 4735741175 ps
CPU time 13.18 seconds
Started Aug 04 05:21:16 PM PDT 24
Finished Aug 04 05:21:30 PM PDT 24
Peak memory 233084 kb
Host smart-ca17ee63-ba61-4525-b79d-b1e6870abb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35991905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.35991905
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1136695101
Short name T349
Test name
Test status
Simulation time 804816767 ps
CPU time 5.37 seconds
Started Aug 04 05:21:15 PM PDT 24
Finished Aug 04 05:21:20 PM PDT 24
Peak memory 233048 kb
Host smart-3f8c15cc-90e3-4e55-a154-9a4fe9d4f9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136695101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1136695101
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3717053136
Short name T554
Test name
Test status
Simulation time 5573830184 ps
CPU time 12.33 seconds
Started Aug 04 05:21:15 PM PDT 24
Finished Aug 04 05:21:28 PM PDT 24
Peak memory 223028 kb
Host smart-e6f55d0f-188f-4dea-997c-30bd9e472b82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3717053136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3717053136
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2822698806
Short name T385
Test name
Test status
Simulation time 2074710864 ps
CPU time 11.55 seconds
Started Aug 04 05:21:13 PM PDT 24
Finished Aug 04 05:21:25 PM PDT 24
Peak memory 216608 kb
Host smart-be68b5a2-981f-4351-8d7a-aad4953e9a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822698806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2822698806
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2847217828
Short name T676
Test name
Test status
Simulation time 666274045 ps
CPU time 3.11 seconds
Started Aug 04 05:21:36 PM PDT 24
Finished Aug 04 05:21:40 PM PDT 24
Peak memory 216508 kb
Host smart-38a3990e-20ac-42a7-8318-8273fa3673ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847217828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2847217828
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.245739459
Short name T437
Test name
Test status
Simulation time 51451223 ps
CPU time 0.83 seconds
Started Aug 04 05:21:16 PM PDT 24
Finished Aug 04 05:21:17 PM PDT 24
Peak memory 206300 kb
Host smart-274b898b-8c15-47aa-b69d-9737553d971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245739459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.245739459
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3703685733
Short name T922
Test name
Test status
Simulation time 347380354 ps
CPU time 0.83 seconds
Started Aug 04 05:21:14 PM PDT 24
Finished Aug 04 05:21:14 PM PDT 24
Peak memory 206324 kb
Host smart-be6fa48f-651b-490b-995a-74d825d7cc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703685733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3703685733
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1597784080
Short name T962
Test name
Test status
Simulation time 1200851794 ps
CPU time 9.77 seconds
Started Aug 04 05:21:13 PM PDT 24
Finished Aug 04 05:21:23 PM PDT 24
Peak memory 233060 kb
Host smart-5e69009f-fded-47a3-8195-a569492a4f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597784080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1597784080
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3810139984
Short name T935
Test name
Test status
Simulation time 47954409 ps
CPU time 0.7 seconds
Started Aug 04 05:21:26 PM PDT 24
Finished Aug 04 05:21:27 PM PDT 24
Peak memory 204432 kb
Host smart-0a1ff135-e175-4a7a-8697-2185ec88bcb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810139984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3810139984
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2849786363
Short name T645
Test name
Test status
Simulation time 178953213 ps
CPU time 4.41 seconds
Started Aug 04 05:21:19 PM PDT 24
Finished Aug 04 05:21:24 PM PDT 24
Peak memory 233028 kb
Host smart-5f36adb2-1ec6-4b1f-9360-615c4a0ddf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849786363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2849786363
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1178447526
Short name T461
Test name
Test status
Simulation time 60052281 ps
CPU time 0.79 seconds
Started Aug 04 05:21:22 PM PDT 24
Finished Aug 04 05:21:23 PM PDT 24
Peak memory 207008 kb
Host smart-d9082dc7-607d-44e3-b69a-e2136c60caba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178447526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1178447526
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1338987100
Short name T575
Test name
Test status
Simulation time 19854522615 ps
CPU time 142.63 seconds
Started Aug 04 05:21:31 PM PDT 24
Finished Aug 04 05:23:53 PM PDT 24
Peak memory 248752 kb
Host smart-cc96c86e-a41c-44ed-a645-7a20f69ad52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338987100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1338987100
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1587276602
Short name T274
Test name
Test status
Simulation time 73424561345 ps
CPU time 200.74 seconds
Started Aug 04 05:21:17 PM PDT 24
Finished Aug 04 05:24:38 PM PDT 24
Peak memory 257808 kb
Host smart-0b6d8b97-ee3a-4604-8cbb-70da9da548dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587276602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1587276602
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1330704042
Short name T381
Test name
Test status
Simulation time 37497554 ps
CPU time 2.82 seconds
Started Aug 04 05:21:22 PM PDT 24
Finished Aug 04 05:21:25 PM PDT 24
Peak memory 232960 kb
Host smart-76c0a788-66f7-4d68-9e49-f9c84c76ca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330704042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1330704042
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3131489848
Short name T852
Test name
Test status
Simulation time 3292169215 ps
CPU time 89.79 seconds
Started Aug 04 05:21:15 PM PDT 24
Finished Aug 04 05:22:45 PM PDT 24
Peak memory 273768 kb
Host smart-00a2ec7d-6a2c-4246-92cf-39a27c3db2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131489848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3131489848
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1490630641
Short name T91
Test name
Test status
Simulation time 8981554639 ps
CPU time 24.89 seconds
Started Aug 04 05:21:13 PM PDT 24
Finished Aug 04 05:21:38 PM PDT 24
Peak memory 224848 kb
Host smart-3feeb8e0-5444-487f-9176-e68b97fe03a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490630641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1490630641
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.723968948
Short name T543
Test name
Test status
Simulation time 816552889 ps
CPU time 13.72 seconds
Started Aug 04 05:21:16 PM PDT 24
Finished Aug 04 05:21:29 PM PDT 24
Peak memory 224792 kb
Host smart-beff9192-afdb-402f-a25c-30d72d38d9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723968948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.723968948
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2322549225
Short name T724
Test name
Test status
Simulation time 15926184801 ps
CPU time 24.54 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:21:50 PM PDT 24
Peak memory 241264 kb
Host smart-f372451e-9cc1-4d9d-8d80-ed4741b466fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322549225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2322549225
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2064043718
Short name T408
Test name
Test status
Simulation time 470063768 ps
CPU time 6.12 seconds
Started Aug 04 05:21:30 PM PDT 24
Finished Aug 04 05:21:36 PM PDT 24
Peak memory 239012 kb
Host smart-d2937cd3-f914-4066-80cb-8ed621c8a1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064043718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2064043718
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4143028460
Short name T498
Test name
Test status
Simulation time 2837503264 ps
CPU time 7.5 seconds
Started Aug 04 05:21:20 PM PDT 24
Finished Aug 04 05:21:27 PM PDT 24
Peak memory 221252 kb
Host smart-e8142cf2-71d3-4311-859c-b5b62363d7b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4143028460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4143028460
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.655933576
Short name T735
Test name
Test status
Simulation time 2794269261 ps
CPU time 8.22 seconds
Started Aug 04 05:21:26 PM PDT 24
Finished Aug 04 05:21:35 PM PDT 24
Peak memory 216820 kb
Host smart-c5359a3c-58d8-4ea6-91f8-d2b8bacb7cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655933576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.655933576
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2939644563
Short name T454
Test name
Test status
Simulation time 728970136 ps
CPU time 2.15 seconds
Started Aug 04 05:21:22 PM PDT 24
Finished Aug 04 05:21:24 PM PDT 24
Peak memory 216660 kb
Host smart-e2d67fa3-dcb2-4036-b281-3d9dd5e5b86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939644563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2939644563
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1251987862
Short name T403
Test name
Test status
Simulation time 27377390 ps
CPU time 1.18 seconds
Started Aug 04 05:21:17 PM PDT 24
Finished Aug 04 05:21:19 PM PDT 24
Peak memory 216604 kb
Host smart-59f57390-6276-4517-b433-5972054e69b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251987862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1251987862
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.889287333
Short name T740
Test name
Test status
Simulation time 70415634 ps
CPU time 1.02 seconds
Started Aug 04 05:21:35 PM PDT 24
Finished Aug 04 05:21:36 PM PDT 24
Peak memory 206264 kb
Host smart-2b179de5-16e6-4979-bb41-a711cc3f6b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889287333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.889287333
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3738434336
Short name T228
Test name
Test status
Simulation time 24953584408 ps
CPU time 19.94 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:21:59 PM PDT 24
Peak memory 233208 kb
Host smart-f8d1bf08-5fde-4921-816b-08789a1daeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738434336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3738434336
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1373825570
Short name T889
Test name
Test status
Simulation time 36610201 ps
CPU time 0.69 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:21:40 PM PDT 24
Peak memory 205188 kb
Host smart-41788b60-c6a7-4447-bf33-ac59dffe3e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373825570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1373825570
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1703889567
Short name T176
Test name
Test status
Simulation time 6377903116 ps
CPU time 15.39 seconds
Started Aug 04 05:21:31 PM PDT 24
Finished Aug 04 05:21:46 PM PDT 24
Peak memory 232384 kb
Host smart-211b1707-a1cb-4f9c-b12d-fcf182cdd852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703889567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1703889567
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1456864434
Short name T827
Test name
Test status
Simulation time 27763626 ps
CPU time 0.74 seconds
Started Aug 04 05:21:38 PM PDT 24
Finished Aug 04 05:21:39 PM PDT 24
Peak memory 205936 kb
Host smart-8f3d9317-b656-48f9-9607-48ab0d94003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456864434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1456864434
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.4247790439
Short name T7
Test name
Test status
Simulation time 24813624956 ps
CPU time 225.38 seconds
Started Aug 04 05:21:40 PM PDT 24
Finished Aug 04 05:25:25 PM PDT 24
Peak memory 266068 kb
Host smart-e75168d0-26e0-4a6e-9755-934cbad12b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247790439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.4247790439
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3875090833
Short name T217
Test name
Test status
Simulation time 71568130273 ps
CPU time 473.13 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:29:33 PM PDT 24
Peak memory 263768 kb
Host smart-d3bc154b-a1ce-4564-8426-8788ba96d92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875090833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3875090833
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4143092985
Short name T301
Test name
Test status
Simulation time 4175990117 ps
CPU time 52.73 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:22:32 PM PDT 24
Peak memory 241436 kb
Host smart-08040336-e514-482d-b347-6cedd30e91be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143092985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4143092985
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2913808281
Short name T429
Test name
Test status
Simulation time 418377929 ps
CPU time 5.08 seconds
Started Aug 04 05:21:27 PM PDT 24
Finished Aug 04 05:21:33 PM PDT 24
Peak memory 224976 kb
Host smart-37b07125-6b51-49cf-a5bc-9b109273a92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913808281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2913808281
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3163026060
Short name T282
Test name
Test status
Simulation time 243580232390 ps
CPU time 457.45 seconds
Started Aug 04 05:21:21 PM PDT 24
Finished Aug 04 05:28:59 PM PDT 24
Peak memory 264168 kb
Host smart-437c9616-a672-44ba-a1d6-47e60194c260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163026060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3163026060
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3644079176
Short name T663
Test name
Test status
Simulation time 2684959570 ps
CPU time 6.67 seconds
Started Aug 04 05:21:40 PM PDT 24
Finished Aug 04 05:21:47 PM PDT 24
Peak memory 233220 kb
Host smart-74311545-9b45-42d8-858b-3e5d00fbec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644079176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3644079176
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3707751715
Short name T871
Test name
Test status
Simulation time 3148519960 ps
CPU time 14.75 seconds
Started Aug 04 05:21:34 PM PDT 24
Finished Aug 04 05:21:49 PM PDT 24
Peak memory 240596 kb
Host smart-d3a773ea-07fa-4cf2-846a-c3678ba3cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707751715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3707751715
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.373895843
Short name T911
Test name
Test status
Simulation time 19227591550 ps
CPU time 13.67 seconds
Started Aug 04 05:21:17 PM PDT 24
Finished Aug 04 05:21:31 PM PDT 24
Peak memory 224944 kb
Host smart-40c0568f-51d1-4b56-8363-77cea4cea2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373895843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.373895843
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1482625171
Short name T572
Test name
Test status
Simulation time 34436629481 ps
CPU time 21.3 seconds
Started Aug 04 05:21:30 PM PDT 24
Finished Aug 04 05:21:51 PM PDT 24
Peak memory 224944 kb
Host smart-80ecc0b1-3912-464f-903b-601c9de10d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482625171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1482625171
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1345093454
Short name T497
Test name
Test status
Simulation time 1235790844 ps
CPU time 11.92 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:21:37 PM PDT 24
Peak memory 220420 kb
Host smart-8272a2ef-4ce2-41cd-8456-67b06cc4376e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1345093454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1345093454
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3920113549
Short name T690
Test name
Test status
Simulation time 7739668468 ps
CPU time 49.85 seconds
Started Aug 04 05:21:16 PM PDT 24
Finished Aug 04 05:22:06 PM PDT 24
Peak memory 254328 kb
Host smart-e36252e6-9c4c-4749-a9a9-d47b3298dc56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920113549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3920113549
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2088510280
Short name T847
Test name
Test status
Simulation time 13134281630 ps
CPU time 37.11 seconds
Started Aug 04 05:21:14 PM PDT 24
Finished Aug 04 05:21:51 PM PDT 24
Peak memory 216668 kb
Host smart-b3eaf47e-eceb-4b23-b463-c849bf283ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088510280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2088510280
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2028022872
Short name T602
Test name
Test status
Simulation time 511006212 ps
CPU time 3.54 seconds
Started Aug 04 05:21:22 PM PDT 24
Finished Aug 04 05:21:25 PM PDT 24
Peak memory 216692 kb
Host smart-5bc91cb4-29f3-48ba-a7fe-b95b37082e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028022872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2028022872
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.621556820
Short name T727
Test name
Test status
Simulation time 46547338 ps
CPU time 1.46 seconds
Started Aug 04 05:21:17 PM PDT 24
Finished Aug 04 05:21:19 PM PDT 24
Peak memory 216900 kb
Host smart-cbe62a35-380f-4a2e-ba63-38d9d0d6ac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621556820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.621556820
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3775928587
Short name T559
Test name
Test status
Simulation time 24506543 ps
CPU time 0.78 seconds
Started Aug 04 05:21:31 PM PDT 24
Finished Aug 04 05:21:32 PM PDT 24
Peak memory 206372 kb
Host smart-d56e5786-aa5a-4a9e-9878-b8d2ebc265fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775928587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3775928587
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.885452304
Short name T761
Test name
Test status
Simulation time 294587371 ps
CPU time 2.45 seconds
Started Aug 04 05:21:18 PM PDT 24
Finished Aug 04 05:21:21 PM PDT 24
Peak memory 224940 kb
Host smart-091a15c3-abc4-4b54-9ca9-841b167433f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885452304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.885452304
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2548172730
Short name T775
Test name
Test status
Simulation time 12564497 ps
CPU time 0.79 seconds
Started Aug 04 05:21:27 PM PDT 24
Finished Aug 04 05:21:28 PM PDT 24
Peak memory 205840 kb
Host smart-9d2afbf1-2003-465a-87f1-156eccb07269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548172730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2548172730
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3092753339
Short name T365
Test name
Test status
Simulation time 1481494765 ps
CPU time 6.13 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:21:45 PM PDT 24
Peak memory 224868 kb
Host smart-52334959-dcac-4a23-a62c-d62a93b7a697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092753339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3092753339
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.621396988
Short name T632
Test name
Test status
Simulation time 31007917 ps
CPU time 0.78 seconds
Started Aug 04 05:21:35 PM PDT 24
Finished Aug 04 05:21:36 PM PDT 24
Peak memory 206880 kb
Host smart-bbdb8e8c-66d8-49d6-a817-5438e8409420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621396988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.621396988
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2057861781
Short name T266
Test name
Test status
Simulation time 10343509034 ps
CPU time 44.15 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:22:09 PM PDT 24
Peak memory 249508 kb
Host smart-009f1489-a6b5-4452-bf4d-9e79f13820ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057861781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2057861781
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2097565120
Short name T720
Test name
Test status
Simulation time 7665969374 ps
CPU time 79.79 seconds
Started Aug 04 05:21:40 PM PDT 24
Finished Aug 04 05:23:00 PM PDT 24
Peak memory 253568 kb
Host smart-8aae4a79-75da-4244-9926-bcf130e8ae96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097565120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2097565120
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2771852490
Short name T576
Test name
Test status
Simulation time 402084636 ps
CPU time 2.53 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:21:41 PM PDT 24
Peak memory 224856 kb
Host smart-35684c5c-6a87-4212-a193-c36e0c2c344d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771852490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2771852490
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1010340498
Short name T758
Test name
Test status
Simulation time 23786184 ps
CPU time 0.76 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:21:26 PM PDT 24
Peak memory 215792 kb
Host smart-4e605b96-3b7e-460b-9011-1c80febc5376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010340498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1010340498
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.462689581
Short name T489
Test name
Test status
Simulation time 3618268604 ps
CPU time 10.05 seconds
Started Aug 04 05:21:19 PM PDT 24
Finished Aug 04 05:21:29 PM PDT 24
Peak memory 233140 kb
Host smart-b017acaa-29fe-43c1-a7b2-0a82750506ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462689581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.462689581
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3710204806
Short name T573
Test name
Test status
Simulation time 1307024617 ps
CPU time 19.51 seconds
Started Aug 04 05:21:32 PM PDT 24
Finished Aug 04 05:21:51 PM PDT 24
Peak memory 233136 kb
Host smart-9860dec5-e1e0-44c2-be53-84002d0b48dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710204806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3710204806
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2988166111
Short name T756
Test name
Test status
Simulation time 2021942721 ps
CPU time 12.07 seconds
Started Aug 04 05:21:17 PM PDT 24
Finished Aug 04 05:21:29 PM PDT 24
Peak memory 224920 kb
Host smart-7bf9d560-77e0-430c-a87a-866af5f278d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988166111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2988166111
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3027103956
Short name T411
Test name
Test status
Simulation time 20566829045 ps
CPU time 28.86 seconds
Started Aug 04 05:21:19 PM PDT 24
Finished Aug 04 05:21:48 PM PDT 24
Peak memory 233060 kb
Host smart-bc3d09ab-1624-4dad-8a99-9779203ac79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027103956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3027103956
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2014515117
Short name T603
Test name
Test status
Simulation time 1533658589 ps
CPU time 12.13 seconds
Started Aug 04 05:21:31 PM PDT 24
Finished Aug 04 05:21:43 PM PDT 24
Peak memory 221048 kb
Host smart-d0d97a18-09b4-4759-a785-f7ec8671aeeb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2014515117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2014515117
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2083705393
Short name T413
Test name
Test status
Simulation time 39915861683 ps
CPU time 33.69 seconds
Started Aug 04 05:21:43 PM PDT 24
Finished Aug 04 05:22:16 PM PDT 24
Peak memory 216740 kb
Host smart-3f5315eb-0958-475c-93b6-930be87a7b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083705393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2083705393
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3926970963
Short name T693
Test name
Test status
Simulation time 11440021475 ps
CPU time 17.58 seconds
Started Aug 04 05:21:34 PM PDT 24
Finished Aug 04 05:21:51 PM PDT 24
Peak memory 216688 kb
Host smart-ebf8ef49-bbdc-49a5-b9c0-0f72804d8c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926970963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3926970963
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1344521372
Short name T478
Test name
Test status
Simulation time 140464164 ps
CPU time 0.95 seconds
Started Aug 04 05:21:32 PM PDT 24
Finished Aug 04 05:21:33 PM PDT 24
Peak memory 207360 kb
Host smart-55b4272e-4c14-496e-b759-75c9698be9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344521372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1344521372
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3901410163
Short name T465
Test name
Test status
Simulation time 45410402 ps
CPU time 0.76 seconds
Started Aug 04 05:21:36 PM PDT 24
Finished Aug 04 05:21:37 PM PDT 24
Peak memory 206260 kb
Host smart-ecbd4718-4831-4ce9-ac06-9f453023d29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901410163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3901410163
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3231116136
Short name T368
Test name
Test status
Simulation time 53986436 ps
CPU time 2.18 seconds
Started Aug 04 05:21:23 PM PDT 24
Finished Aug 04 05:21:26 PM PDT 24
Peak memory 224656 kb
Host smart-d9ff44b6-4783-4603-8fc5-a0719efc8eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231116136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3231116136
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1475300277
Short name T998
Test name
Test status
Simulation time 13422435 ps
CPU time 0.71 seconds
Started Aug 04 05:21:36 PM PDT 24
Finished Aug 04 05:21:37 PM PDT 24
Peak memory 205300 kb
Host smart-08b3e4c1-dde1-4b47-8d0a-25ace3396398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475300277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1475300277
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2620119513
Short name T323
Test name
Test status
Simulation time 628211337 ps
CPU time 6.2 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:21:45 PM PDT 24
Peak memory 233036 kb
Host smart-7d1291ad-324c-4bfa-b76b-563594d2e414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620119513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2620119513
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1951220685
Short name T747
Test name
Test status
Simulation time 39815362 ps
CPU time 0.81 seconds
Started Aug 04 05:21:37 PM PDT 24
Finished Aug 04 05:21:38 PM PDT 24
Peak memory 207004 kb
Host smart-ee003509-5ed0-4592-b7ca-6441599b90b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951220685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1951220685
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.611255809
Short name T202
Test name
Test status
Simulation time 48075796093 ps
CPU time 333.42 seconds
Started Aug 04 05:21:29 PM PDT 24
Finished Aug 04 05:27:03 PM PDT 24
Peak memory 254200 kb
Host smart-92f7655d-807b-41e5-93ed-d13e5a656b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611255809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.611255809
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3780710897
Short name T44
Test name
Test status
Simulation time 3832895064 ps
CPU time 60.85 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:22:26 PM PDT 24
Peak memory 248600 kb
Host smart-c121d687-15d5-492a-a8dc-a5a1fd1914ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780710897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3780710897
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.390999769
Short name T914
Test name
Test status
Simulation time 23018510698 ps
CPU time 168.34 seconds
Started Aug 04 05:21:37 PM PDT 24
Finished Aug 04 05:24:25 PM PDT 24
Peak memory 249776 kb
Host smart-e78a423f-8b93-4b48-af89-48b35914ec90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390999769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.390999769
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1780870820
Short name T627
Test name
Test status
Simulation time 263677204 ps
CPU time 5.59 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:21:31 PM PDT 24
Peak memory 241248 kb
Host smart-88450b12-2ba2-4707-a81a-7c0fee859dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780870820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1780870820
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2790513728
Short name T34
Test name
Test status
Simulation time 18672604268 ps
CPU time 135.23 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:23:54 PM PDT 24
Peak memory 249604 kb
Host smart-e240c980-0440-485f-9e46-b3c3e3069bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790513728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2790513728
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.230150605
Short name T12
Test name
Test status
Simulation time 460192063 ps
CPU time 2.33 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:21:41 PM PDT 24
Peak memory 233048 kb
Host smart-f3524351-71b4-4c4d-85ae-c7c716f81adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230150605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.230150605
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3945866094
Short name T579
Test name
Test status
Simulation time 4910625647 ps
CPU time 11.8 seconds
Started Aug 04 05:21:31 PM PDT 24
Finished Aug 04 05:21:43 PM PDT 24
Peak memory 224992 kb
Host smart-9c8b9ec8-97ac-4953-a6b6-8937d396d856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945866094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3945866094
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3189028424
Short name T252
Test name
Test status
Simulation time 655228972 ps
CPU time 2.52 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:21:42 PM PDT 24
Peak memory 224788 kb
Host smart-ca081589-8566-4fae-989f-3315c9dda9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189028424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3189028424
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1994728954
Short name T759
Test name
Test status
Simulation time 1104036205 ps
CPU time 6.64 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:21:45 PM PDT 24
Peak memory 233060 kb
Host smart-72ac6e93-1d69-4527-9122-66258d873a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994728954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1994728954
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3532920358
Short name T430
Test name
Test status
Simulation time 129612346 ps
CPU time 4.28 seconds
Started Aug 04 05:21:29 PM PDT 24
Finished Aug 04 05:21:33 PM PDT 24
Peak memory 223524 kb
Host smart-fd694501-adc3-41f2-bb57-7c2ae00d8707
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3532920358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3532920358
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1074317681
Short name T153
Test name
Test status
Simulation time 55975823 ps
CPU time 1.02 seconds
Started Aug 04 05:21:21 PM PDT 24
Finished Aug 04 05:21:22 PM PDT 24
Peak memory 205964 kb
Host smart-7d9ef61c-cf13-4b3c-a704-dd9e2cc9c209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074317681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1074317681
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3948470494
Short name T333
Test name
Test status
Simulation time 16514354 ps
CPU time 0.73 seconds
Started Aug 04 05:21:19 PM PDT 24
Finished Aug 04 05:21:20 PM PDT 24
Peak memory 205956 kb
Host smart-45371d66-0974-4735-865c-3f22272d186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948470494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3948470494
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3609155102
Short name T340
Test name
Test status
Simulation time 2111653535 ps
CPU time 11.9 seconds
Started Aug 04 05:21:40 PM PDT 24
Finished Aug 04 05:21:52 PM PDT 24
Peak memory 216600 kb
Host smart-96c18874-8ccc-4abb-b20f-e0c6c1f4ca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609155102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3609155102
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4220573313
Short name T692
Test name
Test status
Simulation time 488017971 ps
CPU time 5.46 seconds
Started Aug 04 05:21:21 PM PDT 24
Finished Aug 04 05:21:26 PM PDT 24
Peak memory 216656 kb
Host smart-dac3d7c8-a986-4b60-b044-2aa944ec5db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220573313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4220573313
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3055284424
Short name T428
Test name
Test status
Simulation time 56721801 ps
CPU time 0.76 seconds
Started Aug 04 05:21:24 PM PDT 24
Finished Aug 04 05:21:25 PM PDT 24
Peak memory 206324 kb
Host smart-c237a291-24df-4c00-9bb9-5ad553e68fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055284424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3055284424
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2408073440
Short name T705
Test name
Test status
Simulation time 2191666661 ps
CPU time 9.21 seconds
Started Aug 04 05:21:37 PM PDT 24
Finished Aug 04 05:21:47 PM PDT 24
Peak memory 233124 kb
Host smart-8d5da50a-7105-4e16-8ac7-c8aeadb65d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408073440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2408073440
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2026128038
Short name T793
Test name
Test status
Simulation time 27166178 ps
CPU time 0.72 seconds
Started Aug 04 05:21:38 PM PDT 24
Finished Aug 04 05:21:38 PM PDT 24
Peak memory 205796 kb
Host smart-3925a66e-0799-4b34-a5c8-aec4eeaf66fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026128038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2026128038
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1727721732
Short name T496
Test name
Test status
Simulation time 9114011375 ps
CPU time 17.02 seconds
Started Aug 04 05:21:22 PM PDT 24
Finished Aug 04 05:21:40 PM PDT 24
Peak memory 233164 kb
Host smart-9251e747-f860-4bc1-a333-6a23d6d04442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727721732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1727721732
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2125398265
Short name T425
Test name
Test status
Simulation time 61155213 ps
CPU time 0.77 seconds
Started Aug 04 05:21:37 PM PDT 24
Finished Aug 04 05:21:37 PM PDT 24
Peak memory 205980 kb
Host smart-4873788c-ef93-4a09-9b1f-5fc20cf6e0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125398265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2125398265
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.138419431
Short name T185
Test name
Test status
Simulation time 3869163211 ps
CPU time 54.36 seconds
Started Aug 04 05:21:35 PM PDT 24
Finished Aug 04 05:22:30 PM PDT 24
Peak memory 257424 kb
Host smart-625b196d-9ef3-4ec3-9831-0a9862a62f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138419431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.138419431
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2769505453
Short name T626
Test name
Test status
Simulation time 27151345251 ps
CPU time 117.98 seconds
Started Aug 04 05:21:36 PM PDT 24
Finished Aug 04 05:23:34 PM PDT 24
Peak memory 249632 kb
Host smart-d1bafe0b-27a9-46c1-ac0f-7e6ea0eaddbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769505453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2769505453
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2070234605
Short name T132
Test name
Test status
Simulation time 3899498317 ps
CPU time 58.91 seconds
Started Aug 04 05:21:38 PM PDT 24
Finished Aug 04 05:22:37 PM PDT 24
Peak memory 252764 kb
Host smart-d6e75cb2-bf5c-4ef1-8451-fa5d8414ef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070234605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2070234605
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3882372638
Short name T296
Test name
Test status
Simulation time 958563477 ps
CPU time 9.35 seconds
Started Aug 04 05:21:26 PM PDT 24
Finished Aug 04 05:21:35 PM PDT 24
Peak memory 232984 kb
Host smart-ac261bb0-9ba3-4499-af91-6821d26897cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882372638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3882372638
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.240942890
Short name T733
Test name
Test status
Simulation time 32375034185 ps
CPU time 216.78 seconds
Started Aug 04 05:21:40 PM PDT 24
Finished Aug 04 05:25:17 PM PDT 24
Peak memory 254692 kb
Host smart-a5a280b2-8ba6-4b2e-9e3d-ff22a544decd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240942890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.240942890
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1089728854
Short name T199
Test name
Test status
Simulation time 125886691 ps
CPU time 3.88 seconds
Started Aug 04 05:21:27 PM PDT 24
Finished Aug 04 05:21:31 PM PDT 24
Peak memory 224712 kb
Host smart-4f5d8860-8201-4f5a-baaf-332d98f4b961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089728854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1089728854
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.416152964
Short name T222
Test name
Test status
Simulation time 1176119538 ps
CPU time 11.78 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:21:37 PM PDT 24
Peak memory 234076 kb
Host smart-d97ddc6e-fde0-4ec7-b7b2-5dcbce6869fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416152964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.416152964
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.414932438
Short name T57
Test name
Test status
Simulation time 777543625 ps
CPU time 6.17 seconds
Started Aug 04 05:21:41 PM PDT 24
Finished Aug 04 05:21:47 PM PDT 24
Peak memory 233204 kb
Host smart-3e73f4a0-feb6-4d54-bb52-bdd58c01e171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414932438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.414932438
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2128499457
Short name T359
Test name
Test status
Simulation time 2818685019 ps
CPU time 11.52 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:21:37 PM PDT 24
Peak memory 224852 kb
Host smart-eab77a7a-42b2-4a52-8370-158d38522638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128499457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2128499457
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1909807764
Short name T1005
Test name
Test status
Simulation time 472718431 ps
CPU time 3.6 seconds
Started Aug 04 05:21:20 PM PDT 24
Finished Aug 04 05:21:24 PM PDT 24
Peak memory 220256 kb
Host smart-21a69fc0-6674-4b3d-a98a-eebff232e338
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1909807764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1909807764
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.4205740948
Short name T21
Test name
Test status
Simulation time 583803420 ps
CPU time 8.37 seconds
Started Aug 04 05:21:36 PM PDT 24
Finished Aug 04 05:21:45 PM PDT 24
Peak memory 223612 kb
Host smart-ae45376b-32a7-475e-a66b-bb975a5a63f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205740948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.4205740948
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.578879122
Short name T457
Test name
Test status
Simulation time 3687452260 ps
CPU time 9.27 seconds
Started Aug 04 05:21:21 PM PDT 24
Finished Aug 04 05:21:31 PM PDT 24
Peak memory 218072 kb
Host smart-6d66b601-71a5-489b-8a83-27f0694d1328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578879122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.578879122
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4088924099
Short name T348
Test name
Test status
Simulation time 895476805 ps
CPU time 5.17 seconds
Started Aug 04 05:21:29 PM PDT 24
Finished Aug 04 05:21:34 PM PDT 24
Peak memory 216632 kb
Host smart-a248dc52-73b6-4ff9-a143-c0abc660f2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088924099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4088924099
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.879009398
Short name T907
Test name
Test status
Simulation time 1436195504 ps
CPU time 1.75 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:21:26 PM PDT 24
Peak memory 216728 kb
Host smart-fa66624b-df91-49d3-831f-67b352d5c7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879009398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.879009398
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1513253844
Short name T946
Test name
Test status
Simulation time 26716546 ps
CPU time 0.83 seconds
Started Aug 04 05:21:24 PM PDT 24
Finished Aug 04 05:21:25 PM PDT 24
Peak memory 206320 kb
Host smart-0cc8dfc9-e5e5-467d-ad22-69b281d67783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513253844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1513253844
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.286495863
Short name T229
Test name
Test status
Simulation time 7429985945 ps
CPU time 23.84 seconds
Started Aug 04 05:21:30 PM PDT 24
Finished Aug 04 05:21:54 PM PDT 24
Peak memory 241236 kb
Host smart-7c0dfcf3-7b22-4e1f-972e-4872fab6642d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286495863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.286495863
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3976788544
Short name T578
Test name
Test status
Simulation time 21622931 ps
CPU time 0.76 seconds
Started Aug 04 05:21:27 PM PDT 24
Finished Aug 04 05:21:28 PM PDT 24
Peak memory 205656 kb
Host smart-9cd67719-8e88-4164-9ba9-ea0c1477f1d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976788544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3976788544
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.50016696
Short name T930
Test name
Test status
Simulation time 1108356979 ps
CPU time 8.75 seconds
Started Aug 04 05:21:35 PM PDT 24
Finished Aug 04 05:21:44 PM PDT 24
Peak memory 233156 kb
Host smart-2fc3f169-2c1e-42d5-b84a-8aa19daf9509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50016696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.50016696
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2931319454
Short name T811
Test name
Test status
Simulation time 24452006 ps
CPU time 0.78 seconds
Started Aug 04 05:21:39 PM PDT 24
Finished Aug 04 05:21:40 PM PDT 24
Peak memory 206968 kb
Host smart-8745d815-13eb-4110-bca8-f2f1de6195e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931319454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2931319454
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3930808561
Short name T244
Test name
Test status
Simulation time 20962334331 ps
CPU time 136.92 seconds
Started Aug 04 05:21:40 PM PDT 24
Finished Aug 04 05:23:57 PM PDT 24
Peak memory 252984 kb
Host smart-0d38bc01-5fd5-4e2f-92f8-299d6af020e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930808561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3930808561
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3055232819
Short name T237
Test name
Test status
Simulation time 317307633382 ps
CPU time 348.58 seconds
Started Aug 04 05:21:23 PM PDT 24
Finished Aug 04 05:27:12 PM PDT 24
Peak memory 257788 kb
Host smart-7d57b2e3-1c8b-42fc-ba20-8665dfa9a0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055232819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3055232819
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2915246667
Short name T618
Test name
Test status
Simulation time 20209456714 ps
CPU time 66.71 seconds
Started Aug 04 05:21:26 PM PDT 24
Finished Aug 04 05:22:33 PM PDT 24
Peak memory 241252 kb
Host smart-9cd9100b-4199-4339-b7cf-a4f7fde4afad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915246667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2915246667
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2492866805
Short name T728
Test name
Test status
Simulation time 119397707 ps
CPU time 6.32 seconds
Started Aug 04 05:21:33 PM PDT 24
Finished Aug 04 05:21:39 PM PDT 24
Peak memory 224880 kb
Host smart-ced9ab12-e71c-4174-81a5-d0560ff93a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492866805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2492866805
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.604304153
Short name T941
Test name
Test status
Simulation time 7000996860 ps
CPU time 96.38 seconds
Started Aug 04 05:21:33 PM PDT 24
Finished Aug 04 05:23:09 PM PDT 24
Peak memory 256020 kb
Host smart-7bbf26bf-93fc-4c17-987f-9be7f70a36f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604304153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.604304153
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3582453743
Short name T799
Test name
Test status
Simulation time 657527306 ps
CPU time 6.5 seconds
Started Aug 04 05:21:25 PM PDT 24
Finished Aug 04 05:21:31 PM PDT 24
Peak memory 233176 kb
Host smart-e6460d35-4ea7-4527-9f24-6bf209047f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582453743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3582453743
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1599347266
Short name T859
Test name
Test status
Simulation time 10969800423 ps
CPU time 20.76 seconds
Started Aug 04 05:21:35 PM PDT 24
Finished Aug 04 05:21:56 PM PDT 24
Peak memory 250976 kb
Host smart-b66a0eb6-6296-4ad6-9617-7bb5462ec489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599347266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1599347266
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.440513056
Short name T253
Test name
Test status
Simulation time 115212661 ps
CPU time 2.62 seconds
Started Aug 04 05:21:28 PM PDT 24
Finished Aug 04 05:21:31 PM PDT 24
Peak memory 233148 kb
Host smart-79848874-3c38-4ca5-8c16-75f489c9afd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440513056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.440513056
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.586878511
Short name T791
Test name
Test status
Simulation time 22563608426 ps
CPU time 16.94 seconds
Started Aug 04 05:21:37 PM PDT 24
Finished Aug 04 05:21:54 PM PDT 24
Peak memory 233168 kb
Host smart-fa3237d2-743a-417a-bbc2-6633b4d4d897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586878511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.586878511
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.802534618
Short name T966
Test name
Test status
Simulation time 388368585 ps
CPU time 3.88 seconds
Started Aug 04 05:21:34 PM PDT 24
Finished Aug 04 05:21:38 PM PDT 24
Peak memory 220832 kb
Host smart-c25c7188-4b6c-4f0f-861a-754a4c71edc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=802534618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.802534618
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2327242325
Short name T538
Test name
Test status
Simulation time 1406964273 ps
CPU time 6.92 seconds
Started Aug 04 05:21:37 PM PDT 24
Finished Aug 04 05:21:44 PM PDT 24
Peak memory 216864 kb
Host smart-4f2fffe7-9e88-4d57-81f9-d2024eb48170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327242325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2327242325
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3190603478
Short name T25
Test name
Test status
Simulation time 2954530528 ps
CPU time 8.82 seconds
Started Aug 04 05:21:29 PM PDT 24
Finished Aug 04 05:21:38 PM PDT 24
Peak memory 216716 kb
Host smart-9cb9135f-2a26-4842-948e-2e11373cbd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190603478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3190603478
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3960338332
Short name T338
Test name
Test status
Simulation time 64179254 ps
CPU time 1.05 seconds
Started Aug 04 05:21:35 PM PDT 24
Finished Aug 04 05:21:36 PM PDT 24
Peak memory 208292 kb
Host smart-48f9b713-fd75-4a8f-a27e-c5b260a17eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960338332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3960338332
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3116798358
Short name T604
Test name
Test status
Simulation time 336280818 ps
CPU time 0.88 seconds
Started Aug 04 05:21:36 PM PDT 24
Finished Aug 04 05:21:37 PM PDT 24
Peak memory 206420 kb
Host smart-f1e231e9-5491-4720-a1a5-2deec9f1b6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116798358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3116798358
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3896800419
Short name T583
Test name
Test status
Simulation time 230360304 ps
CPU time 4.99 seconds
Started Aug 04 05:21:36 PM PDT 24
Finished Aug 04 05:21:41 PM PDT 24
Peak memory 241080 kb
Host smart-3dba9243-bb60-415f-ac65-bf521e640c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896800419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3896800419
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3851633951
Short name T467
Test name
Test status
Simulation time 51405173 ps
CPU time 0.76 seconds
Started Aug 04 05:21:26 PM PDT 24
Finished Aug 04 05:21:27 PM PDT 24
Peak memory 205140 kb
Host smart-ea4be837-20e1-4275-8e07-fd95b7d18820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851633951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3851633951
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2708196676
Short name T439
Test name
Test status
Simulation time 392589621 ps
CPU time 3.89 seconds
Started Aug 04 05:21:26 PM PDT 24
Finished Aug 04 05:21:30 PM PDT 24
Peak memory 224844 kb
Host smart-5dba6029-34f0-45cd-9aa7-df6c7022c820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708196676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2708196676
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2228169888
Short name T738
Test name
Test status
Simulation time 18918394 ps
CPU time 0.78 seconds
Started Aug 04 05:21:35 PM PDT 24
Finished Aug 04 05:21:36 PM PDT 24
Peak memory 207268 kb
Host smart-3d3f2857-4dc0-40ad-86bb-965e24a048e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228169888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2228169888
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3511029000
Short name T680
Test name
Test status
Simulation time 3545121172 ps
CPU time 27.11 seconds
Started Aug 04 05:21:28 PM PDT 24
Finished Aug 04 05:21:55 PM PDT 24
Peak memory 233064 kb
Host smart-8a1aa67b-5f45-4ea0-8537-efd01d5c64ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511029000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3511029000
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2938902636
Short name T842
Test name
Test status
Simulation time 1223927885 ps
CPU time 20.58 seconds
Started Aug 04 05:21:42 PM PDT 24
Finished Aug 04 05:22:02 PM PDT 24
Peak memory 233076 kb
Host smart-c22f7933-3fa5-4e83-8c82-d5702fcf9b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938902636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2938902636
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1884318513
Short name T943
Test name
Test status
Simulation time 2114720117 ps
CPU time 10.81 seconds
Started Aug 04 05:21:40 PM PDT 24
Finished Aug 04 05:21:51 PM PDT 24
Peak memory 224848 kb
Host smart-a723ebe8-cc0b-4d35-8d09-94810bc86407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884318513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1884318513
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3831797108
Short name T804
Test name
Test status
Simulation time 13790118044 ps
CPU time 49.71 seconds
Started Aug 04 05:21:26 PM PDT 24
Finished Aug 04 05:22:16 PM PDT 24
Peak memory 239840 kb
Host smart-dc464ec6-d2d4-4c44-a447-079d8d25f2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831797108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3831797108
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.357318042
Short name T651
Test name
Test status
Simulation time 5251346051 ps
CPU time 16.49 seconds
Started Aug 04 05:21:28 PM PDT 24
Finished Aug 04 05:21:45 PM PDT 24
Peak memory 233100 kb
Host smart-d83c2f10-43b4-4566-a6ee-3adf4742499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357318042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.357318042
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1547089745
Short name T486
Test name
Test status
Simulation time 292484086 ps
CPU time 2.72 seconds
Started Aug 04 05:21:30 PM PDT 24
Finished Aug 04 05:21:32 PM PDT 24
Peak memory 224888 kb
Host smart-51ca887f-3010-462d-bf14-a4214b8e066b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547089745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1547089745
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2911440247
Short name T377
Test name
Test status
Simulation time 749562108 ps
CPU time 11.98 seconds
Started Aug 04 05:21:41 PM PDT 24
Finished Aug 04 05:21:53 PM PDT 24
Peak memory 223488 kb
Host smart-e5be614f-1719-467a-9b33-4251c7eb7173
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2911440247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2911440247
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1460026880
Short name T678
Test name
Test status
Simulation time 6934160040 ps
CPU time 20.35 seconds
Started Aug 04 05:21:22 PM PDT 24
Finished Aug 04 05:21:43 PM PDT 24
Peak memory 216776 kb
Host smart-8bb0d198-5b3c-4df5-93f3-5661e74b113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460026880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1460026880
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3933270818
Short name T367
Test name
Test status
Simulation time 4528487256 ps
CPU time 4.45 seconds
Started Aug 04 05:21:22 PM PDT 24
Finished Aug 04 05:21:27 PM PDT 24
Peak memory 216588 kb
Host smart-ed0b844c-fcdf-46d5-bfe9-028a4b96d17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933270818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3933270818
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1974823494
Short name T897
Test name
Test status
Simulation time 226819904 ps
CPU time 1.37 seconds
Started Aug 04 05:21:37 PM PDT 24
Finished Aug 04 05:21:38 PM PDT 24
Peak memory 216624 kb
Host smart-b9a808d9-e3df-42fe-b94d-78045679f7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974823494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1974823494
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.851208627
Short name T666
Test name
Test status
Simulation time 116611232 ps
CPU time 0.92 seconds
Started Aug 04 05:21:42 PM PDT 24
Finished Aug 04 05:21:43 PM PDT 24
Peak memory 206716 kb
Host smart-b68191bb-5ac9-4e2d-a5d9-c4b80b87464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851208627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.851208627
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1096832139
Short name T262
Test name
Test status
Simulation time 775377462 ps
CPU time 4.82 seconds
Started Aug 04 05:21:40 PM PDT 24
Finished Aug 04 05:21:45 PM PDT 24
Peak memory 224816 kb
Host smart-d6a4e8d6-e96c-4f5c-b433-f6b927f9cb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096832139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1096832139
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1697548956
Short name T752
Test name
Test status
Simulation time 16362561 ps
CPU time 0.71 seconds
Started Aug 04 05:19:45 PM PDT 24
Finished Aug 04 05:19:45 PM PDT 24
Peak memory 205764 kb
Host smart-095ff1a3-0764-4d0f-9d21-e74ad96c7f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697548956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
697548956
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1788858665
Short name T2
Test name
Test status
Simulation time 512252198 ps
CPU time 3.22 seconds
Started Aug 04 05:19:46 PM PDT 24
Finished Aug 04 05:19:49 PM PDT 24
Peak memory 232952 kb
Host smart-29ea1916-2afd-45e2-9c9c-9e7558d71b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788858665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1788858665
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.862318180
Short name T318
Test name
Test status
Simulation time 27351235 ps
CPU time 0.75 seconds
Started Aug 04 05:19:43 PM PDT 24
Finished Aug 04 05:19:43 PM PDT 24
Peak memory 207172 kb
Host smart-2be95ab7-8cdb-4af5-a8e9-e91327a288c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862318180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.862318180
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1347878952
Short name T39
Test name
Test status
Simulation time 186759044100 ps
CPU time 359.97 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:25:50 PM PDT 24
Peak memory 273256 kb
Host smart-157c0c4b-5458-452d-a0b3-b64ea895eba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347878952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1347878952
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2948382812
Short name T40
Test name
Test status
Simulation time 129480261459 ps
CPU time 337.09 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:25:27 PM PDT 24
Peak memory 266016 kb
Host smart-643c02ed-d131-48f9-8bf7-b4caf6278777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948382812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2948382812
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2543750231
Short name T532
Test name
Test status
Simulation time 22832968971 ps
CPU time 187.91 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:23:00 PM PDT 24
Peak memory 253884 kb
Host smart-b36d1c07-3cce-4f83-8ee5-8e025d0025b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543750231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2543750231
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2938598037
Short name T869
Test name
Test status
Simulation time 285302505 ps
CPU time 9.32 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 236836 kb
Host smart-5cbe1ca2-65c4-4791-b1d7-5ee7b11ef76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938598037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2938598037
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2768118984
Short name T501
Test name
Test status
Simulation time 1527729062 ps
CPU time 9.46 seconds
Started Aug 04 05:19:46 PM PDT 24
Finished Aug 04 05:19:55 PM PDT 24
Peak memory 224916 kb
Host smart-8b4313ad-4037-4f6d-afbc-92750b074de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768118984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2768118984
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3434903264
Short name T996
Test name
Test status
Simulation time 25747773315 ps
CPU time 56.49 seconds
Started Aug 04 05:19:41 PM PDT 24
Finished Aug 04 05:20:38 PM PDT 24
Peak memory 233192 kb
Host smart-65af78f9-6de6-40cb-b054-73a9f28354ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434903264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3434903264
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2484633470
Short name T691
Test name
Test status
Simulation time 103753120 ps
CPU time 2.55 seconds
Started Aug 04 05:19:47 PM PDT 24
Finished Aug 04 05:19:50 PM PDT 24
Peak memory 233140 kb
Host smart-2459dfe1-e2e2-4447-84c0-f656baf8c24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484633470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2484633470
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1364284183
Short name T667
Test name
Test status
Simulation time 2227145833 ps
CPU time 7.51 seconds
Started Aug 04 05:19:41 PM PDT 24
Finished Aug 04 05:19:49 PM PDT 24
Peak memory 224840 kb
Host smart-1c517930-e1f6-40a1-9a0a-354c7ef94858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364284183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1364284183
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3305338576
Short name T416
Test name
Test status
Simulation time 296092286 ps
CPU time 6.73 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 223552 kb
Host smart-2ad65c90-876d-403a-9ad6-4c170c18c4cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3305338576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3305338576
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4017366899
Short name T924
Test name
Test status
Simulation time 16661297152 ps
CPU time 15.73 seconds
Started Aug 04 05:19:48 PM PDT 24
Finished Aug 04 05:20:03 PM PDT 24
Peak memory 218536 kb
Host smart-e88fd5d3-0fd4-4638-bfb2-e6bd7dab2f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017366899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4017366899
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3481515608
Short name T760
Test name
Test status
Simulation time 6152098686 ps
CPU time 27.34 seconds
Started Aug 04 05:19:36 PM PDT 24
Finished Aug 04 05:20:04 PM PDT 24
Peak memory 216956 kb
Host smart-46cbd98c-e967-4113-a920-204a13bccd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481515608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3481515608
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1257496620
Short name T346
Test name
Test status
Simulation time 26089285145 ps
CPU time 17.29 seconds
Started Aug 04 05:19:36 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 216680 kb
Host smart-6866b514-b4e3-45e6-ae1a-3b5824271aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257496620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1257496620
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2030470031
Short name T309
Test name
Test status
Simulation time 81603608 ps
CPU time 0.92 seconds
Started Aug 04 05:19:44 PM PDT 24
Finished Aug 04 05:19:45 PM PDT 24
Peak memory 207600 kb
Host smart-480a3413-c900-4067-bf97-7acf54706f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030470031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2030470031
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2726400046
Short name T386
Test name
Test status
Simulation time 69805035 ps
CPU time 0.75 seconds
Started Aug 04 05:19:35 PM PDT 24
Finished Aug 04 05:19:35 PM PDT 24
Peak memory 206248 kb
Host smart-a12237cc-00a1-4c93-bec6-77f9b6b00d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726400046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2726400046
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.353865751
Short name T535
Test name
Test status
Simulation time 2802906345 ps
CPU time 11.61 seconds
Started Aug 04 05:19:47 PM PDT 24
Finished Aug 04 05:19:59 PM PDT 24
Peak memory 235904 kb
Host smart-b859ea36-96ed-4d02-9dac-e87a15189a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353865751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.353865751
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.4106444184
Short name T65
Test name
Test status
Simulation time 35787625 ps
CPU time 0.73 seconds
Started Aug 04 05:19:39 PM PDT 24
Finished Aug 04 05:19:40 PM PDT 24
Peak memory 206076 kb
Host smart-04db6110-5a72-4bf7-a20f-f1c3dce7bb85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106444184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.4
106444184
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.4197323678
Short name T491
Test name
Test status
Simulation time 403583710 ps
CPU time 2.61 seconds
Started Aug 04 05:19:39 PM PDT 24
Finished Aug 04 05:19:42 PM PDT 24
Peak memory 224960 kb
Host smart-a8168704-52b7-4fb4-ac0e-817560ebc1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197323678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4197323678
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.676911729
Short name T633
Test name
Test status
Simulation time 17460402 ps
CPU time 0.76 seconds
Started Aug 04 05:19:41 PM PDT 24
Finished Aug 04 05:19:42 PM PDT 24
Peak memory 206844 kb
Host smart-60859614-a888-49f6-96fb-822e3af4001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676911729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.676911729
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3510365725
Short name T894
Test name
Test status
Simulation time 42701587384 ps
CPU time 187.61 seconds
Started Aug 04 05:19:52 PM PDT 24
Finished Aug 04 05:23:00 PM PDT 24
Peak memory 257696 kb
Host smart-c78b504f-e4c7-48ef-84f2-2d688caaa942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510365725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3510365725
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4125248184
Short name T191
Test name
Test status
Simulation time 47346534680 ps
CPU time 253.5 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:24:05 PM PDT 24
Peak memory 252132 kb
Host smart-938c054e-1549-44f1-8953-3f89d44ca322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125248184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4125248184
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1326919712
Short name T45
Test name
Test status
Simulation time 2746251328 ps
CPU time 49.47 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:20:41 PM PDT 24
Peak memory 249884 kb
Host smart-0bee90e3-4ad5-453d-a300-7cb02bf004e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326919712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1326919712
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1484943222
Short name T481
Test name
Test status
Simulation time 174151766 ps
CPU time 6.17 seconds
Started Aug 04 05:19:43 PM PDT 24
Finished Aug 04 05:19:49 PM PDT 24
Peak memory 240068 kb
Host smart-e52113d2-0c53-4dcc-be83-0c19700fb4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484943222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1484943222
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3477059374
Short name T952
Test name
Test status
Simulation time 1337492405 ps
CPU time 2.36 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 224844 kb
Host smart-a38f4a59-d202-4ce6-99bf-5c3dd6028ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477059374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3477059374
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1089055319
Short name T224
Test name
Test status
Simulation time 468902657 ps
CPU time 6.63 seconds
Started Aug 04 05:19:44 PM PDT 24
Finished Aug 04 05:19:51 PM PDT 24
Peak memory 224856 kb
Host smart-a11b8be5-0d8e-4fd5-8350-48cb7bf13b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089055319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1089055319
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1260774786
Short name T789
Test name
Test status
Simulation time 101977283 ps
CPU time 2.43 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:19:56 PM PDT 24
Peak memory 223364 kb
Host smart-2221dd49-a778-413c-adb6-f1c47b0c7908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260774786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1260774786
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4091382927
Short name T939
Test name
Test status
Simulation time 21242184997 ps
CPU time 14.16 seconds
Started Aug 04 05:19:43 PM PDT 24
Finished Aug 04 05:19:57 PM PDT 24
Peak memory 233076 kb
Host smart-806f79d0-32ee-4249-8158-b3f2d7b9d8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091382927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4091382927
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3150992825
Short name T857
Test name
Test status
Simulation time 133097028 ps
CPU time 3.69 seconds
Started Aug 04 05:19:44 PM PDT 24
Finished Aug 04 05:19:48 PM PDT 24
Peak memory 220320 kb
Host smart-197bf12b-49ae-4c18-9c7b-e23e7692d50a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3150992825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3150992825
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.919578909
Short name T298
Test name
Test status
Simulation time 32480800894 ps
CPU time 32.75 seconds
Started Aug 04 05:19:48 PM PDT 24
Finished Aug 04 05:20:20 PM PDT 24
Peak memory 216704 kb
Host smart-46ceca7e-9840-4494-b352-fef3158de3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919578909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.919578909
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1655323380
Short name T661
Test name
Test status
Simulation time 2811814292 ps
CPU time 6.95 seconds
Started Aug 04 05:19:46 PM PDT 24
Finished Aug 04 05:19:53 PM PDT 24
Peak memory 216600 kb
Host smart-28cbbba4-b94b-4bc9-a484-0f2a256bad57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655323380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1655323380
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2787705830
Short name T845
Test name
Test status
Simulation time 529743821 ps
CPU time 3.81 seconds
Started Aug 04 05:19:41 PM PDT 24
Finished Aug 04 05:19:45 PM PDT 24
Peak memory 216672 kb
Host smart-2ce00f67-da49-4c40-94df-f361a27ae8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787705830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2787705830
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.575373868
Short name T369
Test name
Test status
Simulation time 69258212 ps
CPU time 0.75 seconds
Started Aug 04 05:19:43 PM PDT 24
Finished Aug 04 05:19:44 PM PDT 24
Peak memory 206340 kb
Host smart-0dc85346-b652-4bfd-846d-c38b9766d07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575373868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.575373868
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.4204651021
Short name T157
Test name
Test status
Simulation time 2058056613 ps
CPU time 6.14 seconds
Started Aug 04 05:19:39 PM PDT 24
Finished Aug 04 05:19:45 PM PDT 24
Peak memory 241280 kb
Host smart-9096aa0c-e506-4581-b28b-f9d52c86bad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204651021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4204651021
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2965747381
Short name T828
Test name
Test status
Simulation time 10894207 ps
CPU time 0.69 seconds
Started Aug 04 05:19:56 PM PDT 24
Finished Aug 04 05:19:57 PM PDT 24
Peak memory 205204 kb
Host smart-f870f581-4e4d-472c-853e-b8764efd85cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965747381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
965747381
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.191504262
Short name T782
Test name
Test status
Simulation time 41551833 ps
CPU time 2.62 seconds
Started Aug 04 05:19:48 PM PDT 24
Finished Aug 04 05:19:51 PM PDT 24
Peak memory 233100 kb
Host smart-b826b628-e137-4754-8389-9bb93bf8bf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191504262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.191504262
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3506796048
Short name T24
Test name
Test status
Simulation time 13261750 ps
CPU time 0.76 seconds
Started Aug 04 05:19:46 PM PDT 24
Finished Aug 04 05:19:47 PM PDT 24
Peak memory 206000 kb
Host smart-0956374c-f8ca-4bc4-8e03-72f91da4fe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506796048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3506796048
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1706689966
Short name T378
Test name
Test status
Simulation time 10728212797 ps
CPU time 76.42 seconds
Started Aug 04 05:19:44 PM PDT 24
Finished Aug 04 05:21:01 PM PDT 24
Peak memory 249600 kb
Host smart-2fd3e93a-7602-4f1d-80e9-2ad708748875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706689966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1706689966
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.302528623
Short name T854
Test name
Test status
Simulation time 5453277022 ps
CPU time 63.21 seconds
Started Aug 04 05:19:44 PM PDT 24
Finished Aug 04 05:20:48 PM PDT 24
Peak memory 252616 kb
Host smart-2c7b061a-6c6e-49fb-a4ec-1e5cc3bfd424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302528623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.302528623
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2513638020
Short name T843
Test name
Test status
Simulation time 51586090730 ps
CPU time 204.32 seconds
Started Aug 04 05:19:43 PM PDT 24
Finished Aug 04 05:23:08 PM PDT 24
Peak memory 257196 kb
Host smart-c1e1d9a4-0c6c-436d-b447-e868a7a20bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513638020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2513638020
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.208317935
Short name T291
Test name
Test status
Simulation time 119360918 ps
CPU time 6.37 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:20:03 PM PDT 24
Peak memory 233104 kb
Host smart-d7707aea-3414-41b0-8ef6-ba37c883dc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208317935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.208317935
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.597991804
Short name T611
Test name
Test status
Simulation time 69556664 ps
CPU time 0.81 seconds
Started Aug 04 05:19:41 PM PDT 24
Finished Aug 04 05:19:42 PM PDT 24
Peak memory 216296 kb
Host smart-c8f389a3-efb1-4c33-a483-cbde781a7cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597991804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
597991804
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2565031251
Short name T462
Test name
Test status
Simulation time 318289692 ps
CPU time 3.07 seconds
Started Aug 04 05:19:46 PM PDT 24
Finished Aug 04 05:19:50 PM PDT 24
Peak memory 224788 kb
Host smart-ee60da70-78bb-489e-9387-fa7b3a1c85fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565031251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2565031251
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2466650454
Short name T466
Test name
Test status
Simulation time 1567314174 ps
CPU time 7.06 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:57 PM PDT 24
Peak memory 224800 kb
Host smart-5c9d0dfe-5adf-4e74-98b5-d104d89eb5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466650454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2466650454
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.293419155
Short name T160
Test name
Test status
Simulation time 184180414 ps
CPU time 2.41 seconds
Started Aug 04 05:19:46 PM PDT 24
Finished Aug 04 05:19:49 PM PDT 24
Peak memory 232780 kb
Host smart-99615ab7-8863-4aa1-8d2a-22229b4ac17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293419155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
293419155
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1306069427
Short name T950
Test name
Test status
Simulation time 105889106 ps
CPU time 2.33 seconds
Started Aug 04 05:19:48 PM PDT 24
Finished Aug 04 05:19:51 PM PDT 24
Peak memory 224224 kb
Host smart-1b77412b-4980-4ca1-992f-109194a5d561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306069427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1306069427
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3239230989
Short name T851
Test name
Test status
Simulation time 304067028 ps
CPU time 5.14 seconds
Started Aug 04 05:19:37 PM PDT 24
Finished Aug 04 05:19:42 PM PDT 24
Peak memory 219744 kb
Host smart-cd5ffec0-53b5-4ca1-b006-8a226d03aed9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3239230989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3239230989
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1431273499
Short name T999
Test name
Test status
Simulation time 21952743290 ps
CPU time 174.66 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:22:49 PM PDT 24
Peak memory 257792 kb
Host smart-083e5ee2-0f6e-465a-a98a-deabc9659a61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431273499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1431273499
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4002240998
Short name T81
Test name
Test status
Simulation time 2554210425 ps
CPU time 6.24 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:19:57 PM PDT 24
Peak memory 217032 kb
Host smart-f2ee30a7-944b-47a1-acf6-9e90e903fda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002240998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4002240998
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.510131989
Short name T876
Test name
Test status
Simulation time 249929460 ps
CPU time 2.18 seconds
Started Aug 04 05:19:37 PM PDT 24
Finished Aug 04 05:19:39 PM PDT 24
Peak memory 216560 kb
Host smart-1dbfb581-2d32-4608-a8c0-8b1a672816f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510131989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.510131989
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1152650796
Short name T522
Test name
Test status
Simulation time 50870552 ps
CPU time 2.58 seconds
Started Aug 04 05:19:45 PM PDT 24
Finished Aug 04 05:19:48 PM PDT 24
Peak memory 216552 kb
Host smart-4f8a0c60-7a83-41a5-93e3-8c5b80246f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152650796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1152650796
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1738992886
Short name T82
Test name
Test status
Simulation time 183201244 ps
CPU time 0.88 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:19:55 PM PDT 24
Peak memory 206320 kb
Host smart-bae787ae-d95e-4801-a4c2-a62e964b823a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738992886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1738992886
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2130521282
Short name T469
Test name
Test status
Simulation time 28420987566 ps
CPU time 7.75 seconds
Started Aug 04 05:19:37 PM PDT 24
Finished Aug 04 05:19:44 PM PDT 24
Peak memory 233252 kb
Host smart-e8b6a299-6b9c-4ba9-93b0-bbea93041287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130521282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2130521282
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1772388399
Short name T688
Test name
Test status
Simulation time 20948736 ps
CPU time 0.7 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:19:55 PM PDT 24
Peak memory 205732 kb
Host smart-910e4940-217f-4e18-874c-55d39960fedd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772388399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
772388399
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.482478828
Short name T506
Test name
Test status
Simulation time 1792085086 ps
CPU time 16.08 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:20:07 PM PDT 24
Peak memory 233144 kb
Host smart-909ddbc0-57ff-42e7-9006-c07c41ef4233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482478828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.482478828
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.507598415
Short name T977
Test name
Test status
Simulation time 30356859 ps
CPU time 0.77 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:50 PM PDT 24
Peak memory 205872 kb
Host smart-dcc4453a-9f74-4652-a28e-35a1c08683e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507598415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.507598415
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.378527980
Short name T870
Test name
Test status
Simulation time 51173390694 ps
CPU time 103.6 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:21:34 PM PDT 24
Peak memory 249512 kb
Host smart-d610aaf4-78d7-4bdc-9b15-e79af3e6bb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378527980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.378527980
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3661646529
Short name T629
Test name
Test status
Simulation time 87967595322 ps
CPU time 176.56 seconds
Started Aug 04 05:19:48 PM PDT 24
Finished Aug 04 05:22:45 PM PDT 24
Peak memory 257756 kb
Host smart-728ac1a2-21b5-44bb-9ec2-ba551df341b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661646529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3661646529
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3803380048
Short name T803
Test name
Test status
Simulation time 23843884680 ps
CPU time 81.53 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:21:15 PM PDT 24
Peak memory 249604 kb
Host smart-d59356e8-01d3-4d04-b618-26c89985ffca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803380048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3803380048
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3915445587
Short name T792
Test name
Test status
Simulation time 586726997 ps
CPU time 6.73 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:20:08 PM PDT 24
Peak memory 234524 kb
Host smart-de03c798-1526-47fc-a9ef-7f6a47700a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915445587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3915445587
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3297509226
Short name T241
Test name
Test status
Simulation time 6422504698 ps
CPU time 26.75 seconds
Started Aug 04 05:19:57 PM PDT 24
Finished Aug 04 05:20:24 PM PDT 24
Peak memory 234248 kb
Host smart-69a74d3b-bf60-418c-948c-dfa5e3d224e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297509226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3297509226
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3623477200
Short name T231
Test name
Test status
Simulation time 190357077 ps
CPU time 2.54 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:19:56 PM PDT 24
Peak memory 224816 kb
Host smart-c2112ad3-aa99-4395-82ad-8963ab7be9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623477200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3623477200
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.237833174
Short name T518
Test name
Test status
Simulation time 739261955 ps
CPU time 8.79 seconds
Started Aug 04 05:19:48 PM PDT 24
Finished Aug 04 05:19:57 PM PDT 24
Peak memory 241024 kb
Host smart-38524aa3-281e-43c8-b873-84f5a0e6ef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237833174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.237833174
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1528407351
Short name T254
Test name
Test status
Simulation time 534486265 ps
CPU time 2.54 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 224812 kb
Host smart-f18bbb75-38aa-4260-8ce9-2d700e493192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528407351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1528407351
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2209379369
Short name T196
Test name
Test status
Simulation time 6386560567 ps
CPU time 20.77 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:20:16 PM PDT 24
Peak memory 241116 kb
Host smart-92712c97-6a0e-43eb-ac55-ebc69885f56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209379369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2209379369
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2420022411
Short name T835
Test name
Test status
Simulation time 343989546 ps
CPU time 3.96 seconds
Started Aug 04 05:19:44 PM PDT 24
Finished Aug 04 05:19:48 PM PDT 24
Peak memory 222920 kb
Host smart-21dd96bc-3fc1-4750-90fe-ce04d6ee3c23
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2420022411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2420022411
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1588683126
Short name T544
Test name
Test status
Simulation time 287339147476 ps
CPU time 562.79 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:29:21 PM PDT 24
Peak memory 256916 kb
Host smart-0bb853da-eb2b-45e7-b4d5-0c2eb6380ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588683126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1588683126
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3491483062
Short name T308
Test name
Test status
Simulation time 524277376 ps
CPU time 5.69 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:19:57 PM PDT 24
Peak memory 216412 kb
Host smart-0cf64f49-d6d3-49b0-8779-107c217f3dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491483062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3491483062
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2834789390
Short name T960
Test name
Test status
Simulation time 7278111985 ps
CPU time 20.49 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:13 PM PDT 24
Peak memory 216708 kb
Host smart-92f898dc-0596-4e13-a38c-327421c43ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834789390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2834789390
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3736093810
Short name T595
Test name
Test status
Simulation time 40563509 ps
CPU time 1.06 seconds
Started Aug 04 05:20:01 PM PDT 24
Finished Aug 04 05:20:02 PM PDT 24
Peak memory 207600 kb
Host smart-bd4183bb-a638-40c3-8516-a5637441a722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736093810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3736093810
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4022494977
Short name T325
Test name
Test status
Simulation time 112208915 ps
CPU time 0.81 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:19:55 PM PDT 24
Peak memory 206404 kb
Host smart-45ce2413-1309-4bbb-9c5a-6a3a392cb3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022494977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4022494977
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2276468740
Short name T561
Test name
Test status
Simulation time 37824298349 ps
CPU time 51.79 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:20:45 PM PDT 24
Peak memory 238716 kb
Host smart-b41b4c12-143a-4cfc-916e-79175adffbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276468740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2276468740
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4286218001
Short name T1008
Test name
Test status
Simulation time 15713162 ps
CPU time 0.72 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:19:51 PM PDT 24
Peak memory 205200 kb
Host smart-1eaeff38-cd7c-4d72-aaa9-b82d0e145cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286218001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
286218001
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3269094436
Short name T84
Test name
Test status
Simulation time 968709942 ps
CPU time 4.46 seconds
Started Aug 04 05:19:55 PM PDT 24
Finished Aug 04 05:20:00 PM PDT 24
Peak memory 224900 kb
Host smart-4159478f-b943-4845-94b5-07e4a1e84530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269094436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3269094436
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.919199376
Short name T686
Test name
Test status
Simulation time 24290845 ps
CPU time 0.8 seconds
Started Aug 04 05:19:43 PM PDT 24
Finished Aug 04 05:19:44 PM PDT 24
Peak memory 207000 kb
Host smart-6834b872-ca95-416f-b4d4-3e134d06d4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919199376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.919199376
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1471945292
Short name T817
Test name
Test status
Simulation time 22027459865 ps
CPU time 176.18 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:22:46 PM PDT 24
Peak memory 256428 kb
Host smart-510c2b6f-c44e-4dc2-9589-32150433c224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471945292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1471945292
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.575309513
Short name T980
Test name
Test status
Simulation time 66091807148 ps
CPU time 293.59 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:24:45 PM PDT 24
Peak memory 265956 kb
Host smart-67c85e70-6c71-4b55-9cfa-cffd6afb41ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575309513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
575309513
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3006363003
Short name T510
Test name
Test status
Simulation time 190072668 ps
CPU time 4.25 seconds
Started Aug 04 05:19:53 PM PDT 24
Finished Aug 04 05:19:57 PM PDT 24
Peak memory 224908 kb
Host smart-d8f04f53-e1a2-4484-ac2a-115c5ea6a39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006363003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3006363003
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.159529954
Short name T729
Test name
Test status
Simulation time 10694624574 ps
CPU time 61.13 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:20:52 PM PDT 24
Peak memory 255664 kb
Host smart-67eba057-7786-4340-8a12-69be7a35eca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159529954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
159529954
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1627928262
Short name T642
Test name
Test status
Simulation time 7059072826 ps
CPU time 20.7 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:20:12 PM PDT 24
Peak memory 224868 kb
Host smart-77207915-2e38-4acf-a72e-fdb2e54a0e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627928262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1627928262
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4250531905
Short name T502
Test name
Test status
Simulation time 2764159142 ps
CPU time 25.76 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:20:16 PM PDT 24
Peak memory 233232 kb
Host smart-27b87283-a066-4928-8a2d-d7817e5e01e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250531905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4250531905
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3676667777
Short name T745
Test name
Test status
Simulation time 1441226433 ps
CPU time 4.47 seconds
Started Aug 04 05:19:47 PM PDT 24
Finished Aug 04 05:19:52 PM PDT 24
Peak memory 224936 kb
Host smart-f5f77918-61a9-429b-bcec-1d38b752cb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676667777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3676667777
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1968252264
Short name T320
Test name
Test status
Simulation time 166998978 ps
CPU time 2.26 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:19:52 PM PDT 24
Peak memory 232840 kb
Host smart-78b3a48a-04df-4f6c-af74-83a7a65b8f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968252264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1968252264
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1192931927
Short name T874
Test name
Test status
Simulation time 271285669 ps
CPU time 4.62 seconds
Started Aug 04 05:19:49 PM PDT 24
Finished Aug 04 05:19:54 PM PDT 24
Peak memory 219540 kb
Host smart-62c947f3-5dd9-4ad1-8f0d-fa6c22b54cac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1192931927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1192931927
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3821548129
Short name T62
Test name
Test status
Simulation time 16972660 ps
CPU time 0.75 seconds
Started Aug 04 05:20:00 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 206236 kb
Host smart-aaa3126c-9d00-48ff-af17-6914cbf42ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821548129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3821548129
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1111031833
Short name T565
Test name
Test status
Simulation time 4473673406 ps
CPU time 7.3 seconds
Started Aug 04 05:19:54 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 216712 kb
Host smart-f3175f8d-a8d7-47e9-a213-51a706161e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111031833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1111031833
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2730147182
Short name T335
Test name
Test status
Simulation time 1597020702 ps
CPU time 14.31 seconds
Started Aug 04 05:19:51 PM PDT 24
Finished Aug 04 05:20:05 PM PDT 24
Peak memory 216548 kb
Host smart-5e837752-56fe-481b-8b29-87f26fe71379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730147182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2730147182
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3194865875
Short name T511
Test name
Test status
Simulation time 51612094 ps
CPU time 0.81 seconds
Started Aug 04 05:19:50 PM PDT 24
Finished Aug 04 05:19:52 PM PDT 24
Peak memory 206248 kb
Host smart-8ebf0729-c67e-4cd8-92a8-d1b961a2737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194865875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3194865875
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3903475114
Short name T940
Test name
Test status
Simulation time 9596431749 ps
CPU time 28.41 seconds
Started Aug 04 05:19:58 PM PDT 24
Finished Aug 04 05:20:26 PM PDT 24
Peak memory 236040 kb
Host smart-7592a437-c31b-4377-a3c8-e367f2be890e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903475114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3903475114
Directory /workspace/9.spi_device_upload/latest
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