Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2364053	1			T1	25897		T2	1		T3	7130
all_values[1]	2364053	1			T1	25897		T2	1		T3	7130
all_values[2]	2364053	1			T1	25897		T2	1		T3	7130
all_values[3]	2364053	1			T1	25897		T2	1		T3	7130
all_values[4]	2364053	1			T1	25897		T2	1		T3	7130
all_values[5]	2364053	1			T1	25897		T2	1		T3	7130
all_values[6]	2364053	1			T1	25897		T2	1		T3	7130
all_values[7]	2364053	1			T1	25897		T2	1		T3	7130

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18122891

1

T1

180574

T2

8

T3

57040

auto[1]

789533

1

T1

26602

T20

12

T21

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18889051

1

T1

206726

T2

8

T3

57040

auto[1]

23373

1

T1

450

T7

219

T20

810

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2240417	1			T1	25666		T2	1		T3	7130
all_values[0]	auto[0]	auto[1]	10496	1			T1	230		T7	92		T20	424
all_values[0]	auto[1]	auto[0]	112455	1			T20	1		T21	2		T22	9
all_values[0]	auto[1]	auto[1]	685	1			T1	1		T26	3		T27	1
all_values[1]	auto[0]	auto[0]	2260813	1			T1	19086		T2	1		T3	7130
all_values[1]	auto[0]	auto[1]	6502	1			T1	161		T7	88		T20	257
all_values[1]	auto[1]	auto[0]	96272	1			T1	6647		T21	2		T22	3
all_values[1]	auto[1]	auto[1]	466	1			T1	3		T22	1		T26	2
all_values[2]	auto[0]	auto[0]	2279483	1			T1	19201		T2	1		T3	7130
all_values[2]	auto[0]	auto[1]	2847	1			T1	47		T7	39		T20	120
all_values[2]	auto[1]	auto[0]	81456	1			T1	6647		T20	1		T21	2
all_values[2]	auto[1]	auto[1]	267	1			T1	2		T21	1		T22	2
all_values[3]	auto[0]	auto[0]	2236808	1			T1	19246		T2	1		T3	7130
all_values[3]	auto[0]	auto[1]	228	1			T1	2		T20	3		T21	1
all_values[3]	auto[1]	auto[0]	126780	1			T1	6649		T20	1		T22	2
all_values[3]	auto[1]	auto[1]	237	1			T22	1		T26	1		T28	4
all_values[4]	auto[0]	auto[0]	2294311	1			T1	25896		T2	1		T3	7130
all_values[4]	auto[0]	auto[1]	214	1			T140	1		T27	2		T28	7
all_values[4]	auto[1]	auto[0]	69328	1			T21	1		T22	3		T26	3
all_values[4]	auto[1]	auto[1]	200	1			T1	1		T20	1		T22	1
all_values[5]	auto[0]	auto[0]	2285746	1			T1	25894		T2	1		T3	7130
all_values[5]	auto[0]	auto[1]	209	1			T1	2		T20	1		T21	1
all_values[5]	auto[1]	auto[0]	77913	1			T21	1		T22	10		T26	3
all_values[5]	auto[1]	auto[1]	185	1			T1	1		T20	1		T22	2
all_values[6]	auto[0]	auto[0]	2287686	1			T1	19248		T2	1		T3	7130
all_values[6]	auto[0]	auto[1]	217	1			T20	2		T22	7		T26	3
all_values[6]	auto[1]	auto[0]	75958	1			T1	6649		T21	3		T22	1
all_values[6]	auto[1]	auto[1]	192	1			T20	1		T21	1		T22	2
all_values[7]	auto[0]	auto[0]	2216709	1			T1	25895		T2	1		T3	7130
all_values[7]	auto[0]	auto[1]	205	1			T22	3		T26	6		T28	2
all_values[7]	auto[1]	auto[0]	146916	1			T1	2		T20	6		T21	1
all_values[7]	auto[1]	auto[1]	223	1			T22	2		T26	2		T27	6