Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34922	1			T1	332		T2	6		T7	275
auto[SpiFlashAddrCfg]	7282	1			T1	119		T7	52		T11	2
auto[SpiFlashAddr3b]	9087	1			T1	168		T2	6		T7	52
auto[SpiFlashAddr4b]	7445	1			T1	102		T7	31		T11	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33162

1

T1

384

T2

12

T7

274

auto[1]

25574

1

T1

337

T7

136

T13

90

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30954

1

T1

399

T2

6

T7

211

auto[1]

27782

1

T1

322

T2

6

T7

199

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39374	1			T1	403		T2	6		T7	299
values[1]	1067	1			T1	9		T7	4		T12	4
values[2]	1472	1			T1	30		T7	4		T13	6
values[3]	1511	1			T1	29		T2	2		T7	15
values[4]	1353	1			T1	42		T7	8		T13	5
values[5]	1385	1			T1	26		T7	10		T13	6
values[6]	1391	1			T1	25		T7	9		T13	1
values[7]	1351	1			T1	13		T2	2		T7	4
values[8]	9832	1			T1	144		T2	2		T7	57

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30516

1

T1

721

T2

12

T11

14

auto[1]

28220

1

T7

410

T13

220

T39

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55610

1

T1

694

T2

12

T7

379

write

3126

1

T1

27

T7

31

T13

17

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19013

1

T1

336

T2

8

T7

111

valids[0x1]

39723

1

T1

385

T2

4

T7

299

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1522	1			T1	17		T7	6		T12	2
internal_process_ops[0x5a]	1528	1			T1	19		T7	8		T11	2
internal_process_ops[0x05]	21286	1			T1	147		T7	180		T12	2
internal_process_ops[0x35]	1478	1			T1	23		T2	2		T7	7
internal_process_ops[0x15]	1542	1			T1	16		T7	9		T13	12
internal_process_ops[0x03]	922	1			T1	16		T7	4		T13	2
internal_process_ops[0x0b]	988	1			T1	15		T7	2		T13	4
internal_process_ops[0x3b]	986	1			T1	20		T2	2		T11	4
internal_process_ops[0x6b]	1100	1			T1	23		T7	4		T13	1
internal_process_ops[0xbb]	1024	1			T1	37		T12	4		T13	1
internal_process_ops[0xeb]	1030	1			T1	25		T7	3		T13	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57137

1

T1

709

T2

12

T7

398

auto[1]

1599

1

T1

12

T7

12

T13

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56475

1

T1

699

T2

12

T7

387

auto[1]

2261

1

T1

22

T7

23

T13

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10274

1

T1

171

T2

6

T11

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6406

1

T1

153

T16

2

T18

14

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1983

1

T1

65

T11

2

T12

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1804

1

T1

48

T18

7

T165

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2472

1

T1

86

T2

6

T11

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2133

1

T1

77

T18

4

T34

24

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2098

1

T1

49

T11

4

T18

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1812

1

T1

45

T18

2

T165

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

136

1

T1

3

T94

2

T40

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

120

1

T1

3

T34

3

T35

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

68

1

T34

2

T44

1

T46

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T1

2

T43

2

T35

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

108

1

T1

1

T41

2

T43

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

93

1

T1

2

T35

1

T46

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

84

1

T1

3

T47

1

T166

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

99

1

T18

1

T34

1

T43

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

90

1

T42

4

T34

1

T43

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

108

1

T34

4

T43

1

T44

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

96

1

T1

4

T34

3

T35

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

99

1

T1

1

T16

2

T35

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

87

1

T1

1

T18

1

T44

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

73

1

T1

3

T43

2

T45

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

97

1

T1

3

T35

3

T44

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

86

1

T1

1

T43

4

T35

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10134

1

T7

195

T13

58

T20

91

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7298

1

T7

67

T13

28

T20

67

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1369

1

T7

19

T13

19

T20

16

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1401

1

T7

23

T13

18

T20

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1800

1

T7

25

T13

27

T39

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1816

1

T7

20

T13

20

T20

32

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1402

1

T7

15

T13

17

T20

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1408

1

T7

15

T13

16

T20

21

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

98

1

T7

4

T20

1

T50

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

113

1

T7

2

T50

6

T51

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

64

1

T7

5

T20

2

T50

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

121

1

T7

2

T20

2

T50

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

77

1

T7

4

T20

1

T52

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

80

1

T7

5

T20

3

T50

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

98

1

T51

2

T92

1

T93

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

86

1

T7

1

T13

4

T20

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

130

1

T7

3

T13

2

T20

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

135

1

T7

2

T13

1

T20

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

104

1

T7

2

T13

3

T50

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

104

1

T13

1

T20

1

T167

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

96

1

T13

3

T50

3

T52

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

86

1

T13

3

T51

2

T93

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

94

1

T7

1

T20

1

T92

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

106

1

T50

3

T51

6

T92

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3776	1			T1	124		T2	4		T11	4
auto[0]	values[0]	valids[0x1]	15745	1			T1	279		T2	2		T11	4
auto[0]	values[1]	valids[0x1]	525	1			T1	9		T12	4		T18	1
auto[0]	values[2]	valids[0x0]	607	1			T1	17		T18	1		T87	6
auto[0]	values[2]	valids[0x1]	301	1			T1	13		T34	5		T35	4
auto[0]	values[3]	valids[0x0]	533	1			T1	19		T11	2		T18	1
auto[0]	values[3]	valids[0x1]	289	1			T1	10		T2	2		T41	2
auto[0]	values[4]	valids[0x0]	477	1			T1	27		T18	1		T165	6
auto[0]	values[4]	valids[0x1]	274	1			T1	15		T34	2		T43	1
auto[0]	values[5]	valids[0x0]	529	1			T1	18		T18	4		T41	2
auto[0]	values[5]	valids[0x1]	265	1			T1	8		T35	1		T153	1
auto[0]	values[6]	valids[0x0]	508	1			T1	17		T18	1		T34	4
auto[0]	values[6]	valids[0x1]	292	1			T1	8		T34	2		T43	1
auto[0]	values[7]	valids[0x0]	461	1			T1	12		T2	2		T18	1
auto[0]	values[7]	valids[0x1]	284	1			T1	1		T12	2		T40	2
auto[0]	values[8]	valids[0x0]	3675	1			T1	102		T2	2		T11	4
auto[0]	values[8]	valids[0x1]	1975	1			T1	42		T16	2		T18	4
auto[1]	values[0]	valids[0x0]	3822	1			T7	56		T13	54		T20	64
auto[1]	values[0]	valids[0x1]	16031	1			T7	243		T13	71		T20	126
auto[1]	values[1]	valids[0x1]	542	1			T7	4		T13	2		T20	6
auto[1]	values[2]	valids[0x0]	331	1			T7	2		T13	5		T20	7
auto[1]	values[2]	valids[0x1]	233	1			T7	2		T13	1		T20	5
auto[1]	values[3]	valids[0x0]	403	1			T7	10		T13	2		T20	3
auto[1]	values[3]	valids[0x1]	286	1			T7	5		T13	5		T20	15
auto[1]	values[4]	valids[0x0]	335	1			T7	3		T13	2		T20	5
auto[1]	values[4]	valids[0x1]	267	1			T7	5		T13	3		T20	5
auto[1]	values[5]	valids[0x0]	376	1			T7	2		T13	3		T20	4
auto[1]	values[5]	valids[0x1]	215	1			T7	8		T13	3		T20	2
auto[1]	values[6]	valids[0x0]	360	1			T7	4		T20	5		T50	1
auto[1]	values[6]	valids[0x1]	231	1			T7	5		T13	1		T20	2
auto[1]	values[7]	valids[0x0]	387	1			T7	4		T13	5		T20	4
auto[1]	values[7]	valids[0x1]	219	1			T13	3		T20	5		T50	3
auto[1]	values[8]	valids[0x0]	2433	1			T7	30		T13	35		T36	1
auto[1]	values[8]	valids[0x1]	1749	1			T7	27		T13	25		T39	1