Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3172035

1

T1

40155

T2

1

T7

10117

auto[1]

28584

1

T1

121

T7

170

T13

76

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

893738

1

T1

148

T2

1

T7

88

auto[1]

2306881

1

T1

40128

T7

10199

T11

8

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	595202	1			T1	1764		T2	1		T7	2362
auto[524288:1048575]	364342	1			T1	11824		T7	795		T13	1108
auto[1048576:1572863]	378228	1			T1	2701		T7	2282		T13	220
auto[1572864:2097151]	375230	1			T1	4788		T7	791		T13	275
auto[2097152:2621439]	421572	1			T1	8112		T7	421		T13	5521
auto[2621440:3145727]	355708	1			T1	5904		T7	2238		T13	620
auto[3145728:3670015]	374854	1			T1	4387		T7	734		T13	2181
auto[3670016:4194303]	335483	1			T1	796		T7	664		T13	18

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2339745

1

T1

40274

T2

1

T7

10276

auto[1]

860874

1

T1

2

T7

11

T13

9

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2760864

1

T1

34168

T2

1

T7

9295

auto[1]

439755

1

T1

6108

T7

992

T13

2529

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	175259	1			T1	6		T2	1		T7	3
auto[0]	auto[0]	auto[0:524287]	auto[1]	350775	1			T1	1757		T7	1924		T11	8
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	82871	1			T1	27		T7	5		T13	44
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	226818	1			T1	8967		T7	770		T13	1019
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	105615	1			T1	8		T7	9		T13	83
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	211538	1			T1	2431		T7	2271		T13	128
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	77462	1			T1	7		T7	7		T13	19
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	226265	1			T1	4762		T7	774		T13	256
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	112019	1			T1	11		T7	8		T13	30
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	247444	1			T1	5286		T7	391		T13	3066
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	104367	1			T1	24		T7	1		T13	22
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	212652	1			T1	5868		T7	2189		T13	594
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	120177	1			T1	17		T7	2		T13	72
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	201603	1			T1	4349		T7	313		T13	2071
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	94528	1			T1	8		T7	6		T13	16
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	187620	1			T1	521		T7	514		T13	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	3588	1			T7	7		T13	42		T20	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	61765	1			T7	385		T13	4		T20	634
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1595	1			T1	3		T13	21		T20	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	49829	1			T1	2757		T13	5		T34	1139
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1860	1			T1	3		T13	9		T20	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	56000	1			T1	256		T20	7		T50	896
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1406	1			T1	2		T7	4		T20	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	66791	1			T1	5		T7	2		T20	128
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	3600	1			T1	3		T13	31		T14	44
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	54565	1			T1	2809		T13	2380		T52	2781
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1877	1			T1	1		T7	2		T13	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	32521	1			T7	2		T20	3		T52	1097
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2368	1			T1	2		T7	10		T13	11
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	47063	1			T1	1		T7	389		T20	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1614	1			T1	4		T7	1		T20	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	48580	1			T1	260		T7	128		T20	2415
auto[1]	auto[0]	auto[0:524287]	auto[0]	429	1			T1	1		T7	2		T13	5
auto[1]	auto[0]	auto[0:524287]	auto[1]	2806	1			T7	24		T20	1		T50	17
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	358	1			T1	6		T7	2		T13	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2328	1			T1	64		T7	18		T13	13
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	349	1			T1	2		T7	2		T18	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2040	1			T1	1		T18	77		T20	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	379	1			T1	2		T7	1		T20	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2270	1			T1	10		T20	3		T51	59
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	345	1			T1	1		T7	2		T13	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3211	1			T1	2		T7	20		T20	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	297	1			T1	4		T7	1		T20	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3624	1			T1	7		T7	12		T51	13
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	314	1			T1	4		T7	1		T13	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2553	1			T1	12		T7	8		T13	24
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	361	1			T1	1		T7	2		T20	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2187	1			T1	2		T7	13		T50	51
auto[1]	auto[1]	auto[0:524287]	auto[0]	82	1			T7	1		T13	6		T20	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	498	1			T7	16		T13	5		T20	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	58	1			T13	3		T92	5		T21	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	485	1			T92	194		T21	2		T226	22
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	131	1			T20	2		T34	1		T43	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	695	1			T20	1		T43	32		T178	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	95	1			T7	2		T45	1		T92	33
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	562	1			T7	1		T45	20		T92	110
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	75	1			T13	8		T52	25		T45	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	313	1			T45	1		T77	42		T188	11
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	83	1			T7	2		T20	3		T52	9
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	287	1			T7	29		T20	5		T194	33
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	79	1			T1	1		T7	5		T20	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	697	1			T1	1		T7	6		T20	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	97	1			T20	1		T77	1		T26	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	496	1			T77	26		T26	1		T27	11

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1890002	1			T1	34049		T2	1		T7	9184
auto[0]	auto[0]	auto[1]	847011	1			T7	3		T14	229		T18	2
auto[0]	auto[1]	auto[0]	421841	1			T1	6106		T7	928		T13	2507
auto[0]	auto[1]	auto[1]	13181	1			T7	2		T14	42		T43	1
auto[1]	auto[0]	auto[0]	23308	1			T1	117		T7	103		T13	50
auto[1]	auto[0]	auto[1]	543	1			T1	2		T7	5		T13	4
auto[1]	auto[1]	auto[0]	4594	1			T1	2		T7	61		T13	17
auto[1]	auto[1]	auto[1]	139	1			T7	1		T13	5		T43	1