Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2364053	1			T1	25897		T2	1		T3	7130
all_pins[1]	2364053	1			T1	25897		T2	1		T3	7130
all_pins[2]	2364053	1			T1	25897		T2	1		T3	7130
all_pins[3]	2364053	1			T1	25897		T2	1		T3	7130
all_pins[4]	2364053	1			T1	25897		T2	1		T3	7130
all_pins[5]	2364053	1			T1	25897		T2	1		T3	7130
all_pins[6]	2364053	1			T1	25897		T2	1		T3	7130
all_pins[7]	2364053	1			T1	25897		T2	1		T3	7130

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18833645	1			T1	200533		T2	8		T3	57040
values[0x1]	78779	1			T1	6643		T20	3		T21	2
transitions[0x0=>0x1]	78252	1			T1	6639		T20	3		T21	2
transitions[0x1=>0x0]	78265	1			T1	6639		T20	3		T21	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2363308	1			T1	25896		T2	1		T3	7130
all_pins[0]	values[0x1]	745	1			T1	1		T26	3		T27	1
all_pins[0]	transitions[0x0=>0x1]	594	1			T26	3		T27	1		T28	5
all_pins[0]	transitions[0x1=>0x0]	339	1			T1	5		T22	1		T26	2
all_pins[1]	values[0x0]	2363563	1			T1	25891		T2	1		T3	7130
all_pins[1]	values[0x1]	490	1			T1	6		T22	1		T26	2
all_pins[1]	transitions[0x0=>0x1]	403	1			T1	4		T22	1		T26	2
all_pins[1]	transitions[0x1=>0x0]	189	1			T21	1		T22	2		T26	5
all_pins[2]	values[0x0]	2363777	1			T1	25895		T2	1		T3	7130
all_pins[2]	values[0x1]	276	1			T1	2		T21	1		T22	2
all_pins[2]	transitions[0x0=>0x1]	221	1			T1	2		T21	1		T22	2
all_pins[2]	transitions[0x1=>0x0]	182	1			T22	1		T26	1		T29	3
all_pins[3]	values[0x0]	2363816	1			T1	25897		T2	1		T3	7130
all_pins[3]	values[0x1]	237	1			T22	1		T26	1		T28	4
all_pins[3]	transitions[0x0=>0x1]	179	1			T22	1		T26	1		T28	2
all_pins[3]	transitions[0x1=>0x0]	142	1			T1	1		T20	1		T22	1
all_pins[4]	values[0x0]	2363853	1			T1	25896		T2	1		T3	7130
all_pins[4]	values[0x1]	200	1			T1	1		T20	1		T22	1
all_pins[4]	transitions[0x0=>0x1]	163	1			T20	1		T22	1		T26	2
all_pins[4]	transitions[0x1=>0x0]	974	1			T20	1		T22	2		T26	2
all_pins[5]	values[0x0]	2363042	1			T1	25896		T2	1		T3	7130
all_pins[5]	values[0x1]	1011	1			T1	1		T20	1		T22	2
all_pins[5]	transitions[0x0=>0x1]	978	1			T1	1		T20	1		T22	2
all_pins[5]	transitions[0x1=>0x0]	75564	1			T1	6632		T20	1		T21	1
all_pins[6]	values[0x0]	2288456	1			T1	19265		T2	1		T3	7130
all_pins[6]	values[0x1]	75597	1			T1	6632		T20	1		T21	1
all_pins[6]	transitions[0x0=>0x1]	75545	1			T1	6632		T20	1		T21	1
all_pins[6]	transitions[0x1=>0x0]	171	1			T22	1		T26	1		T27	3
all_pins[7]	values[0x0]	2363830	1			T1	25897		T2	1		T3	7130
all_pins[7]	values[0x1]	223	1			T22	2		T26	2		T27	6
all_pins[7]	transitions[0x0=>0x1]	169	1			T22	2		T26	1		T27	5
all_pins[7]	transitions[0x1=>0x0]	704	1			T1	1		T26	2		T28	3