Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17642

1

T1

384

T2

12

T11

14

auto[1]

12874

1

T1

337

T16

4

T18

28

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3638	1			T1	108		T41	26		T34	45
values[1]	3916	1			T1	53		T2	12		T12	14
values[2]	3700	1			T1	131		T86	20		T165	8
values[3]	4400	1			T1	169		T16	4		T142	4
values[4]	3854	1			T1	60		T18	34		T94	12
values[5]	3710	1			T1	85		T34	62		T43	49
values[6]	3871	1			T1	23		T14	4		T18	88
values[7]	3427	1			T1	92		T11	14		T116	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3790	1			T1	72		T86	20		T34	25
values[1]	3923	1			T1	127		T18	34		T34	22
values[2]	4104	1			T1	101		T14	4		T94	12
values[3]	3907	1			T1	55		T34	44		T44	20
values[4]	3787	1			T1	135		T2	12		T11	14
values[5]	3404	1			T1	88		T16	4		T18	88
values[6]	3438	1			T1	80		T12	14		T116	8
values[7]	4163	1			T1	63		T142	4		T95	4

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	372	1			T34	6		T43	8		T45	36
auto[0]	values[0]	values[1]	202	1			T1	33		T26	15		T186	17
auto[0]	values[0]	values[2]	329	1			T1	6		T45	37		T77	6
auto[0]	values[0]	values[3]	323	1			T77	73		T166	14		T199	9
auto[0]	values[0]	values[4]	132	1			T1	19		T47	13		T227	20
auto[0]	values[0]	values[5]	386	1			T178	6		T194	12		T186	12
auto[0]	values[0]	values[6]	161	1			T228	2		T182	10		T204	2
auto[0]	values[0]	values[7]	277	1			T41	26		T34	12		T229	12
auto[0]	values[1]	values[0]	311	1			T1	13		T45	43		T27	22
auto[0]	values[1]	values[1]	295	1			T44	15		T46	8		T202	16
auto[0]	values[1]	values[2]	258	1			T1	28		T40	18		T35	61
auto[0]	values[1]	values[3]	226	1			T77	22		T199	11		T203	5
auto[0]	values[1]	values[4]	255	1			T2	12		T18	14		T43	14
auto[0]	values[1]	values[5]	291	1			T45	13		T182	21		T230	12
auto[0]	values[1]	values[6]	218	1			T12	14		T46	9		T231	12
auto[0]	values[1]	values[7]	288	1			T35	15		T166	15		T208	15
auto[0]	values[2]	values[0]	119	1			T86	20		T46	11		T194	16
auto[0]	values[2]	values[1]	271	1			T186	7		T146	13		T166	15
auto[0]	values[2]	values[2]	258	1			T232	6		T45	25		T195	14
auto[0]	values[2]	values[3]	390	1			T1	15		T195	13		T77	19
auto[0]	values[2]	values[4]	376	1			T1	22		T47	14		T199	12
auto[0]	values[2]	values[5]	338	1			T1	40		T35	44		T217	39
auto[0]	values[2]	values[6]	130	1			T34	11		T44	11		T45	13
auto[0]	values[2]	values[7]	215	1			T45	24		T183	12		T233	9
auto[0]	values[3]	values[0]	208	1			T1	11		T215	10		T234	10
auto[0]	values[3]	values[1]	268	1			T1	26		T235	4		T236	4
auto[0]	values[3]	values[2]	418	1			T45	38		T46	11		T237	10
auto[0]	values[3]	values[3]	215	1			T1	13		T238	4		T77	11
auto[0]	values[3]	values[4]	388	1			T87	16		T44	13		T217	9
auto[0]	values[3]	values[5]	221	1			T205	20		T182	11		T197	22
auto[0]	values[3]	values[6]	457	1			T1	23		T45	16		T26	34
auto[0]	values[3]	values[7]	340	1			T142	4		T43	104		T223	8
auto[0]	values[4]	values[0]	339	1			T47	24		T190	13		T180	14
auto[0]	values[4]	values[1]	219	1			T18	22		T35	15		T47	25
auto[0]	values[4]	values[2]	219	1			T94	12		T239	6		T225	6
auto[0]	values[4]	values[3]	347	1			T195	10		T240	2		T241	6
auto[0]	values[4]	values[4]	332	1			T1	6		T46	9		T77	67
auto[0]	values[4]	values[5]	150	1			T1	9		T46	13		T242	16
auto[0]	values[4]	values[6]	193	1			T1	9		T35	12		T44	12
auto[0]	values[4]	values[7]	252	1			T34	10		T47	7		T243	35
auto[0]	values[5]	values[0]	383	1			T35	18		T178	11		T47	12
auto[0]	values[5]	values[1]	245	1			T45	10		T244	2		T245	67
auto[0]	values[5]	values[2]	237	1			T1	13		T46	15		T246	2
auto[0]	values[5]	values[3]	157	1			T34	14		T247	6		T208	15
auto[0]	values[5]	values[4]	298	1			T43	46		T248	8		T28	9
auto[0]	values[5]	values[5]	244	1			T1	15		T249	4		T46	8
auto[0]	values[5]	values[6]	340	1			T1	13		T45	16		T47	33
auto[0]	values[5]	values[7]	370	1			T1	13		T34	23		T46	83
auto[0]	values[6]	values[0]	207	1			T43	16		T225	16		T250	6
auto[0]	values[6]	values[1]	327	1			T44	11		T178	8		T251	2
auto[0]	values[6]	values[2]	291	1			T14	4		T46	8		T178	14
auto[0]	values[6]	values[3]	264	1			T34	13		T44	11		T46	40
auto[0]	values[6]	values[4]	268	1			T35	6		T44	25		T192	14
auto[0]	values[6]	values[5]	291	1			T18	78		T44	11		T252	16
auto[0]	values[6]	values[6]	301	1			T42	24		T153	6		T194	53
auto[0]	values[6]	values[7]	381	1			T1	13		T95	4		T44	11
auto[0]	values[7]	values[0]	301	1			T1	9		T35	19		T199	11
auto[0]	values[7]	values[1]	292	1			T34	14		T44	11		T199	41
auto[0]	values[7]	values[2]	235	1			T1	11		T203	21		T209	7
auto[0]	values[7]	values[3]	247	1			T77	10		T194	26		T29	10
auto[0]	values[7]	values[4]	196	1			T1	7		T11	14		T77	18
auto[0]	values[7]	values[5]	201	1			T46	7		T253	6		T191	11
auto[0]	values[7]	values[6]	210	1			T116	8		T77	6		T26	13
auto[0]	values[7]	values[7]	369	1			T1	17		T46	31		T77	10
auto[1]	values[0]	values[0]	222	1			T34	19		T43	12		T45	4
auto[1]	values[0]	values[1]	132	1			T1	29		T26	5		T186	3
auto[1]	values[0]	values[2]	307	1			T1	14		T45	13		T77	14
auto[1]	values[0]	values[3]	199	1			T77	4		T166	6		T199	52
auto[1]	values[0]	values[4]	53	1			T1	7		T47	7		T227	1
auto[1]	values[0]	values[5]	219	1			T178	21		T194	8		T186	8
auto[1]	values[0]	values[6]	85	1			T182	10		T254	14		T255	10
auto[1]	values[0]	values[7]	239	1			T34	8		T194	13		T186	11
auto[1]	values[1]	values[0]	141	1			T1	7		T45	12		T27	9
auto[1]	values[1]	values[1]	269	1			T44	5		T46	30		T256	9
auto[1]	values[1]	values[2]	142	1			T1	5		T35	14		T45	25
auto[1]	values[1]	values[3]	267	1			T77	10		T199	64		T203	61
auto[1]	values[1]	values[4]	205	1			T18	6		T43	56		T77	5
auto[1]	values[1]	values[5]	187	1			T45	7		T182	9		T230	15
auto[1]	values[1]	values[6]	260	1			T46	11		T231	25		T186	21
auto[1]	values[1]	values[7]	303	1			T35	5		T257	18		T258	10
auto[1]	values[2]	values[0]	99	1			T46	49		T194	7		T60	10
auto[1]	values[2]	values[1]	282	1			T186	13		T146	8		T166	5
auto[1]	values[2]	values[2]	294	1			T165	8		T45	6		T195	6
auto[1]	values[2]	values[3]	222	1			T1	8		T195	16		T77	4
auto[1]	values[2]	values[4]	313	1			T1	38		T47	6		T199	8
auto[1]	values[2]	values[5]	140	1			T1	8		T35	8		T217	7
auto[1]	values[2]	values[6]	148	1			T34	9		T44	49		T45	28
auto[1]	values[2]	values[7]	105	1			T45	14		T183	8		T233	11
auto[1]	values[3]	values[0]	186	1			T1	21		T190	9		T184	11
auto[1]	values[3]	values[1]	288	1			T1	39		T259	20		T166	5
auto[1]	values[3]	values[2]	361	1			T45	7		T46	9		T186	8
auto[1]	values[3]	values[3]	364	1			T1	19		T77	9		T186	39
auto[1]	values[3]	values[4]	160	1			T44	7		T217	11		T183	9
auto[1]	values[3]	values[5]	91	1			T16	4		T182	9		T197	11
auto[1]	values[3]	values[6]	160	1			T1	17		T45	4		T26	11
auto[1]	values[3]	values[7]	275	1			T43	25		T28	10		T217	43
auto[1]	values[4]	values[0]	219	1			T47	16		T190	7		T180	6
auto[1]	values[4]	values[1]	248	1			T18	12		T35	18		T47	15
auto[1]	values[4]	values[2]	228	1			T225	21		T186	42		T199	28
auto[1]	values[4]	values[3]	287	1			T195	11		T199	7		T230	6
auto[1]	values[4]	values[4]	412	1			T1	14		T46	91		T77	18
auto[1]	values[4]	values[5]	116	1			T1	11		T46	14		T260	6
auto[1]	values[4]	values[6]	125	1			T1	11		T35	8		T44	15
auto[1]	values[4]	values[7]	168	1			T34	10		T47	13		T261	24
auto[1]	values[5]	values[0]	158	1			T35	8		T178	11		T47	8
auto[1]	values[5]	values[1]	134	1			T45	10		T191	11		T262	11
auto[1]	values[5]	values[2]	218	1			T1	12		T46	5		T27	9
auto[1]	values[5]	values[3]	84	1			T34	7		T208	5		T217	11
auto[1]	values[5]	values[4]	133	1			T43	3		T28	20		T57	20
auto[1]	values[5]	values[5]	272	1			T1	5		T46	21		T208	3
auto[1]	values[5]	values[6]	194	1			T1	7		T45	12		T47	7
auto[1]	values[5]	values[7]	243	1			T1	7		T34	18		T46	9
auto[1]	values[6]	values[0]	289	1			T43	4		T225	14		T263	6
auto[1]	values[6]	values[1]	306	1			T44	72		T178	13		T203	10
auto[1]	values[6]	values[2]	179	1			T46	30		T178	10		T77	5
auto[1]	values[6]	values[3]	131	1			T34	10		T44	9		T46	9
auto[1]	values[6]	values[4]	136	1			T35	14		T44	8		T192	6
auto[1]	values[6]	values[5]	163	1			T18	10		T44	9		T230	10
auto[1]	values[6]	values[6]	163	1			T153	14		T194	4		T182	8
auto[1]	values[6]	values[7]	174	1			T1	10		T44	9		T77	4
auto[1]	values[7]	values[0]	236	1			T1	11		T35	8		T199	20
auto[1]	values[7]	values[1]	145	1			T34	8		T44	11		T199	9
auto[1]	values[7]	values[2]	130	1			T1	12		T203	29		T209	14
auto[1]	values[7]	values[3]	184	1			T77	10		T194	9		T29	11
auto[1]	values[7]	values[4]	130	1			T1	22		T77	7		T264	43
auto[1]	values[7]	values[5]	94	1			T46	13		T265	8		T191	38
auto[1]	values[7]	values[6]	293	1			T266	18		T77	87		T222	22
auto[1]	values[7]	values[7]	164	1			T1	3		T46	9		T77	17