Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	399	1			T1	15		T18	1		T87	2
auto[ReadAddrCrossIntoMailbox]	311	1			T1	12		T18	1		T87	2
auto[ReadAddrCrossOutOfMailbox]	255	1			T1	6		T18	1		T87	4
auto[ReadAddrCrossAllMailbox]	232	1			T1	8		T87	2		T34	6
auto[ReadAddrOutsideMailbox]	3401	1			T1	95		T2	2		T11	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2305

1

T1

67

T2

1

T11

2

auto[1]

2293

1

T1

69

T2

1

T11

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	704	1			T1	16		T18	1		T34	12
read_ops[0x0b]	740	1			T1	15		T18	2		T41	6
read_ops[0x3b]	751	1			T1	20		T2	2		T11	4
read_ops[0x6b]	832	1			T1	23		T18	3		T42	6
read_ops[0xbb]	795	1			T1	37		T94	2		T40	10
read_ops[0xeb]	776	1			T1	25		T18	2		T87	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T1	1		T34	1		T195	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T1	2		T18	1		T44	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T34	1		T46	2		T26	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T1	1		T34	1		T35	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	13	1			T34	1		T186	1		T199	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T35	2		T44	1		T28	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T34	1		T186	1		T209	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T34	2		T45	1		T190	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	244	1			T1	7		T43	1		T35	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T1	5		T34	5		T43	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T1	1		T44	1		T231	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T1	2		T34	2		T178	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T1	2		T34	1		T35	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T1	1		T34	1		T43	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T34	1		T186	1		T209	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T1	1		T34	1		T77	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T186	1		T209	1		T256	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T208	1		T190	1		T191	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T1	8		T18	1		T41	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	261	1			T18	1		T41	3		T40	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T232	1		T196	2		T186	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T1	1		T232	1		T46	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T1	1		T35	1		T178	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T34	1		T45	2		T47	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T87	1		T35	1		T47	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T1	1		T87	1		T45	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T199	2		T203	1		T191	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T34	1		T217	1		T256	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	278	1			T1	6		T2	1		T11	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T1	11		T2	1		T11	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T35	1		T44	1		T46	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T1	4		T35	1		T231	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T87	1		T43	1		T47	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T1	1		T18	1		T87	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T1	2		T87	1		T77	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T87	1		T43	1		T26	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T87	1		T35	1		T186	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T1	3		T87	1		T35	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T1	6		T18	2		T42	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T1	7		T42	3		T34	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T1	2		T47	1		T267	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T1	1		T44	2		T46	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T1	2		T46	1		T186	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T1	3		T199	1		T182	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T1	1		T34	2		T43	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	11	1			T34	1		T26	1		T217	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T1	3		T190	1		T268	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T1	1		T34	1		T44	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T1	20		T94	1		T40	5
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T1	4		T94	1		T40	5
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T1	1		T87	1		T43	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T87	1		T35	1		T46	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T153	1		T77	1		T203	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T1	1		T34	2		T195	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T34	2		T44	1		T46	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T1	1		T18	1		T45	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T246	1		T77	1		T225	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T1	1		T34	1		T246	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	291	1			T1	4		T34	2		T43	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	275	1			T1	17		T18	1		T34	1