Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3256	1			T1	33		T95	4		T41	26
values[1]	3683	1			T1	127		T116	8		T42	24
values[2]	3263	1			T1	40		T87	16		T35	20
values[3]	3527	1			T1	100		T18	122		T35	40
values[4]	5176	1			T1	65		T14	4		T142	4
values[5]	3869	1			T1	98		T2	12		T11	14
values[6]	4189	1			T1	97		T34	42		T43	20
values[7]	3553	1			T1	161		T12	14		T86	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4191	1			T1	97		T11	14		T95	4
values[1]	3391	1			T1	46		T34	63		T235	4
values[2]	3908	1			T1	60		T40	18		T43	40
values[3]	4272	1			T1	40		T18	88		T42	24
values[4]	3730	1			T1	159		T18	54		T165	8
values[5]	4098	1			T1	105		T14	4		T142	4
values[6]	3494	1			T1	63		T2	12		T16	4
values[7]	3432	1			T1	151		T12	14		T116	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29748

1

T1

709

T2

12

T11

14

auto[1]

768

1

T1

12

T16

2

T18

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	458	1			T95	4		T46	54		T77	20
auto[0]	values[0]	values[1]	434	1			T46	49		T203	20		T197	49
auto[0]	values[0]	values[2]	331	1			T40	18		T195	20		T246	2
auto[0]	values[0]	values[3]	398	1			T47	20		T203	16		T269	14
auto[0]	values[0]	values[4]	328	1			T34	25		T46	33		T184	19
auto[0]	values[0]	values[5]	441	1			T1	33		T46	20		T77	20
auto[0]	values[0]	values[6]	508	1			T41	26		T210	20		T245	67
auto[0]	values[0]	values[7]	265	1			T77	19		T199	41		T268	19
auto[0]	values[1]	values[0]	436	1			T1	20		T186	80		T199	50
auto[0]	values[1]	values[1]	365	1			T247	6		T203	59		T217	16
auto[0]	values[1]	values[2]	587	1			T35	52		T44	20		T45	20
auto[0]	values[1]	values[3]	336	1			T1	20		T42	24		T35	25
auto[0]	values[1]	values[4]	508	1			T1	67		T231	37		T208	20
auto[0]	values[1]	values[5]	529	1			T44	33		T178	21		T77	86
auto[0]	values[1]	values[6]	402	1			T43	20		T44	22		T270	14
auto[0]	values[1]	values[7]	436	1			T1	20		T116	8		T234	10
auto[0]	values[2]	values[0]	486	1			T45	45		T237	10		T186	25
auto[0]	values[2]	values[1]	439	1			T27	20		T230	28		T271	14
auto[0]	values[2]	values[2]	355	1			T27	20		T186	20		T166	20
auto[0]	values[2]	values[3]	519	1			T186	18		T146	20		T217	45
auto[0]	values[2]	values[4]	462	1			T44	102		T186	18		T272	2
auto[0]	values[2]	values[5]	246	1			T146	21		T199	35		T203	29
auto[0]	values[2]	values[6]	344	1			T1	20		T35	20		T178	22
auto[0]	values[2]	values[7]	330	1			T1	18		T87	16		T259	20
auto[0]	values[3]	values[0]	479	1			T47	20		T273	12		T233	39
auto[0]	values[3]	values[1]	455	1			T146	21		T197	46		T274	4
auto[0]	values[3]	values[2]	351	1			T46	20		T47	20		T215	10
auto[0]	values[3]	values[3]	495	1			T18	87		T44	20		T186	40
auto[0]	values[3]	values[4]	314	1			T18	34		T257	14		T228	2
auto[0]	values[3]	values[5]	575	1			T1	40		T45	41		T77	32
auto[0]	values[3]	values[6]	341	1			T1	20		T44	45		T222	18
auto[0]	values[3]	values[7]	432	1			T1	40		T35	38		T45	53
auto[0]	values[4]	values[0]	838	1			T1	43		T34	19		T44	60
auto[0]	values[4]	values[1]	435	1			T34	39		T178	24		T47	19
auto[0]	values[4]	values[2]	674	1			T35	72		T45	39		T46	20
auto[0]	values[4]	values[3]	763	1			T35	32		T45	35		T46	129
auto[0]	values[4]	values[4]	593	1			T43	108		T77	90		T88	14
auto[0]	values[4]	values[5]	520	1			T14	4		T142	4		T43	68
auto[0]	values[4]	values[6]	607	1			T34	22		T45	19		T275	14
auto[0]	values[4]	values[7]	612	1			T1	20		T77	20		T27	30
auto[0]	values[5]	values[0]	409	1			T11	14		T182	48		T268	24
auto[0]	values[5]	values[1]	252	1			T45	19		T230	20		T276	20
auto[0]	values[5]	values[2]	476	1			T1	19		T43	15		T194	53
auto[0]	values[5]	values[3]	763	1			T249	4		T183	95		T277	40
auto[0]	values[5]	values[4]	501	1			T18	20		T43	46		T178	22
auto[0]	values[5]	values[5]	521	1			T1	31		T94	12		T223	8
auto[0]	values[5]	values[6]	426	1			T1	22		T2	12		T16	2
auto[0]	values[5]	values[7]	423	1			T1	23		T26	40		T194	20
auto[0]	values[6]	values[0]	470	1			T232	6		T191	47		T256	19
auto[0]	values[6]	values[1]	530	1			T34	21		T248	8		T195	20
auto[0]	values[6]	values[2]	590	1			T43	19		T192	20		T47	19
auto[0]	values[6]	values[3]	527	1			T1	20		T225	43		T182	21
auto[0]	values[6]	values[4]	657	1			T1	46		T45	66		T47	18
auto[0]	values[6]	values[5]	476	1			T45	20		T47	20		T77	22
auto[0]	values[6]	values[6]	387	1			T34	20		T239	6		T203	22
auto[0]	values[6]	values[7]	449	1			T1	28		T45	31		T47	40
auto[0]	values[7]	values[0]	493	1			T1	32		T86	20		T45	26
auto[0]	values[7]	values[1]	400	1			T1	46		T235	4		T194	20
auto[0]	values[7]	values[2]	415	1			T1	40		T240	2		T224	8
auto[0]	values[7]	values[3]	383	1			T34	20		T47	20		T209	21
auto[0]	values[7]	values[4]	265	1			T1	41		T165	8		T35	26
auto[0]	values[7]	values[5]	702	1			T208	40		T198	12		T190	40
auto[0]	values[7]	values[6]	397	1			T238	4		T26	21		T183	20
auto[0]	values[7]	values[7]	409	1			T12	14		T34	18		T199	20
auto[1]	values[0]	values[0]	11	1			T46	2		T199	2		T230	1
auto[1]	values[0]	values[1]	15	1			T197	3		T190	2		T256	3
auto[1]	values[0]	values[2]	10	1			T195	1		T58	1		T278	1
auto[1]	values[0]	values[3]	12	1			T203	4		T212	1		T255	3
auto[1]	values[0]	values[4]	16	1			T46	7		T184	1		T59	4
auto[1]	values[0]	values[5]	12	1			T186	1		T190	1		T233	3
auto[1]	values[0]	values[6]	9	1			T59	1		T201	2		T255	3
auto[1]	values[0]	values[7]	8	1			T77	1		T268	1		T183	3
auto[1]	values[1]	values[0]	11	1			T186	2		T150	1		T279	7
auto[1]	values[1]	values[1]	9	1			T203	2		T217	4		T264	3
auto[1]	values[1]	values[2]	12	1			T182	1		T203	2		T217	1
auto[1]	values[1]	values[3]	3	1			T35	1		T201	1		T280	1
auto[1]	values[1]	values[4]	11	1			T281	6		T282	2		T255	2
auto[1]	values[1]	values[5]	12	1			T77	4		T60	1		T149	2
auto[1]	values[1]	values[6]	10	1			T217	4		T184	1		T283	1
auto[1]	values[1]	values[7]	16	1			T182	3		T203	1		T268	2
auto[1]	values[2]	values[0]	18	1			T186	1		T199	3		T182	3
auto[1]	values[2]	values[1]	11	1			T230	1		T284	2		T285	2
auto[1]	values[2]	values[2]	14	1			T182	1		T209	1		T191	3
auto[1]	values[2]	values[3]	14	1			T186	2		T146	1		T217	1
auto[1]	values[2]	values[4]	10	1			T44	1		T186	2		T264	1
auto[1]	values[2]	values[5]	3	1			T199	2		T264	1		-	-
auto[1]	values[2]	values[6]	7	1			T186	2		T203	2		T255	2
auto[1]	values[2]	values[7]	5	1			T1	2		T201	1		T286	2
auto[1]	values[3]	values[0]	21	1			T233	1		T287	2		T288	2
auto[1]	values[3]	values[1]	6	1			T146	1		T190	3		T149	1
auto[1]	values[3]	values[2]	11	1			T28	4		T277	1		T282	2
auto[1]	values[3]	values[3]	9	1			T18	1		T190	3		T227	3
auto[1]	values[3]	values[4]	10	1			T257	4		T57	2		T281	2
auto[1]	values[3]	values[5]	5	1			T281	1		T289	1		T207	1
auto[1]	values[3]	values[6]	9	1			T44	2		T222	4		T29	1
auto[1]	values[3]	values[7]	14	1			T35	2		T45	2		T290	2
auto[1]	values[4]	values[0]	26	1			T1	2		T34	1		T46	2
auto[1]	values[4]	values[1]	18	1			T34	2		T178	3		T47	1
auto[1]	values[4]	values[2]	25	1			T35	3		T45	1		T281	1
auto[1]	values[4]	values[3]	16	1			T35	1		T45	1		T46	1
auto[1]	values[4]	values[4]	18	1			T43	1		T77	3		T217	2
auto[1]	values[4]	values[5]	11	1			T43	2		T153	1		T46	2
auto[1]	values[4]	values[6]	11	1			T34	1		T45	1		T183	1
auto[1]	values[4]	values[7]	9	1			T27	1		T281	1		T264	1
auto[1]	values[5]	values[0]	10	1			T129	6		T290	1		T33	1
auto[1]	values[5]	values[1]	4	1			T45	1		T291	1		T292	1
auto[1]	values[5]	values[2]	21	1			T1	1		T43	5		T194	4
auto[1]	values[5]	values[3]	10	1			T183	1		T277	1		T293	2
auto[1]	values[5]	values[4]	17	1			T43	3		T77	1		T199	3
auto[1]	values[5]	values[5]	13	1			T1	1		T191	2		T268	3
auto[1]	values[5]	values[6]	15	1			T1	1		T16	2		T46	1
auto[1]	values[5]	values[7]	8	1			T26	5		T281	1		T290	1
auto[1]	values[6]	values[0]	11	1			T191	2		T256	1		T277	1
auto[1]	values[6]	values[1]	10	1			T34	1		T152	3		T294	2
auto[1]	values[6]	values[2]	21	1			T43	1		T47	1		T184	1
auto[1]	values[6]	values[3]	12	1			T182	1		T191	2		T256	1
auto[1]	values[6]	values[4]	15	1			T1	3		T45	2		T47	2
auto[1]	values[6]	values[5]	12	1			T77	1		T230	1		T256	6
auto[1]	values[6]	values[6]	14	1			T268	3		T57	3		T58	1
auto[1]	values[6]	values[7]	8	1			T77	1		T197	2		T180	1
auto[1]	values[7]	values[0]	14	1			T45	2		T47	1		T208	3
auto[1]	values[7]	values[1]	8	1			T208	4		T201	2		T129	1
auto[1]	values[7]	values[2]	15	1			T230	1		T233	1		T148	1
auto[1]	values[7]	values[3]	12	1			T34	1		T152	3		T295	5
auto[1]	values[7]	values[4]	5	1			T1	2		T35	1		T59	1
auto[1]	values[7]	values[5]	20	1			T57	1		T59	1		T227	5
auto[1]	values[7]	values[6]	7	1			T26	1		T233	1		T150	2
auto[1]	values[7]	values[7]	8	1			T34	2		T217	2		T296	2