Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	933	1			T1	4		T20	4		T21	4
all_values[1]	933	1			T1	4		T20	4		T21	4
all_values[2]	933	1			T1	4		T20	4		T21	4
all_values[3]	933	1			T1	4		T20	4		T21	4
all_values[4]	933	1			T1	4		T20	4		T21	4
all_values[5]	933	1			T1	4		T20	4		T21	4
all_values[6]	933	1			T1	4		T20	4		T21	4
all_values[7]	933	1			T1	4		T20	4		T21	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3982

1

T1

19

T20

19

T21

14

auto[1]

3482

1

T1

13

T20

13

T21

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3026

1

T1

16

T20

9

T21

19

auto[1]

4438

1

T1

16

T20

23

T21

13

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4283

1

T1

20

T20

14

T21

22

auto[1]

3181

1

T1

12

T20

18

T21

10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	189	1			T1	2		T21	2		T22	4
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T20	1		T28	2		T29	1
all_values[0]	auto[0]	auto[1]	auto[0]	170	1			T21	1		T22	3		T26	3
all_values[0]	auto[0]	auto[1]	auto[1]	95	1			T26	2		T27	1		T28	3
all_values[0]	auto[1]	auto[0]	auto[1]	221	1			T20	2		T22	1		T26	2
all_values[0]	auto[1]	auto[1]	auto[1]	178	1			T1	2		T20	1		T21	1
all_values[1]	auto[0]	auto[0]	auto[0]	198	1			T1	1		T22	2		T26	2
all_values[1]	auto[0]	auto[0]	auto[1]	92	1			T20	1		T22	1		T28	2
all_values[1]	auto[0]	auto[1]	auto[0]	146	1			T21	2		T22	3		T26	4
all_values[1]	auto[0]	auto[1]	auto[1]	97	1			T1	2		T22	1		T26	1
all_values[1]	auto[1]	auto[0]	auto[1]	225	1			T20	3		T21	2		T22	2
all_values[1]	auto[1]	auto[1]	auto[1]	175	1			T1	1		T22	1		T26	3
all_values[2]	auto[0]	auto[0]	auto[0]	195	1			T1	1		T20	1		T22	2
all_values[2]	auto[0]	auto[0]	auto[1]	94	1			T20	1		T26	1		T28	2
all_values[2]	auto[0]	auto[1]	auto[0]	164	1			T20	1		T21	1		T22	3
all_values[2]	auto[0]	auto[1]	auto[1]	93	1			T1	1		T21	2		T22	1
all_values[2]	auto[1]	auto[0]	auto[1]	211	1			T1	2		T20	1		T26	3
all_values[2]	auto[1]	auto[1]	auto[1]	176	1			T21	1		T22	4		T26	1
all_values[3]	auto[0]	auto[0]	auto[0]	178	1			T21	1		T22	4		T26	5
all_values[3]	auto[0]	auto[0]	auto[1]	90	1			T1	1		T20	1		T21	1
all_values[3]	auto[0]	auto[1]	auto[0]	149	1			T1	1		T22	1		T26	4
all_values[3]	auto[0]	auto[1]	auto[1]	108	1			T26	1		T28	4		T29	3
all_values[3]	auto[1]	auto[0]	auto[1]	227	1			T1	2		T20	1		T21	2
all_values[3]	auto[1]	auto[1]	auto[1]	181	1			T20	2		T22	4		T26	1
all_values[4]	auto[0]	auto[0]	auto[0]	209	1			T1	3		T20	2		T21	2
all_values[4]	auto[0]	auto[0]	auto[1]	90	1			T27	1		T28	3		T29	2
all_values[4]	auto[0]	auto[1]	auto[0]	164	1			T21	2		T22	2		T27	3
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T26	1		T28	3		T29	1
all_values[4]	auto[1]	auto[0]	auto[1]	200	1			T27	2		T28	5		T29	2
all_values[4]	auto[1]	auto[1]	auto[1]	197	1			T1	1		T20	2		T22	3
all_values[5]	auto[0]	auto[0]	auto[0]	295	1			T1	1		T20	1		T21	2
all_values[5]	auto[0]	auto[1]	auto[0]	244	1			T20	1		T21	1		T22	8
all_values[5]	auto[1]	auto[0]	auto[1]	217	1			T1	2		T20	2		T26	3
all_values[5]	auto[1]	auto[1]	auto[1]	177	1			T1	1		T21	1		T22	2
all_values[6]	auto[0]	auto[0]	auto[0]	194	1			T1	3		T26	3		T27	1
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T20	1		T22	2		T28	2
all_values[6]	auto[0]	auto[1]	auto[0]	182	1			T1	1		T21	2		T26	3
all_values[6]	auto[0]	auto[1]	auto[1]	87	1			T22	4		T28	7		T164	1
all_values[6]	auto[1]	auto[0]	auto[1]	209	1			T20	1		T22	3		T26	4
all_values[6]	auto[1]	auto[1]	auto[1]	181	1			T20	2		T21	2		T22	1
all_values[7]	auto[0]	auto[0]	auto[0]	187	1			T1	1		T21	2		T22	1
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T22	1		T26	2		T28	1
all_values[7]	auto[0]	auto[1]	auto[0]	162	1			T1	2		T20	3		T21	1
all_values[7]	auto[0]	auto[1]	auto[1]	91	1			T22	1		T26	1		T27	2
all_values[7]	auto[1]	auto[0]	auto[1]	214	1			T22	2		T26	3		T27	1
all_values[7]	auto[1]	auto[1]	auto[1]	192	1			T1	1		T20	1		T21	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal