Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1789

1

T1

13

T3

6

T6

2

auto[1]

1723

1

T1

10

T3

7

T6

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1710

1

T1

19

T3

11

T6

3

auto[1]

1802

1

T1

4

T3

2

T6

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2878

1

T1

17

T3

9

T6

3

auto[1]

634

1

T1

6

T3

4

T6

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	701	1			T1	8		T3	3		T6	1
valid[1]	697	1			T1	3		T3	2		T6	2
valid[2]	691	1			T1	6		T3	3		T7	1
valid[3]	722	1			T1	2		T3	3		T6	2
valid[4]	701	1			T1	4		T3	2		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	120	1			T1	4		T3	1		T7	1
auto[0]	auto[0]	valid[0]	auto[1]	177	1			T9	6		T82	3		T83	1
auto[0]	auto[0]	valid[1]	auto[0]	105	1			T1	1		T3	1		T7	1
auto[0]	auto[0]	valid[1]	auto[1]	203	1			T1	1		T9	5		T23	1
auto[0]	auto[0]	valid[2]	auto[0]	87	1			T1	1		T7	1		T49	1
auto[0]	auto[0]	valid[2]	auto[1]	179	1			T1	1		T9	7		T23	1
auto[0]	auto[0]	valid[3]	auto[0]	122	1			T3	1		T23	2		T25	1
auto[0]	auto[0]	valid[3]	auto[1]	176	1			T6	1		T9	1		T23	1
auto[0]	auto[0]	valid[4]	auto[0]	129	1			T3	1		T7	1		T24	1
auto[0]	auto[0]	valid[4]	auto[1]	181	1			T9	4		T82	3		T83	2
auto[0]	auto[1]	valid[0]	auto[0]	115	1			T3	1		T7	1		T24	1
auto[0]	auto[1]	valid[0]	auto[1]	172	1			T3	1		T6	1		T9	7
auto[0]	auto[1]	valid[1]	auto[0]	98	1			T3	1		T23	1		T85	1
auto[0]	auto[1]	valid[1]	auto[1]	166	1			T6	1		T9	2		T83	1
auto[0]	auto[1]	valid[2]	auto[0]	109	1			T1	3		T3	1		T101	1
auto[0]	auto[1]	valid[2]	auto[1]	183	1			T3	1		T9	8		T23	1
auto[0]	auto[1]	valid[3]	auto[0]	106	1			T1	2		T7	1		T49	2
auto[0]	auto[1]	valid[3]	auto[1]	180	1			T9	8		T23	1		T82	3
auto[0]	auto[1]	valid[4]	auto[0]	85	1			T1	2		T23	1		T153	2
auto[0]	auto[1]	valid[4]	auto[1]	185	1			T1	2		T9	3		T23	1
auto[1]	auto[0]	valid[0]	auto[0]	54	1			T1	3		T7	1		T23	1
auto[1]	auto[0]	valid[1]	auto[0]	60	1			T1	1		T6	1		T7	2
auto[1]	auto[0]	valid[2]	auto[0]	64	1			T1	1		T3	1		T49	1
auto[1]	auto[0]	valid[3]	auto[0]	77	1			T3	1		T23	1		T49	1
auto[1]	auto[0]	valid[4]	auto[0]	55	1			T49	1		T101	1		T304	1
auto[1]	auto[1]	valid[0]	auto[0]	63	1			T1	1		T101	1		T50	1
auto[1]	auto[1]	valid[1]	auto[0]	65	1			T23	2		T85	1		T309	1
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T23	2		T34	2		T178	1
auto[1]	auto[1]	valid[3]	auto[0]	61	1			T3	1		T6	1		T7	2
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T3	1		T6	1		T23	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal