Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44066

1

T1

630

T3

256

T6

82

auto[1]

18586

1

T1

35

T3

49

T6

16

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46616

1

T1

458

T3

206

T6

68

auto[1]

16036

1

T1

207

T3

99

T6

30

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32369	1			T1	319		T3	155		T6	43
others[1]	5383	1			T1	66		T3	25		T6	8
others[2]	5314	1			T1	64		T3	29		T6	14
others[3]	5949	1			T1	68		T3	32		T6	13
interest[1]	3484	1			T1	41		T3	20		T6	7
interest[4]	21197	1			T1	205		T3	106		T6	28
interest[64]	10153	1			T1	107		T3	44		T6	13

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14343	1			T1	201		T3	79		T6	23
auto[0]	auto[0]	others[1]	2450	1			T1	45		T3	13		T6	4
auto[0]	auto[0]	others[2]	2405	1			T1	40		T3	18		T6	7
auto[0]	auto[0]	others[3]	2681	1			T1	42		T3	15		T6	5
auto[0]	auto[0]	interest[1]	1593	1			T1	24		T3	10		T6	6
auto[0]	auto[0]	interest[4]	9400	1			T1	136		T3	51		T6	14
auto[0]	auto[0]	interest[64]	4558	1			T1	71		T3	22		T6	7
auto[0]	auto[1]	others[0]	9687	1			T1	21		T3	22		T6	3
auto[0]	auto[1]	others[1]	1548	1			T1	1		T3	4		T6	3
auto[0]	auto[1]	others[2]	1531	1			T1	3		T3	2		T6	3
auto[0]	auto[1]	others[3]	1804	1			T1	5		T3	7		T6	4
auto[0]	auto[1]	interest[1]	1017	1			T1	2		T3	4		T6	1
auto[0]	auto[1]	interest[4]	6393	1			T1	14		T3	14		T9	134
auto[0]	auto[1]	interest[64]	2999	1			T1	3		T3	10		T6	2
auto[1]	auto[0]	others[0]	8339	1			T1	97		T3	54		T6	17
auto[1]	auto[0]	others[1]	1385	1			T1	20		T3	8		T6	1
auto[1]	auto[0]	others[2]	1378	1			T1	21		T3	9		T6	4
auto[1]	auto[0]	others[3]	1464	1			T1	21		T3	10		T6	4
auto[1]	auto[0]	interest[1]	874	1			T1	15		T3	6		T7	4
auto[1]	auto[0]	interest[4]	5404	1			T1	55		T3	41		T6	14
auto[1]	auto[0]	interest[64]	2596	1			T1	33		T3	12		T6	4

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal