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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1129
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T144 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3956357813 Aug 05 06:14:41 PM PDT 24 Aug 05 06:15:08 PM PDT 24 1831490197 ps
T123 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1733360670 Aug 05 06:14:58 PM PDT 24 Aug 05 06:15:01 PM PDT 24 216199786 ps
T1027 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2663900907 Aug 05 06:15:42 PM PDT 24 Aug 05 06:15:43 PM PDT 24 14090887 ps
T1028 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.194663035 Aug 05 06:15:24 PM PDT 24 Aug 05 06:15:25 PM PDT 24 14018913 ps
T1029 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2201578002 Aug 05 06:15:36 PM PDT 24 Aug 05 06:15:37 PM PDT 24 56319313 ps
T174 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2317762756 Aug 05 06:14:18 PM PDT 24 Aug 05 06:14:25 PM PDT 24 797874454 ps
T104 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3294205529 Aug 05 06:14:19 PM PDT 24 Aug 05 06:14:24 PM PDT 24 266670358 ps
T1030 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3964807447 Aug 05 06:15:04 PM PDT 24 Aug 05 06:15:05 PM PDT 24 31016547 ps
T145 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1976707215 Aug 05 06:14:53 PM PDT 24 Aug 05 06:15:07 PM PDT 24 2258499578 ps
T1031 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3010844428 Aug 05 06:15:31 PM PDT 24 Aug 05 06:15:33 PM PDT 24 155501995 ps
T1032 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1388676890 Aug 05 06:15:37 PM PDT 24 Aug 05 06:15:38 PM PDT 24 37871125 ps
T107 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3898635169 Aug 05 06:15:25 PM PDT 24 Aug 05 06:15:28 PM PDT 24 77002654 ps
T172 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.226781740 Aug 05 06:15:09 PM PDT 24 Aug 05 06:15:28 PM PDT 24 1269627452 ps
T124 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3253255790 Aug 05 06:15:17 PM PDT 24 Aug 05 06:15:19 PM PDT 24 49734056 ps
T1033 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.850613955 Aug 05 06:15:27 PM PDT 24 Aug 05 06:15:28 PM PDT 24 19553790 ps
T103 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2072270210 Aug 05 06:15:03 PM PDT 24 Aug 05 06:15:08 PM PDT 24 148333892 ps
T1034 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2397890024 Aug 05 06:14:35 PM PDT 24 Aug 05 06:15:07 PM PDT 24 2083987824 ps
T125 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4251037785 Aug 05 06:15:25 PM PDT 24 Aug 05 06:15:26 PM PDT 24 40489873 ps
T1035 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.445449940 Aug 05 06:15:31 PM PDT 24 Aug 05 06:15:33 PM PDT 24 38339676 ps
T1036 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2534851059 Aug 05 06:14:19 PM PDT 24 Aug 05 06:14:20 PM PDT 24 12719827 ps
T1037 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3140894150 Aug 05 06:15:09 PM PDT 24 Aug 05 06:15:11 PM PDT 24 80275700 ps
T1038 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3811905654 Aug 05 06:15:42 PM PDT 24 Aug 05 06:15:43 PM PDT 24 26509656 ps
T1039 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2049699140 Aug 05 06:15:26 PM PDT 24 Aug 05 06:15:27 PM PDT 24 14946002 ps
T106 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1043351760 Aug 05 06:14:43 PM PDT 24 Aug 05 06:14:45 PM PDT 24 274902959 ps
T1040 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2378609388 Aug 05 06:15:37 PM PDT 24 Aug 05 06:15:38 PM PDT 24 12802520 ps
T105 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4211823878 Aug 05 06:14:47 PM PDT 24 Aug 05 06:14:52 PM PDT 24 375496224 ps
T126 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2866297049 Aug 05 06:14:41 PM PDT 24 Aug 05 06:14:43 PM PDT 24 248927471 ps
T1041 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1286421044 Aug 05 06:15:40 PM PDT 24 Aug 05 06:15:41 PM PDT 24 14334892 ps
T1042 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.499185332 Aug 05 06:15:18 PM PDT 24 Aug 05 06:15:22 PM PDT 24 61100470 ps
T1043 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3318122781 Aug 05 06:15:31 PM PDT 24 Aug 05 06:15:32 PM PDT 24 129626499 ps
T1044 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.31869595 Aug 05 06:14:24 PM PDT 24 Aug 05 06:14:31 PM PDT 24 119262801 ps
T1045 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1479679401 Aug 05 06:15:04 PM PDT 24 Aug 05 06:15:26 PM PDT 24 868773377 ps
T1046 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2366970870 Aug 05 06:15:16 PM PDT 24 Aug 05 06:15:19 PM PDT 24 527478851 ps
T109 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.541746820 Aug 05 06:15:08 PM PDT 24 Aug 05 06:15:11 PM PDT 24 424698276 ps
T127 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.914679660 Aug 05 06:14:41 PM PDT 24 Aug 05 06:14:43 PM PDT 24 57213084 ps
T1047 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.161873784 Aug 05 06:15:07 PM PDT 24 Aug 05 06:15:09 PM PDT 24 201472304 ps
T1048 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2523237189 Aug 05 06:15:03 PM PDT 24 Aug 05 06:15:04 PM PDT 24 17981947 ps
T80 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3625606239 Aug 05 06:14:54 PM PDT 24 Aug 05 06:14:55 PM PDT 24 73227989 ps
T1049 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1178955829 Aug 05 06:15:32 PM PDT 24 Aug 05 06:15:35 PM PDT 24 887135614 ps
T168 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2188543316 Aug 05 06:15:08 PM PDT 24 Aug 05 06:15:12 PM PDT 24 686635749 ps
T169 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3552245829 Aug 05 06:15:24 PM PDT 24 Aug 05 06:15:46 PM PDT 24 1671422581 ps
T1050 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3287266540 Aug 05 06:15:31 PM PDT 24 Aug 05 06:15:34 PM PDT 24 41758704 ps
T1051 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2664188001 Aug 05 06:15:05 PM PDT 24 Aug 05 06:15:21 PM PDT 24 4985448669 ps
T1052 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4067093978 Aug 05 06:14:59 PM PDT 24 Aug 05 06:15:00 PM PDT 24 41700389 ps
T1053 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.727198454 Aug 05 06:15:04 PM PDT 24 Aug 05 06:15:08 PM PDT 24 222771017 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.428326115 Aug 05 06:14:57 PM PDT 24 Aug 05 06:15:00 PM PDT 24 215870098 ps
T81 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2744066101 Aug 05 06:14:29 PM PDT 24 Aug 05 06:14:30 PM PDT 24 65042982 ps
T173 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3963471289 Aug 05 06:15:27 PM PDT 24 Aug 05 06:15:42 PM PDT 24 773878278 ps
T110 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.164751562 Aug 05 06:15:15 PM PDT 24 Aug 05 06:15:20 PM PDT 24 77749106 ps
T1055 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2101544995 Aug 05 06:15:18 PM PDT 24 Aug 05 06:15:20 PM PDT 24 189281728 ps
T1056 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1500264918 Aug 05 06:14:30 PM PDT 24 Aug 05 06:14:33 PM PDT 24 741787057 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3408201744 Aug 05 06:14:40 PM PDT 24 Aug 05 06:14:41 PM PDT 24 37688732 ps
T170 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3350962258 Aug 05 06:15:07 PM PDT 24 Aug 05 06:15:15 PM PDT 24 354754688 ps
T1058 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1808407021 Aug 05 06:15:41 PM PDT 24 Aug 05 06:15:42 PM PDT 24 156883648 ps
T1059 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2865043421 Aug 05 06:14:20 PM PDT 24 Aug 05 06:14:22 PM PDT 24 26985528 ps
T1060 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1221590290 Aug 05 06:15:25 PM PDT 24 Aug 05 06:15:29 PM PDT 24 203795895 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1234064700 Aug 05 06:14:34 PM PDT 24 Aug 05 06:14:41 PM PDT 24 120525080 ps
T108 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3779074178 Aug 05 06:15:32 PM PDT 24 Aug 05 06:15:35 PM PDT 24 88762498 ps
T1062 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.617347774 Aug 05 06:15:03 PM PDT 24 Aug 05 06:15:03 PM PDT 24 18256569 ps
T1063 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1480563525 Aug 05 06:14:47 PM PDT 24 Aug 05 06:14:50 PM PDT 24 43890845 ps
T1064 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2567597764 Aug 05 06:15:02 PM PDT 24 Aug 05 06:15:03 PM PDT 24 34712281 ps
T1065 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4196871159 Aug 05 06:15:38 PM PDT 24 Aug 05 06:15:39 PM PDT 24 16499382 ps
T1066 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3899988836 Aug 05 06:14:58 PM PDT 24 Aug 05 06:14:59 PM PDT 24 18734613 ps
T1067 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2695315438 Aug 05 06:15:35 PM PDT 24 Aug 05 06:15:36 PM PDT 24 23947489 ps
T1068 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.62458278 Aug 05 06:14:58 PM PDT 24 Aug 05 06:15:19 PM PDT 24 1209044375 ps
T1069 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.65007065 Aug 05 06:15:41 PM PDT 24 Aug 05 06:15:42 PM PDT 24 177613296 ps
T1070 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1502723444 Aug 05 06:15:15 PM PDT 24 Aug 05 06:15:16 PM PDT 24 38153852 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1296098227 Aug 05 06:14:24 PM PDT 24 Aug 05 06:14:26 PM PDT 24 163805817 ps
T1072 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3522808166 Aug 05 06:15:20 PM PDT 24 Aug 05 06:15:21 PM PDT 24 15354443 ps
T1073 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4023082771 Aug 05 06:15:11 PM PDT 24 Aug 05 06:15:12 PM PDT 24 15545731 ps
T1074 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3277815563 Aug 05 06:15:04 PM PDT 24 Aug 05 06:15:06 PM PDT 24 50382417 ps
T1075 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1908502084 Aug 05 06:15:08 PM PDT 24 Aug 05 06:15:12 PM PDT 24 193277614 ps
T1076 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3702675540 Aug 05 06:14:22 PM PDT 24 Aug 05 06:14:24 PM PDT 24 233999877 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3407187740 Aug 05 06:15:31 PM PDT 24 Aug 05 06:15:49 PM PDT 24 575961464 ps
T1078 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4225450891 Aug 05 06:14:59 PM PDT 24 Aug 05 06:15:02 PM PDT 24 520608364 ps
T1079 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1571479622 Aug 05 06:15:24 PM PDT 24 Aug 05 06:15:28 PM PDT 24 543209904 ps
T1080 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2653265002 Aug 05 06:14:31 PM PDT 24 Aug 05 06:14:33 PM PDT 24 29504306 ps
T1081 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4135397187 Aug 05 06:15:25 PM PDT 24 Aug 05 06:15:29 PM PDT 24 158784825 ps
T1082 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3876672168 Aug 05 06:14:29 PM PDT 24 Aug 05 06:14:29 PM PDT 24 19961809 ps
T1083 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4184325051 Aug 05 06:15:09 PM PDT 24 Aug 05 06:15:09 PM PDT 24 40255901 ps
T1084 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.820226088 Aug 05 06:15:30 PM PDT 24 Aug 05 06:15:45 PM PDT 24 5258889185 ps
T177 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.504249552 Aug 05 06:14:59 PM PDT 24 Aug 05 06:15:07 PM PDT 24 1046758013 ps
T1085 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1964846077 Aug 05 06:15:29 PM PDT 24 Aug 05 06:15:33 PM PDT 24 233228737 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3687464573 Aug 05 06:14:30 PM PDT 24 Aug 05 06:14:31 PM PDT 24 34637281 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2077974104 Aug 05 06:14:48 PM PDT 24 Aug 05 06:14:50 PM PDT 24 174659771 ps
T1088 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4274335483 Aug 05 06:15:08 PM PDT 24 Aug 05 06:15:10 PM PDT 24 78695113 ps
T1089 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4148957081 Aug 05 06:15:38 PM PDT 24 Aug 05 06:15:39 PM PDT 24 56663060 ps
T1090 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3380273973 Aug 05 06:15:37 PM PDT 24 Aug 05 06:15:38 PM PDT 24 34099479 ps
T1091 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2314773389 Aug 05 06:14:52 PM PDT 24 Aug 05 06:14:53 PM PDT 24 35758791 ps
T1092 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3477422194 Aug 05 06:15:19 PM PDT 24 Aug 05 06:15:24 PM PDT 24 614587698 ps
T1093 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.489014006 Aug 05 06:15:10 PM PDT 24 Aug 05 06:15:16 PM PDT 24 113401253 ps
T1094 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2939746784 Aug 05 06:15:19 PM PDT 24 Aug 05 06:15:23 PM PDT 24 202637637 ps
T1095 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3725830720 Aug 05 06:15:04 PM PDT 24 Aug 05 06:15:07 PM PDT 24 56209343 ps
T1096 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.362485104 Aug 05 06:15:26 PM PDT 24 Aug 05 06:15:29 PM PDT 24 42949371 ps
T1097 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3351053321 Aug 05 06:15:40 PM PDT 24 Aug 05 06:15:41 PM PDT 24 12186600 ps
T1098 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2668462627 Aug 05 06:15:37 PM PDT 24 Aug 05 06:15:38 PM PDT 24 27294718 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.12097 Aug 05 06:14:23 PM PDT 24 Aug 05 06:14:24 PM PDT 24 21904706 ps
T1100 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3470443257 Aug 05 06:15:42 PM PDT 24 Aug 05 06:15:43 PM PDT 24 45123175 ps
T1101 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1379313589 Aug 05 06:15:37 PM PDT 24 Aug 05 06:15:38 PM PDT 24 16048681 ps
T1102 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.313549125 Aug 05 06:15:37 PM PDT 24 Aug 05 06:15:37 PM PDT 24 14556674 ps
T1103 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1040291381 Aug 05 06:14:48 PM PDT 24 Aug 05 06:14:48 PM PDT 24 13455765 ps
T1104 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3559482756 Aug 05 06:15:18 PM PDT 24 Aug 05 06:15:20 PM PDT 24 163209466 ps
T1105 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1803874977 Aug 05 06:15:30 PM PDT 24 Aug 05 06:15:32 PM PDT 24 98311978 ps
T1106 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4009184722 Aug 05 06:15:09 PM PDT 24 Aug 05 06:15:12 PM PDT 24 1295625911 ps
T1107 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1521559930 Aug 05 06:15:08 PM PDT 24 Aug 05 06:15:12 PM PDT 24 60594660 ps
T1108 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3199521157 Aug 05 06:15:15 PM PDT 24 Aug 05 06:15:16 PM PDT 24 208831381 ps
T1109 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2164836251 Aug 05 06:15:03 PM PDT 24 Aug 05 06:15:04 PM PDT 24 31388831 ps
T1110 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3159667964 Aug 05 06:15:24 PM PDT 24 Aug 05 06:15:29 PM PDT 24 202078545 ps
T1111 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1245840356 Aug 05 06:14:59 PM PDT 24 Aug 05 06:15:04 PM PDT 24 309981750 ps
T1112 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1259426226 Aug 05 06:14:34 PM PDT 24 Aug 05 06:14:36 PM PDT 24 70939345 ps
T1113 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.814567660 Aug 05 06:15:37 PM PDT 24 Aug 05 06:15:38 PM PDT 24 39907104 ps
T1114 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2151695068 Aug 05 06:15:17 PM PDT 24 Aug 05 06:15:18 PM PDT 24 19892077 ps
T1115 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.399625453 Aug 05 06:14:48 PM PDT 24 Aug 05 06:14:48 PM PDT 24 12869964 ps
T1116 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4195697356 Aug 05 06:15:26 PM PDT 24 Aug 05 06:15:29 PM PDT 24 136719715 ps
T1117 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1873902363 Aug 05 06:15:17 PM PDT 24 Aug 05 06:15:20 PM PDT 24 268744173 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1730341138 Aug 05 06:14:52 PM PDT 24 Aug 05 06:14:54 PM PDT 24 106177656 ps
T1119 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1198702566 Aug 05 06:15:36 PM PDT 24 Aug 05 06:15:40 PM PDT 24 135124616 ps
T1120 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2357841438 Aug 05 06:15:30 PM PDT 24 Aug 05 06:15:34 PM PDT 24 250295793 ps
T1121 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.160567045 Aug 05 06:15:17 PM PDT 24 Aug 05 06:15:18 PM PDT 24 25806483 ps
T1122 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.529923765 Aug 05 06:15:02 PM PDT 24 Aug 05 06:15:06 PM PDT 24 141084384 ps
T1123 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2334534242 Aug 05 06:14:56 PM PDT 24 Aug 05 06:14:58 PM PDT 24 25949486 ps
T171 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4278794194 Aug 05 06:15:04 PM PDT 24 Aug 05 06:15:19 PM PDT 24 700158666 ps
T176 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.206036430 Aug 05 06:15:26 PM PDT 24 Aug 05 06:15:43 PM PDT 24 373619476 ps
T1124 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.525958085 Aug 05 06:15:18 PM PDT 24 Aug 05 06:15:26 PM PDT 24 656782722 ps
T1125 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3364011945 Aug 05 06:15:09 PM PDT 24 Aug 05 06:15:13 PM PDT 24 705092829 ps
T1126 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3714857758 Aug 05 06:15:32 PM PDT 24 Aug 05 06:15:33 PM PDT 24 15303723 ps
T1127 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.187956178 Aug 05 06:14:24 PM PDT 24 Aug 05 06:14:26 PM PDT 24 62149836 ps
T1128 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.466564253 Aug 05 06:14:41 PM PDT 24 Aug 05 06:14:42 PM PDT 24 44613741 ps
T1129 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1257398970 Aug 05 06:15:24 PM PDT 24 Aug 05 06:15:26 PM PDT 24 39679062 ps

Test location /workspace/coverage/default/21.spi_device_stress_all.2063822549
Short name T1
Test name
Test status
Simulation time 65412731539 ps
CPU time 542.63 seconds
Started Aug 05 06:28:44 PM PDT 24
Finished Aug 05 06:37:47 PM PDT 24
Peak memory 283492 kb
Host smart-70a5661f-ab85-48bd-b0b7-da0e24efa3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063822549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2063822549
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1459361160
Short name T13
Test name
Test status
Simulation time 61906360666 ps
CPU time 223.1 seconds
Started Aug 05 06:29:06 PM PDT 24
Finished Aug 05 06:32:49 PM PDT 24
Peak memory 254024 kb
Host smart-a356319c-f933-4c92-9fb0-556bb520eed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459361160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1459361160
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1017350052
Short name T68
Test name
Test status
Simulation time 750315348 ps
CPU time 8.56 seconds
Started Aug 05 06:15:27 PM PDT 24
Finished Aug 05 06:15:35 PM PDT 24
Peak memory 215224 kb
Host smart-f417d084-3829-4727-a115-eac0376f1de7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017350052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1017350052
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.493960829
Short name T27
Test name
Test status
Simulation time 270197684951 ps
CPU time 400.07 seconds
Started Aug 05 06:29:30 PM PDT 24
Finished Aug 05 06:36:10 PM PDT 24
Peak memory 250940 kb
Host smart-6d0d7bcf-89e8-4ff6-94cb-d5231dd99d96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493960829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.493960829
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1631680895
Short name T34
Test name
Test status
Simulation time 47358917409 ps
CPU time 439.08 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:35:10 PM PDT 24
Peak memory 266000 kb
Host smart-f3283181-f1ef-47cf-a999-9085e22c71ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631680895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1631680895
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2884673124
Short name T71
Test name
Test status
Simulation time 34749446 ps
CPU time 0.75 seconds
Started Aug 05 06:27:20 PM PDT 24
Finished Aug 05 06:27:21 PM PDT 24
Peak memory 216636 kb
Host smart-2130c933-ed3a-403f-9a5e-231499c78970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884673124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2884673124
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4151354706
Short name T201
Test name
Test status
Simulation time 131199056848 ps
CPU time 927.57 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:46:02 PM PDT 24
Peak memory 273592 kb
Host smart-d81e0756-ce10-4560-a6e3-57e6bef1f832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151354706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4151354706
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.214700196
Short name T20
Test name
Test status
Simulation time 36708709152 ps
CPU time 361.29 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:36:05 PM PDT 24
Peak memory 257856 kb
Host smart-b4678301-f3ea-473a-a493-3ba21bac65e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214700196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.214700196
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1502920186
Short name T46
Test name
Test status
Simulation time 14107272144 ps
CPU time 97.4 seconds
Started Aug 05 06:28:29 PM PDT 24
Finished Aug 05 06:30:07 PM PDT 24
Peak memory 268676 kb
Host smart-dddd81e9-72c5-4711-8e35-fab9ebed2d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502920186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1502920186
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2484863308
Short name T70
Test name
Test status
Simulation time 39101857 ps
CPU time 2.39 seconds
Started Aug 05 06:15:31 PM PDT 24
Finished Aug 05 06:15:34 PM PDT 24
Peak memory 215324 kb
Host smart-16c1852b-e35a-46fd-bb8e-2e27027cc300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484863308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2484863308
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2488842040
Short name T57
Test name
Test status
Simulation time 97548602722 ps
CPU time 598.55 seconds
Started Aug 05 06:28:27 PM PDT 24
Finished Aug 05 06:38:25 PM PDT 24
Peak memory 286000 kb
Host smart-e39753eb-a280-4ae8-aa7c-433ca8da4da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488842040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2488842040
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2632172566
Short name T15
Test name
Test status
Simulation time 203162316 ps
CPU time 1.13 seconds
Started Aug 05 06:27:38 PM PDT 24
Finished Aug 05 06:27:39 PM PDT 24
Peak memory 236268 kb
Host smart-e0a1b1b3-5252-48aa-acbd-8f5df6e262a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632172566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2632172566
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2679497879
Short name T135
Test name
Test status
Simulation time 4408059630 ps
CPU time 63.83 seconds
Started Aug 05 06:28:52 PM PDT 24
Finished Aug 05 06:29:56 PM PDT 24
Peak memory 241024 kb
Host smart-29f7253e-2577-40fc-92d4-f7299e793122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679497879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2679497879
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2975596632
Short name T203
Test name
Test status
Simulation time 12916974498 ps
CPU time 190.9 seconds
Started Aug 05 06:30:15 PM PDT 24
Finished Aug 05 06:33:26 PM PDT 24
Peak memory 272392 kb
Host smart-b7843ec4-a01c-4217-9c7a-6065ce7d8d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975596632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2975596632
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2152772333
Short name T29
Test name
Test status
Simulation time 159654866446 ps
CPU time 343.99 seconds
Started Aug 05 06:29:34 PM PDT 24
Finished Aug 05 06:35:19 PM PDT 24
Peak memory 257864 kb
Host smart-6fe1284f-37c7-4146-bcd9-ef8d6bf09405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152772333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2152772333
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.501277626
Short name T119
Test name
Test status
Simulation time 54342864 ps
CPU time 1.81 seconds
Started Aug 05 06:14:30 PM PDT 24
Finished Aug 05 06:14:32 PM PDT 24
Peak memory 215208 kb
Host smart-5b9eb7f7-2969-4537-9502-162ab23b296a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501277626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.501277626
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2308384583
Short name T77
Test name
Test status
Simulation time 299724450297 ps
CPU time 335.5 seconds
Started Aug 05 06:29:57 PM PDT 24
Finished Aug 05 06:35:32 PM PDT 24
Peak memory 270920 kb
Host smart-94dcd01f-f362-4d01-a581-393e7b8b619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308384583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2308384583
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.319975052
Short name T191
Test name
Test status
Simulation time 4535055757 ps
CPU time 106.78 seconds
Started Aug 05 06:29:43 PM PDT 24
Finished Aug 05 06:31:30 PM PDT 24
Peak memory 251384 kb
Host smart-b336436c-37b8-438c-ab6b-8ff0da02952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319975052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.319975052
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1467739786
Short name T255
Test name
Test status
Simulation time 172580538677 ps
CPU time 565.71 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:39:46 PM PDT 24
Peak memory 260840 kb
Host smart-5c34ca29-d0bc-453c-865b-6872890e0502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467739786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1467739786
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1904488891
Short name T59
Test name
Test status
Simulation time 9304372208 ps
CPU time 127.75 seconds
Started Aug 05 06:28:09 PM PDT 24
Finished Aug 05 06:30:17 PM PDT 24
Peak memory 256652 kb
Host smart-818e22f4-e2ee-496e-a13a-d68226a9772f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904488891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1904488891
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2288450609
Short name T9
Test name
Test status
Simulation time 1963821552 ps
CPU time 10.84 seconds
Started Aug 05 06:28:26 PM PDT 24
Finished Aug 05 06:28:37 PM PDT 24
Peak memory 216564 kb
Host smart-0a418ed3-733c-4ae8-81f0-70fd003be36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288450609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2288450609
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2664367812
Short name T186
Test name
Test status
Simulation time 236582311438 ps
CPU time 441.75 seconds
Started Aug 05 06:29:01 PM PDT 24
Finished Aug 05 06:36:23 PM PDT 24
Peak memory 257656 kb
Host smart-6c204abb-98e1-4717-bf50-153d1710a1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664367812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2664367812
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.226781740
Short name T172
Test name
Test status
Simulation time 1269627452 ps
CPU time 18.69 seconds
Started Aug 05 06:15:09 PM PDT 24
Finished Aug 05 06:15:28 PM PDT 24
Peak memory 215168 kb
Host smart-e8e5de0d-ac3c-4810-82fa-0ffa5481eb7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226781740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.226781740
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1624111900
Short name T983
Test name
Test status
Simulation time 75025623128 ps
CPU time 480.72 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:37:54 PM PDT 24
Peak memory 263204 kb
Host smart-f67d432d-c2fb-45f2-ab2a-2e9023f9bd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624111900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1624111900
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3792094121
Short name T49
Test name
Test status
Simulation time 12400693763 ps
CPU time 23.98 seconds
Started Aug 05 06:29:30 PM PDT 24
Finished Aug 05 06:29:54 PM PDT 24
Peak memory 216704 kb
Host smart-92067c50-f7e7-4935-bb64-71342a85ba04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792094121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3792094121
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2452632051
Short name T314
Test name
Test status
Simulation time 36425219 ps
CPU time 0.8 seconds
Started Aug 05 06:27:25 PM PDT 24
Finished Aug 05 06:27:26 PM PDT 24
Peak memory 205244 kb
Host smart-4903c1f8-af17-48ae-b717-3683156868a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452632051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
452632051
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2873731995
Short name T290
Test name
Test status
Simulation time 41943586891 ps
CPU time 226.99 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:32:19 PM PDT 24
Peak memory 257344 kb
Host smart-f693b3b9-5298-487b-b4f8-261c3ae477dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873731995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2873731995
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.604310768
Short name T207
Test name
Test status
Simulation time 15753908996 ps
CPU time 115.18 seconds
Started Aug 05 06:29:56 PM PDT 24
Finished Aug 05 06:31:52 PM PDT 24
Peak memory 266952 kb
Host smart-8c9a68db-1be4-4a41-8976-6c03477213d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604310768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.604310768
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2072270210
Short name T103
Test name
Test status
Simulation time 148333892 ps
CPU time 4.47 seconds
Started Aug 05 06:15:03 PM PDT 24
Finished Aug 05 06:15:08 PM PDT 24
Peak memory 216420 kb
Host smart-73bc738e-ad00-48f7-8d70-ad9396301a34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072270210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
072270210
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.942785034
Short name T149
Test name
Test status
Simulation time 45813352836 ps
CPU time 463.79 seconds
Started Aug 05 06:27:35 PM PDT 24
Finished Aug 05 06:35:19 PM PDT 24
Peak memory 256940 kb
Host smart-7c4c77f9-db70-45ff-b875-27422f4570ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942785034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.942785034
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3077530825
Short name T23
Test name
Test status
Simulation time 1992291647 ps
CPU time 26.55 seconds
Started Aug 05 06:30:36 PM PDT 24
Finished Aug 05 06:31:03 PM PDT 24
Peak memory 216708 kb
Host smart-2c1c55c1-98ad-4280-8006-f33499b8277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077530825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3077530825
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2260033441
Short name T283
Test name
Test status
Simulation time 46117108090 ps
CPU time 327.13 seconds
Started Aug 05 06:28:48 PM PDT 24
Finished Aug 05 06:34:15 PM PDT 24
Peak memory 265972 kb
Host smart-c72c6cec-7096-4e49-828a-96f5332ab23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260033441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2260033441
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3466406461
Short name T18
Test name
Test status
Simulation time 1217929584 ps
CPU time 14.99 seconds
Started Aug 05 06:29:03 PM PDT 24
Finished Aug 05 06:29:18 PM PDT 24
Peak memory 223008 kb
Host smart-01ae87aa-8bb5-4ce0-8b1c-3e2646b7557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466406461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3466406461
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3987255371
Short name T54
Test name
Test status
Simulation time 7649834728 ps
CPU time 78.18 seconds
Started Aug 05 06:28:25 PM PDT 24
Finished Aug 05 06:29:43 PM PDT 24
Peak memory 272264 kb
Host smart-ba71f521-805a-4a05-a2ed-f8abf9e7636a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987255371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3987255371
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4278794194
Short name T171
Test name
Test status
Simulation time 700158666 ps
CPU time 14.93 seconds
Started Aug 05 06:15:04 PM PDT 24
Finished Aug 05 06:15:19 PM PDT 24
Peak memory 215276 kb
Host smart-9f35385b-5ae3-442b-844b-d3789e441d62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278794194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4278794194
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2167182296
Short name T180
Test name
Test status
Simulation time 687943678 ps
CPU time 16.76 seconds
Started Aug 05 06:27:27 PM PDT 24
Finished Aug 05 06:27:44 PM PDT 24
Peak memory 224916 kb
Host smart-1a5597a7-33c7-4ffe-89f1-101dd0fe03ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167182296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2167182296
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3473945120
Short name T161
Test name
Test status
Simulation time 326160336 ps
CPU time 10.79 seconds
Started Aug 05 06:28:10 PM PDT 24
Finished Aug 05 06:28:21 PM PDT 24
Peak memory 233220 kb
Host smart-cffc27fb-6d5a-4e0a-a262-01ad9f2f8192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473945120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3473945120
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2783310633
Short name T178
Test name
Test status
Simulation time 13170104171 ps
CPU time 105.79 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:30:07 PM PDT 24
Peak memory 252708 kb
Host smart-85f563b7-a537-4d6c-a8e1-d6acdd39b3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783310633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2783310633
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.163661202
Short name T264
Test name
Test status
Simulation time 3776077350 ps
CPU time 57.5 seconds
Started Aug 05 06:27:33 PM PDT 24
Finished Aug 05 06:28:31 PM PDT 24
Peak memory 249572 kb
Host smart-8f8b49b0-ca21-4ed1-b5f3-697fbe749947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163661202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.163661202
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1694356633
Short name T175
Test name
Test status
Simulation time 204009022 ps
CPU time 12.71 seconds
Started Aug 05 06:15:21 PM PDT 24
Finished Aug 05 06:15:34 PM PDT 24
Peak memory 215180 kb
Host smart-8e3c7f36-eff4-4103-a43a-6379ba39fbb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694356633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1694356633
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.301165333
Short name T156
Test name
Test status
Simulation time 800899746 ps
CPU time 13.11 seconds
Started Aug 05 06:27:56 PM PDT 24
Finished Aug 05 06:28:10 PM PDT 24
Peak memory 233184 kb
Host smart-313601be-a7ff-4476-ba0c-8db14988ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301165333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.301165333
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2379045486
Short name T195
Test name
Test status
Simulation time 100827206495 ps
CPU time 212.85 seconds
Started Aug 05 06:28:23 PM PDT 24
Finished Aug 05 06:31:56 PM PDT 24
Peak memory 252392 kb
Host smart-9e4f7fe6-c610-4e2f-b5e9-a28eb0f53a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379045486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2379045486
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3808735853
Short name T200
Test name
Test status
Simulation time 317854162 ps
CPU time 7.61 seconds
Started Aug 05 06:28:31 PM PDT 24
Finished Aug 05 06:28:39 PM PDT 24
Peak memory 220224 kb
Host smart-1dac2813-9095-458d-92a2-27b5cc010ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808735853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3808735853
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4271132242
Short name T311
Test name
Test status
Simulation time 2897432164 ps
CPU time 14.3 seconds
Started Aug 05 06:29:13 PM PDT 24
Finished Aug 05 06:29:27 PM PDT 24
Peak memory 219768 kb
Host smart-2f6a5417-2884-4ecb-8ca7-b35f0c047d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271132242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4271132242
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3893832519
Short name T86
Test name
Test status
Simulation time 14149999270 ps
CPU time 88.67 seconds
Started Aug 05 06:27:54 PM PDT 24
Finished Aug 05 06:29:23 PM PDT 24
Peak memory 233196 kb
Host smart-56ab068e-f419-4900-91cb-ffe74331edf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893832519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3893832519
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3294205529
Short name T104
Test name
Test status
Simulation time 266670358 ps
CPU time 4.44 seconds
Started Aug 05 06:14:19 PM PDT 24
Finished Aug 05 06:14:24 PM PDT 24
Peak memory 216328 kb
Host smart-3380b089-809f-4793-b9c3-660ba1a5eb04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294205529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
294205529
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3625606239
Short name T80
Test name
Test status
Simulation time 73227989 ps
CPU time 1.12 seconds
Started Aug 05 06:14:54 PM PDT 24
Finished Aug 05 06:14:55 PM PDT 24
Peak memory 217260 kb
Host smart-408ac392-1d1f-4831-9a08-b65ac30c56be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625606239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3625606239
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3442470680
Short name T32
Test name
Test status
Simulation time 61674264840 ps
CPU time 152.28 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:30:25 PM PDT 24
Peak memory 241232 kb
Host smart-76065923-5d9e-4c92-a2a2-592e63b0da99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442470680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3442470680
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.31869595
Short name T1044
Test name
Test status
Simulation time 119262801 ps
CPU time 7.26 seconds
Started Aug 05 06:14:24 PM PDT 24
Finished Aug 05 06:14:31 PM PDT 24
Peak memory 206936 kb
Host smart-34485a3e-0dbd-4286-9deb-6927a06a79ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31869595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
aliasing.31869595
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3495593545
Short name T1022
Test name
Test status
Simulation time 191919630 ps
CPU time 11.38 seconds
Started Aug 05 06:14:24 PM PDT 24
Finished Aug 05 06:14:36 PM PDT 24
Peak memory 207148 kb
Host smart-913184f8-0bae-4e1b-bb0e-cfdfdccdbee2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495593545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3495593545
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.12097
Short name T1099
Test name
Test status
Simulation time 21904706 ps
CPU time 0.93 seconds
Started Aug 05 06:14:23 PM PDT 24
Finished Aug 05 06:14:24 PM PDT 24
Peak memory 206816 kb
Host smart-a44242a2-3195-4d66-a027-362b3f00ffb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_
reset.12097
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3702675540
Short name T1076
Test name
Test status
Simulation time 233999877 ps
CPU time 1.74 seconds
Started Aug 05 06:14:22 PM PDT 24
Finished Aug 05 06:14:24 PM PDT 24
Peak memory 215484 kb
Host smart-4936cd1c-a99d-47aa-b5fc-471e472972d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702675540 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3702675540
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.187956178
Short name T1127
Test name
Test status
Simulation time 62149836 ps
CPU time 1.43 seconds
Started Aug 05 06:14:24 PM PDT 24
Finished Aug 05 06:14:26 PM PDT 24
Peak memory 215232 kb
Host smart-2a353dbd-abec-40b9-b3ec-bd080133701d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187956178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.187956178
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2534851059
Short name T1036
Test name
Test status
Simulation time 12719827 ps
CPU time 0.7 seconds
Started Aug 05 06:14:19 PM PDT 24
Finished Aug 05 06:14:20 PM PDT 24
Peak memory 203676 kb
Host smart-2e357a91-9884-4b30-9644-9fec39d0d0f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534851059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
534851059
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2865043421
Short name T1059
Test name
Test status
Simulation time 26985528 ps
CPU time 1.78 seconds
Started Aug 05 06:14:20 PM PDT 24
Finished Aug 05 06:14:22 PM PDT 24
Peak memory 215152 kb
Host smart-6a7b459d-98ed-41e9-ba9e-1a7222214849
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865043421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2865043421
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2199017924
Short name T1010
Test name
Test status
Simulation time 34852002 ps
CPU time 0.63 seconds
Started Aug 05 06:14:20 PM PDT 24
Finished Aug 05 06:14:21 PM PDT 24
Peak memory 203968 kb
Host smart-868dd461-184b-4950-ab3a-04992209f965
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199017924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2199017924
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1296098227
Short name T1071
Test name
Test status
Simulation time 163805817 ps
CPU time 1.65 seconds
Started Aug 05 06:14:24 PM PDT 24
Finished Aug 05 06:14:26 PM PDT 24
Peak memory 215192 kb
Host smart-e26cd0b5-3858-4888-a5cd-1c397f097f05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296098227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1296098227
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2317762756
Short name T174
Test name
Test status
Simulation time 797874454 ps
CPU time 6.42 seconds
Started Aug 05 06:14:18 PM PDT 24
Finished Aug 05 06:14:25 PM PDT 24
Peak memory 215160 kb
Host smart-311d0752-9c58-4570-8e53-8b1d7d61e9eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317762756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2317762756
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1234064700
Short name T1061
Test name
Test status
Simulation time 120525080 ps
CPU time 7.28 seconds
Started Aug 05 06:14:34 PM PDT 24
Finished Aug 05 06:14:41 PM PDT 24
Peak memory 207072 kb
Host smart-7ab30594-1fcf-4826-812d-3282d13c7eaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234064700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1234064700
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2397890024
Short name T1034
Test name
Test status
Simulation time 2083987824 ps
CPU time 32.46 seconds
Started Aug 05 06:14:35 PM PDT 24
Finished Aug 05 06:15:07 PM PDT 24
Peak memory 206952 kb
Host smart-3f4e0d71-0b23-48e6-8046-fc49a5ff1ff7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397890024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2397890024
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2744066101
Short name T81
Test name
Test status
Simulation time 65042982 ps
CPU time 1.14 seconds
Started Aug 05 06:14:29 PM PDT 24
Finished Aug 05 06:14:30 PM PDT 24
Peak memory 206916 kb
Host smart-e2a12537-5579-4773-b275-c3b12d72cd72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744066101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2744066101
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2111207328
Short name T114
Test name
Test status
Simulation time 59356636 ps
CPU time 1.74 seconds
Started Aug 05 06:14:35 PM PDT 24
Finished Aug 05 06:14:36 PM PDT 24
Peak memory 215120 kb
Host smart-12ef3be8-1858-4f23-972d-06a606ef64f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111207328 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2111207328
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3687464573
Short name T1086
Test name
Test status
Simulation time 34637281 ps
CPU time 0.72 seconds
Started Aug 05 06:14:30 PM PDT 24
Finished Aug 05 06:14:31 PM PDT 24
Peak memory 203652 kb
Host smart-a66e6cb6-f2fd-453c-964d-039341602382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687464573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
687464573
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2653265002
Short name T1080
Test name
Test status
Simulation time 29504306 ps
CPU time 1.84 seconds
Started Aug 05 06:14:31 PM PDT 24
Finished Aug 05 06:14:33 PM PDT 24
Peak memory 215172 kb
Host smart-66d0972b-4279-4ac1-bf2e-212bf4335287
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653265002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2653265002
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3876672168
Short name T1082
Test name
Test status
Simulation time 19961809 ps
CPU time 0.66 seconds
Started Aug 05 06:14:29 PM PDT 24
Finished Aug 05 06:14:29 PM PDT 24
Peak memory 203940 kb
Host smart-f4e24ac3-deb5-452e-bf1f-c957d580a71a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876672168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3876672168
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1259426226
Short name T1112
Test name
Test status
Simulation time 70939345 ps
CPU time 1.77 seconds
Started Aug 05 06:14:34 PM PDT 24
Finished Aug 05 06:14:36 PM PDT 24
Peak memory 215192 kb
Host smart-a1e714e5-3d18-40e7-9a1c-1b0540a9f877
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259426226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1259426226
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1500264918
Short name T1056
Test name
Test status
Simulation time 741787057 ps
CPU time 3.3 seconds
Started Aug 05 06:14:30 PM PDT 24
Finished Aug 05 06:14:33 PM PDT 24
Peak memory 215288 kb
Host smart-d0700672-3fdf-44d5-82f8-b04c01a4d129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500264918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
500264918
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2714605753
Short name T111
Test name
Test status
Simulation time 307385770 ps
CPU time 18.56 seconds
Started Aug 05 06:14:30 PM PDT 24
Finished Aug 05 06:14:48 PM PDT 24
Peak memory 215236 kb
Host smart-5aaeea11-36ae-4bfa-976f-829711dcaf1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714605753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2714605753
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3199521157
Short name T1108
Test name
Test status
Simulation time 208831381 ps
CPU time 1.61 seconds
Started Aug 05 06:15:15 PM PDT 24
Finished Aug 05 06:15:16 PM PDT 24
Peak memory 215312 kb
Host smart-35c66cf5-7204-4a78-b7de-cd6004fc057b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199521157 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3199521157
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2950761114
Short name T121
Test name
Test status
Simulation time 347047164 ps
CPU time 2.46 seconds
Started Aug 05 06:15:15 PM PDT 24
Finished Aug 05 06:15:17 PM PDT 24
Peak memory 215208 kb
Host smart-b64ac346-33ca-4b79-8937-c702387b31f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950761114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2950761114
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1502723444
Short name T1070
Test name
Test status
Simulation time 38153852 ps
CPU time 0.73 seconds
Started Aug 05 06:15:15 PM PDT 24
Finished Aug 05 06:15:16 PM PDT 24
Peak memory 203680 kb
Host smart-2438f934-2763-4c28-9d17-d981ba0cff6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502723444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1502723444
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.264582096
Short name T133
Test name
Test status
Simulation time 144763560 ps
CPU time 1.78 seconds
Started Aug 05 06:15:15 PM PDT 24
Finished Aug 05 06:15:17 PM PDT 24
Peak memory 215152 kb
Host smart-03ab7607-b90e-4b59-86d7-dced84974392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264582096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.264582096
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.541746820
Short name T109
Test name
Test status
Simulation time 424698276 ps
CPU time 2.87 seconds
Started Aug 05 06:15:08 PM PDT 24
Finished Aug 05 06:15:11 PM PDT 24
Peak memory 215212 kb
Host smart-b3792f5e-4670-42bc-b7af-d6365b95f345
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541746820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.541746820
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.489014006
Short name T1093
Test name
Test status
Simulation time 113401253 ps
CPU time 6.26 seconds
Started Aug 05 06:15:10 PM PDT 24
Finished Aug 05 06:15:16 PM PDT 24
Peak memory 215232 kb
Host smart-c28c4674-f02b-45d4-aa60-cc0f28f969b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489014006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.489014006
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3559482756
Short name T1104
Test name
Test status
Simulation time 163209466 ps
CPU time 1.7 seconds
Started Aug 05 06:15:18 PM PDT 24
Finished Aug 05 06:15:20 PM PDT 24
Peak memory 216092 kb
Host smart-987212f8-3a93-4080-8c00-30fcfc1e12da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559482756 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3559482756
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3253255790
Short name T124
Test name
Test status
Simulation time 49734056 ps
CPU time 1.74 seconds
Started Aug 05 06:15:17 PM PDT 24
Finished Aug 05 06:15:19 PM PDT 24
Peak memory 215200 kb
Host smart-debc086b-a8d0-486f-bf53-3cc04553dc4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253255790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3253255790
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2151695068
Short name T1114
Test name
Test status
Simulation time 19892077 ps
CPU time 0.76 seconds
Started Aug 05 06:15:17 PM PDT 24
Finished Aug 05 06:15:18 PM PDT 24
Peak memory 203664 kb
Host smart-ec617199-f073-41e6-9d8e-e95225d67b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151695068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2151695068
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1873902363
Short name T1117
Test name
Test status
Simulation time 268744173 ps
CPU time 3.02 seconds
Started Aug 05 06:15:17 PM PDT 24
Finished Aug 05 06:15:20 PM PDT 24
Peak memory 215144 kb
Host smart-bda94165-13fb-4c33-b525-881ce270ed85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873902363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1873902363
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.164751562
Short name T110
Test name
Test status
Simulation time 77749106 ps
CPU time 4.86 seconds
Started Aug 05 06:15:15 PM PDT 24
Finished Aug 05 06:15:20 PM PDT 24
Peak memory 215332 kb
Host smart-dfd41263-33c0-471e-8473-238bdb487e66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164751562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.164751562
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2669014273
Short name T69
Test name
Test status
Simulation time 1451145910 ps
CPU time 15.08 seconds
Started Aug 05 06:15:17 PM PDT 24
Finished Aug 05 06:15:32 PM PDT 24
Peak memory 215152 kb
Host smart-f91cd8e9-53d6-4955-9c65-f54d0ed8bcc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669014273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2669014273
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2939746784
Short name T1094
Test name
Test status
Simulation time 202637637 ps
CPU time 3.29 seconds
Started Aug 05 06:15:19 PM PDT 24
Finished Aug 05 06:15:23 PM PDT 24
Peak memory 217188 kb
Host smart-6ace8b72-158e-4a78-802f-488c44dc5b6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939746784 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2939746784
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2893829149
Short name T122
Test name
Test status
Simulation time 68806946 ps
CPU time 1.81 seconds
Started Aug 05 06:15:19 PM PDT 24
Finished Aug 05 06:15:21 PM PDT 24
Peak memory 215276 kb
Host smart-a5be01d2-21d8-4c5b-803b-43fa39df8560
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893829149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2893829149
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.194663035
Short name T1028
Test name
Test status
Simulation time 14018913 ps
CPU time 0.68 seconds
Started Aug 05 06:15:24 PM PDT 24
Finished Aug 05 06:15:25 PM PDT 24
Peak memory 203992 kb
Host smart-756bc5aa-792f-434e-a7bd-fc3e716ebf41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194663035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.194663035
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3159667964
Short name T1110
Test name
Test status
Simulation time 202078545 ps
CPU time 4.13 seconds
Started Aug 05 06:15:24 PM PDT 24
Finished Aug 05 06:15:29 PM PDT 24
Peak memory 215144 kb
Host smart-0920c967-33a9-449d-8155-290c120a1d40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159667964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3159667964
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3477422194
Short name T1092
Test name
Test status
Simulation time 614587698 ps
CPU time 4.8 seconds
Started Aug 05 06:15:19 PM PDT 24
Finished Aug 05 06:15:24 PM PDT 24
Peak memory 216328 kb
Host smart-3e87d76d-2065-4e3b-aeb9-b06715c0c468
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477422194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3477422194
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3161233699
Short name T97
Test name
Test status
Simulation time 39773355 ps
CPU time 1.56 seconds
Started Aug 05 06:15:24 PM PDT 24
Finished Aug 05 06:15:25 PM PDT 24
Peak memory 215420 kb
Host smart-7ef988b6-31f3-406e-9b9d-49b881365de0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161233699 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3161233699
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1257398970
Short name T1129
Test name
Test status
Simulation time 39679062 ps
CPU time 1.33 seconds
Started Aug 05 06:15:24 PM PDT 24
Finished Aug 05 06:15:26 PM PDT 24
Peak memory 215168 kb
Host smart-683b53f1-6a61-466b-8793-afeb8a8f014f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257398970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1257398970
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.160567045
Short name T1121
Test name
Test status
Simulation time 25806483 ps
CPU time 0.74 seconds
Started Aug 05 06:15:17 PM PDT 24
Finished Aug 05 06:15:18 PM PDT 24
Peak memory 203852 kb
Host smart-31b09e51-490f-4c53-ae05-0fcc9e9ece3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160567045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.160567045
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.499185332
Short name T1042
Test name
Test status
Simulation time 61100470 ps
CPU time 3.65 seconds
Started Aug 05 06:15:18 PM PDT 24
Finished Aug 05 06:15:22 PM PDT 24
Peak memory 215216 kb
Host smart-266dda6e-8d90-4890-a597-fe978279a5a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499185332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.499185332
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1571479622
Short name T1079
Test name
Test status
Simulation time 543209904 ps
CPU time 3.82 seconds
Started Aug 05 06:15:24 PM PDT 24
Finished Aug 05 06:15:28 PM PDT 24
Peak memory 215320 kb
Host smart-68a97c98-00b7-494c-b6fb-8bd10ab77892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571479622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1571479622
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3552245829
Short name T169
Test name
Test status
Simulation time 1671422581 ps
CPU time 22.2 seconds
Started Aug 05 06:15:24 PM PDT 24
Finished Aug 05 06:15:46 PM PDT 24
Peak memory 223360 kb
Host smart-4777c455-8492-42ea-b693-7f7e1eedc24a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552245829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3552245829
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3898635169
Short name T107
Test name
Test status
Simulation time 77002654 ps
CPU time 3.36 seconds
Started Aug 05 06:15:25 PM PDT 24
Finished Aug 05 06:15:28 PM PDT 24
Peak memory 218504 kb
Host smart-e8af185a-b7ad-442e-89fa-5cae380420ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898635169 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3898635169
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2101544995
Short name T1055
Test name
Test status
Simulation time 189281728 ps
CPU time 1.75 seconds
Started Aug 05 06:15:18 PM PDT 24
Finished Aug 05 06:15:20 PM PDT 24
Peak memory 207000 kb
Host smart-8bda3753-e069-4307-b981-056ca636d18d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101544995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2101544995
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3522808166
Short name T1072
Test name
Test status
Simulation time 15354443 ps
CPU time 0.68 seconds
Started Aug 05 06:15:20 PM PDT 24
Finished Aug 05 06:15:21 PM PDT 24
Peak memory 203684 kb
Host smart-cd57919f-89aa-486b-906f-a31a884e87a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522808166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3522808166
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4135397187
Short name T1081
Test name
Test status
Simulation time 158784825 ps
CPU time 4.2 seconds
Started Aug 05 06:15:25 PM PDT 24
Finished Aug 05 06:15:29 PM PDT 24
Peak memory 215140 kb
Host smart-8819920d-c3d2-4f59-9fcf-6dbccdbebf53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135397187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.4135397187
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2366970870
Short name T1046
Test name
Test status
Simulation time 527478851 ps
CPU time 3.28 seconds
Started Aug 05 06:15:16 PM PDT 24
Finished Aug 05 06:15:19 PM PDT 24
Peak memory 215324 kb
Host smart-6206738e-f87f-481a-9ca9-29be7e77bbf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366970870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2366970870
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.525958085
Short name T1124
Test name
Test status
Simulation time 656782722 ps
CPU time 7.63 seconds
Started Aug 05 06:15:18 PM PDT 24
Finished Aug 05 06:15:26 PM PDT 24
Peak memory 215768 kb
Host smart-8dcbbf50-405b-41ed-a7c8-14e25782fe95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525958085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.525958085
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3851345501
Short name T112
Test name
Test status
Simulation time 192736596 ps
CPU time 2.65 seconds
Started Aug 05 06:15:25 PM PDT 24
Finished Aug 05 06:15:28 PM PDT 24
Peak memory 216348 kb
Host smart-bc78baaf-6f82-4722-b9d2-697074f9db04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851345501 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3851345501
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4251037785
Short name T125
Test name
Test status
Simulation time 40489873 ps
CPU time 1.24 seconds
Started Aug 05 06:15:25 PM PDT 24
Finished Aug 05 06:15:26 PM PDT 24
Peak memory 215216 kb
Host smart-11c8912d-4a04-4a87-866c-faea3689e0ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251037785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4251037785
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2157427315
Short name T1024
Test name
Test status
Simulation time 34201058 ps
CPU time 0.76 seconds
Started Aug 05 06:15:28 PM PDT 24
Finished Aug 05 06:15:28 PM PDT 24
Peak memory 203716 kb
Host smart-fc5d34fd-f6b7-4a7c-a035-5381d54d42a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157427315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2157427315
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1964846077
Short name T1085
Test name
Test status
Simulation time 233228737 ps
CPU time 3.76 seconds
Started Aug 05 06:15:29 PM PDT 24
Finished Aug 05 06:15:33 PM PDT 24
Peak memory 215224 kb
Host smart-d4877728-226e-4b31-b7f5-64fb7140e4ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964846077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1964846077
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.362485104
Short name T1096
Test name
Test status
Simulation time 42949371 ps
CPU time 2.48 seconds
Started Aug 05 06:15:26 PM PDT 24
Finished Aug 05 06:15:29 PM PDT 24
Peak memory 216328 kb
Host smart-4ac73c88-edf4-4bb4-b23c-5a50f98da7f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362485104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.362485104
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1221590290
Short name T1060
Test name
Test status
Simulation time 203795895 ps
CPU time 3.59 seconds
Started Aug 05 06:15:25 PM PDT 24
Finished Aug 05 06:15:29 PM PDT 24
Peak memory 218620 kb
Host smart-8f996e65-e560-4bc0-842a-9828b0ab6490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221590290 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1221590290
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.17448014
Short name T134
Test name
Test status
Simulation time 90166507 ps
CPU time 2.2 seconds
Started Aug 05 06:15:25 PM PDT 24
Finished Aug 05 06:15:28 PM PDT 24
Peak memory 215188 kb
Host smart-6b6b0ea5-1504-4d00-b414-556ba888a2f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17448014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.17448014
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.850613955
Short name T1033
Test name
Test status
Simulation time 19553790 ps
CPU time 0.76 seconds
Started Aug 05 06:15:27 PM PDT 24
Finished Aug 05 06:15:28 PM PDT 24
Peak memory 203696 kb
Host smart-20fae5d0-652c-400c-af5c-40d8f146eca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850613955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.850613955
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4209916661
Short name T1023
Test name
Test status
Simulation time 66100897 ps
CPU time 1.84 seconds
Started Aug 05 06:15:26 PM PDT 24
Finished Aug 05 06:15:28 PM PDT 24
Peak memory 215196 kb
Host smart-75e28bd5-b8ff-4cda-ba0a-009b7836e87b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209916661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4209916661
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4195697356
Short name T1116
Test name
Test status
Simulation time 136719715 ps
CPU time 3.21 seconds
Started Aug 05 06:15:26 PM PDT 24
Finished Aug 05 06:15:29 PM PDT 24
Peak memory 215248 kb
Host smart-70763c2d-93c6-4c98-8b65-254b493411d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195697356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4195697356
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.206036430
Short name T176
Test name
Test status
Simulation time 373619476 ps
CPU time 17.39 seconds
Started Aug 05 06:15:26 PM PDT 24
Finished Aug 05 06:15:43 PM PDT 24
Peak memory 215320 kb
Host smart-cd1f8284-3537-4e56-ad3d-6a7676f92b83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206036430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.206036430
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.445449940
Short name T1035
Test name
Test status
Simulation time 38339676 ps
CPU time 2.56 seconds
Started Aug 05 06:15:31 PM PDT 24
Finished Aug 05 06:15:33 PM PDT 24
Peak memory 216364 kb
Host smart-ca3581a1-cc8a-4e48-97b1-c998e0205b84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445449940 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.445449940
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2987089660
Short name T117
Test name
Test status
Simulation time 43051665 ps
CPU time 2.5 seconds
Started Aug 05 06:15:28 PM PDT 24
Finished Aug 05 06:15:30 PM PDT 24
Peak memory 206952 kb
Host smart-8dd3bade-1b07-4603-99bc-1a60e581a9cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987089660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2987089660
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2049699140
Short name T1039
Test name
Test status
Simulation time 14946002 ps
CPU time 0.68 seconds
Started Aug 05 06:15:26 PM PDT 24
Finished Aug 05 06:15:27 PM PDT 24
Peak memory 203976 kb
Host smart-806e9d4a-e65f-4328-8383-38b09157e80c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049699140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2049699140
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3287266540
Short name T1050
Test name
Test status
Simulation time 41758704 ps
CPU time 2.49 seconds
Started Aug 05 06:15:31 PM PDT 24
Finished Aug 05 06:15:34 PM PDT 24
Peak memory 215116 kb
Host smart-714392b6-0b37-47cc-9f0c-be9b188e1827
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287266540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3287266540
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4076274461
Short name T99
Test name
Test status
Simulation time 34720689 ps
CPU time 2.05 seconds
Started Aug 05 06:15:25 PM PDT 24
Finished Aug 05 06:15:27 PM PDT 24
Peak memory 215328 kb
Host smart-ac8c9d15-6633-4acd-9017-497d008d245a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076274461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4076274461
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3963471289
Short name T173
Test name
Test status
Simulation time 773878278 ps
CPU time 15.26 seconds
Started Aug 05 06:15:27 PM PDT 24
Finished Aug 05 06:15:42 PM PDT 24
Peak memory 215232 kb
Host smart-b6608c93-64ca-4c8e-a1fc-9c4cc9fecc53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963471289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3963471289
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2357841438
Short name T1120
Test name
Test status
Simulation time 250295793 ps
CPU time 3.39 seconds
Started Aug 05 06:15:30 PM PDT 24
Finished Aug 05 06:15:34 PM PDT 24
Peak memory 218136 kb
Host smart-66deebbe-a8bc-45ee-b94b-bf37d83e3a96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357841438 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2357841438
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3010844428
Short name T1031
Test name
Test status
Simulation time 155501995 ps
CPU time 1.38 seconds
Started Aug 05 06:15:31 PM PDT 24
Finished Aug 05 06:15:33 PM PDT 24
Peak memory 206948 kb
Host smart-4931aa78-e75f-4535-ae5e-648bc22e0f59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010844428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3010844428
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.10921037
Short name T1016
Test name
Test status
Simulation time 17260783 ps
CPU time 0.75 seconds
Started Aug 05 06:15:36 PM PDT 24
Finished Aug 05 06:15:37 PM PDT 24
Peak memory 203664 kb
Host smart-f241b5bf-111c-4ab9-ae4c-2c1c14deb57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10921037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.10921037
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1803874977
Short name T1105
Test name
Test status
Simulation time 98311978 ps
CPU time 1.59 seconds
Started Aug 05 06:15:30 PM PDT 24
Finished Aug 05 06:15:32 PM PDT 24
Peak memory 215228 kb
Host smart-9cefc49a-b210-4354-afb7-7d5d9993aeb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803874977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1803874977
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3407187740
Short name T1077
Test name
Test status
Simulation time 575961464 ps
CPU time 17.24 seconds
Started Aug 05 06:15:31 PM PDT 24
Finished Aug 05 06:15:49 PM PDT 24
Peak memory 215232 kb
Host smart-ccd69e4e-2c98-4edc-bf75-ee9dd539a8e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407187740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3407187740
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1198702566
Short name T1119
Test name
Test status
Simulation time 135124616 ps
CPU time 3.76 seconds
Started Aug 05 06:15:36 PM PDT 24
Finished Aug 05 06:15:40 PM PDT 24
Peak memory 218080 kb
Host smart-fff679fc-7fed-4e86-a54d-a357e4bb78fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198702566 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1198702566
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3318122781
Short name T1043
Test name
Test status
Simulation time 129626499 ps
CPU time 1.39 seconds
Started Aug 05 06:15:31 PM PDT 24
Finished Aug 05 06:15:32 PM PDT 24
Peak memory 206888 kb
Host smart-729675ae-3b0f-4294-bfcc-3bef4e9e61cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318122781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3318122781
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3714857758
Short name T1126
Test name
Test status
Simulation time 15303723 ps
CPU time 0.7 seconds
Started Aug 05 06:15:32 PM PDT 24
Finished Aug 05 06:15:33 PM PDT 24
Peak memory 203676 kb
Host smart-fb12a424-24b7-40ea-89ad-ca21aea3adc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714857758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3714857758
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1178955829
Short name T1049
Test name
Test status
Simulation time 887135614 ps
CPU time 2.83 seconds
Started Aug 05 06:15:32 PM PDT 24
Finished Aug 05 06:15:35 PM PDT 24
Peak memory 215144 kb
Host smart-f1b0c37b-f314-42c6-95db-33bc8f716263
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178955829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1178955829
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3779074178
Short name T108
Test name
Test status
Simulation time 88762498 ps
CPU time 2.5 seconds
Started Aug 05 06:15:32 PM PDT 24
Finished Aug 05 06:15:35 PM PDT 24
Peak memory 215408 kb
Host smart-8d5b5925-c0f8-420c-931d-d3b758d7de13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779074178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3779074178
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.820226088
Short name T1084
Test name
Test status
Simulation time 5258889185 ps
CPU time 15.06 seconds
Started Aug 05 06:15:30 PM PDT 24
Finished Aug 05 06:15:45 PM PDT 24
Peak memory 216524 kb
Host smart-3c837cc9-227d-497b-94bc-c0042f3da5b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820226088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.820226088
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2527602729
Short name T143
Test name
Test status
Simulation time 422774661 ps
CPU time 8.32 seconds
Started Aug 05 06:14:40 PM PDT 24
Finished Aug 05 06:14:48 PM PDT 24
Peak memory 206892 kb
Host smart-f1ab1963-0dfd-472e-af4d-d09b8a29b10f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527602729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2527602729
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3956357813
Short name T144
Test name
Test status
Simulation time 1831490197 ps
CPU time 26.65 seconds
Started Aug 05 06:14:41 PM PDT 24
Finished Aug 05 06:15:08 PM PDT 24
Peak memory 206996 kb
Host smart-a65bd099-e284-4310-a32a-892263dcb3ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956357813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3956357813
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3192990990
Short name T78
Test name
Test status
Simulation time 14023634 ps
CPU time 0.91 seconds
Started Aug 05 06:14:40 PM PDT 24
Finished Aug 05 06:14:41 PM PDT 24
Peak memory 206704 kb
Host smart-5b33673f-da04-4759-b317-8906df05228b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192990990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3192990990
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2077974104
Short name T1087
Test name
Test status
Simulation time 174659771 ps
CPU time 1.82 seconds
Started Aug 05 06:14:48 PM PDT 24
Finished Aug 05 06:14:50 PM PDT 24
Peak memory 216168 kb
Host smart-56964821-f704-4e45-9d3f-e73cfb81f687
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077974104 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2077974104
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2866297049
Short name T126
Test name
Test status
Simulation time 248927471 ps
CPU time 1.88 seconds
Started Aug 05 06:14:41 PM PDT 24
Finished Aug 05 06:14:43 PM PDT 24
Peak memory 215308 kb
Host smart-4aa765b3-4148-4169-b0f4-30fb0c8b5ddf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866297049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
866297049
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.466564253
Short name T1128
Test name
Test status
Simulation time 44613741 ps
CPU time 0.68 seconds
Started Aug 05 06:14:41 PM PDT 24
Finished Aug 05 06:14:42 PM PDT 24
Peak memory 203656 kb
Host smart-976d5567-50ce-490a-9a0b-5baf221f92b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466564253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.466564253
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.914679660
Short name T127
Test name
Test status
Simulation time 57213084 ps
CPU time 2.13 seconds
Started Aug 05 06:14:41 PM PDT 24
Finished Aug 05 06:14:43 PM PDT 24
Peak memory 215176 kb
Host smart-7e671fc2-a0ae-4636-8f4a-70dc37bc0342
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914679660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.914679660
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3408201744
Short name T1057
Test name
Test status
Simulation time 37688732 ps
CPU time 0.64 seconds
Started Aug 05 06:14:40 PM PDT 24
Finished Aug 05 06:14:41 PM PDT 24
Peak memory 203920 kb
Host smart-11a16915-0d65-4c1b-9c9e-43929151af68
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408201744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3408201744
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1480563525
Short name T1063
Test name
Test status
Simulation time 43890845 ps
CPU time 2.72 seconds
Started Aug 05 06:14:47 PM PDT 24
Finished Aug 05 06:14:50 PM PDT 24
Peak memory 215232 kb
Host smart-040dc759-ee68-4c18-b8cf-539f9b23de36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480563525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1480563525
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1043351760
Short name T106
Test name
Test status
Simulation time 274902959 ps
CPU time 2 seconds
Started Aug 05 06:14:43 PM PDT 24
Finished Aug 05 06:14:45 PM PDT 24
Peak memory 215328 kb
Host smart-aa8d9bf5-95f8-43f5-adaf-8854ae505de6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043351760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
043351760
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3586205113
Short name T113
Test name
Test status
Simulation time 877575383 ps
CPU time 19.06 seconds
Started Aug 05 06:14:41 PM PDT 24
Finished Aug 05 06:15:00 PM PDT 24
Peak memory 215148 kb
Host smart-680dae1e-68df-4e64-bf3e-57f367e3a141
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586205113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3586205113
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4196871159
Short name T1065
Test name
Test status
Simulation time 16499382 ps
CPU time 0.71 seconds
Started Aug 05 06:15:38 PM PDT 24
Finished Aug 05 06:15:39 PM PDT 24
Peak memory 204004 kb
Host smart-7c509000-9cd5-4d69-9132-d7ab9f9b5a20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196871159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
4196871159
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2695315438
Short name T1067
Test name
Test status
Simulation time 23947489 ps
CPU time 0.76 seconds
Started Aug 05 06:15:35 PM PDT 24
Finished Aug 05 06:15:36 PM PDT 24
Peak memory 203668 kb
Host smart-50a4abc8-e811-4ebd-a64c-1885e5e20ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695315438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2695315438
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.590107444
Short name T1012
Test name
Test status
Simulation time 58647316 ps
CPU time 0.72 seconds
Started Aug 05 06:15:38 PM PDT 24
Finished Aug 05 06:15:39 PM PDT 24
Peak memory 203684 kb
Host smart-c17abdb6-5d44-4063-a0be-ed5ff5b22a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590107444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.590107444
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2424848339
Short name T1019
Test name
Test status
Simulation time 14676614 ps
CPU time 0.67 seconds
Started Aug 05 06:15:36 PM PDT 24
Finished Aug 05 06:15:36 PM PDT 24
Peak memory 203712 kb
Host smart-00a8e8a3-877f-4134-99df-ba252e3efbe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424848339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2424848339
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1379313589
Short name T1101
Test name
Test status
Simulation time 16048681 ps
CPU time 0.71 seconds
Started Aug 05 06:15:37 PM PDT 24
Finished Aug 05 06:15:38 PM PDT 24
Peak memory 203988 kb
Host smart-a783706f-29ec-43cf-a9b5-d29ca7ba2902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379313589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1379313589
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2378609388
Short name T1040
Test name
Test status
Simulation time 12802520 ps
CPU time 0.71 seconds
Started Aug 05 06:15:37 PM PDT 24
Finished Aug 05 06:15:38 PM PDT 24
Peak memory 203684 kb
Host smart-f56de482-226c-4179-99db-8ba77f5f6f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378609388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2378609388
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2918716895
Short name T1021
Test name
Test status
Simulation time 37300912 ps
CPU time 0.72 seconds
Started Aug 05 06:15:39 PM PDT 24
Finished Aug 05 06:15:40 PM PDT 24
Peak memory 203656 kb
Host smart-8ec0a117-1d3c-4d0e-858b-a3beaac89d7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918716895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2918716895
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.814567660
Short name T1113
Test name
Test status
Simulation time 39907104 ps
CPU time 0.66 seconds
Started Aug 05 06:15:37 PM PDT 24
Finished Aug 05 06:15:38 PM PDT 24
Peak memory 203948 kb
Host smart-3c5ce215-4851-441e-8341-2e004d988f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814567660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.814567660
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2668462627
Short name T1098
Test name
Test status
Simulation time 27294718 ps
CPU time 0.78 seconds
Started Aug 05 06:15:37 PM PDT 24
Finished Aug 05 06:15:38 PM PDT 24
Peak memory 203688 kb
Host smart-ea3d0d3e-c4cd-4ccb-b954-a66be6601d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668462627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2668462627
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4148957081
Short name T1089
Test name
Test status
Simulation time 56663060 ps
CPU time 0.72 seconds
Started Aug 05 06:15:38 PM PDT 24
Finished Aug 05 06:15:39 PM PDT 24
Peak memory 203680 kb
Host smart-e9f5e1a0-5614-4ffc-95f4-6b67bc145752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148957081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4148957081
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1814775624
Short name T118
Test name
Test status
Simulation time 3633625104 ps
CPU time 23.94 seconds
Started Aug 05 06:14:53 PM PDT 24
Finished Aug 05 06:15:17 PM PDT 24
Peak memory 215208 kb
Host smart-8973567a-4571-4e71-b88c-f806cb8ab478
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814775624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1814775624
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1976707215
Short name T145
Test name
Test status
Simulation time 2258499578 ps
CPU time 13.14 seconds
Started Aug 05 06:14:53 PM PDT 24
Finished Aug 05 06:15:07 PM PDT 24
Peak memory 207072 kb
Host smart-013d8311-9d98-4193-918c-f52d01fde737
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976707215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1976707215
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3647833906
Short name T96
Test name
Test status
Simulation time 364812314 ps
CPU time 2.7 seconds
Started Aug 05 06:14:53 PM PDT 24
Finished Aug 05 06:14:56 PM PDT 24
Peak memory 216580 kb
Host smart-034508ab-ede7-466a-989e-8b511c67a098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647833906 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3647833906
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2314773389
Short name T1091
Test name
Test status
Simulation time 35758791 ps
CPU time 1.27 seconds
Started Aug 05 06:14:52 PM PDT 24
Finished Aug 05 06:14:53 PM PDT 24
Peak memory 206872 kb
Host smart-e4493c7e-2d9d-417e-8ab9-ebe87ec26d16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314773389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
314773389
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1040291381
Short name T1103
Test name
Test status
Simulation time 13455765 ps
CPU time 0.74 seconds
Started Aug 05 06:14:48 PM PDT 24
Finished Aug 05 06:14:48 PM PDT 24
Peak memory 203772 kb
Host smart-634c127a-54c3-43a5-b93d-5d2fa6b6ee22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040291381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
040291381
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1570087986
Short name T120
Test name
Test status
Simulation time 129187470 ps
CPU time 1.3 seconds
Started Aug 05 06:14:47 PM PDT 24
Finished Aug 05 06:14:48 PM PDT 24
Peak memory 215104 kb
Host smart-52c5f86a-1bd5-4800-83dd-56637d262924
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570087986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1570087986
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.399625453
Short name T1115
Test name
Test status
Simulation time 12869964 ps
CPU time 0.69 seconds
Started Aug 05 06:14:48 PM PDT 24
Finished Aug 05 06:14:48 PM PDT 24
Peak memory 203952 kb
Host smart-c4124a96-cb2d-4609-a44d-c08f28a5cd24
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399625453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.399625453
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1730341138
Short name T1118
Test name
Test status
Simulation time 106177656 ps
CPU time 1.72 seconds
Started Aug 05 06:14:52 PM PDT 24
Finished Aug 05 06:14:54 PM PDT 24
Peak memory 215176 kb
Host smart-9282b5e8-0e95-40e2-b46b-21159cad4567
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730341138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1730341138
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4211823878
Short name T105
Test name
Test status
Simulation time 375496224 ps
CPU time 5.66 seconds
Started Aug 05 06:14:47 PM PDT 24
Finished Aug 05 06:14:52 PM PDT 24
Peak memory 215256 kb
Host smart-11a46766-54c7-4d0f-a753-bfea765323c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211823878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
211823878
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1684914911
Short name T98
Test name
Test status
Simulation time 1355510643 ps
CPU time 14.03 seconds
Started Aug 05 06:14:47 PM PDT 24
Finished Aug 05 06:15:01 PM PDT 24
Peak memory 215096 kb
Host smart-086732e6-e1ba-4f09-99cd-bbf5d556f73d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684914911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1684914911
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1286421044
Short name T1041
Test name
Test status
Simulation time 14334892 ps
CPU time 0.77 seconds
Started Aug 05 06:15:40 PM PDT 24
Finished Aug 05 06:15:41 PM PDT 24
Peak memory 203676 kb
Host smart-623bec13-9063-4544-9ded-dc00bbd880f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286421044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1286421044
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3380273973
Short name T1090
Test name
Test status
Simulation time 34099479 ps
CPU time 0.68 seconds
Started Aug 05 06:15:37 PM PDT 24
Finished Aug 05 06:15:38 PM PDT 24
Peak memory 203680 kb
Host smart-bf83234b-b0c3-42d1-ba9d-3d4e1d431449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380273973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3380273973
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1388676890
Short name T1032
Test name
Test status
Simulation time 37871125 ps
CPU time 0.72 seconds
Started Aug 05 06:15:37 PM PDT 24
Finished Aug 05 06:15:38 PM PDT 24
Peak memory 203684 kb
Host smart-80d050ad-e799-497e-b2fc-83e9e550c22d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388676890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1388676890
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1021928248
Short name T1014
Test name
Test status
Simulation time 38813806 ps
CPU time 0.78 seconds
Started Aug 05 06:15:41 PM PDT 24
Finished Aug 05 06:15:42 PM PDT 24
Peak memory 203984 kb
Host smart-bac394ae-0307-41ca-a13b-0f2956cebb66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021928248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1021928248
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2201578002
Short name T1029
Test name
Test status
Simulation time 56319313 ps
CPU time 0.73 seconds
Started Aug 05 06:15:36 PM PDT 24
Finished Aug 05 06:15:37 PM PDT 24
Peak memory 203908 kb
Host smart-2491d2f5-4fc6-4196-82c3-9337cbd515db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201578002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2201578002
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3351053321
Short name T1097
Test name
Test status
Simulation time 12186600 ps
CPU time 0.76 seconds
Started Aug 05 06:15:40 PM PDT 24
Finished Aug 05 06:15:41 PM PDT 24
Peak memory 203992 kb
Host smart-88899550-33bc-470c-82fa-9aa5195afa14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351053321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3351053321
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.313549125
Short name T1102
Test name
Test status
Simulation time 14556674 ps
CPU time 0.7 seconds
Started Aug 05 06:15:37 PM PDT 24
Finished Aug 05 06:15:37 PM PDT 24
Peak memory 203984 kb
Host smart-522c2b39-dc59-4ae1-9203-9a7225e5dbc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313549125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.313549125
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2266452750
Short name T1026
Test name
Test status
Simulation time 32199792 ps
CPU time 0.67 seconds
Started Aug 05 06:15:40 PM PDT 24
Finished Aug 05 06:15:41 PM PDT 24
Peak memory 203668 kb
Host smart-27449870-e55c-4c81-891f-ffaa548cb171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266452750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2266452750
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.932485011
Short name T1020
Test name
Test status
Simulation time 11722499 ps
CPU time 0.7 seconds
Started Aug 05 06:15:42 PM PDT 24
Finished Aug 05 06:15:43 PM PDT 24
Peak memory 203644 kb
Host smart-ec1c2f87-0f87-4264-bde4-7ac97f1b53e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932485011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.932485011
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1808407021
Short name T1058
Test name
Test status
Simulation time 156883648 ps
CPU time 0.77 seconds
Started Aug 05 06:15:41 PM PDT 24
Finished Aug 05 06:15:42 PM PDT 24
Peak memory 203672 kb
Host smart-2e382956-bd5e-43dc-8699-cf836901070d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808407021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1808407021
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.62458278
Short name T1068
Test name
Test status
Simulation time 1209044375 ps
CPU time 21.38 seconds
Started Aug 05 06:14:58 PM PDT 24
Finished Aug 05 06:15:19 PM PDT 24
Peak memory 215152 kb
Host smart-6f015915-d2b5-49a0-8018-8988e1275832
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62458278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
aliasing.62458278
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3015413707
Short name T1025
Test name
Test status
Simulation time 1264941709 ps
CPU time 24 seconds
Started Aug 05 06:15:00 PM PDT 24
Finished Aug 05 06:15:24 PM PDT 24
Peak memory 206980 kb
Host smart-fa303f6f-2b6b-44d0-9dd4-aa74e0484aec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015413707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3015413707
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3550329105
Short name T79
Test name
Test status
Simulation time 31029581 ps
CPU time 1.17 seconds
Started Aug 05 06:14:58 PM PDT 24
Finished Aug 05 06:14:59 PM PDT 24
Peak memory 207020 kb
Host smart-f859cf2c-8582-4886-99e6-4b548e8fca33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550329105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3550329105
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2334534242
Short name T1123
Test name
Test status
Simulation time 25949486 ps
CPU time 1.67 seconds
Started Aug 05 06:14:56 PM PDT 24
Finished Aug 05 06:14:58 PM PDT 24
Peak memory 216376 kb
Host smart-892a3141-4e75-4446-8adb-cfd3276b8ef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334534242 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2334534242
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3899988836
Short name T1066
Test name
Test status
Simulation time 18734613 ps
CPU time 1.15 seconds
Started Aug 05 06:14:58 PM PDT 24
Finished Aug 05 06:14:59 PM PDT 24
Peak memory 215152 kb
Host smart-7323e684-1e0b-4a2b-bc03-8b3b1af5c101
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899988836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
899988836
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1811407116
Short name T1018
Test name
Test status
Simulation time 18108819 ps
CPU time 0.69 seconds
Started Aug 05 06:14:59 PM PDT 24
Finished Aug 05 06:15:00 PM PDT 24
Peak memory 203656 kb
Host smart-d08f2eb0-e410-4f85-8548-b3cc9361dedf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811407116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
811407116
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4067093978
Short name T1052
Test name
Test status
Simulation time 41700389 ps
CPU time 1.32 seconds
Started Aug 05 06:14:59 PM PDT 24
Finished Aug 05 06:15:00 PM PDT 24
Peak memory 215136 kb
Host smart-a588d143-848f-47c0-b830-a1b36069cdae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067093978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4067093978
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2164836251
Short name T1109
Test name
Test status
Simulation time 31388831 ps
CPU time 0.71 seconds
Started Aug 05 06:15:03 PM PDT 24
Finished Aug 05 06:15:04 PM PDT 24
Peak memory 203612 kb
Host smart-f3832910-d78a-488c-b92b-747f16419d0a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164836251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2164836251
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.428326115
Short name T1054
Test name
Test status
Simulation time 215870098 ps
CPU time 3.48 seconds
Started Aug 05 06:14:57 PM PDT 24
Finished Aug 05 06:15:00 PM PDT 24
Peak memory 215132 kb
Host smart-923130e2-ad70-407a-ac13-32d886a1ae51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428326115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.428326115
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1245840356
Short name T1111
Test name
Test status
Simulation time 309981750 ps
CPU time 5.5 seconds
Started Aug 05 06:14:59 PM PDT 24
Finished Aug 05 06:15:04 PM PDT 24
Peak memory 215264 kb
Host smart-715adba9-8716-4647-8f61-12dcd4e4896c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245840356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
245840356
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1479679401
Short name T1045
Test name
Test status
Simulation time 868773377 ps
CPU time 22.02 seconds
Started Aug 05 06:15:04 PM PDT 24
Finished Aug 05 06:15:26 PM PDT 24
Peak memory 215224 kb
Host smart-a7eae463-c729-4914-b7ff-62686b407cd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479679401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1479679401
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1180106409
Short name T1011
Test name
Test status
Simulation time 18956992 ps
CPU time 0.73 seconds
Started Aug 05 06:15:42 PM PDT 24
Finished Aug 05 06:15:43 PM PDT 24
Peak memory 203624 kb
Host smart-c8af6166-481c-4e4d-9a1f-fa5fd7ac03bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180106409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1180106409
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2019456139
Short name T1015
Test name
Test status
Simulation time 15962179 ps
CPU time 0.7 seconds
Started Aug 05 06:15:40 PM PDT 24
Finished Aug 05 06:15:41 PM PDT 24
Peak memory 203624 kb
Host smart-a1e42511-cdcb-4749-9c37-d0d3744f5c5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019456139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2019456139
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1315498137
Short name T1013
Test name
Test status
Simulation time 89351312 ps
CPU time 0.75 seconds
Started Aug 05 06:15:42 PM PDT 24
Finished Aug 05 06:15:43 PM PDT 24
Peak memory 204008 kb
Host smart-2babf4eb-2506-4bcb-a4b3-65fa5bc7169a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315498137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1315498137
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3147491303
Short name T1017
Test name
Test status
Simulation time 11319618 ps
CPU time 0.67 seconds
Started Aug 05 06:15:40 PM PDT 24
Finished Aug 05 06:15:41 PM PDT 24
Peak memory 203608 kb
Host smart-f1efdb97-d180-49e9-8bcd-e8320d0d407a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147491303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3147491303
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.563054848
Short name T1008
Test name
Test status
Simulation time 111888847 ps
CPU time 0.74 seconds
Started Aug 05 06:15:43 PM PDT 24
Finished Aug 05 06:15:44 PM PDT 24
Peak memory 203636 kb
Host smart-bce5de1f-58ff-410d-925f-aa8a8e68893e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563054848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.563054848
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2663900907
Short name T1027
Test name
Test status
Simulation time 14090887 ps
CPU time 0.73 seconds
Started Aug 05 06:15:42 PM PDT 24
Finished Aug 05 06:15:43 PM PDT 24
Peak memory 203688 kb
Host smart-9b6b63a0-eee9-4e8c-8df3-f93542045542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663900907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2663900907
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.65007065
Short name T1069
Test name
Test status
Simulation time 177613296 ps
CPU time 0.73 seconds
Started Aug 05 06:15:41 PM PDT 24
Finished Aug 05 06:15:42 PM PDT 24
Peak memory 204020 kb
Host smart-328d1404-9e96-4e5d-90d6-93d0d23e8826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65007065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.65007065
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3470443257
Short name T1100
Test name
Test status
Simulation time 45123175 ps
CPU time 0.66 seconds
Started Aug 05 06:15:42 PM PDT 24
Finished Aug 05 06:15:43 PM PDT 24
Peak memory 203972 kb
Host smart-e5fa3413-715f-41d5-97b3-f3aabebc62c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470443257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3470443257
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3170490772
Short name T1009
Test name
Test status
Simulation time 16223622 ps
CPU time 0.68 seconds
Started Aug 05 06:15:40 PM PDT 24
Finished Aug 05 06:15:41 PM PDT 24
Peak memory 203684 kb
Host smart-3e13668c-c997-402e-8a24-51d41ee2dd04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170490772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3170490772
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3811905654
Short name T1038
Test name
Test status
Simulation time 26509656 ps
CPU time 0.69 seconds
Started Aug 05 06:15:42 PM PDT 24
Finished Aug 05 06:15:43 PM PDT 24
Peak memory 203628 kb
Host smart-186733b4-3286-4541-aa78-53f06553c250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811905654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3811905654
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1908502084
Short name T1075
Test name
Test status
Simulation time 193277614 ps
CPU time 3.57 seconds
Started Aug 05 06:15:08 PM PDT 24
Finished Aug 05 06:15:12 PM PDT 24
Peak memory 217372 kb
Host smart-702d817b-90af-4add-9615-f944a6bf304f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908502084 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1908502084
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1733360670
Short name T123
Test name
Test status
Simulation time 216199786 ps
CPU time 2.85 seconds
Started Aug 05 06:14:58 PM PDT 24
Finished Aug 05 06:15:01 PM PDT 24
Peak memory 215204 kb
Host smart-b4122eca-c94f-4e73-b930-2fe5d05c3642
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733360670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
733360670
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2523237189
Short name T1048
Test name
Test status
Simulation time 17981947 ps
CPU time 0.81 seconds
Started Aug 05 06:15:03 PM PDT 24
Finished Aug 05 06:15:04 PM PDT 24
Peak memory 203652 kb
Host smart-001f3e80-5a70-431a-9aa4-1b9c38a34544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523237189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
523237189
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4225450891
Short name T1078
Test name
Test status
Simulation time 520608364 ps
CPU time 2.91 seconds
Started Aug 05 06:14:59 PM PDT 24
Finished Aug 05 06:15:02 PM PDT 24
Peak memory 215096 kb
Host smart-ed06b00d-d20b-4770-acdf-bd1c996dc63d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225450891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4225450891
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1608524230
Short name T102
Test name
Test status
Simulation time 584641872 ps
CPU time 4.09 seconds
Started Aug 05 06:14:59 PM PDT 24
Finished Aug 05 06:15:03 PM PDT 24
Peak memory 215228 kb
Host smart-691703b8-a40d-4b49-97d1-9e94f282cf30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608524230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
608524230
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.504249552
Short name T177
Test name
Test status
Simulation time 1046758013 ps
CPU time 7.76 seconds
Started Aug 05 06:14:59 PM PDT 24
Finished Aug 05 06:15:07 PM PDT 24
Peak memory 215408 kb
Host smart-c43d463f-6dd4-4cd1-a682-c806e7b3299a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504249552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.504249552
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.529923765
Short name T1122
Test name
Test status
Simulation time 141084384 ps
CPU time 3.84 seconds
Started Aug 05 06:15:02 PM PDT 24
Finished Aug 05 06:15:06 PM PDT 24
Peak memory 217420 kb
Host smart-af82814f-1204-4c3e-a160-ed4f7095bf13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529923765 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.529923765
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2567597764
Short name T1064
Test name
Test status
Simulation time 34712281 ps
CPU time 1.33 seconds
Started Aug 05 06:15:02 PM PDT 24
Finished Aug 05 06:15:03 PM PDT 24
Peak memory 215156 kb
Host smart-640d8579-5f55-455c-b483-a2e3febef047
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567597764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
567597764
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.617347774
Short name T1062
Test name
Test status
Simulation time 18256569 ps
CPU time 0.82 seconds
Started Aug 05 06:15:03 PM PDT 24
Finished Aug 05 06:15:03 PM PDT 24
Peak memory 203640 kb
Host smart-723bf9f9-02dc-47d8-9cc3-13584a638478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617347774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.617347774
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3140113801
Short name T132
Test name
Test status
Simulation time 82374462 ps
CPU time 1.6 seconds
Started Aug 05 06:15:03 PM PDT 24
Finished Aug 05 06:15:05 PM PDT 24
Peak memory 215152 kb
Host smart-876e5444-f538-452c-a656-fe5d94e0213a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140113801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3140113801
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3725830720
Short name T1095
Test name
Test status
Simulation time 56209343 ps
CPU time 3.1 seconds
Started Aug 05 06:15:04 PM PDT 24
Finished Aug 05 06:15:07 PM PDT 24
Peak memory 215292 kb
Host smart-d8ed635b-29a9-423a-a0b3-d999767141a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725830720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
725830720
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2664188001
Short name T1051
Test name
Test status
Simulation time 4985448669 ps
CPU time 15.63 seconds
Started Aug 05 06:15:05 PM PDT 24
Finished Aug 05 06:15:21 PM PDT 24
Peak memory 215228 kb
Host smart-4d5b3fc5-df55-4f07-938e-1278920c9561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664188001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2664188001
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4009184722
Short name T1106
Test name
Test status
Simulation time 1295625911 ps
CPU time 3.61 seconds
Started Aug 05 06:15:09 PM PDT 24
Finished Aug 05 06:15:12 PM PDT 24
Peak memory 217248 kb
Host smart-4e84fbe9-f842-43cd-84c8-593123163e72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009184722 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4009184722
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3277815563
Short name T1074
Test name
Test status
Simulation time 50382417 ps
CPU time 1.38 seconds
Started Aug 05 06:15:04 PM PDT 24
Finished Aug 05 06:15:06 PM PDT 24
Peak memory 215144 kb
Host smart-f7981760-551b-47b5-9aa6-27c4ab7fc4ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277815563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
277815563
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3964807447
Short name T1030
Test name
Test status
Simulation time 31016547 ps
CPU time 0.76 seconds
Started Aug 05 06:15:04 PM PDT 24
Finished Aug 05 06:15:05 PM PDT 24
Peak memory 203980 kb
Host smart-f189279c-0b6c-4c09-866b-dd71cac08155
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964807447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
964807447
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.727198454
Short name T1053
Test name
Test status
Simulation time 222771017 ps
CPU time 3.73 seconds
Started Aug 05 06:15:04 PM PDT 24
Finished Aug 05 06:15:08 PM PDT 24
Peak memory 215112 kb
Host smart-2d170b49-2173-4189-818e-c1dd6950d2fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727198454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.727198454
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2188543316
Short name T168
Test name
Test status
Simulation time 686635749 ps
CPU time 3.75 seconds
Started Aug 05 06:15:08 PM PDT 24
Finished Aug 05 06:15:12 PM PDT 24
Peak memory 218044 kb
Host smart-96484e05-15d1-4ba9-a215-9b4758276317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188543316 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2188543316
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4274335483
Short name T1088
Test name
Test status
Simulation time 78695113 ps
CPU time 1.99 seconds
Started Aug 05 06:15:08 PM PDT 24
Finished Aug 05 06:15:10 PM PDT 24
Peak memory 206852 kb
Host smart-f940d40d-85cc-4135-b2ff-a57eb8f24e74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274335483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
274335483
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4023082771
Short name T1073
Test name
Test status
Simulation time 15545731 ps
CPU time 0.76 seconds
Started Aug 05 06:15:11 PM PDT 24
Finished Aug 05 06:15:12 PM PDT 24
Peak memory 203684 kb
Host smart-e822dde2-bb0d-45d3-b552-9fb8e09a0114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023082771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.4
023082771
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.161873784
Short name T1047
Test name
Test status
Simulation time 201472304 ps
CPU time 1.8 seconds
Started Aug 05 06:15:07 PM PDT 24
Finished Aug 05 06:15:09 PM PDT 24
Peak memory 215128 kb
Host smart-c3478f5e-1f1e-40b8-ab3f-25a50e1fec62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161873784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.161873784
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1521559930
Short name T1107
Test name
Test status
Simulation time 60594660 ps
CPU time 3.8 seconds
Started Aug 05 06:15:08 PM PDT 24
Finished Aug 05 06:15:12 PM PDT 24
Peak memory 215400 kb
Host smart-1a0a2374-380f-404b-95cd-3c1dea128384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521559930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
521559930
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3350962258
Short name T170
Test name
Test status
Simulation time 354754688 ps
CPU time 7.53 seconds
Started Aug 05 06:15:07 PM PDT 24
Finished Aug 05 06:15:15 PM PDT 24
Peak memory 215184 kb
Host smart-7d83bae7-d838-435b-844a-2af3b74fc665
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350962258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3350962258
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.551990424
Short name T115
Test name
Test status
Simulation time 1405063224 ps
CPU time 2.68 seconds
Started Aug 05 06:15:10 PM PDT 24
Finished Aug 05 06:15:12 PM PDT 24
Peak memory 216180 kb
Host smart-c3043bfa-6628-430d-bff5-e5be1cc2bfc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551990424 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.551990424
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3140894150
Short name T1037
Test name
Test status
Simulation time 80275700 ps
CPU time 1.26 seconds
Started Aug 05 06:15:09 PM PDT 24
Finished Aug 05 06:15:11 PM PDT 24
Peak memory 215200 kb
Host smart-abf3a3b7-d6f4-4e57-95f3-a9c682f10034
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140894150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
140894150
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4184325051
Short name T1083
Test name
Test status
Simulation time 40255901 ps
CPU time 0.69 seconds
Started Aug 05 06:15:09 PM PDT 24
Finished Aug 05 06:15:09 PM PDT 24
Peak memory 203676 kb
Host smart-962930c8-702e-49d3-8cfb-26541b2c1465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184325051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
184325051
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3364011945
Short name T1125
Test name
Test status
Simulation time 705092829 ps
CPU time 3.96 seconds
Started Aug 05 06:15:09 PM PDT 24
Finished Aug 05 06:15:13 PM PDT 24
Peak memory 215212 kb
Host smart-f52efc4c-ec1a-4711-8260-b3c8ef25138b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364011945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3364011945
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.787918633
Short name T100
Test name
Test status
Simulation time 354518272 ps
CPU time 2.56 seconds
Started Aug 05 06:15:08 PM PDT 24
Finished Aug 05 06:15:11 PM PDT 24
Peak memory 215128 kb
Host smart-b9dd75b0-63db-42db-985b-56f6215e23af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787918633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.787918633
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1708543770
Short name T452
Test name
Test status
Simulation time 376601084 ps
CPU time 2.29 seconds
Started Aug 05 06:27:22 PM PDT 24
Finished Aug 05 06:27:24 PM PDT 24
Peak memory 224616 kb
Host smart-682a7ded-ae62-4ef9-a54a-aee5c1fcd0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708543770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1708543770
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3718404643
Short name T65
Test name
Test status
Simulation time 14990406 ps
CPU time 0.84 seconds
Started Aug 05 06:27:25 PM PDT 24
Finished Aug 05 06:27:26 PM PDT 24
Peak memory 207316 kb
Host smart-1e93d422-954a-4596-8132-8d0d5c9380e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718404643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3718404643
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3074653340
Short name T55
Test name
Test status
Simulation time 1644238240 ps
CPU time 20.44 seconds
Started Aug 05 06:27:21 PM PDT 24
Finished Aug 05 06:27:42 PM PDT 24
Peak memory 241356 kb
Host smart-bbe8f038-8ee3-4b6f-84df-e8c196ad22b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074653340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3074653340
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.723853896
Short name T891
Test name
Test status
Simulation time 78384101426 ps
CPU time 153.42 seconds
Started Aug 05 06:27:23 PM PDT 24
Finished Aug 05 06:29:57 PM PDT 24
Peak memory 237184 kb
Host smart-e5c20a74-ef24-4442-8960-7a26f9c2d581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723853896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.723853896
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2366531604
Short name T277
Test name
Test status
Simulation time 12217643292 ps
CPU time 87.08 seconds
Started Aug 05 06:27:26 PM PDT 24
Finished Aug 05 06:28:53 PM PDT 24
Peak memory 266032 kb
Host smart-40c8f3ac-dd1f-4bdc-b8be-a35139d23944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366531604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2366531604
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.187431177
Short name T882
Test name
Test status
Simulation time 466045141 ps
CPU time 10.68 seconds
Started Aug 05 06:27:24 PM PDT 24
Finished Aug 05 06:27:34 PM PDT 24
Peak memory 224900 kb
Host smart-6469edc5-7b48-4b54-a984-4a9ebf55e355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187431177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.187431177
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2569397052
Short name T271
Test name
Test status
Simulation time 1254724670 ps
CPU time 6.56 seconds
Started Aug 05 06:27:24 PM PDT 24
Finished Aug 05 06:27:30 PM PDT 24
Peak memory 224940 kb
Host smart-afdd8ef3-81a7-4e55-b08b-893b439c2d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569397052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2569397052
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4036621005
Short name T699
Test name
Test status
Simulation time 1205480133 ps
CPU time 16.23 seconds
Started Aug 05 06:27:26 PM PDT 24
Finished Aug 05 06:27:42 PM PDT 24
Peak memory 233156 kb
Host smart-fc186e3f-46dc-443c-a2f1-5100ae37487c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036621005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4036621005
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.749182159
Short name T409
Test name
Test status
Simulation time 652563822 ps
CPU time 3.38 seconds
Started Aug 05 06:27:22 PM PDT 24
Finished Aug 05 06:27:26 PM PDT 24
Peak memory 224932 kb
Host smart-792b581f-3825-4d6f-b792-765cf763ffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749182159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
749182159
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3069866364
Short name T568
Test name
Test status
Simulation time 3776391145 ps
CPU time 9.1 seconds
Started Aug 05 06:27:24 PM PDT 24
Finished Aug 05 06:27:33 PM PDT 24
Peak memory 234272 kb
Host smart-f8fda801-ea29-4599-b6e6-06d4d375a255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069866364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3069866364
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3238418456
Short name T388
Test name
Test status
Simulation time 87181091 ps
CPU time 4.24 seconds
Started Aug 05 06:27:23 PM PDT 24
Finished Aug 05 06:27:28 PM PDT 24
Peak memory 223484 kb
Host smart-a94a6e1c-8e80-4776-9f53-0206b3bc7653
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3238418456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3238418456
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3118937124
Short name T73
Test name
Test status
Simulation time 239647121 ps
CPU time 1.14 seconds
Started Aug 05 06:27:25 PM PDT 24
Finished Aug 05 06:27:27 PM PDT 24
Peak memory 236860 kb
Host smart-dbe7f4f6-be6e-4d75-885a-05e6c4b29b69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118937124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3118937124
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3467709921
Short name T217
Test name
Test status
Simulation time 221689247457 ps
CPU time 441.28 seconds
Started Aug 05 06:27:23 PM PDT 24
Finished Aug 05 06:34:44 PM PDT 24
Peak memory 265940 kb
Host smart-e20d8a4f-c1a5-4501-9f4a-877765c831d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467709921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3467709921
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2878586764
Short name T63
Test name
Test status
Simulation time 12936935 ps
CPU time 0.73 seconds
Started Aug 05 06:27:25 PM PDT 24
Finished Aug 05 06:27:25 PM PDT 24
Peak memory 205964 kb
Host smart-87d562b2-c684-481b-8d53-5d2977a96ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878586764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2878586764
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1174534523
Short name T800
Test name
Test status
Simulation time 263300650 ps
CPU time 1.32 seconds
Started Aug 05 06:27:22 PM PDT 24
Finished Aug 05 06:27:23 PM PDT 24
Peak memory 208208 kb
Host smart-87ab57b4-0f72-4c4b-b72c-8ab10bac501b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174534523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1174534523
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1710038422
Short name T752
Test name
Test status
Simulation time 28106871 ps
CPU time 1.42 seconds
Started Aug 05 06:27:22 PM PDT 24
Finished Aug 05 06:27:24 PM PDT 24
Peak memory 216704 kb
Host smart-bf29f170-6c65-4910-9f55-f92935aa7f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710038422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1710038422
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3583043771
Short name T946
Test name
Test status
Simulation time 220032619 ps
CPU time 0.87 seconds
Started Aug 05 06:27:23 PM PDT 24
Finished Aug 05 06:27:24 PM PDT 24
Peak memory 206348 kb
Host smart-1d5e2d6a-6aaa-4283-b437-a33043d77144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583043771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3583043771
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2150633169
Short name T11
Test name
Test status
Simulation time 568141215 ps
CPU time 3.49 seconds
Started Aug 05 06:27:24 PM PDT 24
Finished Aug 05 06:27:28 PM PDT 24
Peak memory 224856 kb
Host smart-369a1ebe-cf35-40df-a0b7-07be0f865244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150633169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2150633169
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1897872098
Short name T325
Test name
Test status
Simulation time 24579364 ps
CPU time 0.74 seconds
Started Aug 05 06:27:28 PM PDT 24
Finished Aug 05 06:27:29 PM PDT 24
Peak memory 205836 kb
Host smart-ebeed8d5-a940-4b25-8903-cdd531725dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897872098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
897872098
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2143112981
Short name T903
Test name
Test status
Simulation time 3590964697 ps
CPU time 20.04 seconds
Started Aug 05 06:27:28 PM PDT 24
Finished Aug 05 06:27:48 PM PDT 24
Peak memory 234208 kb
Host smart-24116c10-0138-4f30-a4d1-f4d6a54fd2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143112981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2143112981
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1768437886
Short name T615
Test name
Test status
Simulation time 60026431 ps
CPU time 0.82 seconds
Started Aug 05 06:27:23 PM PDT 24
Finished Aug 05 06:27:24 PM PDT 24
Peak memory 207012 kb
Host smart-2d48def5-665a-4267-a423-584f46a92ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768437886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1768437886
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2839551110
Short name T433
Test name
Test status
Simulation time 244843939615 ps
CPU time 161.16 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:30:15 PM PDT 24
Peak memory 249592 kb
Host smart-896022ac-7249-4be5-ae13-2be10db1c33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839551110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2839551110
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.4148325487
Short name T908
Test name
Test status
Simulation time 23292338816 ps
CPU time 88.41 seconds
Started Aug 05 06:27:26 PM PDT 24
Finished Aug 05 06:28:54 PM PDT 24
Peak memory 249636 kb
Host smart-b67518ec-d53d-4f5c-860a-a6e2747b1cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148325487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.4148325487
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.4039855299
Short name T610
Test name
Test status
Simulation time 22401230527 ps
CPU time 86.73 seconds
Started Aug 05 06:27:29 PM PDT 24
Finished Aug 05 06:28:56 PM PDT 24
Peak memory 253120 kb
Host smart-75790c59-2cb6-4504-88f8-e7129fcb8595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039855299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.4039855299
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1422788774
Short name T155
Test name
Test status
Simulation time 858113376 ps
CPU time 14.77 seconds
Started Aug 05 06:27:28 PM PDT 24
Finished Aug 05 06:27:43 PM PDT 24
Peak memory 233168 kb
Host smart-7ad51092-5418-4641-9ce8-bb0a6cf67a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422788774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1422788774
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4151157059
Short name T234
Test name
Test status
Simulation time 515945154 ps
CPU time 4.71 seconds
Started Aug 05 06:27:31 PM PDT 24
Finished Aug 05 06:27:36 PM PDT 24
Peak memory 224816 kb
Host smart-4782ee5a-b865-44b6-89fe-75b3524a86f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151157059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4151157059
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3859082424
Short name T654
Test name
Test status
Simulation time 4566791416 ps
CPU time 39.33 seconds
Started Aug 05 06:27:28 PM PDT 24
Finished Aug 05 06:28:07 PM PDT 24
Peak memory 224928 kb
Host smart-0f0957c6-3266-4df3-969b-3b2702d30f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859082424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3859082424
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3623947363
Short name T669
Test name
Test status
Simulation time 59652349 ps
CPU time 3.21 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:27:38 PM PDT 24
Peak memory 233092 kb
Host smart-6b1e6a0c-9690-42b7-bd90-f49ad4d5806d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623947363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3623947363
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3459664074
Short name T570
Test name
Test status
Simulation time 9196820440 ps
CPU time 27.71 seconds
Started Aug 05 06:27:35 PM PDT 24
Finished Aug 05 06:28:03 PM PDT 24
Peak memory 234992 kb
Host smart-a995b0ae-772d-4863-abf5-156417ad68d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459664074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3459664074
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3701264341
Short name T138
Test name
Test status
Simulation time 1927427251 ps
CPU time 7.56 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:27:42 PM PDT 24
Peak memory 223000 kb
Host smart-80829d20-7c8f-45b9-a691-512268fa2af6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3701264341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3701264341
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.618838932
Short name T74
Test name
Test status
Simulation time 702133020 ps
CPU time 1.16 seconds
Started Aug 05 06:27:27 PM PDT 24
Finished Aug 05 06:27:29 PM PDT 24
Peak memory 235928 kb
Host smart-d4cda4a1-d09c-49cc-a039-2c8dddec3829
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618838932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.618838932
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3183904561
Short name T85
Test name
Test status
Simulation time 4932686840 ps
CPU time 21.97 seconds
Started Aug 05 06:27:28 PM PDT 24
Finished Aug 05 06:27:50 PM PDT 24
Peak memory 215956 kb
Host smart-eb64d65e-5095-4d25-8d09-4fa0ccebe53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183904561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3183904561
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2122141001
Short name T434
Test name
Test status
Simulation time 37251541317 ps
CPU time 27.41 seconds
Started Aug 05 06:27:28 PM PDT 24
Finished Aug 05 06:27:56 PM PDT 24
Peak memory 216612 kb
Host smart-f491a6cd-6aad-41d3-88c4-45824b3602f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122141001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2122141001
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1251746991
Short name T8
Test name
Test status
Simulation time 301357411 ps
CPU time 1.13 seconds
Started Aug 05 06:27:28 PM PDT 24
Finished Aug 05 06:27:29 PM PDT 24
Peak memory 207448 kb
Host smart-f84e2645-95b5-43a2-9a16-5c416a7a1fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251746991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1251746991
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1376137084
Short name T461
Test name
Test status
Simulation time 46258226 ps
CPU time 0.78 seconds
Started Aug 05 06:27:27 PM PDT 24
Finished Aug 05 06:27:28 PM PDT 24
Peak memory 205536 kb
Host smart-cc9a7a4d-eff7-4384-8593-6ec30a2dab99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376137084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1376137084
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2745340811
Short name T703
Test name
Test status
Simulation time 975755013 ps
CPU time 8.07 seconds
Started Aug 05 06:27:28 PM PDT 24
Finished Aug 05 06:27:36 PM PDT 24
Peak memory 233084 kb
Host smart-de9b7977-b601-4120-bc59-fd054a789d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745340811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2745340811
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2058758056
Short name T453
Test name
Test status
Simulation time 12848758 ps
CPU time 0.73 seconds
Started Aug 05 06:27:56 PM PDT 24
Finished Aug 05 06:27:57 PM PDT 24
Peak memory 205240 kb
Host smart-b8ec71a6-f9d6-4ad9-b81c-a58ca6438a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058758056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2058758056
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2203522223
Short name T14
Test name
Test status
Simulation time 181416644 ps
CPU time 3.22 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:27:55 PM PDT 24
Peak memory 224852 kb
Host smart-c9f47d0a-e913-4d32-ba6c-68e61bb532b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203522223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2203522223
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2476215792
Short name T918
Test name
Test status
Simulation time 19639371 ps
CPU time 0.81 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:27:53 PM PDT 24
Peak memory 207044 kb
Host smart-0d6d2428-2086-4998-aec7-b6a08625e87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476215792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2476215792
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4286195221
Short name T45
Test name
Test status
Simulation time 585788896337 ps
CPU time 469.79 seconds
Started Aug 05 06:27:54 PM PDT 24
Finished Aug 05 06:35:44 PM PDT 24
Peak memory 265180 kb
Host smart-b9828dc9-1cc6-49ee-b109-80488be98752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286195221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4286195221
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3269521933
Short name T262
Test name
Test status
Simulation time 60158862922 ps
CPU time 120.67 seconds
Started Aug 05 06:27:54 PM PDT 24
Finished Aug 05 06:29:55 PM PDT 24
Peak memory 225060 kb
Host smart-372aa29c-09b0-4a17-87de-80ba170f47e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269521933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3269521933
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3846255793
Short name T683
Test name
Test status
Simulation time 21627559538 ps
CPU time 169.25 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:30:41 PM PDT 24
Peak memory 255668 kb
Host smart-5d140aef-6251-4cb9-98ca-ffa2e934f041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846255793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3846255793
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1879297860
Short name T500
Test name
Test status
Simulation time 268509395 ps
CPU time 4.74 seconds
Started Aug 05 06:27:50 PM PDT 24
Finished Aug 05 06:27:54 PM PDT 24
Peak memory 233132 kb
Host smart-df394f4c-dd05-4452-98ad-685380bd32f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879297860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1879297860
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.24124067
Short name T787
Test name
Test status
Simulation time 2832681680 ps
CPU time 7.6 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:27:59 PM PDT 24
Peak memory 225036 kb
Host smart-fc21a3b5-882a-454c-b1fc-5b7869a8a314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24124067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.24124067
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.335897986
Short name T251
Test name
Test status
Simulation time 446242649 ps
CPU time 3.15 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:27:54 PM PDT 24
Peak memory 224944 kb
Host smart-ebe13ba1-b7fd-4017-aa7c-b7567ce717db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335897986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.335897986
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2850763160
Short name T355
Test name
Test status
Simulation time 1655602461 ps
CPU time 9.76 seconds
Started Aug 05 06:27:54 PM PDT 24
Finished Aug 05 06:28:04 PM PDT 24
Peak memory 223580 kb
Host smart-34ce4c2f-8ad8-4b30-b3fb-fb6d1809079d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2850763160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2850763160
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3224817134
Short name T729
Test name
Test status
Simulation time 64797389 ps
CPU time 1.14 seconds
Started Aug 05 06:27:57 PM PDT 24
Finished Aug 05 06:27:58 PM PDT 24
Peak memory 207308 kb
Host smart-26c3e328-5240-42ad-a8ed-7f98e858e959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224817134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3224817134
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1212145151
Short name T101
Test name
Test status
Simulation time 9660911674 ps
CPU time 12.91 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:28:04 PM PDT 24
Peak memory 216564 kb
Host smart-d33f9c3a-9b5d-444c-8958-93ee723af216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212145151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1212145151
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2993830535
Short name T356
Test name
Test status
Simulation time 1307484772 ps
CPU time 5.37 seconds
Started Aug 05 06:27:53 PM PDT 24
Finished Aug 05 06:27:59 PM PDT 24
Peak memory 216688 kb
Host smart-187e5be0-8a77-4ba2-8be2-450293f5b89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993830535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2993830535
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3505898038
Short name T844
Test name
Test status
Simulation time 32224619 ps
CPU time 0.85 seconds
Started Aug 05 06:27:55 PM PDT 24
Finished Aug 05 06:27:56 PM PDT 24
Peak memory 206356 kb
Host smart-d62efcbf-1cee-4fa7-9f86-1e3a58297a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505898038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3505898038
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4281055724
Short name T736
Test name
Test status
Simulation time 203264292 ps
CPU time 0.93 seconds
Started Aug 05 06:27:56 PM PDT 24
Finished Aug 05 06:27:57 PM PDT 24
Peak memory 206368 kb
Host smart-80d7d603-2d1f-4bc4-88b1-1b9f6180feec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281055724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4281055724
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3861359457
Short name T964
Test name
Test status
Simulation time 4115274442 ps
CPU time 20.37 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:28:13 PM PDT 24
Peak memory 224980 kb
Host smart-1589afb1-d7f6-4275-bbaf-0ed0c6af116b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861359457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3861359457
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1327630581
Short name T338
Test name
Test status
Simulation time 52325929 ps
CPU time 0.74 seconds
Started Aug 05 06:28:06 PM PDT 24
Finished Aug 05 06:28:07 PM PDT 24
Peak memory 205848 kb
Host smart-dcabf029-8190-4548-80cd-9356644e6e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327630581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1327630581
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4283871116
Short name T581
Test name
Test status
Simulation time 2075300916 ps
CPU time 18.23 seconds
Started Aug 05 06:27:59 PM PDT 24
Finished Aug 05 06:28:17 PM PDT 24
Peak memory 224916 kb
Host smart-6eda8869-3f61-48d1-8203-01cb6a432039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283871116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4283871116
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.929377662
Short name T412
Test name
Test status
Simulation time 46184285 ps
CPU time 0.74 seconds
Started Aug 05 06:27:55 PM PDT 24
Finished Aug 05 06:27:55 PM PDT 24
Peak memory 206976 kb
Host smart-177352a9-0e01-41a8-8a29-17121b612f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929377662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.929377662
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1821263559
Short name T544
Test name
Test status
Simulation time 49598257121 ps
CPU time 173.54 seconds
Started Aug 05 06:27:58 PM PDT 24
Finished Aug 05 06:30:52 PM PDT 24
Peak memory 251632 kb
Host smart-585b9fa9-8555-45e1-8b09-30de3c95a8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821263559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1821263559
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2561638396
Short name T445
Test name
Test status
Simulation time 65802361228 ps
CPU time 107.96 seconds
Started Aug 05 06:27:57 PM PDT 24
Finished Aug 05 06:29:45 PM PDT 24
Peak memory 224984 kb
Host smart-c7babe3a-8eb1-46d4-afca-3323abb70b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561638396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2561638396
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.433855488
Short name T596
Test name
Test status
Simulation time 21180078064 ps
CPU time 58.92 seconds
Started Aug 05 06:28:05 PM PDT 24
Finished Aug 05 06:29:04 PM PDT 24
Peak memory 233296 kb
Host smart-a1e96a3c-fb4a-456a-8a65-d0aed90616f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433855488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.433855488
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1899289652
Short name T439
Test name
Test status
Simulation time 3859104137 ps
CPU time 27.07 seconds
Started Aug 05 06:27:57 PM PDT 24
Finished Aug 05 06:28:24 PM PDT 24
Peak memory 249520 kb
Host smart-44d6b1d8-1965-4fb7-b9f3-9c631dd54e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899289652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1899289652
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.875559705
Short name T91
Test name
Test status
Simulation time 7878224618 ps
CPU time 69.97 seconds
Started Aug 05 06:27:56 PM PDT 24
Finished Aug 05 06:29:06 PM PDT 24
Peak memory 251400 kb
Host smart-a7918536-22f8-48df-a7d3-1ca96d611899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875559705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.875559705
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2663714548
Short name T620
Test name
Test status
Simulation time 96502396 ps
CPU time 3.14 seconds
Started Aug 05 06:27:58 PM PDT 24
Finished Aug 05 06:28:01 PM PDT 24
Peak memory 224848 kb
Host smart-efb32526-e624-44d5-919c-290b6bca854b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663714548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2663714548
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.939076112
Short name T648
Test name
Test status
Simulation time 592022821 ps
CPU time 5.1 seconds
Started Aug 05 06:27:57 PM PDT 24
Finished Aug 05 06:28:02 PM PDT 24
Peak memory 224880 kb
Host smart-de6e2cb3-e104-4a99-8280-a0e642f60ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939076112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.939076112
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.341359632
Short name T866
Test name
Test status
Simulation time 37954386183 ps
CPU time 25.52 seconds
Started Aug 05 06:27:57 PM PDT 24
Finished Aug 05 06:28:23 PM PDT 24
Peak memory 233144 kb
Host smart-8609621e-9d10-4830-8c85-e3d7e642738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341359632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.341359632
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.341230576
Short name T953
Test name
Test status
Simulation time 8439430996 ps
CPU time 17.06 seconds
Started Aug 05 06:27:56 PM PDT 24
Finished Aug 05 06:28:13 PM PDT 24
Peak memory 241268 kb
Host smart-403f5065-00f2-4007-b266-67a070a66af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341230576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.341230576
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2639966332
Short name T971
Test name
Test status
Simulation time 780865223 ps
CPU time 6.4 seconds
Started Aug 05 06:27:58 PM PDT 24
Finished Aug 05 06:28:04 PM PDT 24
Peak memory 223512 kb
Host smart-0680d1da-4b58-4ca0-9653-b437a9a1bfab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2639966332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2639966332
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2557776038
Short name T780
Test name
Test status
Simulation time 4074639234 ps
CPU time 50.48 seconds
Started Aug 05 06:28:06 PM PDT 24
Finished Aug 05 06:28:57 PM PDT 24
Peak memory 249600 kb
Host smart-eb8a5d5b-1c3f-4f70-b0b9-f5610129d001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557776038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2557776038
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2046454589
Short name T299
Test name
Test status
Simulation time 2485405599 ps
CPU time 11.79 seconds
Started Aug 05 06:27:58 PM PDT 24
Finished Aug 05 06:28:10 PM PDT 24
Peak memory 216628 kb
Host smart-b7c8be36-3af2-4ac2-bbd3-e7eab977837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046454589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2046454589
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2504830861
Short name T858
Test name
Test status
Simulation time 1815786882 ps
CPU time 6.02 seconds
Started Aug 05 06:28:00 PM PDT 24
Finished Aug 05 06:28:06 PM PDT 24
Peak memory 216724 kb
Host smart-d8f73d2e-c28c-4206-ab7c-fa0f4268fc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504830861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2504830861
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.557804598
Short name T612
Test name
Test status
Simulation time 12440842 ps
CPU time 0.69 seconds
Started Aug 05 06:27:57 PM PDT 24
Finished Aug 05 06:27:57 PM PDT 24
Peak memory 205964 kb
Host smart-722f0037-3b36-4758-8469-878812a7fb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557804598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.557804598
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3128176017
Short name T791
Test name
Test status
Simulation time 27470444 ps
CPU time 0.86 seconds
Started Aug 05 06:27:58 PM PDT 24
Finished Aug 05 06:27:59 PM PDT 24
Peak memory 206360 kb
Host smart-b8d7c8fd-189f-4466-b2ba-44e7718e5199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128176017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3128176017
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.371630975
Short name T543
Test name
Test status
Simulation time 17448300313 ps
CPU time 13.79 seconds
Started Aug 05 06:27:59 PM PDT 24
Finished Aug 05 06:28:13 PM PDT 24
Peak memory 233160 kb
Host smart-cd97f6b1-fe81-44a0-a478-ccadb47e4d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371630975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.371630975
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.825107287
Short name T708
Test name
Test status
Simulation time 38140709 ps
CPU time 0.71 seconds
Started Aug 05 06:28:08 PM PDT 24
Finished Aug 05 06:28:09 PM PDT 24
Peak memory 206168 kb
Host smart-30c4a9ca-bfee-488d-83eb-725bbc3034bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825107287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.825107287
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.782953489
Short name T270
Test name
Test status
Simulation time 303982628 ps
CPU time 3.17 seconds
Started Aug 05 06:28:05 PM PDT 24
Finished Aug 05 06:28:08 PM PDT 24
Peak memory 225136 kb
Host smart-4cf45198-1daa-4095-ad7e-1033612b73ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782953489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.782953489
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.520524224
Short name T527
Test name
Test status
Simulation time 49784602 ps
CPU time 0.81 seconds
Started Aug 05 06:28:08 PM PDT 24
Finished Aug 05 06:28:09 PM PDT 24
Peak memory 206968 kb
Host smart-563d1697-d978-428b-a8da-96c49e3998f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520524224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.520524224
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1756146130
Short name T401
Test name
Test status
Simulation time 32439381178 ps
CPU time 57.8 seconds
Started Aug 05 06:28:06 PM PDT 24
Finished Aug 05 06:29:04 PM PDT 24
Peak memory 250048 kb
Host smart-4646ef73-2a15-481a-b7cc-2fc5c8c44f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756146130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1756146130
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3419198951
Short name T548
Test name
Test status
Simulation time 30203476588 ps
CPU time 47.21 seconds
Started Aug 05 06:28:07 PM PDT 24
Finished Aug 05 06:28:54 PM PDT 24
Peak memory 241680 kb
Host smart-fe66f6b1-ded7-474a-a74d-b7e5175458cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419198951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3419198951
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1535536865
Short name T219
Test name
Test status
Simulation time 14729406123 ps
CPU time 74.37 seconds
Started Aug 05 06:28:07 PM PDT 24
Finished Aug 05 06:29:22 PM PDT 24
Peak memory 240132 kb
Host smart-7edc4089-cc0f-4653-a5c6-546a4444d651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535536865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1535536865
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2797675320
Short name T982
Test name
Test status
Simulation time 1872653763 ps
CPU time 14.67 seconds
Started Aug 05 06:28:06 PM PDT 24
Finished Aug 05 06:28:21 PM PDT 24
Peak memory 241364 kb
Host smart-0bb144af-c360-4944-b409-2f9d3ba7d513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797675320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2797675320
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.771544587
Short name T256
Test name
Test status
Simulation time 49648563364 ps
CPU time 59.82 seconds
Started Aug 05 06:28:05 PM PDT 24
Finished Aug 05 06:29:05 PM PDT 24
Peak memory 257764 kb
Host smart-58b656b3-75d5-4597-bff0-ae6ebb33fe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771544587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.771544587
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1660311485
Short name T629
Test name
Test status
Simulation time 2251372988 ps
CPU time 8.03 seconds
Started Aug 05 06:28:05 PM PDT 24
Finished Aug 05 06:28:14 PM PDT 24
Peak memory 225004 kb
Host smart-99c2682a-57aa-4c07-89c3-238b95387df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660311485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1660311485
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1585071346
Short name T742
Test name
Test status
Simulation time 4734065764 ps
CPU time 11.41 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:28:24 PM PDT 24
Peak memory 239024 kb
Host smart-81295399-52b2-4919-966c-455cebbb5b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585071346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1585071346
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1274948837
Short name T257
Test name
Test status
Simulation time 5375838566 ps
CPU time 6.25 seconds
Started Aug 05 06:28:07 PM PDT 24
Finished Aug 05 06:28:13 PM PDT 24
Peak memory 233168 kb
Host smart-88775d46-e447-41ea-ae98-2e953b3ffba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274948837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1274948837
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.593001470
Short name T269
Test name
Test status
Simulation time 4976328882 ps
CPU time 11.5 seconds
Started Aug 05 06:28:05 PM PDT 24
Finished Aug 05 06:28:17 PM PDT 24
Peak memory 225040 kb
Host smart-38396c72-8497-4713-b9a2-815662992c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593001470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.593001470
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.445790792
Short name T37
Test name
Test status
Simulation time 545768445 ps
CPU time 3.7 seconds
Started Aug 05 06:28:06 PM PDT 24
Finished Aug 05 06:28:10 PM PDT 24
Peak memory 219768 kb
Host smart-4fe41941-4c40-4cd4-b141-2fac2ff7d9b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=445790792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.445790792
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.417247413
Short name T446
Test name
Test status
Simulation time 21252919829 ps
CPU time 163.18 seconds
Started Aug 05 06:28:06 PM PDT 24
Finished Aug 05 06:30:50 PM PDT 24
Peak memory 268880 kb
Host smart-113e2c14-6ac2-4232-abd2-f8c1480e3fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417247413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.417247413
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3874996057
Short name T779
Test name
Test status
Simulation time 108958594 ps
CPU time 1.86 seconds
Started Aug 05 06:28:07 PM PDT 24
Finished Aug 05 06:28:09 PM PDT 24
Peak memory 216700 kb
Host smart-53622caf-c5c8-4dbb-bd3e-37e0852c468d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874996057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3874996057
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1479715797
Short name T413
Test name
Test status
Simulation time 4654433952 ps
CPU time 5.29 seconds
Started Aug 05 06:28:06 PM PDT 24
Finished Aug 05 06:28:11 PM PDT 24
Peak memory 216776 kb
Host smart-8975cc56-15db-4c29-8c7f-605cdd13d2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479715797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1479715797
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1677327415
Short name T877
Test name
Test status
Simulation time 525855192 ps
CPU time 2.09 seconds
Started Aug 05 06:28:08 PM PDT 24
Finished Aug 05 06:28:10 PM PDT 24
Peak memory 216712 kb
Host smart-30106236-00c8-4f49-9890-c8b85a2f94db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677327415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1677327415
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1547408496
Short name T342
Test name
Test status
Simulation time 32076423 ps
CPU time 0.88 seconds
Started Aug 05 06:28:07 PM PDT 24
Finished Aug 05 06:28:08 PM PDT 24
Peak memory 206380 kb
Host smart-0f53218f-22c4-4414-ac58-88c79d43cd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547408496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1547408496
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2036550547
Short name T949
Test name
Test status
Simulation time 828155260 ps
CPU time 4.68 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:28:18 PM PDT 24
Peak memory 224936 kb
Host smart-c22d9761-8329-4cf3-8d37-720da0d1a893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036550547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2036550547
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2339217156
Short name T633
Test name
Test status
Simulation time 12761565 ps
CPU time 0.74 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:28:14 PM PDT 24
Peak memory 205800 kb
Host smart-e61e061c-3b21-4814-81c4-a99596c83f7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339217156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2339217156
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3456198666
Short name T116
Test name
Test status
Simulation time 1387130364 ps
CPU time 15.83 seconds
Started Aug 05 06:28:10 PM PDT 24
Finished Aug 05 06:28:26 PM PDT 24
Peak memory 224952 kb
Host smart-cf5aa628-3155-43eb-a208-bcb64ea756d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456198666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3456198666
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3380355314
Short name T510
Test name
Test status
Simulation time 22955301 ps
CPU time 0.74 seconds
Started Aug 05 06:28:06 PM PDT 24
Finished Aug 05 06:28:07 PM PDT 24
Peak memory 207300 kb
Host smart-c826f435-7dfc-43f0-a35a-c840d75ab214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380355314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3380355314
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2267484956
Short name T766
Test name
Test status
Simulation time 13479522483 ps
CPU time 49.49 seconds
Started Aug 05 06:28:09 PM PDT 24
Finished Aug 05 06:28:58 PM PDT 24
Peak memory 237276 kb
Host smart-323c796f-a859-4585-8241-ea2926978cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267484956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2267484956
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.238465542
Short name T280
Test name
Test status
Simulation time 11031648725 ps
CPU time 167.91 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:31:02 PM PDT 24
Peak memory 265616 kb
Host smart-8719f49f-f6ba-4555-8234-7ceaeb8ca885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238465542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.238465542
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.132238175
Short name T731
Test name
Test status
Simulation time 121997490929 ps
CPU time 282.99 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:32:57 PM PDT 24
Peak memory 264228 kb
Host smart-766af401-36fa-469b-b19d-aae39d804989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132238175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.132238175
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3402693072
Short name T562
Test name
Test status
Simulation time 1951139184 ps
CPU time 2.99 seconds
Started Aug 05 06:28:08 PM PDT 24
Finished Aug 05 06:28:11 PM PDT 24
Peak memory 224824 kb
Host smart-4f178850-4928-467e-a987-b7bb22fbab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402693072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3402693072
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3848224339
Short name T214
Test name
Test status
Simulation time 2287932992 ps
CPU time 11.3 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:28:25 PM PDT 24
Peak memory 240108 kb
Host smart-278b2c2a-18f6-4b47-8b06-9de139524486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848224339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3848224339
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.595316107
Short name T601
Test name
Test status
Simulation time 60053736213 ps
CPU time 8.64 seconds
Started Aug 05 06:28:08 PM PDT 24
Finished Aug 05 06:28:17 PM PDT 24
Peak memory 233088 kb
Host smart-8e925905-c95f-466e-ac59-fa7aa1962aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595316107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.595316107
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.340923146
Short name T12
Test name
Test status
Simulation time 16545306326 ps
CPU time 11.57 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:28:25 PM PDT 24
Peak memory 233196 kb
Host smart-789c7e21-e151-4c2c-ac40-5504ea440442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340923146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.340923146
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.681397075
Short name T617
Test name
Test status
Simulation time 160784200 ps
CPU time 4.34 seconds
Started Aug 05 06:28:10 PM PDT 24
Finished Aug 05 06:28:14 PM PDT 24
Peak memory 223180 kb
Host smart-fa1bdca5-2523-4c85-94ad-12a14c7c936f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=681397075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.681397075
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2276011246
Short name T33
Test name
Test status
Simulation time 143262324389 ps
CPU time 630.25 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:38:44 PM PDT 24
Peak memory 274076 kb
Host smart-220d7a1f-5e77-4585-809e-93212e16e1cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276011246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2276011246
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1845797082
Short name T396
Test name
Test status
Simulation time 1141392453 ps
CPU time 6.74 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:28:20 PM PDT 24
Peak memory 218880 kb
Host smart-767ff241-868e-4f86-8cf7-62a1885c03eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845797082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1845797082
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4107952986
Short name T82
Test name
Test status
Simulation time 6897220975 ps
CPU time 7.48 seconds
Started Aug 05 06:28:08 PM PDT 24
Finished Aug 05 06:28:15 PM PDT 24
Peak memory 216728 kb
Host smart-b4f41d7b-04f1-40b3-97ba-c6e252ebf85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107952986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4107952986
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3808678319
Short name T341
Test name
Test status
Simulation time 17586252 ps
CPU time 1.18 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:28:15 PM PDT 24
Peak memory 208472 kb
Host smart-8f223047-f442-47dc-9073-298a2480378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808678319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3808678319
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3813964461
Short name T1006
Test name
Test status
Simulation time 122726066 ps
CPU time 0.97 seconds
Started Aug 05 06:28:09 PM PDT 24
Finished Aug 05 06:28:10 PM PDT 24
Peak memory 207412 kb
Host smart-a2e51f16-e335-4924-9d5f-38224801ffdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813964461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3813964461
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4019367543
Short name T582
Test name
Test status
Simulation time 126666407947 ps
CPU time 34.19 seconds
Started Aug 05 06:28:10 PM PDT 24
Finished Aug 05 06:28:44 PM PDT 24
Peak memory 233212 kb
Host smart-1e2aba4d-1548-49b3-8f78-3a0aefbd947c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019367543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4019367543
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3763250689
Short name T783
Test name
Test status
Simulation time 169641819 ps
CPU time 0.7 seconds
Started Aug 05 06:28:23 PM PDT 24
Finished Aug 05 06:28:24 PM PDT 24
Peak memory 205900 kb
Host smart-2ce272f2-f47f-45f7-b6b3-e09817da6aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763250689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3763250689
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2015067901
Short name T955
Test name
Test status
Simulation time 74937372 ps
CPU time 2.32 seconds
Started Aug 05 06:28:23 PM PDT 24
Finished Aug 05 06:28:25 PM PDT 24
Peak memory 224852 kb
Host smart-707f9092-0135-47b7-8499-82705114fc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015067901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2015067901
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3902725475
Short name T941
Test name
Test status
Simulation time 19914410 ps
CPU time 0.77 seconds
Started Aug 05 06:28:14 PM PDT 24
Finished Aug 05 06:28:15 PM PDT 24
Peak memory 205976 kb
Host smart-6821133d-aeb1-4f94-aecd-469fbe9a17ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902725475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3902725475
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3855528589
Short name T834
Test name
Test status
Simulation time 7599758146 ps
CPU time 111.27 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:30:12 PM PDT 24
Peak memory 249516 kb
Host smart-d757a487-411d-437e-a4cb-342bd44aab2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855528589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3855528589
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2019294101
Short name T414
Test name
Test status
Simulation time 4606249072 ps
CPU time 38 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:28:59 PM PDT 24
Peak memory 241432 kb
Host smart-940df453-7c9d-4e07-9e3a-b938b17a200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019294101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2019294101
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3749229650
Short name T430
Test name
Test status
Simulation time 4645377747 ps
CPU time 53.69 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:29:15 PM PDT 24
Peak memory 253572 kb
Host smart-7fa685ec-a5d9-4097-8743-360d5b7d822d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749229650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3749229650
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2745380678
Short name T502
Test name
Test status
Simulation time 611108733 ps
CPU time 4.62 seconds
Started Aug 05 06:28:25 PM PDT 24
Finished Aug 05 06:28:30 PM PDT 24
Peak memory 233152 kb
Host smart-fcb1c7e5-f00c-4c51-8660-0ae36e7c83be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745380678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2745380678
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.29703679
Short name T992
Test name
Test status
Simulation time 88964018250 ps
CPU time 149.14 seconds
Started Aug 05 06:28:14 PM PDT 24
Finished Aug 05 06:30:43 PM PDT 24
Peak memory 249636 kb
Host smart-30138831-c5a5-4e7a-8f77-98dadf7a0276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29703679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.29703679
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.270626480
Short name T94
Test name
Test status
Simulation time 231517733 ps
CPU time 5.07 seconds
Started Aug 05 06:28:26 PM PDT 24
Finished Aug 05 06:28:31 PM PDT 24
Peak memory 233216 kb
Host smart-edbc6ad2-295d-4220-9490-3a21c4b2e4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270626480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.270626480
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2320495876
Short name T642
Test name
Test status
Simulation time 5588475031 ps
CPU time 52.22 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:29:06 PM PDT 24
Peak memory 241172 kb
Host smart-6fb5fbde-cb90-4e28-8b04-cdf34ebd271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320495876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2320495876
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2802498671
Short name T363
Test name
Test status
Simulation time 6011313738 ps
CPU time 10.44 seconds
Started Aug 05 06:28:14 PM PDT 24
Finished Aug 05 06:28:25 PM PDT 24
Peak memory 233168 kb
Host smart-22f65f68-bc5f-46a0-a309-7035901ed6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802498671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2802498671
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3452387373
Short name T248
Test name
Test status
Simulation time 184746843 ps
CPU time 3.61 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:28:25 PM PDT 24
Peak memory 233112 kb
Host smart-92932c52-123d-4534-8b1e-fe465fc47b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452387373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3452387373
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.111185979
Short name T38
Test name
Test status
Simulation time 3995905025 ps
CPU time 8.02 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:28:30 PM PDT 24
Peak memory 223588 kb
Host smart-ba506c41-5b41-414d-abee-c1e3c5c1b257
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=111185979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.111185979
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1245474530
Short name T793
Test name
Test status
Simulation time 5492435453 ps
CPU time 58.69 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:29:20 PM PDT 24
Peak memory 249604 kb
Host smart-594eb6a6-990b-4958-8455-e61f1db9548e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245474530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1245474530
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.252103573
Short name T924
Test name
Test status
Simulation time 1547533628 ps
CPU time 9.5 seconds
Started Aug 05 06:28:14 PM PDT 24
Finished Aug 05 06:28:24 PM PDT 24
Peak memory 216608 kb
Host smart-364757e3-680c-48a9-8ed9-4ac23fbbb6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252103573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.252103573
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2910522914
Short name T534
Test name
Test status
Simulation time 4094600488 ps
CPU time 6.06 seconds
Started Aug 05 06:28:14 PM PDT 24
Finished Aug 05 06:28:21 PM PDT 24
Peak memory 216652 kb
Host smart-7d1ecf8f-9738-4042-a023-4991e44cae44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910522914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2910522914
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3777230030
Short name T942
Test name
Test status
Simulation time 193361372 ps
CPU time 1.44 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:28:23 PM PDT 24
Peak memory 218192 kb
Host smart-fe471b2e-e136-418b-a8f3-f22ae4dc4ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777230030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3777230030
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.570548864
Short name T819
Test name
Test status
Simulation time 162964678 ps
CPU time 0.94 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:28:14 PM PDT 24
Peak memory 206348 kb
Host smart-535e5883-df3f-4f09-a8f9-33f7d60b1ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570548864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.570548864
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.50285531
Short name T243
Test name
Test status
Simulation time 4379165639 ps
CPU time 9.27 seconds
Started Aug 05 06:28:22 PM PDT 24
Finished Aug 05 06:28:32 PM PDT 24
Peak memory 233228 kb
Host smart-13c94005-77f2-4c58-a384-a7eac62ad4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50285531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.50285531
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2380075796
Short name T573
Test name
Test status
Simulation time 14163559 ps
CPU time 0.75 seconds
Started Aug 05 06:28:22 PM PDT 24
Finished Aug 05 06:28:23 PM PDT 24
Peak memory 206296 kb
Host smart-30926172-c2aa-440b-92f2-38cf4f3f8b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380075796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2380075796
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.379362532
Short name T274
Test name
Test status
Simulation time 901848667 ps
CPU time 2.99 seconds
Started Aug 05 06:28:22 PM PDT 24
Finished Aug 05 06:28:25 PM PDT 24
Peak memory 224904 kb
Host smart-19680c26-61f1-44f2-b46b-afdfbf1d72d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379362532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.379362532
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3650708618
Short name T718
Test name
Test status
Simulation time 19919113 ps
CPU time 0.77 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:28:22 PM PDT 24
Peak memory 206968 kb
Host smart-7462b1ec-c982-4f2b-bd2a-4dcbbeb4358b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650708618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3650708618
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.390118839
Short name T904
Test name
Test status
Simulation time 78660908319 ps
CPU time 290.29 seconds
Started Aug 05 06:28:22 PM PDT 24
Finished Aug 05 06:33:12 PM PDT 24
Peak memory 249632 kb
Host smart-3dc56ce7-5efe-4c8b-9e12-1b38ae1ebde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390118839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.390118839
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1065186813
Short name T318
Test name
Test status
Simulation time 261441819 ps
CPU time 0.81 seconds
Started Aug 05 06:28:25 PM PDT 24
Finished Aug 05 06:28:26 PM PDT 24
Peak memory 217520 kb
Host smart-02bbfa9f-4221-42dc-8bdd-967cf67fbad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065186813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1065186813
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3265262744
Short name T630
Test name
Test status
Simulation time 12165214067 ps
CPU time 14.31 seconds
Started Aug 05 06:28:23 PM PDT 24
Finished Aug 05 06:28:38 PM PDT 24
Peak memory 217988 kb
Host smart-c1fea62d-3ea9-43f1-9c99-82aede211eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265262744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3265262744
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2161678419
Short name T523
Test name
Test status
Simulation time 2118645623 ps
CPU time 19.22 seconds
Started Aug 05 06:28:27 PM PDT 24
Finished Aug 05 06:28:46 PM PDT 24
Peak memory 249500 kb
Host smart-40312227-b424-4405-9735-a8064ddb9975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161678419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2161678419
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.537201627
Short name T51
Test name
Test status
Simulation time 118322366560 ps
CPU time 202.11 seconds
Started Aug 05 06:28:24 PM PDT 24
Finished Aug 05 06:31:46 PM PDT 24
Peak memory 249636 kb
Host smart-f13ba8ad-38e6-415c-a0de-e63d51a0a9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537201627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.537201627
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3673638467
Short name T95
Test name
Test status
Simulation time 571730492 ps
CPU time 7.03 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:28:28 PM PDT 24
Peak memory 233008 kb
Host smart-56d0c016-8f9e-4c03-be15-7f3417e7d4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673638467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3673638467
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1222108448
Short name T716
Test name
Test status
Simulation time 8059215862 ps
CPU time 74.83 seconds
Started Aug 05 06:28:23 PM PDT 24
Finished Aug 05 06:29:38 PM PDT 24
Peak memory 237088 kb
Host smart-e2090010-e4e5-49c9-a4f6-fcb4a8198175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222108448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1222108448
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3272996694
Short name T165
Test name
Test status
Simulation time 818720367 ps
CPU time 4.94 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:28:27 PM PDT 24
Peak memory 233072 kb
Host smart-b0a73ad9-5c9b-4283-9aba-b5697b1e5aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272996694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3272996694
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.707678813
Short name T961
Test name
Test status
Simulation time 1333372895 ps
CPU time 8.35 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:28:30 PM PDT 24
Peak memory 233088 kb
Host smart-bb94430b-a341-4a39-b781-cb5c8472598b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707678813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.707678813
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1625540321
Short name T888
Test name
Test status
Simulation time 98696883 ps
CPU time 3.47 seconds
Started Aug 05 06:28:26 PM PDT 24
Finished Aug 05 06:28:30 PM PDT 24
Peak memory 220616 kb
Host smart-c3426fb7-bc3d-4bc0-b339-c3d94b47886e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1625540321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1625540321
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1059100094
Short name T147
Test name
Test status
Simulation time 39986894113 ps
CPU time 46.86 seconds
Started Aug 05 06:28:26 PM PDT 24
Finished Aug 05 06:29:13 PM PDT 24
Peak memory 249752 kb
Host smart-a52cbf12-e8c8-4a23-a2c0-abc6f02e266d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059100094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1059100094
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1737415384
Short name T376
Test name
Test status
Simulation time 1759788528 ps
CPU time 21.61 seconds
Started Aug 05 06:28:13 PM PDT 24
Finished Aug 05 06:28:35 PM PDT 24
Peak memory 216732 kb
Host smart-748310bc-c264-464c-be11-4f1728d6dd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737415384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1737415384
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3137418708
Short name T864
Test name
Test status
Simulation time 8708469248 ps
CPU time 13.71 seconds
Started Aug 05 06:28:22 PM PDT 24
Finished Aug 05 06:28:36 PM PDT 24
Peak memory 216740 kb
Host smart-8a3cb867-089b-4d6f-b294-764a02c44520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137418708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3137418708
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.358051321
Short name T560
Test name
Test status
Simulation time 39104362 ps
CPU time 0.83 seconds
Started Aug 05 06:28:22 PM PDT 24
Finished Aug 05 06:28:23 PM PDT 24
Peak memory 206956 kb
Host smart-a7951481-296e-4d8f-89bb-13604d5366b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358051321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.358051321
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2779307653
Short name T429
Test name
Test status
Simulation time 117347433 ps
CPU time 0.95 seconds
Started Aug 05 06:28:27 PM PDT 24
Finished Aug 05 06:28:28 PM PDT 24
Peak memory 207428 kb
Host smart-fb6bb2c9-18e4-4c7c-aa1a-10d05c13f94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779307653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2779307653
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4204148590
Short name T482
Test name
Test status
Simulation time 644021386 ps
CPU time 3.64 seconds
Started Aug 05 06:28:24 PM PDT 24
Finished Aug 05 06:28:28 PM PDT 24
Peak memory 224956 kb
Host smart-75e0d886-047e-4987-86ec-2ed8676f870e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204148590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4204148590
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1815011734
Short name T365
Test name
Test status
Simulation time 67911036 ps
CPU time 0.7 seconds
Started Aug 05 06:28:29 PM PDT 24
Finished Aug 05 06:28:30 PM PDT 24
Peak memory 205316 kb
Host smart-12794806-a358-40bb-8c0a-2b2c504f9b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815011734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1815011734
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.987412155
Short name T385
Test name
Test status
Simulation time 855284801 ps
CPU time 6.93 seconds
Started Aug 05 06:28:26 PM PDT 24
Finished Aug 05 06:28:33 PM PDT 24
Peak memory 224872 kb
Host smart-56303c9d-8f45-439b-a457-f9c861157803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987412155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.987412155
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.257150399
Short name T375
Test name
Test status
Simulation time 14724661 ps
CPU time 0.79 seconds
Started Aug 05 06:28:23 PM PDT 24
Finished Aug 05 06:28:25 PM PDT 24
Peak memory 206968 kb
Host smart-92c1426e-4aa9-4857-842c-7e06982325f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257150399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.257150399
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2346233779
Short name T513
Test name
Test status
Simulation time 106385123 ps
CPU time 0.87 seconds
Started Aug 05 06:28:25 PM PDT 24
Finished Aug 05 06:28:26 PM PDT 24
Peak memory 216376 kb
Host smart-3112ba46-9765-4b79-8909-c433db4c065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346233779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2346233779
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3127467474
Short name T366
Test name
Test status
Simulation time 458951142 ps
CPU time 7.41 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:28:29 PM PDT 24
Peak memory 233144 kb
Host smart-afd2f1ba-762b-4136-9f5b-1d623e538466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127467474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3127467474
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2399170907
Short name T849
Test name
Test status
Simulation time 114942371254 ps
CPU time 355.29 seconds
Started Aug 05 06:28:23 PM PDT 24
Finished Aug 05 06:34:18 PM PDT 24
Peak memory 249552 kb
Host smart-3aacdb2d-8d44-46b0-8498-2626ab1a5392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399170907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2399170907
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1167767443
Short name T951
Test name
Test status
Simulation time 996309862 ps
CPU time 14.03 seconds
Started Aug 05 06:28:23 PM PDT 24
Finished Aug 05 06:28:37 PM PDT 24
Peak memory 224960 kb
Host smart-a19d0f17-7a02-4024-ab03-e75b621ffedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167767443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1167767443
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4154700675
Short name T364
Test name
Test status
Simulation time 553380212 ps
CPU time 2.27 seconds
Started Aug 05 06:28:23 PM PDT 24
Finished Aug 05 06:28:25 PM PDT 24
Peak memory 224128 kb
Host smart-4fa7ab8a-37d8-45d7-9365-afa3efd8d087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154700675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4154700675
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1738401052
Short name T846
Test name
Test status
Simulation time 2402781426 ps
CPU time 4.74 seconds
Started Aug 05 06:28:27 PM PDT 24
Finished Aug 05 06:28:31 PM PDT 24
Peak memory 233156 kb
Host smart-ad71c392-a534-4c9c-b43a-b8a0dd800a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738401052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1738401052
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2075792222
Short name T486
Test name
Test status
Simulation time 1049995470 ps
CPU time 6.11 seconds
Started Aug 05 06:28:23 PM PDT 24
Finished Aug 05 06:28:29 PM PDT 24
Peak memory 233172 kb
Host smart-569ab231-9a5c-4977-bc3c-ca289c98f057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075792222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2075792222
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2628437112
Short name T674
Test name
Test status
Simulation time 793630291 ps
CPU time 10.09 seconds
Started Aug 05 06:28:24 PM PDT 24
Finished Aug 05 06:28:34 PM PDT 24
Peak memory 222632 kb
Host smart-eb88de39-fb73-4080-b830-c8d824e75ead
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2628437112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2628437112
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2521273026
Short name T576
Test name
Test status
Simulation time 23636937103 ps
CPU time 28.01 seconds
Started Aug 05 06:28:24 PM PDT 24
Finished Aug 05 06:28:52 PM PDT 24
Peak memory 221120 kb
Host smart-987c7ae3-47a2-4ccb-ae7f-2c8e33393c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521273026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2521273026
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1704560886
Short name T332
Test name
Test status
Simulation time 1757404402 ps
CPU time 7.09 seconds
Started Aug 05 06:28:22 PM PDT 24
Finished Aug 05 06:28:29 PM PDT 24
Peak memory 216696 kb
Host smart-cc7c1a20-d6ec-4104-a417-c0732a1305d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704560886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1704560886
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4275858180
Short name T390
Test name
Test status
Simulation time 630466879 ps
CPU time 1.71 seconds
Started Aug 05 06:28:25 PM PDT 24
Finished Aug 05 06:28:26 PM PDT 24
Peak memory 216672 kb
Host smart-9dba700d-4db8-47d1-a9db-773c57b41b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275858180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4275858180
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2777822628
Short name T351
Test name
Test status
Simulation time 185057081 ps
CPU time 0.81 seconds
Started Aug 05 06:28:24 PM PDT 24
Finished Aug 05 06:28:25 PM PDT 24
Peak memory 206344 kb
Host smart-069f03c0-1f93-4e9f-927d-23a0bb5b51bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777822628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2777822628
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1152482820
Short name T781
Test name
Test status
Simulation time 9685918268 ps
CPU time 10.87 seconds
Started Aug 05 06:28:21 PM PDT 24
Finished Aug 05 06:28:32 PM PDT 24
Peak memory 241384 kb
Host smart-4926e100-fb2f-41b9-9b62-3a22d7a3cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152482820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1152482820
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2131208476
Short name T459
Test name
Test status
Simulation time 37963156 ps
CPU time 0.7 seconds
Started Aug 05 06:28:29 PM PDT 24
Finished Aug 05 06:28:30 PM PDT 24
Peak memory 205240 kb
Host smart-d0204d8a-303a-4295-bafb-f0e587574413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131208476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2131208476
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3952287027
Short name T728
Test name
Test status
Simulation time 52833270 ps
CPU time 2.91 seconds
Started Aug 05 06:28:27 PM PDT 24
Finished Aug 05 06:28:30 PM PDT 24
Peak memory 233156 kb
Host smart-48ebbe31-01c4-4f41-9f8a-762c58eb5596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952287027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3952287027
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2666896968
Short name T679
Test name
Test status
Simulation time 98176890 ps
CPU time 0.73 seconds
Started Aug 05 06:28:26 PM PDT 24
Finished Aug 05 06:28:27 PM PDT 24
Peak memory 206284 kb
Host smart-15c4097f-0b9b-452b-a74c-2a0bc1e2d8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666896968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2666896968
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2735884034
Short name T647
Test name
Test status
Simulation time 17633318235 ps
CPU time 169.65 seconds
Started Aug 05 06:28:31 PM PDT 24
Finished Aug 05 06:31:20 PM PDT 24
Peak memory 234432 kb
Host smart-4f974538-0c57-4c1c-8d09-7baaf8892ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735884034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2735884034
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3696189044
Short name T878
Test name
Test status
Simulation time 1222538709 ps
CPU time 19.91 seconds
Started Aug 05 06:28:31 PM PDT 24
Finished Aug 05 06:28:51 PM PDT 24
Peak memory 241312 kb
Host smart-575194ad-2e05-48f4-b083-6197668d46e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696189044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3696189044
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.394283019
Short name T824
Test name
Test status
Simulation time 406326590 ps
CPU time 8.89 seconds
Started Aug 05 06:28:28 PM PDT 24
Finished Aug 05 06:28:37 PM PDT 24
Peak memory 235224 kb
Host smart-58dd64ca-42fb-4e17-99fa-a5ade6a5333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394283019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.394283019
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2118946630
Short name T567
Test name
Test status
Simulation time 1897566583 ps
CPU time 7.95 seconds
Started Aug 05 06:28:29 PM PDT 24
Finished Aug 05 06:28:37 PM PDT 24
Peak memory 233188 kb
Host smart-8101d2ed-32cd-4beb-b648-37b0bca40f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118946630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2118946630
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.397647856
Short name T795
Test name
Test status
Simulation time 4347755494 ps
CPU time 16.03 seconds
Started Aug 05 06:28:25 PM PDT 24
Finished Aug 05 06:28:41 PM PDT 24
Peak memory 233204 kb
Host smart-1ff584cf-df30-4b0a-8373-406950b9d2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397647856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.397647856
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2306709263
Short name T809
Test name
Test status
Simulation time 13509558887 ps
CPU time 11.34 seconds
Started Aug 05 06:28:28 PM PDT 24
Finished Aug 05 06:28:39 PM PDT 24
Peak memory 233224 kb
Host smart-84c429d6-cc73-498b-90bf-78b344d5f554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306709263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2306709263
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.777042984
Short name T804
Test name
Test status
Simulation time 1919684605 ps
CPU time 8.95 seconds
Started Aug 05 06:28:24 PM PDT 24
Finished Aug 05 06:28:33 PM PDT 24
Peak memory 224948 kb
Host smart-b8dc5763-1357-4fe7-ab05-21afd14a6572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777042984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.777042984
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2454020580
Short name T975
Test name
Test status
Simulation time 3529869744 ps
CPU time 18.83 seconds
Started Aug 05 06:28:24 PM PDT 24
Finished Aug 05 06:28:43 PM PDT 24
Peak memory 223648 kb
Host smart-9145ef6c-09e2-4797-b73e-7ad345cce50c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2454020580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2454020580
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2259627254
Short name T503
Test name
Test status
Simulation time 33323697606 ps
CPU time 336.51 seconds
Started Aug 05 06:28:28 PM PDT 24
Finished Aug 05 06:34:05 PM PDT 24
Peak memory 254064 kb
Host smart-bf76dabb-45f5-44ae-be5c-09c0b71dfaa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259627254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2259627254
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2833704271
Short name T650
Test name
Test status
Simulation time 15077135 ps
CPU time 0.73 seconds
Started Aug 05 06:28:29 PM PDT 24
Finished Aug 05 06:28:30 PM PDT 24
Peak memory 206152 kb
Host smart-e7371ad2-1fcc-483e-9767-4532e3017e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833704271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2833704271
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.412495289
Short name T840
Test name
Test status
Simulation time 5476476835 ps
CPU time 6.86 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:28:39 PM PDT 24
Peak memory 216744 kb
Host smart-cf7faef4-bf78-4ce3-bc18-e6966b61599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412495289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.412495289
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3188574262
Short name T10
Test name
Test status
Simulation time 103426195 ps
CPU time 0.79 seconds
Started Aug 05 06:28:27 PM PDT 24
Finished Aug 05 06:28:28 PM PDT 24
Peak memory 206304 kb
Host smart-76c4ab81-e739-425c-b390-ef2a0aa6b552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188574262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3188574262
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.56633898
Short name T923
Test name
Test status
Simulation time 63190502 ps
CPU time 0.76 seconds
Started Aug 05 06:28:26 PM PDT 24
Finished Aug 05 06:28:27 PM PDT 24
Peak memory 206300 kb
Host smart-daaf2b4a-5066-4199-aaab-b7dc7482cac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56633898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.56633898
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2126931259
Short name T574
Test name
Test status
Simulation time 1439382913 ps
CPU time 8.13 seconds
Started Aug 05 06:28:26 PM PDT 24
Finished Aug 05 06:28:35 PM PDT 24
Peak memory 233048 kb
Host smart-15451c6a-603c-4155-a5ea-65bde809e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126931259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2126931259
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1956429209
Short name T5
Test name
Test status
Simulation time 12813753 ps
CPU time 0.77 seconds
Started Aug 05 06:28:41 PM PDT 24
Finished Aug 05 06:28:42 PM PDT 24
Peak memory 205872 kb
Host smart-3afbeb62-1584-4abf-a38c-85f8c981259f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956429209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1956429209
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2193755501
Short name T181
Test name
Test status
Simulation time 7441994708 ps
CPU time 7.52 seconds
Started Aug 05 06:28:29 PM PDT 24
Finished Aug 05 06:28:36 PM PDT 24
Peak memory 233088 kb
Host smart-5087df62-31cf-4f9b-9e9d-ca4169e84a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193755501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2193755501
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2325847207
Short name T687
Test name
Test status
Simulation time 20650143 ps
CPU time 0.81 seconds
Started Aug 05 06:28:29 PM PDT 24
Finished Aug 05 06:28:30 PM PDT 24
Peak memory 206004 kb
Host smart-15913b14-caf0-4c5c-b66a-9353fc70237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325847207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2325847207
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.4099274696
Short name T416
Test name
Test status
Simulation time 1559892656 ps
CPU time 21.42 seconds
Started Aug 05 06:28:29 PM PDT 24
Finished Aug 05 06:28:50 PM PDT 24
Peak memory 253400 kb
Host smart-875c0d0d-271e-4385-b55c-c60f8829df6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099274696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.4099274696
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2673169144
Short name T847
Test name
Test status
Simulation time 52022021104 ps
CPU time 492.6 seconds
Started Aug 05 06:28:31 PM PDT 24
Finished Aug 05 06:36:44 PM PDT 24
Peak memory 261848 kb
Host smart-074b528c-e3d7-4951-9d5a-36e2f44ae073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673169144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2673169144
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.879122976
Short name T934
Test name
Test status
Simulation time 12799013897 ps
CPU time 44.42 seconds
Started Aug 05 06:28:29 PM PDT 24
Finished Aug 05 06:29:13 PM PDT 24
Peak memory 233116 kb
Host smart-dc93c566-0484-4e31-899d-23be8bf45800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879122976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.879122976
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3455217667
Short name T592
Test name
Test status
Simulation time 129309086519 ps
CPU time 287.37 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:33:19 PM PDT 24
Peak memory 255836 kb
Host smart-f5294116-c4de-4215-9dce-676e30b306fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455217667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3455217667
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2075263553
Short name T420
Test name
Test status
Simulation time 875008087 ps
CPU time 4.27 seconds
Started Aug 05 06:28:25 PM PDT 24
Finished Aug 05 06:28:29 PM PDT 24
Peak memory 224876 kb
Host smart-be80461a-75d7-4706-9e10-4c101ee6ce27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075263553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2075263553
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1132013311
Short name T660
Test name
Test status
Simulation time 10546309003 ps
CPU time 96.21 seconds
Started Aug 05 06:28:29 PM PDT 24
Finished Aug 05 06:30:05 PM PDT 24
Peak memory 249644 kb
Host smart-10cd5d77-23dd-419c-8649-20cdd5cfa40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132013311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1132013311
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1294239499
Short name T585
Test name
Test status
Simulation time 116340028 ps
CPU time 2.26 seconds
Started Aug 05 06:28:26 PM PDT 24
Finished Aug 05 06:28:29 PM PDT 24
Peak memory 232784 kb
Host smart-dcea5185-dcca-4129-942a-843aa4f6989d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294239499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1294239499
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3202114678
Short name T215
Test name
Test status
Simulation time 1293491125 ps
CPU time 4.77 seconds
Started Aug 05 06:28:29 PM PDT 24
Finished Aug 05 06:28:33 PM PDT 24
Peak memory 233152 kb
Host smart-71c4e4ef-7d35-46c1-81d4-7ac77b34b5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202114678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3202114678
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2631866388
Short name T404
Test name
Test status
Simulation time 744071689 ps
CPU time 7.76 seconds
Started Aug 05 06:28:28 PM PDT 24
Finished Aug 05 06:28:36 PM PDT 24
Peak memory 220216 kb
Host smart-6b88fed8-4cda-4684-b38b-ee9343ca92a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2631866388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2631866388
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3698713767
Short name T883
Test name
Test status
Simulation time 57865738191 ps
CPU time 500.34 seconds
Started Aug 05 06:28:33 PM PDT 24
Finished Aug 05 06:36:53 PM PDT 24
Peak memory 250080 kb
Host smart-5ea8d127-abff-4d1d-9b86-6f428bc46b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698713767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3698713767
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.724401067
Short name T826
Test name
Test status
Simulation time 1015222925 ps
CPU time 5.66 seconds
Started Aug 05 06:28:26 PM PDT 24
Finished Aug 05 06:28:32 PM PDT 24
Peak memory 216652 kb
Host smart-6ca3f255-c97e-4320-89bc-52fbffbc590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724401067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.724401067
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1374519358
Short name T352
Test name
Test status
Simulation time 26029879 ps
CPU time 1.05 seconds
Started Aug 05 06:28:27 PM PDT 24
Finished Aug 05 06:28:28 PM PDT 24
Peak memory 208196 kb
Host smart-b2ccda6b-fb28-491b-9ad4-de5aca3ba27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374519358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1374519358
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2239237196
Short name T868
Test name
Test status
Simulation time 87439893 ps
CPU time 0.84 seconds
Started Aug 05 06:28:25 PM PDT 24
Finished Aug 05 06:28:26 PM PDT 24
Peak memory 206352 kb
Host smart-527a6748-3ce8-42de-9d37-58b63cac1d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239237196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2239237196
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1152802370
Short name T697
Test name
Test status
Simulation time 2629091795 ps
CPU time 7.69 seconds
Started Aug 05 06:28:30 PM PDT 24
Finished Aug 05 06:28:38 PM PDT 24
Peak memory 241456 kb
Host smart-b37ae724-49eb-4acd-a0be-20589bb3d172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152802370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1152802370
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4242624224
Short name T622
Test name
Test status
Simulation time 24135716 ps
CPU time 0.74 seconds
Started Aug 05 06:28:31 PM PDT 24
Finished Aug 05 06:28:32 PM PDT 24
Peak memory 205816 kb
Host smart-8c488929-fc79-4f09-bab3-3e466210274f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242624224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4242624224
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3544412609
Short name T690
Test name
Test status
Simulation time 1677107086 ps
CPU time 5.57 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:28:37 PM PDT 24
Peak memory 224880 kb
Host smart-26455634-14b8-458f-8d45-a5719fea9fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544412609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3544412609
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2957636480
Short name T367
Test name
Test status
Simulation time 29792273 ps
CPU time 0.74 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:28:33 PM PDT 24
Peak memory 206940 kb
Host smart-4205110e-08c1-4acb-b947-9967bce8adbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957636480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2957636480
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3185257273
Short name T565
Test name
Test status
Simulation time 155280056639 ps
CPU time 205.17 seconds
Started Aug 05 06:28:31 PM PDT 24
Finished Aug 05 06:31:56 PM PDT 24
Peak memory 250676 kb
Host smart-f9f7da32-1c87-4297-9a64-740c4d48ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185257273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3185257273
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2339631715
Short name T932
Test name
Test status
Simulation time 13194955915 ps
CPU time 77.7 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:29:50 PM PDT 24
Peak memory 252804 kb
Host smart-a5bedcfb-31d9-4caf-8969-210c236787e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339631715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2339631715
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2758368325
Short name T444
Test name
Test status
Simulation time 15825666288 ps
CPU time 20.26 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:28:52 PM PDT 24
Peak memory 241456 kb
Host smart-3554804c-14b0-486c-af47-6e14619904c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758368325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2758368325
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1974913906
Short name T753
Test name
Test status
Simulation time 252572426 ps
CPU time 2.88 seconds
Started Aug 05 06:28:35 PM PDT 24
Finished Aug 05 06:28:38 PM PDT 24
Peak memory 233192 kb
Host smart-62f83345-82da-4841-8fea-aa57da1ca348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974913906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1974913906
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3604009860
Short name T212
Test name
Test status
Simulation time 35144994759 ps
CPU time 116.68 seconds
Started Aug 05 06:28:35 PM PDT 24
Finished Aug 05 06:30:32 PM PDT 24
Peak memory 257472 kb
Host smart-357c68ec-e43b-4120-a122-0dcfdb79d92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604009860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3604009860
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.105625402
Short name T732
Test name
Test status
Simulation time 13096030167 ps
CPU time 32.26 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:29:04 PM PDT 24
Peak memory 233244 kb
Host smart-2358d70d-e458-44d9-ae41-34ba0c497640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105625402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.105625402
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3844915828
Short name T284
Test name
Test status
Simulation time 1223317419 ps
CPU time 5.66 seconds
Started Aug 05 06:28:30 PM PDT 24
Finished Aug 05 06:28:36 PM PDT 24
Peak memory 233112 kb
Host smart-12fb2f43-ff31-4d93-906d-55e208735d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844915828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3844915828
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1405143509
Short name T714
Test name
Test status
Simulation time 166946897 ps
CPU time 4.36 seconds
Started Aug 05 06:28:41 PM PDT 24
Finished Aug 05 06:28:45 PM PDT 24
Peak memory 233152 kb
Host smart-4f28a7fb-dd43-4ba4-84be-73ee2264cdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405143509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1405143509
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.61720337
Short name T137
Test name
Test status
Simulation time 23638653593 ps
CPU time 12.86 seconds
Started Aug 05 06:28:33 PM PDT 24
Finished Aug 05 06:28:46 PM PDT 24
Peak memory 222528 kb
Host smart-07f91f47-f96e-48ce-ad44-328a465d917d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=61720337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direc
t.61720337
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1845551270
Short name T150
Test name
Test status
Simulation time 4342075575 ps
CPU time 93.42 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:30:06 PM PDT 24
Peak memory 273788 kb
Host smart-e4973b62-df6f-4453-9364-80941e59fd3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845551270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1845551270
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1132630586
Short name T431
Test name
Test status
Simulation time 30554535174 ps
CPU time 40.78 seconds
Started Aug 05 06:28:35 PM PDT 24
Finished Aug 05 06:29:16 PM PDT 24
Peak memory 216732 kb
Host smart-6f0d045e-e9c6-4669-9ec6-e58009ce3308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132630586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1132630586
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3965332320
Short name T692
Test name
Test status
Simulation time 6157290398 ps
CPU time 11 seconds
Started Aug 05 06:28:33 PM PDT 24
Finished Aug 05 06:28:44 PM PDT 24
Peak memory 216728 kb
Host smart-7e3b2d52-7da8-4e23-aed5-17f3619f1846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965332320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3965332320
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1431336882
Short name T727
Test name
Test status
Simulation time 712725506 ps
CPU time 3.46 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:28:35 PM PDT 24
Peak memory 216680 kb
Host smart-1b1ef631-5f32-43ee-a5c1-160e49805d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431336882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1431336882
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2823556354
Short name T853
Test name
Test status
Simulation time 106185977 ps
CPU time 1.12 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:28:33 PM PDT 24
Peak memory 207376 kb
Host smart-6f23ce72-73ba-4076-b497-292b95b1f6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823556354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2823556354
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2802606145
Short name T252
Test name
Test status
Simulation time 4103514943 ps
CPU time 9.43 seconds
Started Aug 05 06:28:34 PM PDT 24
Finished Aug 05 06:28:44 PM PDT 24
Peak memory 241336 kb
Host smart-31193383-dbb3-4901-8847-7302e911edc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802606145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2802606145
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1847595601
Short name T334
Test name
Test status
Simulation time 71203552 ps
CPU time 0.76 seconds
Started Aug 05 06:27:33 PM PDT 24
Finished Aug 05 06:27:34 PM PDT 24
Peak memory 205840 kb
Host smart-8bc0fe96-9fdb-4ebb-96c4-117cafe2c0ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847595601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
847595601
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3480986153
Short name T632
Test name
Test status
Simulation time 645770149 ps
CPU time 5.56 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:27:40 PM PDT 24
Peak memory 233060 kb
Host smart-0a70d0e9-841c-44b1-9847-7ce94c8e5fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480986153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3480986153
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2569332799
Short name T345
Test name
Test status
Simulation time 55679316 ps
CPU time 0.75 seconds
Started Aug 05 06:27:31 PM PDT 24
Finished Aug 05 06:27:32 PM PDT 24
Peak memory 205824 kb
Host smart-e941165c-1471-41b1-be72-39e79b6b6a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569332799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2569332799
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.819111020
Short name T521
Test name
Test status
Simulation time 2431150182 ps
CPU time 17.16 seconds
Started Aug 05 06:27:27 PM PDT 24
Finished Aug 05 06:27:44 PM PDT 24
Peak memory 233164 kb
Host smart-54a448af-986d-46dd-b4a3-825b318fffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819111020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.819111020
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4056531644
Short name T702
Test name
Test status
Simulation time 3066237665 ps
CPU time 28.8 seconds
Started Aug 05 06:27:33 PM PDT 24
Finished Aug 05 06:28:03 PM PDT 24
Peak memory 241152 kb
Host smart-29e8a8b7-aee2-44cb-abaa-2e434d78d522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056531644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4056531644
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3474180306
Short name T330
Test name
Test status
Simulation time 2442622095 ps
CPU time 12.96 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:27:48 PM PDT 24
Peak memory 241344 kb
Host smart-7f509b16-596a-40ef-a7e3-7e1b35dac7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474180306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3474180306
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1743345460
Short name T60
Test name
Test status
Simulation time 6746434792 ps
CPU time 40.78 seconds
Started Aug 05 06:27:27 PM PDT 24
Finished Aug 05 06:28:08 PM PDT 24
Peak memory 239472 kb
Host smart-a5ee1479-38a4-4551-8df2-ebd12ad76232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743345460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1743345460
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1864884929
Short name T368
Test name
Test status
Simulation time 514663597 ps
CPU time 6.78 seconds
Started Aug 05 06:27:35 PM PDT 24
Finished Aug 05 06:27:41 PM PDT 24
Peak memory 224928 kb
Host smart-7358b9f3-72fb-4641-9a5c-d7f4163c026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864884929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1864884929
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1958098582
Short name T241
Test name
Test status
Simulation time 1640470798 ps
CPU time 17.78 seconds
Started Aug 05 06:27:30 PM PDT 24
Finished Aug 05 06:27:48 PM PDT 24
Peak memory 241092 kb
Host smart-7fba2cee-148d-4ba6-b8f6-dae4c9ca40b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958098582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1958098582
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.14491204
Short name T614
Test name
Test status
Simulation time 6030789373 ps
CPU time 21.78 seconds
Started Aug 05 06:27:29 PM PDT 24
Finished Aug 05 06:27:51 PM PDT 24
Peak memory 233248 kb
Host smart-9c2f45f2-14a2-4311-838d-b4cac33d6d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14491204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.14491204
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2604029446
Short name T402
Test name
Test status
Simulation time 31256505 ps
CPU time 2.16 seconds
Started Aug 05 06:27:28 PM PDT 24
Finished Aug 05 06:27:31 PM PDT 24
Peak memory 224244 kb
Host smart-ac057d2d-64f3-45f3-8204-25ddc9dceaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604029446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2604029446
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.781884243
Short name T480
Test name
Test status
Simulation time 956242783 ps
CPU time 6.97 seconds
Started Aug 05 06:27:30 PM PDT 24
Finished Aug 05 06:27:37 PM PDT 24
Peak memory 223492 kb
Host smart-d5e3a8aa-f874-485c-8166-9b4101539672
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=781884243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.781884243
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1430430014
Short name T808
Test name
Test status
Simulation time 73152373445 ps
CPU time 185.99 seconds
Started Aug 05 06:27:35 PM PDT 24
Finished Aug 05 06:30:41 PM PDT 24
Peak memory 254576 kb
Host smart-9d7d9091-2be7-4a3f-9615-b81c4e5d618d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430430014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1430430014
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3123677916
Short name T881
Test name
Test status
Simulation time 1680646220 ps
CPU time 14.31 seconds
Started Aug 05 06:27:28 PM PDT 24
Finished Aug 05 06:27:43 PM PDT 24
Peak memory 219636 kb
Host smart-a317a3bd-c915-4967-b8ec-4a1674cb8760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123677916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3123677916
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1405250503
Short name T855
Test name
Test status
Simulation time 1577063243 ps
CPU time 6.25 seconds
Started Aug 05 06:27:31 PM PDT 24
Finished Aug 05 06:27:37 PM PDT 24
Peak memory 216624 kb
Host smart-9eeaad57-d850-4a03-b4ef-8b3a42f6db0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405250503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1405250503
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3783477199
Short name T525
Test name
Test status
Simulation time 20248828 ps
CPU time 0.85 seconds
Started Aug 05 06:27:26 PM PDT 24
Finished Aug 05 06:27:27 PM PDT 24
Peak memory 206356 kb
Host smart-7dd3e535-fdaa-4f41-8064-c7d7c6d73eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783477199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3783477199
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2775773915
Short name T370
Test name
Test status
Simulation time 32011408 ps
CPU time 0.79 seconds
Started Aug 05 06:27:28 PM PDT 24
Finished Aug 05 06:27:29 PM PDT 24
Peak memory 206380 kb
Host smart-f07a3383-6687-4bd1-bdf0-875334a1577c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775773915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2775773915
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1605555931
Short name T476
Test name
Test status
Simulation time 1105705174 ps
CPU time 6.07 seconds
Started Aug 05 06:27:33 PM PDT 24
Finished Aug 05 06:27:40 PM PDT 24
Peak memory 233144 kb
Host smart-64c01987-eb14-4a04-9074-3d017c7318a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605555931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1605555931
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1348852762
Short name T681
Test name
Test status
Simulation time 10579916 ps
CPU time 0.69 seconds
Started Aug 05 06:28:37 PM PDT 24
Finished Aug 05 06:28:38 PM PDT 24
Peak memory 205712 kb
Host smart-c8cb700d-4cd7-4fd0-bbd6-57b512b894ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348852762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1348852762
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.669553560
Short name T448
Test name
Test status
Simulation time 774305778 ps
CPU time 9.07 seconds
Started Aug 05 06:28:41 PM PDT 24
Finished Aug 05 06:28:50 PM PDT 24
Peak memory 233152 kb
Host smart-93fc5f84-de07-41a2-82eb-a104d46e4a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669553560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.669553560
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.463811872
Short name T664
Test name
Test status
Simulation time 53028433 ps
CPU time 0.76 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:28:33 PM PDT 24
Peak memory 207420 kb
Host smart-cfae0872-fc16-46b3-a21e-5d23b9678204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463811872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.463811872
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1955719085
Short name T496
Test name
Test status
Simulation time 39041756340 ps
CPU time 223.1 seconds
Started Aug 05 06:28:38 PM PDT 24
Finished Aug 05 06:32:21 PM PDT 24
Peak memory 253892 kb
Host smart-a2cb8004-da0f-4bd8-b644-3b98ead6d22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955719085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1955719085
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2653401612
Short name T675
Test name
Test status
Simulation time 1986567705 ps
CPU time 41.56 seconds
Started Aug 05 06:28:38 PM PDT 24
Finished Aug 05 06:29:19 PM PDT 24
Peak memory 234232 kb
Host smart-ad9cb6cf-5319-441c-b218-12429bdda0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653401612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2653401612
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2202824655
Short name T755
Test name
Test status
Simulation time 15933670838 ps
CPU time 101.06 seconds
Started Aug 05 06:28:39 PM PDT 24
Finished Aug 05 06:30:20 PM PDT 24
Peak memory 240988 kb
Host smart-65040b59-73d1-48be-96be-d16534bc2a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202824655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2202824655
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.403122861
Short name T686
Test name
Test status
Simulation time 101460876 ps
CPU time 2.58 seconds
Started Aug 05 06:28:37 PM PDT 24
Finished Aug 05 06:28:40 PM PDT 24
Peak memory 224880 kb
Host smart-8dfcadf2-7a6b-4700-a3ec-d6275f8970de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403122861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.403122861
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3556122726
Short name T711
Test name
Test status
Simulation time 21843478853 ps
CPU time 44.14 seconds
Started Aug 05 06:28:36 PM PDT 24
Finished Aug 05 06:29:21 PM PDT 24
Peak memory 256476 kb
Host smart-d970ce4c-f084-428c-8f83-cd56d351cf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556122726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3556122726
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1676907218
Short name T803
Test name
Test status
Simulation time 7242522078 ps
CPU time 15.04 seconds
Started Aug 05 06:28:34 PM PDT 24
Finished Aug 05 06:28:49 PM PDT 24
Peak memory 233172 kb
Host smart-c94e9402-4439-456a-835f-28ab76519ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676907218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1676907218
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3613763665
Short name T579
Test name
Test status
Simulation time 4009947927 ps
CPU time 43.89 seconds
Started Aug 05 06:28:41 PM PDT 24
Finished Aug 05 06:29:25 PM PDT 24
Peak memory 240908 kb
Host smart-8e855140-c6bf-4149-9ea7-2d7c4dc7ca94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613763665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3613763665
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.884162560
Short name T671
Test name
Test status
Simulation time 1996805635 ps
CPU time 8.92 seconds
Started Aug 05 06:28:30 PM PDT 24
Finished Aug 05 06:28:39 PM PDT 24
Peak memory 224940 kb
Host smart-c719e9c0-3591-4538-892a-eed3416b1873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884162560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.884162560
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3867917706
Short name T40
Test name
Test status
Simulation time 6484472587 ps
CPU time 13.82 seconds
Started Aug 05 06:28:35 PM PDT 24
Finished Aug 05 06:28:49 PM PDT 24
Peak memory 232956 kb
Host smart-9d52cb7c-bdcc-4519-8a36-86b254dcaa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867917706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3867917706
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.966329977
Short name T393
Test name
Test status
Simulation time 239151259 ps
CPU time 4.79 seconds
Started Aug 05 06:28:39 PM PDT 24
Finished Aug 05 06:28:44 PM PDT 24
Peak memory 220992 kb
Host smart-8b98c8f4-0cb9-4444-9f37-85455c36d43b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=966329977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.966329977
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2780142429
Short name T130
Test name
Test status
Simulation time 34682269549 ps
CPU time 157.91 seconds
Started Aug 05 06:28:36 PM PDT 24
Finished Aug 05 06:31:14 PM PDT 24
Peak memory 249660 kb
Host smart-c933a1ce-11a6-4a7f-8c9a-d98adf40375e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780142429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2780142429
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1168590304
Short name T306
Test name
Test status
Simulation time 4135092045 ps
CPU time 28.13 seconds
Started Aug 05 06:28:31 PM PDT 24
Finished Aug 05 06:29:00 PM PDT 24
Peak memory 216792 kb
Host smart-2e39859b-6bbc-4b96-958a-b0345bccfd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168590304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1168590304
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4290161192
Short name T988
Test name
Test status
Simulation time 2391298682 ps
CPU time 6.13 seconds
Started Aug 05 06:28:31 PM PDT 24
Finished Aug 05 06:28:37 PM PDT 24
Peak memory 216704 kb
Host smart-2599f5d6-e521-4990-9e9c-288e8e9d2f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290161192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4290161192
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2492766670
Short name T936
Test name
Test status
Simulation time 1337933808 ps
CPU time 1.41 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:28:33 PM PDT 24
Peak memory 216672 kb
Host smart-49566163-f64a-43bf-a302-7432b50e2088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492766670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2492766670
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.903027675
Short name T631
Test name
Test status
Simulation time 352078355 ps
CPU time 0.76 seconds
Started Aug 05 06:28:32 PM PDT 24
Finished Aug 05 06:28:33 PM PDT 24
Peak memory 206364 kb
Host smart-915dfc4c-efd1-4463-92c8-d51df90d043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903027675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.903027675
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1540735302
Short name T426
Test name
Test status
Simulation time 2050317024 ps
CPU time 3.89 seconds
Started Aug 05 06:28:41 PM PDT 24
Finished Aug 05 06:28:45 PM PDT 24
Peak memory 233156 kb
Host smart-b5b5ea2c-622b-4064-8002-6833bac0fe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540735302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1540735302
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4209498974
Short name T895
Test name
Test status
Simulation time 21820084 ps
CPU time 0.73 seconds
Started Aug 05 06:28:45 PM PDT 24
Finished Aug 05 06:28:46 PM PDT 24
Peak memory 205288 kb
Host smart-a225d5bb-66f0-4c92-b289-c65c4e4d0aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209498974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4209498974
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.706142117
Short name T945
Test name
Test status
Simulation time 2813713638 ps
CPU time 13.99 seconds
Started Aug 05 06:28:43 PM PDT 24
Finished Aug 05 06:28:57 PM PDT 24
Peak memory 224976 kb
Host smart-160a338c-0899-44dc-abc7-949f3451ba4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706142117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.706142117
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2479242105
Short name T607
Test name
Test status
Simulation time 56119238 ps
CPU time 0.76 seconds
Started Aug 05 06:28:40 PM PDT 24
Finished Aug 05 06:28:41 PM PDT 24
Peak memory 205924 kb
Host smart-8ce4a6eb-8015-4f33-b310-cceaa13da11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479242105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2479242105
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1725005867
Short name T43
Test name
Test status
Simulation time 88591817373 ps
CPU time 130.62 seconds
Started Aug 05 06:28:43 PM PDT 24
Finished Aug 05 06:30:53 PM PDT 24
Peak memory 249552 kb
Host smart-7b1a044e-61dc-4afa-b71b-4979f395a466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725005867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1725005867
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.39827360
Short name T986
Test name
Test status
Simulation time 2398479578 ps
CPU time 54.4 seconds
Started Aug 05 06:28:43 PM PDT 24
Finished Aug 05 06:29:37 PM PDT 24
Peak memory 251712 kb
Host smart-27aadaab-116c-4d28-a99b-e9626ee92632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39827360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.39827360
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.247420016
Short name T194
Test name
Test status
Simulation time 39533869583 ps
CPU time 331.51 seconds
Started Aug 05 06:28:44 PM PDT 24
Finished Aug 05 06:34:16 PM PDT 24
Peak memory 252896 kb
Host smart-e43d2948-6427-4376-9862-3f04b2241910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247420016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.247420016
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1814287766
Short name T382
Test name
Test status
Simulation time 384666697 ps
CPU time 4.13 seconds
Started Aug 05 06:28:42 PM PDT 24
Finished Aug 05 06:28:46 PM PDT 24
Peak memory 224820 kb
Host smart-ef4373e6-6dbf-46e2-b255-9354f4b134da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814287766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1814287766
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.4045625326
Short name T655
Test name
Test status
Simulation time 28788880000 ps
CPU time 221.3 seconds
Started Aug 05 06:28:42 PM PDT 24
Finished Aug 05 06:32:23 PM PDT 24
Peak memory 249552 kb
Host smart-d8dc70df-6881-4481-bb08-99938fb36d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045625326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.4045625326
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4016766581
Short name T218
Test name
Test status
Simulation time 2075905457 ps
CPU time 11.86 seconds
Started Aug 05 06:28:35 PM PDT 24
Finished Aug 05 06:28:48 PM PDT 24
Peak memory 233104 kb
Host smart-3add5dd4-db3b-4d85-a55d-d9e65e75c3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016766581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4016766581
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3409866613
Short name T228
Test name
Test status
Simulation time 5807489032 ps
CPU time 54.36 seconds
Started Aug 05 06:28:37 PM PDT 24
Finished Aug 05 06:29:31 PM PDT 24
Peak memory 233252 kb
Host smart-c07fcb5c-92f7-4949-aba2-806360787924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409866613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3409866613
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2401940406
Short name T549
Test name
Test status
Simulation time 174366515 ps
CPU time 2.49 seconds
Started Aug 05 06:28:37 PM PDT 24
Finished Aug 05 06:28:40 PM PDT 24
Peak memory 224952 kb
Host smart-52b7fd9c-0c95-4050-9981-80988b6080ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401940406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2401940406
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2775912477
Short name T811
Test name
Test status
Simulation time 12077480238 ps
CPU time 11.62 seconds
Started Aug 05 06:28:38 PM PDT 24
Finished Aug 05 06:28:49 PM PDT 24
Peak memory 238528 kb
Host smart-51b24d97-3bbc-48ad-9fda-42b0bab47c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775912477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2775912477
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.585210783
Short name T627
Test name
Test status
Simulation time 192773105 ps
CPU time 4.71 seconds
Started Aug 05 06:28:43 PM PDT 24
Finished Aug 05 06:28:48 PM PDT 24
Peak memory 223552 kb
Host smart-39f5c6cf-b8dd-4d90-a862-9354e599ef78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=585210783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.585210783
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.341698171
Short name T400
Test name
Test status
Simulation time 4017678995 ps
CPU time 26.35 seconds
Started Aug 05 06:28:39 PM PDT 24
Finished Aug 05 06:29:06 PM PDT 24
Peak memory 221104 kb
Host smart-3b593cad-277f-41a6-838b-b64cd1e0b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341698171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.341698171
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3750955047
Short name T652
Test name
Test status
Simulation time 20264444947 ps
CPU time 16.45 seconds
Started Aug 05 06:28:37 PM PDT 24
Finished Aug 05 06:28:54 PM PDT 24
Peak memory 218028 kb
Host smart-cdc7125d-a07c-4629-927b-ffb83c6fb909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750955047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3750955047
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.945214552
Short name T473
Test name
Test status
Simulation time 45601427 ps
CPU time 0.89 seconds
Started Aug 05 06:28:37 PM PDT 24
Finished Aug 05 06:28:38 PM PDT 24
Peak memory 208184 kb
Host smart-639db84b-98a8-4d7b-be21-bac3632fab87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945214552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.945214552
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4034695630
Short name T691
Test name
Test status
Simulation time 300626413 ps
CPU time 0.81 seconds
Started Aug 05 06:28:38 PM PDT 24
Finished Aug 05 06:28:39 PM PDT 24
Peak memory 206344 kb
Host smart-9b5686a3-e257-4a66-a544-264a12a9bd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034695630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4034695630
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.205725617
Short name T449
Test name
Test status
Simulation time 13077978723 ps
CPU time 13.7 seconds
Started Aug 05 06:28:36 PM PDT 24
Finished Aug 05 06:28:50 PM PDT 24
Peak memory 224932 kb
Host smart-cafb6a7b-3e70-4f90-b9fd-74d109abf1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205725617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.205725617
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2530515806
Short name T470
Test name
Test status
Simulation time 15933913 ps
CPU time 0.74 seconds
Started Aug 05 06:28:48 PM PDT 24
Finished Aug 05 06:28:49 PM PDT 24
Peak memory 205316 kb
Host smart-ae40b217-ae7f-4e88-b060-c7fbb667b2a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530515806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2530515806
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1508311960
Short name T350
Test name
Test status
Simulation time 138628803 ps
CPU time 2.18 seconds
Started Aug 05 06:28:48 PM PDT 24
Finished Aug 05 06:28:50 PM PDT 24
Peak memory 232752 kb
Host smart-4dfed454-5b50-45a8-aa40-9fdc43eb4805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508311960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1508311960
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.61151359
Short name T599
Test name
Test status
Simulation time 39642218 ps
CPU time 0.79 seconds
Started Aug 05 06:28:43 PM PDT 24
Finished Aug 05 06:28:44 PM PDT 24
Peak memory 207292 kb
Host smart-7e9f4201-d968-4e97-91ad-4e0564162331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61151359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.61151359
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1285719210
Short name T344
Test name
Test status
Simulation time 1172712696 ps
CPU time 18.6 seconds
Started Aug 05 06:28:47 PM PDT 24
Finished Aug 05 06:29:06 PM PDT 24
Peak memory 238764 kb
Host smart-f27f9388-dde8-49ea-b7ef-3a5e752ee085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285719210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1285719210
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2938911904
Short name T381
Test name
Test status
Simulation time 4764628555 ps
CPU time 50.53 seconds
Started Aug 05 06:28:47 PM PDT 24
Finished Aug 05 06:29:38 PM PDT 24
Peak memory 249628 kb
Host smart-e8ed437d-48fb-4400-80bd-8aa689cc41a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938911904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2938911904
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1194857899
Short name T221
Test name
Test status
Simulation time 57633328629 ps
CPU time 141.98 seconds
Started Aug 05 06:28:49 PM PDT 24
Finished Aug 05 06:31:11 PM PDT 24
Peak memory 252736 kb
Host smart-692a18a8-fa6f-4030-8bd3-2508614b1c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194857899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1194857899
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1683458057
Short name T603
Test name
Test status
Simulation time 309822477 ps
CPU time 9.7 seconds
Started Aug 05 06:28:48 PM PDT 24
Finished Aug 05 06:28:58 PM PDT 24
Peak memory 249520 kb
Host smart-2d65dded-e734-4715-aa07-692b4034435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683458057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1683458057
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4017575978
Short name T698
Test name
Test status
Simulation time 1353663263 ps
CPU time 25.44 seconds
Started Aug 05 06:28:46 PM PDT 24
Finished Aug 05 06:29:12 PM PDT 24
Peak memory 241352 kb
Host smart-9944736b-7eff-4219-a627-610dfb38f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017575978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4017575978
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3604972612
Short name T619
Test name
Test status
Simulation time 3513368543 ps
CPU time 18.93 seconds
Started Aug 05 06:28:43 PM PDT 24
Finished Aug 05 06:29:02 PM PDT 24
Peak memory 233196 kb
Host smart-1d8be484-4575-4be7-89a5-44dbfc545d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604972612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3604972612
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.263962918
Short name T62
Test name
Test status
Simulation time 505187779 ps
CPU time 5.58 seconds
Started Aug 05 06:28:43 PM PDT 24
Finished Aug 05 06:28:49 PM PDT 24
Peak memory 233180 kb
Host smart-a2cac272-be96-481f-abd4-19b669b4b3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263962918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.263962918
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2945176651
Short name T275
Test name
Test status
Simulation time 365626841 ps
CPU time 4.7 seconds
Started Aug 05 06:28:45 PM PDT 24
Finished Aug 05 06:28:50 PM PDT 24
Peak memory 233212 kb
Host smart-42aad236-a7fa-467c-943f-c6743d9025a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945176651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2945176651
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1995351468
Short name T223
Test name
Test status
Simulation time 1285417379 ps
CPU time 4.25 seconds
Started Aug 05 06:28:42 PM PDT 24
Finished Aug 05 06:28:47 PM PDT 24
Peak memory 224856 kb
Host smart-65e86d98-90dc-468e-9678-dc1a6bd2c0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995351468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1995351468
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3999383907
Short name T479
Test name
Test status
Simulation time 8614288670 ps
CPU time 18.33 seconds
Started Aug 05 06:28:55 PM PDT 24
Finished Aug 05 06:29:13 PM PDT 24
Peak memory 220772 kb
Host smart-c1eebe11-dc22-4100-8f98-d6434b11a77d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3999383907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3999383907
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3050981212
Short name T985
Test name
Test status
Simulation time 68805717028 ps
CPU time 289.91 seconds
Started Aug 05 06:28:48 PM PDT 24
Finished Aug 05 06:33:38 PM PDT 24
Peak memory 253280 kb
Host smart-a907d11d-3cf7-4e4e-90aa-9b609d52396c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050981212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3050981212
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4204402386
Short name T24
Test name
Test status
Simulation time 4475525292 ps
CPU time 17.17 seconds
Started Aug 05 06:28:43 PM PDT 24
Finished Aug 05 06:29:01 PM PDT 24
Peak memory 216724 kb
Host smart-945a711c-3235-4e56-840f-64f3d95eb91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204402386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4204402386
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.74912834
Short name T328
Test name
Test status
Simulation time 10301255930 ps
CPU time 16.6 seconds
Started Aug 05 06:28:43 PM PDT 24
Finished Aug 05 06:28:59 PM PDT 24
Peak memory 216736 kb
Host smart-429d8772-4f48-45de-baba-04a45cdee7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74912834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.74912834
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2980140125
Short name T623
Test name
Test status
Simulation time 269325264 ps
CPU time 2.29 seconds
Started Aug 05 06:28:45 PM PDT 24
Finished Aug 05 06:28:47 PM PDT 24
Peak memory 216644 kb
Host smart-4f896090-cfb6-4275-a671-fa58d58371e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980140125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2980140125
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1702328964
Short name T554
Test name
Test status
Simulation time 81600473 ps
CPU time 0.79 seconds
Started Aug 05 06:28:43 PM PDT 24
Finished Aug 05 06:28:44 PM PDT 24
Peak memory 206544 kb
Host smart-90b5adde-ae1f-4a44-8e61-89affc682cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702328964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1702328964
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.159653405
Short name T377
Test name
Test status
Simulation time 417937078 ps
CPU time 2.54 seconds
Started Aug 05 06:28:43 PM PDT 24
Finished Aug 05 06:28:46 PM PDT 24
Peak memory 233076 kb
Host smart-dde758c3-fb2e-43ce-aa72-8223113b8a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159653405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.159653405
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2971748351
Short name T670
Test name
Test status
Simulation time 16117972 ps
CPU time 0.76 seconds
Started Aug 05 06:28:57 PM PDT 24
Finished Aug 05 06:28:58 PM PDT 24
Peak memory 205244 kb
Host smart-beee9cca-f211-4bb7-b660-5dc87d0c1612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971748351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2971748351
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2056698201
Short name T249
Test name
Test status
Simulation time 2584980057 ps
CPU time 13.38 seconds
Started Aug 05 06:28:48 PM PDT 24
Finished Aug 05 06:29:02 PM PDT 24
Peak memory 233192 kb
Host smart-505a94f6-8c3f-4da0-b677-955c74c03a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056698201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2056698201
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4231627923
Short name T801
Test name
Test status
Simulation time 17855511 ps
CPU time 0.76 seconds
Started Aug 05 06:28:47 PM PDT 24
Finished Aug 05 06:28:48 PM PDT 24
Peak memory 206020 kb
Host smart-7bde72d3-13f9-40a2-a907-ddcb031290c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231627923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4231627923
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1181348730
Short name T798
Test name
Test status
Simulation time 8128649795 ps
CPU time 61.61 seconds
Started Aug 05 06:28:51 PM PDT 24
Finished Aug 05 06:29:53 PM PDT 24
Peak memory 254292 kb
Host smart-99e5a7bf-e332-45c4-bd71-590a1758b947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181348730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1181348730
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2685858055
Short name T153
Test name
Test status
Simulation time 45867669613 ps
CPU time 74.02 seconds
Started Aug 05 06:29:02 PM PDT 24
Finished Aug 05 06:30:16 PM PDT 24
Peak memory 239360 kb
Host smart-583d47e0-b2f7-4fd1-ab3e-f07b3afd602e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685858055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2685858055
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.165816880
Short name T959
Test name
Test status
Simulation time 3200397006 ps
CPU time 40.67 seconds
Started Aug 05 06:28:51 PM PDT 24
Finished Aug 05 06:29:32 PM PDT 24
Peak memory 239936 kb
Host smart-e69be14f-113d-4350-a7c4-deed86bce299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165816880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.165816880
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1831707707
Short name T943
Test name
Test status
Simulation time 5788689826 ps
CPU time 7.57 seconds
Started Aug 05 06:28:47 PM PDT 24
Finished Aug 05 06:28:55 PM PDT 24
Peak memory 225044 kb
Host smart-3de89758-e264-48f1-be26-487b5ee177a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831707707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1831707707
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3788280344
Short name T954
Test name
Test status
Simulation time 30138162 ps
CPU time 2.38 seconds
Started Aug 05 06:28:49 PM PDT 24
Finished Aug 05 06:28:51 PM PDT 24
Peak memory 232036 kb
Host smart-ef0657cf-166e-437f-b848-1c1b2c1d0ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788280344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3788280344
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1404651278
Short name T263
Test name
Test status
Simulation time 250792603 ps
CPU time 3.82 seconds
Started Aug 05 06:28:49 PM PDT 24
Finished Aug 05 06:28:53 PM PDT 24
Peak memory 232304 kb
Host smart-196f85f8-db06-4178-841b-7e6f7c2a15e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404651278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1404651278
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.734134362
Short name T210
Test name
Test status
Simulation time 842277992 ps
CPU time 10.09 seconds
Started Aug 05 06:28:48 PM PDT 24
Finished Aug 05 06:28:58 PM PDT 24
Peak memory 224916 kb
Host smart-290367dd-c2ff-4d0e-a82c-e02c83757f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734134362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.734134362
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1189686997
Short name T789
Test name
Test status
Simulation time 14545739309 ps
CPU time 14.23 seconds
Started Aug 05 06:28:55 PM PDT 24
Finished Aug 05 06:29:09 PM PDT 24
Peak memory 223644 kb
Host smart-ce934e97-129b-4292-b781-1027fcfd2fb4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1189686997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1189686997
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1745013535
Short name T185
Test name
Test status
Simulation time 13883237470 ps
CPU time 104.86 seconds
Started Aug 05 06:28:56 PM PDT 24
Finished Aug 05 06:30:41 PM PDT 24
Peak memory 266412 kb
Host smart-baeb9be0-cb8a-40dd-a97c-79b90de93f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745013535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1745013535
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1542969433
Short name T667
Test name
Test status
Simulation time 1800662038 ps
CPU time 11.73 seconds
Started Aug 05 06:28:51 PM PDT 24
Finished Aug 05 06:29:03 PM PDT 24
Peak memory 216668 kb
Host smart-f38a37fd-0fd9-45aa-bc35-25cd11f9e150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542969433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1542969433
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.537679177
Short name T553
Test name
Test status
Simulation time 7992844672 ps
CPU time 14.54 seconds
Started Aug 05 06:28:55 PM PDT 24
Finished Aug 05 06:29:09 PM PDT 24
Peak memory 216724 kb
Host smart-e7e81394-9690-4b01-8a2c-e94221c3df80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537679177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.537679177
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4169206821
Short name T556
Test name
Test status
Simulation time 45103624 ps
CPU time 1 seconds
Started Aug 05 06:28:49 PM PDT 24
Finished Aug 05 06:28:50 PM PDT 24
Peak memory 207780 kb
Host smart-b8343721-bcfd-4b16-9470-8bb31902f4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169206821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4169206821
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1545576528
Short name T546
Test name
Test status
Simulation time 80920227 ps
CPU time 0.92 seconds
Started Aug 05 06:28:47 PM PDT 24
Finished Aug 05 06:28:48 PM PDT 24
Peak memory 206324 kb
Host smart-56be57f5-dd2c-47b8-9b92-ba5bd76d15a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545576528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1545576528
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.974115113
Short name T276
Test name
Test status
Simulation time 9154887145 ps
CPU time 28.49 seconds
Started Aug 05 06:28:48 PM PDT 24
Finished Aug 05 06:29:16 PM PDT 24
Peak memory 233224 kb
Host smart-3db1b3db-3f8a-411f-878c-fe164e632ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974115113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.974115113
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1221005262
Short name T640
Test name
Test status
Simulation time 13669945 ps
CPU time 0.74 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:08 PM PDT 24
Peak memory 205248 kb
Host smart-784004c8-f363-40b5-a840-e79810f88875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221005262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1221005262
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1721909209
Short name T796
Test name
Test status
Simulation time 129895950 ps
CPU time 2.5 seconds
Started Aug 05 06:29:11 PM PDT 24
Finished Aug 05 06:29:14 PM PDT 24
Peak memory 233072 kb
Host smart-1bca24c6-3e5d-4452-979d-5d6491178738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721909209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1721909209
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2056143728
Short name T769
Test name
Test status
Simulation time 17766914 ps
CPU time 0.77 seconds
Started Aug 05 06:28:57 PM PDT 24
Finished Aug 05 06:28:58 PM PDT 24
Peak memory 206324 kb
Host smart-dcae8e9b-6e19-47bc-be08-9fee2f7cd73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056143728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2056143728
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1502631533
Short name T720
Test name
Test status
Simulation time 22430582751 ps
CPU time 46.59 seconds
Started Aug 05 06:29:00 PM PDT 24
Finished Aug 05 06:29:47 PM PDT 24
Peak memory 251528 kb
Host smart-79b2e4c2-06a9-430d-bd9e-02b6d7edbceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502631533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1502631533
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2428131149
Short name T7
Test name
Test status
Simulation time 29576108640 ps
CPU time 270.73 seconds
Started Aug 05 06:29:01 PM PDT 24
Finished Aug 05 06:33:32 PM PDT 24
Peak memory 255916 kb
Host smart-c79216da-5240-42b4-b405-ef57b338ad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428131149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2428131149
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1847011529
Short name T39
Test name
Test status
Simulation time 196827790 ps
CPU time 3.65 seconds
Started Aug 05 06:29:11 PM PDT 24
Finished Aug 05 06:29:15 PM PDT 24
Peak memory 224900 kb
Host smart-2d66b0f8-dba2-4992-a332-63690df34bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847011529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1847011529
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3240058005
Short name T179
Test name
Test status
Simulation time 10045526111 ps
CPU time 39.81 seconds
Started Aug 05 06:28:59 PM PDT 24
Finished Aug 05 06:29:39 PM PDT 24
Peak memory 249632 kb
Host smart-8a44d8ed-b325-41bb-a41e-7c5359c3488d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240058005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3240058005
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.751816664
Short name T61
Test name
Test status
Simulation time 38876603 ps
CPU time 2.57 seconds
Started Aug 05 06:28:55 PM PDT 24
Finished Aug 05 06:28:58 PM PDT 24
Peak memory 233064 kb
Host smart-50ec9dc5-b8e5-4d61-8e06-bd85043844b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751816664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.751816664
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1054556677
Short name T437
Test name
Test status
Simulation time 3939787862 ps
CPU time 23.86 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:31 PM PDT 24
Peak memory 241304 kb
Host smart-bb3274ff-0d41-44bf-b206-1f363fc48fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054556677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1054556677
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1566473574
Short name T646
Test name
Test status
Simulation time 7260262215 ps
CPU time 8.72 seconds
Started Aug 05 06:28:59 PM PDT 24
Finished Aug 05 06:29:08 PM PDT 24
Peak memory 241204 kb
Host smart-d9da2697-9ccc-4ec3-b7db-e5c0b2cc3566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566473574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1566473574
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2991907780
Short name T741
Test name
Test status
Simulation time 3167075902 ps
CPU time 7.13 seconds
Started Aug 05 06:28:55 PM PDT 24
Finished Aug 05 06:29:02 PM PDT 24
Peak memory 224920 kb
Host smart-e43d70d7-7ee5-4d39-af9b-778f016cc710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991907780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2991907780
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2875572926
Short name T910
Test name
Test status
Simulation time 1554148394 ps
CPU time 5.84 seconds
Started Aug 05 06:29:02 PM PDT 24
Finished Aug 05 06:29:08 PM PDT 24
Peak memory 222008 kb
Host smart-5eab8ca6-08aa-4725-8a39-d1a656adb7d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2875572926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2875572926
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1340898237
Short name T829
Test name
Test status
Simulation time 100714719 ps
CPU time 1.1 seconds
Started Aug 05 06:28:59 PM PDT 24
Finished Aug 05 06:29:00 PM PDT 24
Peak memory 207632 kb
Host smart-3ade5928-0163-4c1f-999e-aeede0386455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340898237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1340898237
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.212677739
Short name T719
Test name
Test status
Simulation time 8383887853 ps
CPU time 21.87 seconds
Started Aug 05 06:28:55 PM PDT 24
Finished Aug 05 06:29:17 PM PDT 24
Peak memory 216788 kb
Host smart-794d91aa-9743-4c15-8ba3-7edd4a32e512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212677739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.212677739
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.487213143
Short name T785
Test name
Test status
Simulation time 22606659 ps
CPU time 0.71 seconds
Started Aug 05 06:28:54 PM PDT 24
Finished Aug 05 06:28:55 PM PDT 24
Peak memory 206104 kb
Host smart-ffee3f56-2d12-4268-8f14-31926cd4a250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487213143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.487213143
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1379353114
Short name T587
Test name
Test status
Simulation time 564522890 ps
CPU time 3.25 seconds
Started Aug 05 06:29:02 PM PDT 24
Finished Aug 05 06:29:06 PM PDT 24
Peak memory 216592 kb
Host smart-a69e0c32-1f79-4cf5-8d4e-49c2fdbd6bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379353114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1379353114
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.307664252
Short name T597
Test name
Test status
Simulation time 56556517 ps
CPU time 0.7 seconds
Started Aug 05 06:28:56 PM PDT 24
Finished Aug 05 06:28:57 PM PDT 24
Peak memory 206396 kb
Host smart-f5acb373-2e0c-4233-a090-74e29161c2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307664252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.307664252
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1082399323
Short name T604
Test name
Test status
Simulation time 47824613 ps
CPU time 2.59 seconds
Started Aug 05 06:29:00 PM PDT 24
Finished Aug 05 06:29:03 PM PDT 24
Peak memory 233120 kb
Host smart-4b9c365e-f573-480d-9272-484e1d95cc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082399323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1082399323
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3671770527
Short name T788
Test name
Test status
Simulation time 43381452 ps
CPU time 0.74 seconds
Started Aug 05 06:28:59 PM PDT 24
Finished Aug 05 06:29:00 PM PDT 24
Peak memory 205836 kb
Host smart-68a436e1-eccf-4e72-abb3-6af276d121f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671770527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3671770527
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2979521561
Short name T963
Test name
Test status
Simulation time 388376009 ps
CPU time 5.69 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:12 PM PDT 24
Peak memory 224908 kb
Host smart-ab08ebcb-8cc2-4a46-80ca-9d9ce897c368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979521561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2979521561
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3307245093
Short name T990
Test name
Test status
Simulation time 17397891 ps
CPU time 0.81 seconds
Started Aug 05 06:29:01 PM PDT 24
Finished Aug 05 06:29:02 PM PDT 24
Peak memory 206988 kb
Host smart-df4158ed-682a-4c13-8aa9-7c45b2828dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307245093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3307245093
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.844657355
Short name T44
Test name
Test status
Simulation time 6468729937 ps
CPU time 96.39 seconds
Started Aug 05 06:29:00 PM PDT 24
Finished Aug 05 06:30:37 PM PDT 24
Peak memory 256404 kb
Host smart-6b1fdb61-70c6-4c3c-a3e4-89b26c850140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844657355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.844657355
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1886876955
Short name T166
Test name
Test status
Simulation time 2771503463 ps
CPU time 68.75 seconds
Started Aug 05 06:29:03 PM PDT 24
Finished Aug 05 06:30:12 PM PDT 24
Peak memory 253928 kb
Host smart-6a9f4b96-5925-4cb7-9ac0-bd59d09d3bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886876955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1886876955
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.798334663
Short name T154
Test name
Test status
Simulation time 1011607090 ps
CPU time 12.86 seconds
Started Aug 05 06:29:00 PM PDT 24
Finished Aug 05 06:29:13 PM PDT 24
Peak memory 249476 kb
Host smart-a910d3cf-1978-4a9d-ac1a-df63f2bdf9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798334663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.798334663
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.786615259
Short name T509
Test name
Test status
Simulation time 753837816 ps
CPU time 8 seconds
Started Aug 05 06:29:00 PM PDT 24
Finished Aug 05 06:29:08 PM PDT 24
Peak memory 224928 kb
Host smart-44d03427-b26e-4701-9eec-c08181141ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786615259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.786615259
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3755007587
Short name T564
Test name
Test status
Simulation time 403882964 ps
CPU time 2.35 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:10 PM PDT 24
Peak memory 224808 kb
Host smart-64cb032f-a1f0-4b00-8fd3-c54704878d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755007587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3755007587
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3467280685
Short name T746
Test name
Test status
Simulation time 1047595860 ps
CPU time 3.57 seconds
Started Aug 05 06:28:59 PM PDT 24
Finished Aug 05 06:29:02 PM PDT 24
Peak memory 233188 kb
Host smart-378f1196-3fa8-4008-aff0-bb6ba129284b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467280685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3467280685
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3939806917
Short name T867
Test name
Test status
Simulation time 2007727147 ps
CPU time 8.16 seconds
Started Aug 05 06:29:11 PM PDT 24
Finished Aug 05 06:29:19 PM PDT 24
Peak memory 233080 kb
Host smart-28a3a1ef-9368-43da-90d9-4786ea72381d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939806917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3939806917
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1689457506
Short name T424
Test name
Test status
Simulation time 1501642686 ps
CPU time 6.77 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:13 PM PDT 24
Peak memory 220780 kb
Host smart-cbc4ac49-af3f-479e-8179-da359eb4156b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1689457506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1689457506
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1667724412
Short name T921
Test name
Test status
Simulation time 168592404 ps
CPU time 1.01 seconds
Started Aug 05 06:29:01 PM PDT 24
Finished Aug 05 06:29:02 PM PDT 24
Peak memory 207464 kb
Host smart-e702098b-3193-4218-95eb-b1adb7aa8f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667724412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1667724412
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.458260444
Short name T309
Test name
Test status
Simulation time 870129197 ps
CPU time 9.61 seconds
Started Aug 05 06:29:10 PM PDT 24
Finished Aug 05 06:29:20 PM PDT 24
Peak memory 220252 kb
Host smart-2dfce1bf-a677-46b0-8fc8-633d42250d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458260444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.458260444
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.820482646
Short name T865
Test name
Test status
Simulation time 4378344707 ps
CPU time 8.07 seconds
Started Aug 05 06:29:03 PM PDT 24
Finished Aug 05 06:29:11 PM PDT 24
Peak memory 216676 kb
Host smart-5113ec89-0a5b-465d-bd19-ed6ce6cad2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820482646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.820482646
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2595600530
Short name T354
Test name
Test status
Simulation time 59969408 ps
CPU time 1.28 seconds
Started Aug 05 06:29:01 PM PDT 24
Finished Aug 05 06:29:02 PM PDT 24
Peak memory 216676 kb
Host smart-0df36b8f-7348-4b6a-9101-568c4117cb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595600530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2595600530
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2065572806
Short name T83
Test name
Test status
Simulation time 285958872 ps
CPU time 0.87 seconds
Started Aug 05 06:29:00 PM PDT 24
Finished Aug 05 06:29:01 PM PDT 24
Peak memory 206276 kb
Host smart-3e383453-7ce2-4477-8126-5dcb1008d6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065572806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2065572806
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2169997155
Short name T820
Test name
Test status
Simulation time 449256057 ps
CPU time 3.11 seconds
Started Aug 05 06:29:00 PM PDT 24
Finished Aug 05 06:29:03 PM PDT 24
Peak memory 233148 kb
Host smart-fa1d49c2-1ab3-40d9-92a3-2cb0ea3ceeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169997155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2169997155
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.386771355
Short name T748
Test name
Test status
Simulation time 46436527 ps
CPU time 0.71 seconds
Started Aug 05 06:29:11 PM PDT 24
Finished Aug 05 06:29:12 PM PDT 24
Peak memory 205868 kb
Host smart-4fc161e5-c28f-4408-b346-2cab0f8018a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386771355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.386771355
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.61073975
Short name T142
Test name
Test status
Simulation time 698716911 ps
CPU time 3.09 seconds
Started Aug 05 06:29:08 PM PDT 24
Finished Aug 05 06:29:11 PM PDT 24
Peak memory 233048 kb
Host smart-9784dcc8-51ff-4e25-a2a6-bee61c48d516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61073975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.61073975
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1091380330
Short name T919
Test name
Test status
Simulation time 12763617 ps
CPU time 0.8 seconds
Started Aug 05 06:29:00 PM PDT 24
Finished Aug 05 06:29:01 PM PDT 24
Peak memory 206292 kb
Host smart-1ff7a10a-5910-4d5a-aa5b-e8635fcde0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091380330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1091380330
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3529662967
Short name T900
Test name
Test status
Simulation time 16169590 ps
CPU time 0.75 seconds
Started Aug 05 06:29:10 PM PDT 24
Finished Aug 05 06:29:11 PM PDT 24
Peak memory 216132 kb
Host smart-fbc8ba95-c838-4391-b5ee-b85766b364bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529662967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3529662967
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.805280656
Short name T522
Test name
Test status
Simulation time 3852326731 ps
CPU time 22.59 seconds
Started Aug 05 06:29:08 PM PDT 24
Finished Aug 05 06:29:30 PM PDT 24
Peak memory 241432 kb
Host smart-45a0aca7-dcf1-4c84-842a-a4986c1396cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805280656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.805280656
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.274426153
Short name T209
Test name
Test status
Simulation time 106525256957 ps
CPU time 313.53 seconds
Started Aug 05 06:29:08 PM PDT 24
Finished Aug 05 06:34:22 PM PDT 24
Peak memory 250772 kb
Host smart-48f9fb5a-0f9d-46dd-af5b-753e0c465222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274426153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.274426153
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4231926306
Short name T831
Test name
Test status
Simulation time 16908856121 ps
CPU time 47.07 seconds
Started Aug 05 06:29:10 PM PDT 24
Finished Aug 05 06:29:58 PM PDT 24
Peak memory 241388 kb
Host smart-6a1d929a-85cf-4559-b92d-6fc9bc14ef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231926306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4231926306
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2902814602
Short name T52
Test name
Test status
Simulation time 27742965613 ps
CPU time 66.42 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:30:14 PM PDT 24
Peak memory 249696 kb
Host smart-d6773cdb-bc4d-482e-9272-7df5d115162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902814602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2902814602
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.63737958
Short name T872
Test name
Test status
Simulation time 4910727897 ps
CPU time 10.8 seconds
Started Aug 05 06:29:03 PM PDT 24
Finished Aug 05 06:29:14 PM PDT 24
Peak memory 224924 kb
Host smart-d4f6b519-d0c7-48fc-bf83-150e7c67fa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63737958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.63737958
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3513343304
Short name T776
Test name
Test status
Simulation time 25781468826 ps
CPU time 57.38 seconds
Started Aug 05 06:29:06 PM PDT 24
Finished Aug 05 06:30:04 PM PDT 24
Peak memory 233236 kb
Host smart-c492f1f9-6440-4847-966a-8fc8253f3bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513343304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3513343304
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1424853176
Short name T761
Test name
Test status
Simulation time 1048738816 ps
CPU time 8.63 seconds
Started Aug 05 06:29:10 PM PDT 24
Finished Aug 05 06:29:19 PM PDT 24
Peak memory 224892 kb
Host smart-f81f74d0-7b8d-4dc8-941a-0e1522532499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424853176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1424853176
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1785736647
Short name T512
Test name
Test status
Simulation time 1587217164 ps
CPU time 4.31 seconds
Started Aug 05 06:29:00 PM PDT 24
Finished Aug 05 06:29:04 PM PDT 24
Peak memory 224872 kb
Host smart-c7e6dbfc-0eb2-4ca8-a723-1137d816e5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785736647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1785736647
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1260563620
Short name T710
Test name
Test status
Simulation time 11936699068 ps
CPU time 10.9 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:18 PM PDT 24
Peak memory 221732 kb
Host smart-41485c26-23e5-42b7-90b6-dede8f561875
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1260563620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1260563620
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.308614667
Short name T845
Test name
Test status
Simulation time 87688256 ps
CPU time 0.88 seconds
Started Aug 05 06:29:11 PM PDT 24
Finished Aug 05 06:29:12 PM PDT 24
Peak memory 207352 kb
Host smart-88a00ddd-e15c-4708-a2fb-a59fd9047244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308614667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.308614667
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3712317316
Short name T6
Test name
Test status
Simulation time 421962174 ps
CPU time 6.13 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:14 PM PDT 24
Peak memory 219652 kb
Host smart-92349809-dde1-4274-af29-dba8086cd761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712317316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3712317316
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1666485690
Short name T418
Test name
Test status
Simulation time 14788182 ps
CPU time 0.76 seconds
Started Aug 05 06:29:02 PM PDT 24
Finished Aug 05 06:29:02 PM PDT 24
Peak memory 206076 kb
Host smart-9bcf36c4-e944-41f3-b2df-61beb0495cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666485690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1666485690
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2580524690
Short name T871
Test name
Test status
Simulation time 484189897 ps
CPU time 2.09 seconds
Started Aug 05 06:29:02 PM PDT 24
Finished Aug 05 06:29:04 PM PDT 24
Peak memory 216604 kb
Host smart-83014b57-b515-48ab-a384-4b5697b025e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580524690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2580524690
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.480817488
Short name T998
Test name
Test status
Simulation time 54391720 ps
CPU time 0.74 seconds
Started Aug 05 06:29:03 PM PDT 24
Finished Aug 05 06:29:04 PM PDT 24
Peak memory 206348 kb
Host smart-fcdf2ad5-2a20-42dc-ae42-aab5f19be799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480817488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.480817488
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2264872802
Short name T723
Test name
Test status
Simulation time 5056161550 ps
CPU time 8.55 seconds
Started Aug 05 06:29:06 PM PDT 24
Finished Aug 05 06:29:15 PM PDT 24
Peak memory 224944 kb
Host smart-02d02529-f5dc-42a8-8268-5c88b683df2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264872802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2264872802
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.244677861
Short name T346
Test name
Test status
Simulation time 24928624 ps
CPU time 0.71 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:08 PM PDT 24
Peak memory 205828 kb
Host smart-16af93c3-8355-4958-a9fc-74edc9f98a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244677861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.244677861
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3598059429
Short name T894
Test name
Test status
Simulation time 1852343717 ps
CPU time 12.54 seconds
Started Aug 05 06:29:10 PM PDT 24
Finished Aug 05 06:29:23 PM PDT 24
Peak memory 233104 kb
Host smart-bb2a8016-c106-437e-b2b9-92ddee05e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598059429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3598059429
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.95888302
Short name T590
Test name
Test status
Simulation time 55344975 ps
CPU time 0.76 seconds
Started Aug 05 06:29:06 PM PDT 24
Finished Aug 05 06:29:07 PM PDT 24
Peak memory 207248 kb
Host smart-74f2c439-a39d-494c-8ae4-e7c84e6e51d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95888302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.95888302
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.474066123
Short name T206
Test name
Test status
Simulation time 22902487200 ps
CPU time 99.41 seconds
Started Aug 05 06:29:08 PM PDT 24
Finished Aug 05 06:30:47 PM PDT 24
Peak memory 241436 kb
Host smart-8b9ac6b8-fba3-417b-8d8f-c025b0b65713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474066123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.474066123
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3428469050
Short name T460
Test name
Test status
Simulation time 4138112554 ps
CPU time 36.91 seconds
Started Aug 05 06:29:08 PM PDT 24
Finished Aug 05 06:29:45 PM PDT 24
Peak memory 249952 kb
Host smart-c712b689-3822-447e-96c0-5dab9c249b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428469050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3428469050
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3145214412
Short name T291
Test name
Test status
Simulation time 59415543386 ps
CPU time 193.02 seconds
Started Aug 05 06:29:12 PM PDT 24
Finished Aug 05 06:32:25 PM PDT 24
Peak memory 264224 kb
Host smart-a67e1a1f-5fad-4b0a-b71a-9357245240dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145214412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3145214412
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.334860166
Short name T981
Test name
Test status
Simulation time 2048164781 ps
CPU time 5.7 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:13 PM PDT 24
Peak memory 233176 kb
Host smart-552339d7-ae84-40a2-8b53-ae21ee7f3455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334860166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.334860166
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2075179617
Short name T947
Test name
Test status
Simulation time 535693196 ps
CPU time 5.45 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:13 PM PDT 24
Peak memory 224936 kb
Host smart-665eec77-f8bc-4b95-a152-820f217be950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075179617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2075179617
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3441628455
Short name T713
Test name
Test status
Simulation time 3093803486 ps
CPU time 6.09 seconds
Started Aug 05 06:29:08 PM PDT 24
Finished Aug 05 06:29:14 PM PDT 24
Peak memory 224844 kb
Host smart-3d097f7f-1d95-48d4-9948-81d77245d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441628455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3441628455
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1271831151
Short name T672
Test name
Test status
Simulation time 49012507145 ps
CPU time 11.25 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:19 PM PDT 24
Peak memory 233180 kb
Host smart-2adf2a08-62e0-43d2-923d-8f49390e41f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271831151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1271831151
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.538419775
Short name T939
Test name
Test status
Simulation time 2154566343 ps
CPU time 9.49 seconds
Started Aug 05 06:29:11 PM PDT 24
Finished Aug 05 06:29:21 PM PDT 24
Peak memory 240244 kb
Host smart-201aa2f6-2fee-4009-a548-a0d966069e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538419775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.538419775
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.787893180
Short name T892
Test name
Test status
Simulation time 1938291650 ps
CPU time 5.42 seconds
Started Aug 05 06:29:12 PM PDT 24
Finished Aug 05 06:29:17 PM PDT 24
Peak memory 220500 kb
Host smart-ae7a298f-2d40-41fd-9488-1404dcc52744
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=787893180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.787893180
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1929109451
Short name T146
Test name
Test status
Simulation time 63190748444 ps
CPU time 250.65 seconds
Started Aug 05 06:29:09 PM PDT 24
Finished Aug 05 06:33:20 PM PDT 24
Peak memory 252256 kb
Host smart-bd29a9d1-27d4-4973-a21a-4c8e10d4fa52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929109451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1929109451
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2830968641
Short name T383
Test name
Test status
Simulation time 445539566 ps
CPU time 3.79 seconds
Started Aug 05 06:29:08 PM PDT 24
Finished Aug 05 06:29:12 PM PDT 24
Peak memory 216604 kb
Host smart-a66ad78c-a7e3-4ed8-8d88-f647ad56bb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830968641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2830968641
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4227462921
Short name T913
Test name
Test status
Simulation time 4937057353 ps
CPU time 15.6 seconds
Started Aug 05 06:29:09 PM PDT 24
Finished Aug 05 06:29:25 PM PDT 24
Peak memory 216660 kb
Host smart-807f677b-2c6e-4654-8352-f861bb8dad49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227462921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4227462921
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.758932234
Short name T756
Test name
Test status
Simulation time 48259582 ps
CPU time 0.83 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:08 PM PDT 24
Peak memory 206324 kb
Host smart-b0a4aea0-cb46-41cf-82fe-eaa2dfd8c61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758932234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.758932234
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3696937545
Short name T839
Test name
Test status
Simulation time 13025192 ps
CPU time 0.67 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:08 PM PDT 24
Peak memory 206056 kb
Host smart-5fc74f79-b787-44e0-b947-8dd1f22e3e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696937545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3696937545
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.253996556
Short name T244
Test name
Test status
Simulation time 414253162 ps
CPU time 2.67 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:09 PM PDT 24
Peak memory 233108 kb
Host smart-83f218fa-ac2f-4b0d-8b71-2ef0c2592e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253996556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.253996556
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1225671435
Short name T738
Test name
Test status
Simulation time 47085651 ps
CPU time 0.72 seconds
Started Aug 05 06:29:13 PM PDT 24
Finished Aug 05 06:29:14 PM PDT 24
Peak memory 205820 kb
Host smart-10d1b733-d2d9-4ada-9833-b767827b9ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225671435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1225671435
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3926300911
Short name T744
Test name
Test status
Simulation time 253686486 ps
CPU time 2.48 seconds
Started Aug 05 06:29:14 PM PDT 24
Finished Aug 05 06:29:17 PM PDT 24
Peak memory 233236 kb
Host smart-6cb693f7-dad5-4e24-8527-58b576b2e049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926300911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3926300911
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.680158557
Short name T327
Test name
Test status
Simulation time 14858943 ps
CPU time 0.79 seconds
Started Aug 05 06:29:11 PM PDT 24
Finished Aug 05 06:29:12 PM PDT 24
Peak memory 207336 kb
Host smart-31531a6e-2d7c-4591-87d5-066ed9f0ac3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680158557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.680158557
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3886969573
Short name T190
Test name
Test status
Simulation time 75127565333 ps
CPU time 267.69 seconds
Started Aug 05 06:29:16 PM PDT 24
Finished Aug 05 06:33:44 PM PDT 24
Peak memory 257792 kb
Host smart-43bdf59e-cb7b-4ac2-9c84-be7560ea3171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886969573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3886969573
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2548573157
Short name T302
Test name
Test status
Simulation time 1566665994 ps
CPU time 7.37 seconds
Started Aug 05 06:29:13 PM PDT 24
Finished Aug 05 06:29:20 PM PDT 24
Peak memory 219716 kb
Host smart-c52f5950-52ac-496f-8299-9b890c142644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548573157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2548573157
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2787523893
Short name T762
Test name
Test status
Simulation time 162187305 ps
CPU time 4.93 seconds
Started Aug 05 06:29:13 PM PDT 24
Finished Aug 05 06:29:18 PM PDT 24
Peak memory 225000 kb
Host smart-33f32e68-30ff-4850-a27f-4936f94148a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787523893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2787523893
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2449032891
Short name T362
Test name
Test status
Simulation time 14328616 ps
CPU time 0.78 seconds
Started Aug 05 06:29:14 PM PDT 24
Finished Aug 05 06:29:14 PM PDT 24
Peak memory 216148 kb
Host smart-0365f5a4-9fe8-403b-9d8f-03c4399846bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449032891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2449032891
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3256656409
Short name T384
Test name
Test status
Simulation time 2816417199 ps
CPU time 8.17 seconds
Started Aug 05 06:29:18 PM PDT 24
Finished Aug 05 06:29:26 PM PDT 24
Peak memory 224932 kb
Host smart-83a25017-613e-4e78-8d60-51bd150c13ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256656409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3256656409
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1204203396
Short name T933
Test name
Test status
Simulation time 80836342 ps
CPU time 2.36 seconds
Started Aug 05 06:29:12 PM PDT 24
Finished Aug 05 06:29:14 PM PDT 24
Peak memory 223232 kb
Host smart-d5acb11e-22c3-4726-84d1-f2fb10aaf97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204203396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1204203396
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.503399950
Short name T222
Test name
Test status
Simulation time 6136038630 ps
CPU time 10.43 seconds
Started Aug 05 06:29:11 PM PDT 24
Finished Aug 05 06:29:22 PM PDT 24
Peak memory 233240 kb
Host smart-c3dd01cd-0de7-4f83-9172-d890a140639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503399950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.503399950
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.341693859
Short name T958
Test name
Test status
Simulation time 14336229949 ps
CPU time 17.36 seconds
Started Aug 05 06:29:07 PM PDT 24
Finished Aug 05 06:29:24 PM PDT 24
Peak memory 235776 kb
Host smart-5c119856-954b-47ff-85d5-2c0409e34101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341693859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.341693859
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1241657848
Short name T136
Test name
Test status
Simulation time 629007116 ps
CPU time 6.83 seconds
Started Aug 05 06:29:18 PM PDT 24
Finished Aug 05 06:29:25 PM PDT 24
Peak memory 221044 kb
Host smart-d7a3ae2c-4b37-4cd0-abd3-4fdcdd0c5254
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1241657848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1241657848
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1177046359
Short name T148
Test name
Test status
Simulation time 6843829578 ps
CPU time 79.46 seconds
Started Aug 05 06:29:13 PM PDT 24
Finished Aug 05 06:30:33 PM PDT 24
Peak memory 241392 kb
Host smart-91ffccfc-4b83-435f-8c55-b0c692a343b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177046359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1177046359
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3711361986
Short name T323
Test name
Test status
Simulation time 77764935 ps
CPU time 0.73 seconds
Started Aug 05 06:29:08 PM PDT 24
Finished Aug 05 06:29:09 PM PDT 24
Peak memory 206136 kb
Host smart-50d6a09d-f2a3-44fc-8290-df30135af990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711361986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3711361986
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2442452930
Short name T715
Test name
Test status
Simulation time 3146556168 ps
CPU time 10.04 seconds
Started Aug 05 06:29:05 PM PDT 24
Finished Aug 05 06:29:15 PM PDT 24
Peak memory 216716 kb
Host smart-f3376925-3239-4aad-bc46-7ea36f3b979f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442452930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2442452930
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2336153394
Short name T859
Test name
Test status
Simulation time 200280308 ps
CPU time 1.21 seconds
Started Aug 05 06:29:11 PM PDT 24
Finished Aug 05 06:29:12 PM PDT 24
Peak memory 208288 kb
Host smart-3513e3c4-10e2-4e96-9b39-8e3a4377a67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336153394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2336153394
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3159736198
Short name T319
Test name
Test status
Simulation time 112136438 ps
CPU time 0.96 seconds
Started Aug 05 06:29:11 PM PDT 24
Finished Aug 05 06:29:12 PM PDT 24
Peak memory 206868 kb
Host smart-ee666fcc-1f19-44d1-82f1-9d7f16188070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159736198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3159736198
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3452593698
Short name T974
Test name
Test status
Simulation time 256292814 ps
CPU time 2.64 seconds
Started Aug 05 06:29:15 PM PDT 24
Finished Aug 05 06:29:18 PM PDT 24
Peak memory 218296 kb
Host smart-b672939d-815e-4bcc-add9-88d62d178ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452593698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3452593698
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1677093904
Short name T1007
Test name
Test status
Simulation time 42376119 ps
CPU time 0.73 seconds
Started Aug 05 06:29:18 PM PDT 24
Finished Aug 05 06:29:19 PM PDT 24
Peak memory 205792 kb
Host smart-bb9fc958-4b98-4646-8fa3-8f45dd9ec671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677093904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1677093904
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2723231274
Short name T740
Test name
Test status
Simulation time 330656568 ps
CPU time 4.41 seconds
Started Aug 05 06:29:13 PM PDT 24
Finished Aug 05 06:29:17 PM PDT 24
Peak memory 224776 kb
Host smart-b40480e5-9023-4587-8cfd-d8c2f6e45491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723231274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2723231274
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.4045359684
Short name T441
Test name
Test status
Simulation time 53335018 ps
CPU time 0.78 seconds
Started Aug 05 06:29:12 PM PDT 24
Finished Aug 05 06:29:13 PM PDT 24
Peak memory 206968 kb
Host smart-dba56aa2-b4b4-409e-b763-0992fcb8e9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045359684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4045359684
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1574317322
Short name T735
Test name
Test status
Simulation time 18239630124 ps
CPU time 86.45 seconds
Started Aug 05 06:29:13 PM PDT 24
Finished Aug 05 06:30:39 PM PDT 24
Peak memory 249604 kb
Host smart-3a20f8d0-a7ca-45e5-b3ca-8621552d7c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574317322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1574317322
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4014407797
Short name T995
Test name
Test status
Simulation time 5080331853 ps
CPU time 81.29 seconds
Started Aug 05 06:29:14 PM PDT 24
Finished Aug 05 06:30:35 PM PDT 24
Peak memory 254120 kb
Host smart-0adfe0e2-23d6-47a7-9738-a33f5c1ae05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014407797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4014407797
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2910782070
Short name T305
Test name
Test status
Simulation time 30750937614 ps
CPU time 48.85 seconds
Started Aug 05 06:29:12 PM PDT 24
Finished Aug 05 06:30:01 PM PDT 24
Peak memory 218108 kb
Host smart-acf0c5a7-66cb-4806-86b1-db043434e08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910782070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2910782070
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1766195767
Short name T140
Test name
Test status
Simulation time 273348658 ps
CPU time 6.4 seconds
Started Aug 05 06:29:11 PM PDT 24
Finished Aug 05 06:29:18 PM PDT 24
Peak memory 224940 kb
Host smart-b07e6311-c6c8-4730-84ab-f615502e0850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766195767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1766195767
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2261206279
Short name T220
Test name
Test status
Simulation time 1459017863 ps
CPU time 29.42 seconds
Started Aug 05 06:29:15 PM PDT 24
Finished Aug 05 06:29:44 PM PDT 24
Peak memory 250892 kb
Host smart-d30e7794-5c01-4be6-8179-aea4ffd0d571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261206279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2261206279
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2539374220
Short name T397
Test name
Test status
Simulation time 6119455614 ps
CPU time 11.4 seconds
Started Aug 05 06:29:14 PM PDT 24
Finished Aug 05 06:29:26 PM PDT 24
Peak memory 224972 kb
Host smart-37471adf-a301-4f8f-84a0-a77df3b5708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539374220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2539374220
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2603995170
Short name T442
Test name
Test status
Simulation time 1723339920 ps
CPU time 12.26 seconds
Started Aug 05 06:29:13 PM PDT 24
Finished Aug 05 06:29:26 PM PDT 24
Peak memory 233156 kb
Host smart-88eccf29-a52e-41ad-b4b5-ba4518673bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603995170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2603995170
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3086028634
Short name T261
Test name
Test status
Simulation time 2503715436 ps
CPU time 6.86 seconds
Started Aug 05 06:29:12 PM PDT 24
Finished Aug 05 06:29:19 PM PDT 24
Peak memory 224944 kb
Host smart-3cf57272-266e-48c1-b47e-8a8f5ea97f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086028634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3086028634
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1971873094
Short name T531
Test name
Test status
Simulation time 365332192 ps
CPU time 3.83 seconds
Started Aug 05 06:29:13 PM PDT 24
Finished Aug 05 06:29:17 PM PDT 24
Peak memory 233104 kb
Host smart-2b306a91-7de4-4909-a0a4-66a2e421a1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971873094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1971873094
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1359229241
Short name T422
Test name
Test status
Simulation time 849347926 ps
CPU time 3.74 seconds
Started Aug 05 06:29:18 PM PDT 24
Finished Aug 05 06:29:22 PM PDT 24
Peak memory 223188 kb
Host smart-bd5c1fce-43dd-4fc4-945a-d46e5a26edac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1359229241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1359229241
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.785369831
Short name T227
Test name
Test status
Simulation time 178483547407 ps
CPU time 439.1 seconds
Started Aug 05 06:29:16 PM PDT 24
Finished Aug 05 06:36:35 PM PDT 24
Peak memory 257188 kb
Host smart-9a12ed72-de62-47f8-a257-3325849a3a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785369831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.785369831
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4092211964
Short name T1000
Test name
Test status
Simulation time 43865803474 ps
CPU time 34.07 seconds
Started Aug 05 06:29:13 PM PDT 24
Finished Aug 05 06:29:47 PM PDT 24
Peak memory 216748 kb
Host smart-8c2b8c3f-cb8b-4322-96f9-4fb13d7f2b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092211964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4092211964
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1076535757
Short name T340
Test name
Test status
Simulation time 1732146507 ps
CPU time 10.17 seconds
Started Aug 05 06:29:15 PM PDT 24
Finished Aug 05 06:29:25 PM PDT 24
Peak memory 216616 kb
Host smart-a5848497-8919-47aa-8d5e-4e40dd540d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076535757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1076535757
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.563580307
Short name T927
Test name
Test status
Simulation time 210939626 ps
CPU time 1.18 seconds
Started Aug 05 06:29:14 PM PDT 24
Finished Aug 05 06:29:15 PM PDT 24
Peak memory 216756 kb
Host smart-9508303f-22f4-43b7-b884-1ff9c8977c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563580307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.563580307
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.602610426
Short name T763
Test name
Test status
Simulation time 177436443 ps
CPU time 0.87 seconds
Started Aug 05 06:29:13 PM PDT 24
Finished Aug 05 06:29:14 PM PDT 24
Peak memory 206332 kb
Host smart-68172df0-2c50-4100-9d5c-70ae0cb17b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602610426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.602610426
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.748408616
Short name T709
Test name
Test status
Simulation time 5250066949 ps
CPU time 22.79 seconds
Started Aug 05 06:29:14 PM PDT 24
Finished Aug 05 06:29:37 PM PDT 24
Peak memory 241320 kb
Host smart-320a8764-6036-46fc-9269-39ec743da068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748408616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.748408616
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1089559171
Short name T317
Test name
Test status
Simulation time 14459143 ps
CPU time 0.72 seconds
Started Aug 05 06:27:32 PM PDT 24
Finished Aug 05 06:27:33 PM PDT 24
Peak memory 205272 kb
Host smart-2a78ba2c-285c-4914-bf70-9836b406492f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089559171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
089559171
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3742518906
Short name T790
Test name
Test status
Simulation time 399953308 ps
CPU time 6.89 seconds
Started Aug 05 06:27:36 PM PDT 24
Finished Aug 05 06:27:43 PM PDT 24
Peak memory 224796 kb
Host smart-3e15c48c-c587-42d3-aa89-ae3d4ece09e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742518906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3742518906
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2316363890
Short name T454
Test name
Test status
Simulation time 14873076 ps
CPU time 0.78 seconds
Started Aug 05 06:27:33 PM PDT 24
Finished Aug 05 06:27:34 PM PDT 24
Peak memory 206996 kb
Host smart-b8bc2683-1755-4018-9537-060edd6c2fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316363890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2316363890
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3643994385
Short name T896
Test name
Test status
Simulation time 7355723748 ps
CPU time 67.39 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:28:41 PM PDT 24
Peak memory 249576 kb
Host smart-a5f5de34-14c2-4ae3-8900-547f39a2cd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643994385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3643994385
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.86991128
Short name T289
Test name
Test status
Simulation time 38466369212 ps
CPU time 132.85 seconds
Started Aug 05 06:27:36 PM PDT 24
Finished Aug 05 06:29:49 PM PDT 24
Peak memory 233264 kb
Host smart-a35382a2-f3df-4145-9a72-8e5fd34042c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86991128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.86991128
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.410030537
Short name T260
Test name
Test status
Simulation time 10877544822 ps
CPU time 88.21 seconds
Started Aug 05 06:27:36 PM PDT 24
Finished Aug 05 06:29:05 PM PDT 24
Peak memory 253392 kb
Host smart-0c12b859-ced7-44d4-8159-342c7309d49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410030537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
410030537
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2781045749
Short name T885
Test name
Test status
Simulation time 745454889 ps
CPU time 15.11 seconds
Started Aug 05 06:27:37 PM PDT 24
Finished Aug 05 06:27:52 PM PDT 24
Peak memory 241372 kb
Host smart-46fe04f2-2707-47ae-90b4-4f134426c940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781045749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2781045749
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1698404784
Short name T316
Test name
Test status
Simulation time 35562449 ps
CPU time 0.74 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:27:35 PM PDT 24
Peak memory 216136 kb
Host smart-8efda098-da14-4fc2-81c5-478af7e02a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698404784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1698404784
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1960444926
Short name T267
Test name
Test status
Simulation time 657672595 ps
CPU time 4.96 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:27:40 PM PDT 24
Peak memory 228096 kb
Host smart-8cc930f8-50c9-435c-aec1-d8aaa8435275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960444926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1960444926
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.322552802
Short name T76
Test name
Test status
Simulation time 404215028 ps
CPU time 2.27 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:27:37 PM PDT 24
Peak memory 224572 kb
Host smart-9a6dff1d-e4c2-4b9b-8ce4-b94b7ff8ef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322552802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.322552802
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2816082558
Short name T860
Test name
Test status
Simulation time 809017293 ps
CPU time 5.5 seconds
Started Aug 05 06:27:36 PM PDT 24
Finished Aug 05 06:27:41 PM PDT 24
Peak memory 233168 kb
Host smart-a00fa498-eed9-4e02-8957-d91cf893571d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816082558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2816082558
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1434613239
Short name T242
Test name
Test status
Simulation time 646104372 ps
CPU time 5.55 seconds
Started Aug 05 06:27:32 PM PDT 24
Finished Aug 05 06:27:38 PM PDT 24
Peak memory 224872 kb
Host smart-2d5d417e-9662-4d87-aeae-fadf6f33ae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434613239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1434613239
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2739269969
Short name T141
Test name
Test status
Simulation time 1062482212 ps
CPU time 5.33 seconds
Started Aug 05 06:27:33 PM PDT 24
Finished Aug 05 06:27:38 PM PDT 24
Peak memory 223096 kb
Host smart-284e451a-64a0-44fe-b61b-4a017de1c913
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2739269969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2739269969
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3970351887
Short name T72
Test name
Test status
Simulation time 591337864 ps
CPU time 1.24 seconds
Started Aug 05 06:27:36 PM PDT 24
Finished Aug 05 06:27:38 PM PDT 24
Peak memory 236428 kb
Host smart-58be273f-5680-4588-bedc-9749413574a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970351887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3970351887
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3526340638
Short name T282
Test name
Test status
Simulation time 8426719484 ps
CPU time 121.26 seconds
Started Aug 05 06:27:33 PM PDT 24
Finished Aug 05 06:29:34 PM PDT 24
Peak memory 256960 kb
Host smart-0b79cae2-6ebc-42e7-b006-bff34df37b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526340638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3526340638
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1354784336
Short name T665
Test name
Test status
Simulation time 2798035793 ps
CPU time 22.59 seconds
Started Aug 05 06:27:35 PM PDT 24
Finished Aug 05 06:27:58 PM PDT 24
Peak memory 217112 kb
Host smart-55d3ba41-4357-47af-b4c8-b98ad75aed98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354784336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1354784336
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2023663213
Short name T458
Test name
Test status
Simulation time 13704643 ps
CPU time 0.74 seconds
Started Aug 05 06:27:33 PM PDT 24
Finished Aug 05 06:27:34 PM PDT 24
Peak memory 206076 kb
Host smart-094e6a81-e4d5-453c-b9f3-a4c183db4b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023663213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2023663213
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1301859823
Short name T472
Test name
Test status
Simulation time 56410855 ps
CPU time 0.86 seconds
Started Aug 05 06:27:33 PM PDT 24
Finished Aug 05 06:27:34 PM PDT 24
Peak memory 207048 kb
Host smart-7aa23fd4-7f18-4e69-9834-2c97f8fe3b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301859823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1301859823
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1634625223
Short name T315
Test name
Test status
Simulation time 24167576 ps
CPU time 0.73 seconds
Started Aug 05 06:27:35 PM PDT 24
Finished Aug 05 06:27:36 PM PDT 24
Peak memory 206448 kb
Host smart-c114559f-908a-4cd2-a977-b413886c8441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634625223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1634625223
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1869549705
Short name T485
Test name
Test status
Simulation time 75410514 ps
CPU time 2.15 seconds
Started Aug 05 06:27:40 PM PDT 24
Finished Aug 05 06:27:42 PM PDT 24
Peak memory 223988 kb
Host smart-beb1520f-bd7a-4dda-8773-b761a315cf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869549705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1869549705
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3926934917
Short name T821
Test name
Test status
Simulation time 146461853 ps
CPU time 0.73 seconds
Started Aug 05 06:29:17 PM PDT 24
Finished Aug 05 06:29:17 PM PDT 24
Peak memory 205784 kb
Host smart-e1c965f8-81e4-4a21-bdbd-c124253438a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926934917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3926934917
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2676331917
Short name T641
Test name
Test status
Simulation time 431578453 ps
CPU time 3.79 seconds
Started Aug 05 06:29:19 PM PDT 24
Finished Aug 05 06:29:23 PM PDT 24
Peak memory 233168 kb
Host smart-4be1a760-78ec-4752-a7a8-cf0b1694c17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676331917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2676331917
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4131105635
Short name T321
Test name
Test status
Simulation time 20552938 ps
CPU time 0.79 seconds
Started Aug 05 06:29:15 PM PDT 24
Finished Aug 05 06:29:16 PM PDT 24
Peak memory 206988 kb
Host smart-8f5c07a5-137a-4606-a5fe-3681ff7c595a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131105635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4131105635
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.601994502
Short name T378
Test name
Test status
Simulation time 61170035 ps
CPU time 0.81 seconds
Started Aug 05 06:29:18 PM PDT 24
Finished Aug 05 06:29:19 PM PDT 24
Peak memory 216164 kb
Host smart-5d81424d-2984-4268-8501-7001a058d9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601994502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.601994502
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2764468045
Short name T230
Test name
Test status
Simulation time 342882219092 ps
CPU time 279.5 seconds
Started Aug 05 06:29:19 PM PDT 24
Finished Aug 05 06:33:59 PM PDT 24
Peak memory 251724 kb
Host smart-39244998-1f6e-40d5-be63-41c2694c3ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764468045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2764468045
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.108993006
Short name T516
Test name
Test status
Simulation time 17786135625 ps
CPU time 161.79 seconds
Started Aug 05 06:29:17 PM PDT 24
Finished Aug 05 06:31:59 PM PDT 24
Peak memory 250612 kb
Host smart-4170cf81-38b1-4592-911c-aee29e9ef8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108993006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.108993006
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2766695875
Short name T36
Test name
Test status
Simulation time 224209507 ps
CPU time 5.54 seconds
Started Aug 05 06:29:20 PM PDT 24
Finished Aug 05 06:29:26 PM PDT 24
Peak memory 224972 kb
Host smart-e8b62e03-7ff6-4b38-a1b0-40ed6808d633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766695875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2766695875
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1470224651
Short name T387
Test name
Test status
Simulation time 56413240 ps
CPU time 0.81 seconds
Started Aug 05 06:29:18 PM PDT 24
Finished Aug 05 06:29:19 PM PDT 24
Peak memory 216112 kb
Host smart-42c03de1-381b-400a-88ad-6bb2c3b716d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470224651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1470224651
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2552219337
Short name T358
Test name
Test status
Simulation time 29041991 ps
CPU time 1.96 seconds
Started Aug 05 06:29:20 PM PDT 24
Finished Aug 05 06:29:22 PM PDT 24
Peak memory 223356 kb
Host smart-14f4d85b-e67e-4e8a-b2aa-1df09cad8ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552219337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2552219337
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2885286428
Short name T428
Test name
Test status
Simulation time 214193783 ps
CPU time 2.23 seconds
Started Aug 05 06:29:19 PM PDT 24
Finished Aug 05 06:29:21 PM PDT 24
Peak memory 224396 kb
Host smart-71a147dd-0588-4017-b4cb-2d5a9ac9ae66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885286428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2885286428
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3642905253
Short name T551
Test name
Test status
Simulation time 9379842626 ps
CPU time 18.01 seconds
Started Aug 05 06:29:17 PM PDT 24
Finished Aug 05 06:29:35 PM PDT 24
Peak memory 224968 kb
Host smart-d17712fe-1278-4e99-bb47-2a5ca307e50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642905253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3642905253
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2260221879
Short name T236
Test name
Test status
Simulation time 1095111794 ps
CPU time 5.53 seconds
Started Aug 05 06:29:20 PM PDT 24
Finished Aug 05 06:29:25 PM PDT 24
Peak memory 233104 kb
Host smart-a0133f07-8b61-4df9-8198-c3db86e52b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260221879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2260221879
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.683963419
Short name T862
Test name
Test status
Simulation time 5616864237 ps
CPU time 7.18 seconds
Started Aug 05 06:29:19 PM PDT 24
Finished Aug 05 06:29:26 PM PDT 24
Peak memory 220668 kb
Host smart-f8b3a2b9-60ca-45d5-81bc-6b7dfbc4ee00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=683963419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.683963419
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3747457076
Short name T164
Test name
Test status
Simulation time 156050739 ps
CPU time 0.92 seconds
Started Aug 05 06:29:20 PM PDT 24
Finished Aug 05 06:29:21 PM PDT 24
Peak memory 207912 kb
Host smart-055b9994-6f32-4b55-ac03-22c0486b6dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747457076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3747457076
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2738857097
Short name T435
Test name
Test status
Simulation time 2271666733 ps
CPU time 13.32 seconds
Started Aug 05 06:29:15 PM PDT 24
Finished Aug 05 06:29:29 PM PDT 24
Peak memory 216732 kb
Host smart-6bfce53d-3d69-4a2b-ad9d-b3d9a4a0b75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738857097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2738857097
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2938849710
Short name T372
Test name
Test status
Simulation time 2154012996 ps
CPU time 9.47 seconds
Started Aug 05 06:29:15 PM PDT 24
Finished Aug 05 06:29:24 PM PDT 24
Peak memory 216768 kb
Host smart-80dd90c1-9852-4abd-b5fe-a6fab10470b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938849710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2938849710
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3685760841
Short name T483
Test name
Test status
Simulation time 166989981 ps
CPU time 1.9 seconds
Started Aug 05 06:29:15 PM PDT 24
Finished Aug 05 06:29:17 PM PDT 24
Peak memory 216652 kb
Host smart-f87e0170-0335-49f6-9871-990ce8c5a791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685760841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3685760841
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.287013268
Short name T721
Test name
Test status
Simulation time 62345739 ps
CPU time 0.85 seconds
Started Aug 05 06:29:15 PM PDT 24
Finished Aug 05 06:29:16 PM PDT 24
Peak memory 206332 kb
Host smart-2ecbbf36-a32b-419c-8229-957379ad30ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287013268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.287013268
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.940648811
Short name T937
Test name
Test status
Simulation time 24963990588 ps
CPU time 12.84 seconds
Started Aug 05 06:29:20 PM PDT 24
Finished Aug 05 06:29:33 PM PDT 24
Peak memory 225028 kb
Host smart-4d259d03-8584-4267-af73-a7c8893f99b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940648811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.940648811
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1507992760
Short name T488
Test name
Test status
Simulation time 37646655 ps
CPU time 0.73 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:29:25 PM PDT 24
Peak memory 205268 kb
Host smart-e0f70434-fb43-428d-9ffa-a4b58a686acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507992760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1507992760
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.57073528
Short name T621
Test name
Test status
Simulation time 18200336052 ps
CPU time 28.44 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:29:52 PM PDT 24
Peak memory 233212 kb
Host smart-89cc4c3f-3253-4cb3-928f-181702b89feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57073528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.57073528
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.14044025
Short name T957
Test name
Test status
Simulation time 72049315 ps
CPU time 0.77 seconds
Started Aug 05 06:29:20 PM PDT 24
Finished Aug 05 06:29:21 PM PDT 24
Peak memory 206284 kb
Host smart-733030eb-81e2-4f62-9e32-caf923484a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14044025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.14044025
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1906856257
Short name T817
Test name
Test status
Simulation time 5523705344 ps
CPU time 32.48 seconds
Started Aug 05 06:29:25 PM PDT 24
Finished Aug 05 06:29:57 PM PDT 24
Peak memory 251240 kb
Host smart-7365af7a-69ed-4324-b437-937b53244f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906856257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1906856257
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1897890411
Short name T295
Test name
Test status
Simulation time 340555467596 ps
CPU time 751.1 seconds
Started Aug 05 06:29:25 PM PDT 24
Finished Aug 05 06:41:57 PM PDT 24
Peak memory 264252 kb
Host smart-9c5744b6-50a5-41bf-9ebd-4615e5875dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897890411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1897890411
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3477732460
Short name T589
Test name
Test status
Simulation time 2018560991 ps
CPU time 16.4 seconds
Started Aug 05 06:29:25 PM PDT 24
Finished Aug 05 06:29:42 PM PDT 24
Peak memory 238896 kb
Host smart-5b67a3cc-e835-4175-832a-f9f21c401c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477732460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3477732460
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.328555549
Short name T466
Test name
Test status
Simulation time 204643014 ps
CPU time 2.6 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:29:27 PM PDT 24
Peak memory 233140 kb
Host smart-7076a5c8-4a68-42a6-84a7-4ffa96a73966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328555549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.328555549
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.4230925627
Short name T993
Test name
Test status
Simulation time 20667543265 ps
CPU time 87.38 seconds
Started Aug 05 06:29:25 PM PDT 24
Finished Aug 05 06:30:52 PM PDT 24
Peak memory 239604 kb
Host smart-1f1b350e-6b5f-4c1e-8968-0fd3c6099c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230925627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.4230925627
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.293304805
Short name T253
Test name
Test status
Simulation time 1058993558 ps
CPU time 9.21 seconds
Started Aug 05 06:29:17 PM PDT 24
Finished Aug 05 06:29:27 PM PDT 24
Peak memory 224924 kb
Host smart-8fe46931-ae07-4250-b675-a2b2bd219e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293304805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.293304805
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1778283042
Short name T87
Test name
Test status
Simulation time 252933032 ps
CPU time 8.11 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:29:32 PM PDT 24
Peak memory 235708 kb
Host smart-06ba325b-3f33-4acd-ac4f-a0c1dd7953b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778283042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1778283042
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.928794323
Short name T497
Test name
Test status
Simulation time 21452504137 ps
CPU time 18.79 seconds
Started Aug 05 06:29:19 PM PDT 24
Finished Aug 05 06:29:38 PM PDT 24
Peak memory 233196 kb
Host smart-57388c9f-de5b-4a87-8f66-3bf8a38b9590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928794323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.928794323
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2989379662
Short name T2
Test name
Test status
Simulation time 3255333768 ps
CPU time 4.51 seconds
Started Aug 05 06:29:17 PM PDT 24
Finished Aug 05 06:29:22 PM PDT 24
Peak memory 224984 kb
Host smart-412fc265-826f-4cc1-97f4-32aef7578b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989379662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2989379662
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3569916321
Short name T555
Test name
Test status
Simulation time 2737361688 ps
CPU time 10.57 seconds
Started Aug 05 06:29:27 PM PDT 24
Finished Aug 05 06:29:37 PM PDT 24
Peak memory 222780 kb
Host smart-99ae97f8-fba3-43fe-8d27-b875640311f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3569916321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3569916321
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3314106222
Short name T254
Test name
Test status
Simulation time 91055995933 ps
CPU time 614.52 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:39:39 PM PDT 24
Peak memory 266048 kb
Host smart-0339e08f-00ff-4af2-beab-5c6a96d83a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314106222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3314106222
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1289658304
Short name T455
Test name
Test status
Simulation time 81367442 ps
CPU time 0.73 seconds
Started Aug 05 06:29:18 PM PDT 24
Finished Aug 05 06:29:19 PM PDT 24
Peak memory 206104 kb
Host smart-7b174ef8-f03f-4161-a867-8a97ac54833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289658304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1289658304
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3002311843
Short name T310
Test name
Test status
Simulation time 2594985297 ps
CPU time 12.01 seconds
Started Aug 05 06:29:19 PM PDT 24
Finished Aug 05 06:29:31 PM PDT 24
Peak memory 216792 kb
Host smart-24039435-b7c3-4549-aa42-57869b08bd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002311843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3002311843
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2356520941
Short name T759
Test name
Test status
Simulation time 882797533 ps
CPU time 3.23 seconds
Started Aug 05 06:29:19 PM PDT 24
Finished Aug 05 06:29:22 PM PDT 24
Peak memory 216668 kb
Host smart-a966a1d7-e32b-4e1e-941a-f64649927f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356520941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2356520941
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3472713576
Short name T778
Test name
Test status
Simulation time 204486314 ps
CPU time 0.83 seconds
Started Aug 05 06:29:17 PM PDT 24
Finished Aug 05 06:29:18 PM PDT 24
Peak memory 206360 kb
Host smart-1132674c-6a4c-450b-ae07-84ce2b56642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472713576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3472713576
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.867735007
Short name T977
Test name
Test status
Simulation time 480381350 ps
CPU time 4.85 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:29:29 PM PDT 24
Peak memory 241224 kb
Host smart-c690d01c-2d28-458a-800d-c5e6d107967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867735007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.867735007
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.291743529
Short name T863
Test name
Test status
Simulation time 22464877 ps
CPU time 0.75 seconds
Started Aug 05 06:29:29 PM PDT 24
Finished Aug 05 06:29:30 PM PDT 24
Peak memory 205200 kb
Host smart-73d50b49-acc3-4e57-ab11-14c52452e0db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291743529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.291743529
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1905542292
Short name T391
Test name
Test status
Simulation time 1549572905 ps
CPU time 5.53 seconds
Started Aug 05 06:29:25 PM PDT 24
Finished Aug 05 06:29:30 PM PDT 24
Peak memory 233012 kb
Host smart-28f38f20-22ea-4960-bfc2-60f681471121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905542292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1905542292
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3103002421
Short name T406
Test name
Test status
Simulation time 57556785 ps
CPU time 0.81 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:29:25 PM PDT 24
Peak memory 205952 kb
Host smart-f456953e-03f4-4f0a-bdb1-2e085c637b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103002421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3103002421
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1941176591
Short name T225
Test name
Test status
Simulation time 104769890814 ps
CPU time 71.1 seconds
Started Aug 05 06:29:30 PM PDT 24
Finished Aug 05 06:30:41 PM PDT 24
Peak memory 241376 kb
Host smart-a788101d-6eea-471b-912d-c0a04b44267a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941176591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1941176591
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2468151373
Short name T984
Test name
Test status
Simulation time 6427630729 ps
CPU time 48.85 seconds
Started Aug 05 06:29:32 PM PDT 24
Finished Aug 05 06:30:21 PM PDT 24
Peak memory 249676 kb
Host smart-0c6ee70f-adaa-459f-8b25-5a7e94ca21e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468151373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2468151373
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3726683095
Short name T50
Test name
Test status
Simulation time 3722434475 ps
CPU time 69.66 seconds
Started Aug 05 06:29:31 PM PDT 24
Finished Aug 05 06:30:41 PM PDT 24
Peak memory 257748 kb
Host smart-e360081b-fc15-4f15-889e-142a6288cf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726683095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3726683095
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.206031861
Short name T861
Test name
Test status
Simulation time 8196541782 ps
CPU time 14.11 seconds
Started Aug 05 06:29:25 PM PDT 24
Finished Aug 05 06:29:39 PM PDT 24
Peak memory 224908 kb
Host smart-941b2133-bd34-46c6-9839-032bf1cba300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206031861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.206031861
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.4073354193
Short name T233
Test name
Test status
Simulation time 10103270538 ps
CPU time 107.41 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:31:11 PM PDT 24
Peak memory 272656 kb
Host smart-6c41dc74-86c3-4fba-8060-82319b375e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073354193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.4073354193
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3150192370
Short name T232
Test name
Test status
Simulation time 3365046939 ps
CPU time 16.11 seconds
Started Aug 05 06:29:25 PM PDT 24
Finished Aug 05 06:29:42 PM PDT 24
Peak memory 233260 kb
Host smart-5394729a-219f-4592-a748-47f011841ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150192370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3150192370
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1605134013
Short name T843
Test name
Test status
Simulation time 1714817365 ps
CPU time 15.43 seconds
Started Aug 05 06:29:27 PM PDT 24
Finished Aug 05 06:29:43 PM PDT 24
Peak memory 240452 kb
Host smart-cb76f27a-8fd5-4ba6-baf0-cf13c56b36b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605134013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1605134013
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1068448447
Short name T563
Test name
Test status
Simulation time 1415318998 ps
CPU time 4.75 seconds
Started Aug 05 06:29:25 PM PDT 24
Finished Aug 05 06:29:30 PM PDT 24
Peak memory 224860 kb
Host smart-921b81d6-a656-4ab2-8988-ba74ee5edd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068448447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1068448447
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.867283811
Short name T467
Test name
Test status
Simulation time 16282701494 ps
CPU time 16.16 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:29:40 PM PDT 24
Peak memory 241020 kb
Host smart-9601ee62-d4d8-446b-adbe-7c6be577ddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867283811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.867283811
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2499665132
Short name T616
Test name
Test status
Simulation time 317695479 ps
CPU time 3.41 seconds
Started Aug 05 06:29:28 PM PDT 24
Finished Aug 05 06:29:32 PM PDT 24
Peak memory 219460 kb
Host smart-95ac0f23-1f8d-482e-9aa9-4d1d624a81fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2499665132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2499665132
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.495229386
Short name T906
Test name
Test status
Simulation time 998954813 ps
CPU time 12.97 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:29:37 PM PDT 24
Peak memory 216628 kb
Host smart-fae3a39f-0629-4abd-8557-fc8aee14f7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495229386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.495229386
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2512741174
Short name T969
Test name
Test status
Simulation time 37002547647 ps
CPU time 19.83 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:29:44 PM PDT 24
Peak memory 216812 kb
Host smart-89df25f6-0c09-43be-8817-b145bae68aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512741174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2512741174
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.699542810
Short name T757
Test name
Test status
Simulation time 58102320 ps
CPU time 1.65 seconds
Started Aug 05 06:29:24 PM PDT 24
Finished Aug 05 06:29:26 PM PDT 24
Peak memory 216628 kb
Host smart-96460e4a-af1d-4e71-b57d-56475ab7e590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699542810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.699542810
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3632073844
Short name T905
Test name
Test status
Simulation time 38287961 ps
CPU time 0.69 seconds
Started Aug 05 06:29:23 PM PDT 24
Finished Aug 05 06:29:24 PM PDT 24
Peak memory 206360 kb
Host smart-46fe9608-19b2-4aba-a57e-29c0f29ef1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632073844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3632073844
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2847856773
Short name T968
Test name
Test status
Simulation time 489505884 ps
CPU time 5.1 seconds
Started Aug 05 06:29:25 PM PDT 24
Finished Aug 05 06:29:30 PM PDT 24
Peak memory 233140 kb
Host smart-70368a01-6b9e-41a6-803a-4dc5984cc9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847856773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2847856773
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3309099820
Short name T962
Test name
Test status
Simulation time 18192989 ps
CPU time 0.74 seconds
Started Aug 05 06:29:40 PM PDT 24
Finished Aug 05 06:29:41 PM PDT 24
Peak memory 205284 kb
Host smart-348a9fda-19fe-4f82-8403-cbbcc084d140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309099820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3309099820
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4267647680
Short name T419
Test name
Test status
Simulation time 542073268 ps
CPU time 7.12 seconds
Started Aug 05 06:29:30 PM PDT 24
Finished Aug 05 06:29:38 PM PDT 24
Peak memory 233140 kb
Host smart-3e0c9f6f-e8da-4998-8078-a2a96a4b22a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267647680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4267647680
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1066356894
Short name T857
Test name
Test status
Simulation time 21309366 ps
CPU time 0.76 seconds
Started Aug 05 06:29:29 PM PDT 24
Finished Aug 05 06:29:30 PM PDT 24
Peak memory 206908 kb
Host smart-796f09ce-eed5-42cd-abfd-6cb6b3ff4498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066356894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1066356894
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2215941534
Short name T813
Test name
Test status
Simulation time 959068184 ps
CPU time 21.92 seconds
Started Aug 05 06:29:36 PM PDT 24
Finished Aug 05 06:29:59 PM PDT 24
Peak memory 238208 kb
Host smart-4b795370-b806-4a6f-b232-ae33f692f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215941534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2215941534
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.562773951
Short name T296
Test name
Test status
Simulation time 30104143150 ps
CPU time 266.09 seconds
Started Aug 05 06:29:35 PM PDT 24
Finished Aug 05 06:34:02 PM PDT 24
Peak memory 257804 kb
Host smart-e7edb626-39e1-4f4d-b4af-d8fd0fbf8321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562773951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.562773951
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1318870488
Short name T278
Test name
Test status
Simulation time 13622488343 ps
CPU time 56.29 seconds
Started Aug 05 06:29:36 PM PDT 24
Finished Aug 05 06:30:32 PM PDT 24
Peak memory 264340 kb
Host smart-63f1b4e7-d0dd-41df-82b1-18c00be0654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318870488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1318870488
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1175006932
Short name T158
Test name
Test status
Simulation time 6726345057 ps
CPU time 31.44 seconds
Started Aug 05 06:29:34 PM PDT 24
Finished Aug 05 06:30:06 PM PDT 24
Peak memory 224976 kb
Host smart-dfa6ae9c-4195-43c1-beaa-a120a1cb82ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175006932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1175006932
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2116227078
Short name T192
Test name
Test status
Simulation time 13738150993 ps
CPU time 29.88 seconds
Started Aug 05 06:29:36 PM PDT 24
Finished Aug 05 06:30:07 PM PDT 24
Peak memory 241312 kb
Host smart-ff12240c-e519-4742-a643-63c74437d48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116227078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2116227078
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2859030038
Short name T822
Test name
Test status
Simulation time 417124251 ps
CPU time 5.54 seconds
Started Aug 05 06:29:30 PM PDT 24
Finished Aug 05 06:29:35 PM PDT 24
Peak memory 233108 kb
Host smart-d9e81909-1762-405b-91fb-1d8c1dc12aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859030038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2859030038
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1772463244
Short name T884
Test name
Test status
Simulation time 8777102686 ps
CPU time 42.25 seconds
Started Aug 05 06:29:30 PM PDT 24
Finished Aug 05 06:30:13 PM PDT 24
Peak memory 235936 kb
Host smart-3830877a-fe9b-411f-932d-bcd23600ead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772463244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1772463244
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.767604483
Short name T403
Test name
Test status
Simulation time 117499709 ps
CPU time 2.84 seconds
Started Aug 05 06:29:30 PM PDT 24
Finished Aug 05 06:29:33 PM PDT 24
Peak memory 233140 kb
Host smart-ba0c8a1f-9124-4f5e-abec-fce430573a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767604483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.767604483
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2958847202
Short name T578
Test name
Test status
Simulation time 405409774 ps
CPU time 2.88 seconds
Started Aug 05 06:29:34 PM PDT 24
Finished Aug 05 06:29:37 PM PDT 24
Peak memory 233108 kb
Host smart-ce912446-0f37-49ef-ba4c-ae0d09377a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958847202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2958847202
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2445052834
Short name T584
Test name
Test status
Simulation time 377348978 ps
CPU time 3.9 seconds
Started Aug 05 06:29:40 PM PDT 24
Finished Aug 05 06:29:44 PM PDT 24
Peak memory 221088 kb
Host smart-268c13b1-3ea0-4517-89d6-02bbd7c0f092
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2445052834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2445052834
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.628179567
Short name T353
Test name
Test status
Simulation time 8435347329 ps
CPU time 7.95 seconds
Started Aug 05 06:29:34 PM PDT 24
Finished Aug 05 06:29:42 PM PDT 24
Peak memory 216648 kb
Host smart-ce4ee27e-a80d-4529-8c99-138ac79b9802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628179567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.628179567
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.712309482
Short name T303
Test name
Test status
Simulation time 85897357 ps
CPU time 1.59 seconds
Started Aug 05 06:29:32 PM PDT 24
Finished Aug 05 06:29:34 PM PDT 24
Peak memory 216604 kb
Host smart-a7c942d8-ee52-4587-a80c-6cc0a7aa5d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712309482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.712309482
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.949464489
Short name T760
Test name
Test status
Simulation time 322959842 ps
CPU time 0.82 seconds
Started Aug 05 06:29:28 PM PDT 24
Finished Aug 05 06:29:29 PM PDT 24
Peak memory 206392 kb
Host smart-67c957bb-3dc1-4511-b03f-47d291140f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949464489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.949464489
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.63805097
Short name T519
Test name
Test status
Simulation time 2002565955 ps
CPU time 9.17 seconds
Started Aug 05 06:29:31 PM PDT 24
Finished Aug 05 06:29:40 PM PDT 24
Peak memory 233184 kb
Host smart-2609f9df-fffb-45d3-bc4a-9e3f89ffd98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63805097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.63805097
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.722008070
Short name T897
Test name
Test status
Simulation time 91486301 ps
CPU time 0.71 seconds
Started Aug 05 06:29:39 PM PDT 24
Finished Aug 05 06:29:40 PM PDT 24
Peak memory 205896 kb
Host smart-28bba31d-cc23-4f36-8f31-f92a9f73f011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722008070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.722008070
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1459621759
Short name T695
Test name
Test status
Simulation time 8957903975 ps
CPU time 31.15 seconds
Started Aug 05 06:29:35 PM PDT 24
Finished Aug 05 06:30:06 PM PDT 24
Peak memory 224944 kb
Host smart-4ac56f79-c80f-422b-ab6a-90ed27821155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459621759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1459621759
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1635902432
Short name T313
Test name
Test status
Simulation time 45752625 ps
CPU time 0.75 seconds
Started Aug 05 06:29:35 PM PDT 24
Finished Aug 05 06:29:36 PM PDT 24
Peak memory 206136 kb
Host smart-c60f0f31-19d9-47e8-b8cc-3a76a27fc2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635902432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1635902432
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.966288494
Short name T651
Test name
Test status
Simulation time 112924901670 ps
CPU time 201.51 seconds
Started Aug 05 06:29:41 PM PDT 24
Finished Aug 05 06:33:03 PM PDT 24
Peak memory 250604 kb
Host smart-431bacda-58ff-48ed-8dd2-327394b2f753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966288494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.966288494
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2843633256
Short name T226
Test name
Test status
Simulation time 3931906860 ps
CPU time 69.54 seconds
Started Aug 05 06:29:42 PM PDT 24
Finished Aug 05 06:30:52 PM PDT 24
Peak memory 254336 kb
Host smart-f208d983-8ce2-4b1a-b1ca-6abb7e013654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843633256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2843633256
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2821575928
Short name T211
Test name
Test status
Simulation time 7515097775 ps
CPU time 29.41 seconds
Started Aug 05 06:29:39 PM PDT 24
Finished Aug 05 06:30:08 PM PDT 24
Peak memory 241420 kb
Host smart-e2746221-7e14-4610-8a68-621dc624efb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821575928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2821575928
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3463971212
Short name T920
Test name
Test status
Simulation time 61462711524 ps
CPU time 72.44 seconds
Started Aug 05 06:29:39 PM PDT 24
Finished Aug 05 06:30:52 PM PDT 24
Peak memory 254656 kb
Host smart-8872ab27-ccc7-42dc-b1b4-a21c2b96fe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463971212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3463971212
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3564149158
Short name T272
Test name
Test status
Simulation time 1017777438 ps
CPU time 3.44 seconds
Started Aug 05 06:29:37 PM PDT 24
Finished Aug 05 06:29:41 PM PDT 24
Peak memory 219312 kb
Host smart-16263dca-db6f-4563-8d58-b88879b41d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564149158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3564149158
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1031316473
Short name T529
Test name
Test status
Simulation time 7797819885 ps
CPU time 70.8 seconds
Started Aug 05 06:29:34 PM PDT 24
Finished Aug 05 06:30:45 PM PDT 24
Peak memory 236620 kb
Host smart-130d208c-9b51-4e39-bddf-5d06bcb1e721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031316473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1031316473
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1337146358
Short name T912
Test name
Test status
Simulation time 32745613 ps
CPU time 2.37 seconds
Started Aug 05 06:29:35 PM PDT 24
Finished Aug 05 06:29:37 PM PDT 24
Peak memory 232816 kb
Host smart-d457fc37-c8f4-4e8c-b335-c9457bd38ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337146358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1337146358
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3739945228
Short name T591
Test name
Test status
Simulation time 7665472200 ps
CPU time 13.43 seconds
Started Aug 05 06:29:35 PM PDT 24
Finished Aug 05 06:29:49 PM PDT 24
Peak memory 225008 kb
Host smart-ea51368d-f014-4b02-8016-8b4310f2a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739945228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3739945228
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3282028051
Short name T550
Test name
Test status
Simulation time 1720465052 ps
CPU time 16.71 seconds
Started Aug 05 06:29:42 PM PDT 24
Finished Aug 05 06:29:59 PM PDT 24
Peak memory 223588 kb
Host smart-697f99ff-29a2-482c-abe6-0fa9f02e1fe7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3282028051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3282028051
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1525487838
Short name T456
Test name
Test status
Simulation time 32199211670 ps
CPU time 155.12 seconds
Started Aug 05 06:29:43 PM PDT 24
Finished Aug 05 06:32:18 PM PDT 24
Peak memory 261072 kb
Host smart-960d34af-da38-49b0-8098-6691a820b138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525487838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1525487838
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2868505749
Short name T304
Test name
Test status
Simulation time 48476619026 ps
CPU time 28.45 seconds
Started Aug 05 06:29:36 PM PDT 24
Finished Aug 05 06:30:04 PM PDT 24
Peak memory 216712 kb
Host smart-273295f7-78d9-467d-aea6-d2dee1eda2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868505749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2868505749
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4030779335
Short name T491
Test name
Test status
Simulation time 526820695 ps
CPU time 4.3 seconds
Started Aug 05 06:29:36 PM PDT 24
Finished Aug 05 06:29:41 PM PDT 24
Peak memory 216624 kb
Host smart-d41d086f-68f6-483c-9e08-7fc6cc854b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030779335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4030779335
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3930495938
Short name T774
Test name
Test status
Simulation time 490075414 ps
CPU time 3.43 seconds
Started Aug 05 06:29:35 PM PDT 24
Finished Aug 05 06:29:39 PM PDT 24
Peak memory 216656 kb
Host smart-b2de7704-b809-49cb-9424-1c6ed6ecf2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930495938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3930495938
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2072470408
Short name T706
Test name
Test status
Simulation time 71975712 ps
CPU time 0.91 seconds
Started Aug 05 06:29:35 PM PDT 24
Finished Aug 05 06:29:36 PM PDT 24
Peak memory 207428 kb
Host smart-3e349c8d-6910-4c92-9589-865a1d7a2bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072470408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2072470408
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2790653524
Short name T423
Test name
Test status
Simulation time 3298132096 ps
CPU time 8.46 seconds
Started Aug 05 06:29:35 PM PDT 24
Finished Aug 05 06:29:44 PM PDT 24
Peak memory 238164 kb
Host smart-084c8a6b-78fd-48e3-b1e9-8bca90dc406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790653524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2790653524
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1950382058
Short name T638
Test name
Test status
Simulation time 41246685 ps
CPU time 0.74 seconds
Started Aug 05 06:29:41 PM PDT 24
Finished Aug 05 06:29:42 PM PDT 24
Peak memory 206192 kb
Host smart-5ac2b613-23b8-4628-acab-5ff2bb2569cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950382058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1950382058
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3544331938
Short name T312
Test name
Test status
Simulation time 547673729 ps
CPU time 3.99 seconds
Started Aug 05 06:29:41 PM PDT 24
Finished Aug 05 06:29:45 PM PDT 24
Peak memory 233076 kb
Host smart-d72ba5b6-6981-4f0a-a4ba-a4599444dd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544331938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3544331938
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.220630311
Short name T528
Test name
Test status
Simulation time 90405282 ps
CPU time 0.74 seconds
Started Aug 05 06:29:40 PM PDT 24
Finished Aug 05 06:29:41 PM PDT 24
Peak memory 207344 kb
Host smart-de883316-a178-4af9-8668-8bd4eff38c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220630311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.220630311
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.586360082
Short name T286
Test name
Test status
Simulation time 375435831623 ps
CPU time 343.21 seconds
Started Aug 05 06:29:44 PM PDT 24
Finished Aug 05 06:35:27 PM PDT 24
Peak memory 257696 kb
Host smart-6d390c6f-c50b-4f09-a2c6-d5ef1e0b3ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586360082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.586360082
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1276172464
Short name T536
Test name
Test status
Simulation time 77747462 ps
CPU time 0.82 seconds
Started Aug 05 06:29:40 PM PDT 24
Finished Aug 05 06:29:41 PM PDT 24
Peak memory 217612 kb
Host smart-4d9255ca-778f-4ff6-a521-7638338ef31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276172464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1276172464
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3708027062
Short name T183
Test name
Test status
Simulation time 14272542398 ps
CPU time 104.8 seconds
Started Aug 05 06:29:40 PM PDT 24
Finished Aug 05 06:31:25 PM PDT 24
Peak memory 265576 kb
Host smart-833f2aae-6867-408d-a6c4-a2e8f49bcbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708027062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3708027062
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.64333180
Short name T837
Test name
Test status
Simulation time 705533764 ps
CPU time 11.81 seconds
Started Aug 05 06:29:47 PM PDT 24
Finished Aug 05 06:29:59 PM PDT 24
Peak memory 224944 kb
Host smart-a0b8a377-88c2-446f-a7b5-b9832f1f5579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64333180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.64333180
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3968035914
Short name T659
Test name
Test status
Simulation time 512805189 ps
CPU time 9.21 seconds
Started Aug 05 06:29:41 PM PDT 24
Finished Aug 05 06:29:51 PM PDT 24
Peak memory 224992 kb
Host smart-574c6ed1-7974-4f30-a391-5f820eb9b5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968035914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3968035914
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.256325183
Short name T494
Test name
Test status
Simulation time 264821215 ps
CPU time 4 seconds
Started Aug 05 06:29:44 PM PDT 24
Finished Aug 05 06:29:48 PM PDT 24
Peak memory 233064 kb
Host smart-bf1449cc-f110-46d4-ac18-de5da3fca275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256325183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.256325183
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.955715291
Short name T807
Test name
Test status
Simulation time 2223805042 ps
CPU time 9.54 seconds
Started Aug 05 06:29:40 PM PDT 24
Finished Aug 05 06:29:50 PM PDT 24
Peak memory 233188 kb
Host smart-e4f4f95e-9baa-4d59-b129-b0c75737679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955715291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.955715291
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2516085227
Short name T991
Test name
Test status
Simulation time 198741299 ps
CPU time 3.13 seconds
Started Aug 05 06:29:43 PM PDT 24
Finished Aug 05 06:29:47 PM PDT 24
Peak memory 233096 kb
Host smart-74b74bb0-213f-4399-85ef-c17c145280da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516085227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2516085227
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1350434162
Short name T224
Test name
Test status
Simulation time 10191349952 ps
CPU time 14.62 seconds
Started Aug 05 06:29:40 PM PDT 24
Finished Aug 05 06:29:55 PM PDT 24
Peak memory 233136 kb
Host smart-ce97e51d-ebb1-4418-9262-a4d0e6181be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350434162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1350434162
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3549808728
Short name T357
Test name
Test status
Simulation time 3526769438 ps
CPU time 6.46 seconds
Started Aug 05 06:29:39 PM PDT 24
Finished Aug 05 06:29:46 PM PDT 24
Peak memory 223576 kb
Host smart-813f95c4-764f-4a49-9553-064e00b01c85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3549808728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3549808728
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3634521258
Short name T288
Test name
Test status
Simulation time 61478650751 ps
CPU time 586.78 seconds
Started Aug 05 06:29:40 PM PDT 24
Finished Aug 05 06:39:27 PM PDT 24
Peak memory 274212 kb
Host smart-f078afe3-e30b-47cf-b218-a728c466a19e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634521258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3634521258
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.267345893
Short name T307
Test name
Test status
Simulation time 1133474993 ps
CPU time 6.96 seconds
Started Aug 05 06:29:47 PM PDT 24
Finished Aug 05 06:29:54 PM PDT 24
Peak memory 216860 kb
Host smart-8ffdc643-cc60-403a-b30c-6c01b222829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267345893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.267345893
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3779014935
Short name T688
Test name
Test status
Simulation time 21917267763 ps
CPU time 13.56 seconds
Started Aug 05 06:29:44 PM PDT 24
Finished Aug 05 06:29:57 PM PDT 24
Peak memory 216684 kb
Host smart-7d2d0fdc-444e-4d58-b515-656301681121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779014935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3779014935
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.206449566
Short name T978
Test name
Test status
Simulation time 131307225 ps
CPU time 0.79 seconds
Started Aug 05 06:29:42 PM PDT 24
Finished Aug 05 06:29:43 PM PDT 24
Peak memory 206340 kb
Host smart-0ffdb3a1-3da1-4d8c-bdb8-cf85fea1ad3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206449566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.206449566
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4014024976
Short name T643
Test name
Test status
Simulation time 384058067 ps
CPU time 0.74 seconds
Started Aug 05 06:29:42 PM PDT 24
Finished Aug 05 06:29:43 PM PDT 24
Peak memory 206348 kb
Host smart-3ac5f1fb-3101-4963-a1f1-847558388ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014024976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4014024976
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1209589791
Short name T202
Test name
Test status
Simulation time 22612273224 ps
CPU time 20.13 seconds
Started Aug 05 06:29:41 PM PDT 24
Finished Aug 05 06:30:01 PM PDT 24
Peak memory 241420 kb
Host smart-c7fb73d4-fce6-49bf-a626-83ce63c565d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209589791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1209589791
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4053657212
Short name T371
Test name
Test status
Simulation time 47941317 ps
CPU time 0.68 seconds
Started Aug 05 06:29:50 PM PDT 24
Finished Aug 05 06:29:51 PM PDT 24
Peak memory 205296 kb
Host smart-c2e9e655-33ed-4137-9c2d-b03e516dd3e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053657212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4053657212
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1845836001
Short name T394
Test name
Test status
Simulation time 500103367 ps
CPU time 3.92 seconds
Started Aug 05 06:29:50 PM PDT 24
Finished Aug 05 06:29:54 PM PDT 24
Peak memory 232924 kb
Host smart-c65c9e59-7141-4fd9-9fa5-89445db53e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845836001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1845836001
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2510377559
Short name T893
Test name
Test status
Simulation time 20244608 ps
CPU time 0.77 seconds
Started Aug 05 06:29:40 PM PDT 24
Finished Aug 05 06:29:41 PM PDT 24
Peak memory 206964 kb
Host smart-ea6b8a07-a830-4999-810e-ea88ff951d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510377559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2510377559
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3599230778
Short name T469
Test name
Test status
Simulation time 3141224074 ps
CPU time 62.47 seconds
Started Aug 05 06:29:47 PM PDT 24
Finished Aug 05 06:30:50 PM PDT 24
Peak memory 253624 kb
Host smart-35a609d7-51d9-441c-a0d4-4dcec14084aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599230778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3599230778
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1452604605
Short name T841
Test name
Test status
Simulation time 11665587957 ps
CPU time 85.76 seconds
Started Aug 05 06:29:45 PM PDT 24
Finished Aug 05 06:31:11 PM PDT 24
Peak memory 255532 kb
Host smart-7dcec00d-35d9-4efb-8bbf-fffd6e9deb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452604605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1452604605
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3926019632
Short name T635
Test name
Test status
Simulation time 4337936147 ps
CPU time 37.55 seconds
Started Aug 05 06:29:45 PM PDT 24
Finished Aug 05 06:30:23 PM PDT 24
Peak memory 249624 kb
Host smart-8d976f7d-b734-40ac-b3d3-222fb7107b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926019632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3926019632
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2714336395
Short name T586
Test name
Test status
Simulation time 354837920 ps
CPU time 9.92 seconds
Started Aug 05 06:29:45 PM PDT 24
Finished Aug 05 06:29:55 PM PDT 24
Peak memory 241352 kb
Host smart-b1f6d541-5b2b-43f3-b056-db5b71323468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714336395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2714336395
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1929682565
Short name T901
Test name
Test status
Simulation time 38075884968 ps
CPU time 56.29 seconds
Started Aug 05 06:29:50 PM PDT 24
Finished Aug 05 06:30:46 PM PDT 24
Peak memory 240108 kb
Host smart-d8a4788d-e800-4fc0-bf54-6d0ef0fb6e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929682565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1929682565
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3535110605
Short name T1001
Test name
Test status
Simulation time 1493727237 ps
CPU time 19 seconds
Started Aug 05 06:29:52 PM PDT 24
Finished Aug 05 06:30:11 PM PDT 24
Peak memory 224972 kb
Host smart-1b6b4d9e-9f44-4cf6-baef-cde889d2fd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535110605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3535110605
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1041162512
Short name T701
Test name
Test status
Simulation time 466540581 ps
CPU time 8.67 seconds
Started Aug 05 06:29:50 PM PDT 24
Finished Aug 05 06:29:59 PM PDT 24
Peak memory 233144 kb
Host smart-fb0c86e4-06ee-4153-8ce4-a6133cea7028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041162512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1041162512
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4280198207
Short name T329
Test name
Test status
Simulation time 74328770 ps
CPU time 2.09 seconds
Started Aug 05 06:29:50 PM PDT 24
Finished Aug 05 06:29:53 PM PDT 24
Peak memory 224544 kb
Host smart-87e693ac-397f-4677-ad29-54e08f360573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280198207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4280198207
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1009965263
Short name T205
Test name
Test status
Simulation time 678249577 ps
CPU time 4.82 seconds
Started Aug 05 06:29:46 PM PDT 24
Finished Aug 05 06:29:51 PM PDT 24
Peak memory 233128 kb
Host smart-09d6bfd4-07f8-49e3-a6d3-3301f158c0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009965263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1009965263
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3219246772
Short name T490
Test name
Test status
Simulation time 38485508962 ps
CPU time 18.16 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:30:11 PM PDT 24
Peak memory 219948 kb
Host smart-e4089aed-0e87-4bbe-b29f-3b72240bf3bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3219246772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3219246772
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3122157479
Short name T58
Test name
Test status
Simulation time 31528427979 ps
CPU time 100.22 seconds
Started Aug 05 06:29:47 PM PDT 24
Finished Aug 05 06:31:27 PM PDT 24
Peak memory 256228 kb
Host smart-b950db1f-2406-48b2-b8ae-5cf1fd881e0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122157479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3122157479
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1908346643
Short name T598
Test name
Test status
Simulation time 1411550743 ps
CPU time 18.93 seconds
Started Aug 05 06:29:41 PM PDT 24
Finished Aug 05 06:30:00 PM PDT 24
Peak memory 216908 kb
Host smart-28acc251-03a8-4934-be92-8d946b48ac26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908346643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1908346643
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.178336136
Short name T712
Test name
Test status
Simulation time 2499843501 ps
CPU time 9.76 seconds
Started Aug 05 06:29:42 PM PDT 24
Finished Aug 05 06:29:52 PM PDT 24
Peak memory 216764 kb
Host smart-676626f7-a07f-4ba1-9f93-99f2b1540160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178336136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.178336136
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1190552912
Short name T25
Test name
Test status
Simulation time 1127293373 ps
CPU time 2.57 seconds
Started Aug 05 06:29:46 PM PDT 24
Finished Aug 05 06:29:49 PM PDT 24
Peak memory 216740 kb
Host smart-ff625172-c33f-42cd-bd0c-f756646db35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190552912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1190552912
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3869503517
Short name T928
Test name
Test status
Simulation time 90747684 ps
CPU time 0.74 seconds
Started Aug 05 06:29:42 PM PDT 24
Finished Aug 05 06:29:43 PM PDT 24
Peak memory 206344 kb
Host smart-26f506f5-4fb3-4c68-b0e9-ce7d76b70371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869503517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3869503517
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1098571809
Short name T605
Test name
Test status
Simulation time 60893078149 ps
CPU time 15.46 seconds
Started Aug 05 06:29:46 PM PDT 24
Finished Aug 05 06:30:02 PM PDT 24
Peak memory 224908 kb
Host smart-b40ccd25-e536-405e-9ca1-27db64ceff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098571809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1098571809
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3930604502
Short name T545
Test name
Test status
Simulation time 16357550 ps
CPU time 0.79 seconds
Started Aug 05 06:29:54 PM PDT 24
Finished Aug 05 06:29:55 PM PDT 24
Peak memory 206156 kb
Host smart-0e148b73-1446-48a9-b783-ed91cd3869e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930604502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3930604502
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3456256997
Short name T405
Test name
Test status
Simulation time 713909172 ps
CPU time 6.71 seconds
Started Aug 05 06:29:50 PM PDT 24
Finished Aug 05 06:29:57 PM PDT 24
Peak memory 224700 kb
Host smart-0971276a-0309-4221-af89-6668a7eeecee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456256997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3456256997
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2579417129
Short name T518
Test name
Test status
Simulation time 70779884 ps
CPU time 0.8 seconds
Started Aug 05 06:29:46 PM PDT 24
Finished Aug 05 06:29:47 PM PDT 24
Peak memory 207044 kb
Host smart-08b55960-9791-4d72-b8c0-a4e778a18fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579417129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2579417129
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1195957053
Short name T818
Test name
Test status
Simulation time 42722406125 ps
CPU time 108.77 seconds
Started Aug 05 06:29:46 PM PDT 24
Finished Aug 05 06:31:35 PM PDT 24
Peak memory 256496 kb
Host smart-511622d7-e977-44dc-bdaa-c8464898a562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195957053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1195957053
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.329035670
Short name T972
Test name
Test status
Simulation time 10664838011 ps
CPU time 16.11 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:30:09 PM PDT 24
Peak memory 218000 kb
Host smart-2a3927a5-0fdf-4b70-b08b-236426b3c00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329035670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.329035670
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3714315210
Short name T159
Test name
Test status
Simulation time 4869796102 ps
CPU time 39.87 seconds
Started Aug 05 06:29:52 PM PDT 24
Finished Aug 05 06:30:32 PM PDT 24
Peak memory 233244 kb
Host smart-a27ec375-ae32-4805-8948-b634c9a90543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714315210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3714315210
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.658166095
Short name T281
Test name
Test status
Simulation time 46252275635 ps
CPU time 291.65 seconds
Started Aug 05 06:29:45 PM PDT 24
Finished Aug 05 06:34:37 PM PDT 24
Peak memory 272708 kb
Host smart-4244e1f7-1695-4c7a-9de0-ecd2e486ae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658166095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.658166095
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.243061014
Short name T600
Test name
Test status
Simulation time 13667398796 ps
CPU time 10.82 seconds
Started Aug 05 06:29:54 PM PDT 24
Finished Aug 05 06:30:05 PM PDT 24
Peak memory 224980 kb
Host smart-41143d49-4c8b-4d8d-b91b-8efdc64c98ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243061014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.243061014
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1131882404
Short name T398
Test name
Test status
Simulation time 2901842314 ps
CPU time 13.3 seconds
Started Aug 05 06:29:54 PM PDT 24
Finished Aug 05 06:30:08 PM PDT 24
Peak memory 224984 kb
Host smart-8238e30e-e8d9-4370-9b89-28bbf30a4ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131882404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1131882404
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1350240011
Short name T890
Test name
Test status
Simulation time 35723236769 ps
CPU time 27.26 seconds
Started Aug 05 06:29:47 PM PDT 24
Finished Aug 05 06:30:14 PM PDT 24
Peak memory 233216 kb
Host smart-4a201899-57fb-4059-b3a9-0447c76ad539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350240011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1350240011
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1546931298
Short name T996
Test name
Test status
Simulation time 4004286792 ps
CPU time 12.52 seconds
Started Aug 05 06:29:47 PM PDT 24
Finished Aug 05 06:30:00 PM PDT 24
Peak memory 241076 kb
Host smart-3d3223c7-6046-4eab-b3e0-d66f85ed2664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546931298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1546931298
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1482065244
Short name T724
Test name
Test status
Simulation time 710754264 ps
CPU time 7.18 seconds
Started Aug 05 06:29:48 PM PDT 24
Finished Aug 05 06:29:55 PM PDT 24
Peak memory 223560 kb
Host smart-e1faa974-8d60-4ee9-b40a-6cea5d6d6e25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1482065244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1482065244
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.535661688
Short name T747
Test name
Test status
Simulation time 69377251 ps
CPU time 1.17 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:29:54 PM PDT 24
Peak memory 207600 kb
Host smart-0b6ce669-c8ba-4330-83a2-6473b81ba421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535661688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.535661688
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2764264355
Short name T298
Test name
Test status
Simulation time 16945411818 ps
CPU time 17.81 seconds
Started Aug 05 06:29:47 PM PDT 24
Finished Aug 05 06:30:05 PM PDT 24
Peak memory 216848 kb
Host smart-eda800dc-37cf-47b0-99ab-bf2bd3fb3979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764264355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2764264355
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1616706239
Short name T326
Test name
Test status
Simulation time 19369278194 ps
CPU time 14.51 seconds
Started Aug 05 06:29:52 PM PDT 24
Finished Aug 05 06:30:07 PM PDT 24
Peak memory 216696 kb
Host smart-5967b871-7d35-4baf-89f9-7eca649ede90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616706239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1616706239
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3107287830
Short name T637
Test name
Test status
Simulation time 512144811 ps
CPU time 2.38 seconds
Started Aug 05 06:29:47 PM PDT 24
Finished Aug 05 06:29:50 PM PDT 24
Peak memory 216688 kb
Host smart-0718ad13-10dc-4959-87d9-0a164af51de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107287830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3107287830
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2214789107
Short name T410
Test name
Test status
Simulation time 31884949 ps
CPU time 0.81 seconds
Started Aug 05 06:29:52 PM PDT 24
Finished Aug 05 06:29:53 PM PDT 24
Peak memory 206392 kb
Host smart-92f4e99b-2f55-49ed-a174-b3b8739a79da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214789107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2214789107
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.542375088
Short name T737
Test name
Test status
Simulation time 31102503828 ps
CPU time 16.95 seconds
Started Aug 05 06:29:50 PM PDT 24
Finished Aug 05 06:30:07 PM PDT 24
Peak memory 233176 kb
Host smart-06b44a67-de49-4622-adde-1a24eba0d268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542375088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.542375088
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.596148326
Short name T322
Test name
Test status
Simulation time 41604015 ps
CPU time 0.68 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:29:54 PM PDT 24
Peak memory 205216 kb
Host smart-d8e4547c-e350-44b4-b141-8582e9ac710c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596148326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.596148326
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2921674325
Short name T639
Test name
Test status
Simulation time 141079270 ps
CPU time 2.58 seconds
Started Aug 05 06:29:54 PM PDT 24
Finished Aug 05 06:29:56 PM PDT 24
Peak memory 233108 kb
Host smart-c560e14e-5f4a-4942-8ed1-23ecba39559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921674325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2921674325
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.831630510
Short name T389
Test name
Test status
Simulation time 17924738 ps
CPU time 0.76 seconds
Started Aug 05 06:29:54 PM PDT 24
Finished Aug 05 06:29:55 PM PDT 24
Peak memory 205924 kb
Host smart-26c3a735-3abe-4212-a93d-67d7aae57faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831630510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.831630510
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.993258537
Short name T343
Test name
Test status
Simulation time 17482164978 ps
CPU time 39.41 seconds
Started Aug 05 06:29:56 PM PDT 24
Finished Aug 05 06:30:36 PM PDT 24
Peak memory 236788 kb
Host smart-15732839-41c4-4533-ae1a-4c87cb10459f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993258537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.993258537
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.4103867274
Short name T770
Test name
Test status
Simulation time 55101284653 ps
CPU time 520.95 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:38:35 PM PDT 24
Peak memory 265536 kb
Host smart-a8d9ea78-cdea-4931-9d9e-a3dd7ea58061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103867274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.4103867274
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3258967425
Short name T517
Test name
Test status
Simulation time 341919142 ps
CPU time 4.17 seconds
Started Aug 05 06:29:54 PM PDT 24
Finished Aug 05 06:29:58 PM PDT 24
Peak memory 234520 kb
Host smart-4300f17a-b197-4335-83a7-a396e673124d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258967425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3258967425
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.4114562175
Short name T196
Test name
Test status
Simulation time 27581422660 ps
CPU time 18.2 seconds
Started Aug 05 06:29:55 PM PDT 24
Finished Aug 05 06:30:14 PM PDT 24
Peak memory 233252 kb
Host smart-d322357f-a6dd-4f40-b4df-a9e8f46517d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114562175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.4114562175
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1749802033
Short name T204
Test name
Test status
Simulation time 1456612094 ps
CPU time 8.86 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:30:03 PM PDT 24
Peak memory 233140 kb
Host smart-39aab495-5652-4694-b7e5-d549dcd5e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749802033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1749802033
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.852442775
Short name T577
Test name
Test status
Simulation time 3746218467 ps
CPU time 14 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:30:08 PM PDT 24
Peak memory 224944 kb
Host smart-18a738b6-d4bf-440a-9161-f73050a15c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852442775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.852442775
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1975777021
Short name T833
Test name
Test status
Simulation time 237020434 ps
CPU time 3.92 seconds
Started Aug 05 06:29:54 PM PDT 24
Finished Aug 05 06:29:58 PM PDT 24
Peak memory 233132 kb
Host smart-2672adea-aba5-438d-b4ec-5d24ec7b489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975777021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1975777021
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1159600208
Short name T976
Test name
Test status
Simulation time 522701006 ps
CPU time 4.51 seconds
Started Aug 05 06:29:52 PM PDT 24
Finished Aug 05 06:29:56 PM PDT 24
Peak memory 222884 kb
Host smart-dc11dd5e-f09a-4c7a-aeff-f9113c4967ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1159600208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1159600208
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1136343712
Short name T30
Test name
Test status
Simulation time 22421183117 ps
CPU time 159.19 seconds
Started Aug 05 06:29:57 PM PDT 24
Finished Aug 05 06:32:36 PM PDT 24
Peak memory 257324 kb
Host smart-ac809396-8892-4500-a55e-4fa1068cd2ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136343712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1136343712
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2431432133
Short name T547
Test name
Test status
Simulation time 24175464779 ps
CPU time 29.28 seconds
Started Aug 05 06:29:52 PM PDT 24
Finished Aug 05 06:30:22 PM PDT 24
Peak memory 220432 kb
Host smart-578eff81-dede-4d8e-b4e3-d6a1f9b859a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431432133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2431432133
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.878449564
Short name T561
Test name
Test status
Simulation time 530663359 ps
CPU time 3.54 seconds
Started Aug 05 06:29:52 PM PDT 24
Finished Aug 05 06:29:56 PM PDT 24
Peak memory 216628 kb
Host smart-528463cc-e2e0-4b60-a044-55a556bf1909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878449564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.878449564
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4246585503
Short name T320
Test name
Test status
Simulation time 13699331 ps
CPU time 0.73 seconds
Started Aug 05 06:29:52 PM PDT 24
Finished Aug 05 06:29:53 PM PDT 24
Peak memory 206288 kb
Host smart-895cc97d-073a-407a-94dd-fe96db654351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246585503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4246585503
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3819087955
Short name T84
Test name
Test status
Simulation time 28475815 ps
CPU time 0.75 seconds
Started Aug 05 06:29:55 PM PDT 24
Finished Aug 05 06:29:56 PM PDT 24
Peak memory 206392 kb
Host smart-4f5db4ba-aeb6-4583-a834-225358992136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819087955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3819087955
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3685389813
Short name T464
Test name
Test status
Simulation time 9993604426 ps
CPU time 9.72 seconds
Started Aug 05 06:29:52 PM PDT 24
Finished Aug 05 06:30:02 PM PDT 24
Peak memory 225036 kb
Host smart-001c20fc-a8fa-4562-97c1-a52ece0d08eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685389813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3685389813
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2278458152
Short name T331
Test name
Test status
Simulation time 38647723 ps
CPU time 0.71 seconds
Started Aug 05 06:29:59 PM PDT 24
Finished Aug 05 06:30:00 PM PDT 24
Peak memory 205756 kb
Host smart-75e84a88-5393-4645-b1a4-13f742e0da1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278458152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2278458152
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.146326685
Short name T88
Test name
Test status
Simulation time 64480968 ps
CPU time 2.8 seconds
Started Aug 05 06:29:55 PM PDT 24
Finished Aug 05 06:29:58 PM PDT 24
Peak memory 233072 kb
Host smart-ae61b119-f98d-495d-8da9-6a5e43442115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146326685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.146326685
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.578457819
Short name T533
Test name
Test status
Simulation time 18255799 ps
CPU time 0.78 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:29:54 PM PDT 24
Peak memory 205972 kb
Host smart-cacdb30f-65ba-4822-a65c-985f7a05a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578457819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.578457819
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3233502677
Short name T948
Test name
Test status
Simulation time 168830537506 ps
CPU time 147.86 seconds
Started Aug 05 06:29:59 PM PDT 24
Finished Aug 05 06:32:27 PM PDT 24
Peak memory 265956 kb
Host smart-6e1e2d8a-3ee2-45c8-a595-631534287c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233502677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3233502677
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3885777692
Short name T625
Test name
Test status
Simulation time 23533568481 ps
CPU time 36.45 seconds
Started Aug 05 06:30:00 PM PDT 24
Finished Aug 05 06:30:36 PM PDT 24
Peak memory 240860 kb
Host smart-02260339-e31d-4880-a08e-5991196a868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885777692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3885777692
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3108704965
Short name T167
Test name
Test status
Simulation time 3873442394 ps
CPU time 42.07 seconds
Started Aug 05 06:29:58 PM PDT 24
Finished Aug 05 06:30:40 PM PDT 24
Peak memory 240400 kb
Host smart-be049127-5082-4179-bff5-1e6c8c7e713d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108704965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3108704965
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2662822199
Short name T805
Test name
Test status
Simulation time 60195861 ps
CPU time 2.56 seconds
Started Aug 05 06:29:58 PM PDT 24
Finished Aug 05 06:30:01 PM PDT 24
Peak memory 233256 kb
Host smart-ed1537fd-a6bd-4e9f-95e2-c7f362858623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662822199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2662822199
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1875656817
Short name T337
Test name
Test status
Simulation time 22860696 ps
CPU time 0.81 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:29:54 PM PDT 24
Peak memory 216372 kb
Host smart-0315c17e-3d2a-4892-b11b-43d8a8c27a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875656817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1875656817
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1444551075
Short name T347
Test name
Test status
Simulation time 174888006 ps
CPU time 4.05 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:29:57 PM PDT 24
Peak memory 224964 kb
Host smart-796a92c4-161b-4077-bdf3-88b64dc722e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444551075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1444551075
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2881694119
Short name T246
Test name
Test status
Simulation time 1384808477 ps
CPU time 9.13 seconds
Started Aug 05 06:29:54 PM PDT 24
Finished Aug 05 06:30:04 PM PDT 24
Peak memory 239744 kb
Host smart-a14d056f-5410-4a28-82e6-79cc7a0ffb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881694119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2881694119
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.186968518
Short name T931
Test name
Test status
Simulation time 3760394654 ps
CPU time 6.72 seconds
Started Aug 05 06:29:57 PM PDT 24
Finished Aug 05 06:30:04 PM PDT 24
Peak memory 224984 kb
Host smart-d9c840f1-6424-4787-b629-c52cc3fb34fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186968518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.186968518
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3132575566
Short name T595
Test name
Test status
Simulation time 8256971870 ps
CPU time 22.95 seconds
Started Aug 05 06:29:57 PM PDT 24
Finished Aug 05 06:30:20 PM PDT 24
Peak memory 234240 kb
Host smart-0dc5fdfd-8f0a-4b69-9f95-8af2f2ec63e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132575566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3132575566
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1573260972
Short name T19
Test name
Test status
Simulation time 655141209 ps
CPU time 4.7 seconds
Started Aug 05 06:30:00 PM PDT 24
Finished Aug 05 06:30:05 PM PDT 24
Peak memory 223524 kb
Host smart-d6f2d078-97ec-45d4-93f9-442cf2bbab27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1573260972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1573260972
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.987522044
Short name T28
Test name
Test status
Simulation time 6083104634 ps
CPU time 79.01 seconds
Started Aug 05 06:30:00 PM PDT 24
Finished Aug 05 06:31:19 PM PDT 24
Peak memory 250664 kb
Host smart-17018a5d-d891-4acd-aca0-c2be1ec9b43d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987522044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.987522044
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1107213601
Short name T530
Test name
Test status
Simulation time 11204912318 ps
CPU time 10.83 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:30:04 PM PDT 24
Peak memory 216680 kb
Host smart-30eeb8cc-4d21-4485-87db-07e441ccbb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107213601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1107213601
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3528531880
Short name T700
Test name
Test status
Simulation time 6911212621 ps
CPU time 7.2 seconds
Started Aug 05 06:29:52 PM PDT 24
Finished Aug 05 06:30:00 PM PDT 24
Peak memory 216716 kb
Host smart-14573d63-77e9-4621-864a-2dddf8697271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528531880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3528531880
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2012703721
Short name T415
Test name
Test status
Simulation time 50197080 ps
CPU time 0.9 seconds
Started Aug 05 06:29:58 PM PDT 24
Finished Aug 05 06:29:59 PM PDT 24
Peak memory 207708 kb
Host smart-c4c105f1-1056-41af-87b8-1fd3904ac63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012703721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2012703721
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3036065843
Short name T611
Test name
Test status
Simulation time 56102575 ps
CPU time 0.82 seconds
Started Aug 05 06:29:53 PM PDT 24
Finished Aug 05 06:29:54 PM PDT 24
Peak memory 206344 kb
Host smart-24d0825d-4c9e-44b6-b761-d397a4f4db4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036065843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3036065843
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.59907759
Short name T842
Test name
Test status
Simulation time 8902365911 ps
CPU time 26.52 seconds
Started Aug 05 06:29:55 PM PDT 24
Finished Aug 05 06:30:22 PM PDT 24
Peak memory 237480 kb
Host smart-5bd9befa-dac5-4d4e-a318-fe1c5b2492f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59907759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.59907759
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2260085137
Short name T538
Test name
Test status
Simulation time 18091362 ps
CPU time 0.72 seconds
Started Aug 05 06:27:41 PM PDT 24
Finished Aug 05 06:27:42 PM PDT 24
Peak memory 205248 kb
Host smart-8569cd03-804a-4a54-badc-b2746de8590a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260085137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
260085137
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1168505676
Short name T628
Test name
Test status
Simulation time 181452212 ps
CPU time 3.68 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:27:38 PM PDT 24
Peak memory 233144 kb
Host smart-b36b44f1-010f-4f4e-9f56-2bf333946a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168505676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1168505676
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2001563937
Short name T764
Test name
Test status
Simulation time 35897213 ps
CPU time 0.82 seconds
Started Aug 05 06:27:35 PM PDT 24
Finished Aug 05 06:27:36 PM PDT 24
Peak memory 207044 kb
Host smart-1c311002-94b5-4848-abc0-5a1cd973b9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001563937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2001563937
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.707788887
Short name T815
Test name
Test status
Simulation time 51381608000 ps
CPU time 359.03 seconds
Started Aug 05 06:27:42 PM PDT 24
Finished Aug 05 06:33:42 PM PDT 24
Peak memory 254640 kb
Host smart-7b5fba86-ea51-47b2-bc85-05476e955a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707788887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.707788887
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3969462668
Short name T794
Test name
Test status
Simulation time 16814878893 ps
CPU time 85.67 seconds
Started Aug 05 06:27:43 PM PDT 24
Finished Aug 05 06:29:08 PM PDT 24
Peak memory 256728 kb
Host smart-5391890b-8957-4d25-a9f5-3ff56892eacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969462668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3969462668
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2504810587
Short name T199
Test name
Test status
Simulation time 69786835976 ps
CPU time 176.89 seconds
Started Aug 05 06:27:40 PM PDT 24
Finished Aug 05 06:30:37 PM PDT 24
Peak memory 257840 kb
Host smart-972f917c-2698-48ad-8343-6b5ee0fb4f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504810587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2504810587
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.552197470
Short name T478
Test name
Test status
Simulation time 7783226862 ps
CPU time 9.98 seconds
Started Aug 05 06:27:40 PM PDT 24
Finished Aug 05 06:27:50 PM PDT 24
Peak memory 234512 kb
Host smart-1414e0b6-dfd4-4238-96be-434e0394a311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552197470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.552197470
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.603536331
Short name T909
Test name
Test status
Simulation time 26723942004 ps
CPU time 59.39 seconds
Started Aug 05 06:27:36 PM PDT 24
Finished Aug 05 06:28:35 PM PDT 24
Peak memory 251928 kb
Host smart-48025d4d-133e-4b3b-bbf0-66f1106c50ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603536331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
603536331
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3775753512
Short name T511
Test name
Test status
Simulation time 31196297 ps
CPU time 2.38 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:27:36 PM PDT 24
Peak memory 232864 kb
Host smart-7fbe1b24-46aa-4301-93cd-702f6359de40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775753512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3775753512
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3172519667
Short name T661
Test name
Test status
Simulation time 7001850538 ps
CPU time 22.36 seconds
Started Aug 05 06:27:37 PM PDT 24
Finished Aug 05 06:27:59 PM PDT 24
Peak memory 249896 kb
Host smart-bd460fa5-233b-4df4-8481-fb473b1d6f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172519667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3172519667
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3564740430
Short name T285
Test name
Test status
Simulation time 40713475903 ps
CPU time 12.71 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:27:47 PM PDT 24
Peak memory 233120 kb
Host smart-0ed4f778-ad95-40fe-95e9-b96ef8dd1f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564740430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3564740430
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2755163960
Short name T922
Test name
Test status
Simulation time 157862879 ps
CPU time 2.48 seconds
Started Aug 05 06:27:40 PM PDT 24
Finished Aug 05 06:27:42 PM PDT 24
Peak memory 233140 kb
Host smart-77fcf3b8-e583-4786-88dd-980856513086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755163960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2755163960
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3072047100
Short name T501
Test name
Test status
Simulation time 1629054313 ps
CPU time 8.9 seconds
Started Aug 05 06:27:42 PM PDT 24
Finished Aug 05 06:27:51 PM PDT 24
Peak memory 219352 kb
Host smart-e73c1592-bc01-4d37-b186-ec4452aa6afd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3072047100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3072047100
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3751728864
Short name T75
Test name
Test status
Simulation time 297263155 ps
CPU time 1 seconds
Started Aug 05 06:27:39 PM PDT 24
Finished Aug 05 06:27:40 PM PDT 24
Peak memory 236264 kb
Host smart-0150569c-128a-4368-9d12-896eea8b51f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751728864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3751728864
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.119001739
Short name T373
Test name
Test status
Simulation time 119999820 ps
CPU time 0.88 seconds
Started Aug 05 06:27:40 PM PDT 24
Finished Aug 05 06:27:41 PM PDT 24
Peak memory 207352 kb
Host smart-ea39267e-fe58-4d85-b46d-efd0d7e887a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119001739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.119001739
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1904401107
Short name T745
Test name
Test status
Simulation time 3494951368 ps
CPU time 11.4 seconds
Started Aug 05 06:27:35 PM PDT 24
Finished Aug 05 06:27:46 PM PDT 24
Peak memory 220260 kb
Host smart-43a65f98-5586-411e-85a9-abcc2ca4ab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904401107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1904401107
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3566609355
Short name T810
Test name
Test status
Simulation time 142524950 ps
CPU time 1.79 seconds
Started Aug 05 06:27:33 PM PDT 24
Finished Aug 05 06:27:35 PM PDT 24
Peak memory 208188 kb
Host smart-f4017db2-6f79-404e-b39a-b5e29060fec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566609355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3566609355
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4089502775
Short name T64
Test name
Test status
Simulation time 204663495 ps
CPU time 6.37 seconds
Started Aug 05 06:27:35 PM PDT 24
Finished Aug 05 06:27:42 PM PDT 24
Peak memory 216676 kb
Host smart-89b5a77f-a63f-4ae6-aec7-56209219f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089502775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4089502775
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3626033519
Short name T507
Test name
Test status
Simulation time 52204542 ps
CPU time 0.86 seconds
Started Aug 05 06:27:33 PM PDT 24
Finished Aug 05 06:27:34 PM PDT 24
Peak memory 206352 kb
Host smart-d970be4f-6388-474d-b621-c834ffb13ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626033519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3626033519
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.824628049
Short name T1003
Test name
Test status
Simulation time 14457269086 ps
CPU time 13.9 seconds
Started Aug 05 06:27:34 PM PDT 24
Finished Aug 05 06:27:48 PM PDT 24
Peak memory 233216 kb
Host smart-89e1b17b-55d7-4ea1-ab10-df9c756b11f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824628049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.824628049
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.638746712
Short name T566
Test name
Test status
Simulation time 13735877 ps
CPU time 0.74 seconds
Started Aug 05 06:30:01 PM PDT 24
Finished Aug 05 06:30:02 PM PDT 24
Peak memory 205796 kb
Host smart-e5076fda-1a3e-48c0-9b4e-d855a891a2c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638746712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.638746712
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4245716890
Short name T89
Test name
Test status
Simulation time 247019053 ps
CPU time 2.83 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:30:07 PM PDT 24
Peak memory 224980 kb
Host smart-2898a7b5-0bb8-4c0d-9422-df8b1c453af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245716890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4245716890
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2645688755
Short name T887
Test name
Test status
Simulation time 19953244 ps
CPU time 0.83 seconds
Started Aug 05 06:30:02 PM PDT 24
Finished Aug 05 06:30:02 PM PDT 24
Peak memory 206976 kb
Host smart-dd3e94c8-5dc4-40cc-893b-d1fd5bd10e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645688755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2645688755
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.884565844
Short name T417
Test name
Test status
Simulation time 192839523 ps
CPU time 3.77 seconds
Started Aug 05 06:30:00 PM PDT 24
Finished Aug 05 06:30:04 PM PDT 24
Peak memory 225052 kb
Host smart-7313ce3f-c68c-4b65-bf5f-40fd49229ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884565844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.884565844
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2068160685
Short name T540
Test name
Test status
Simulation time 66167490182 ps
CPU time 136.16 seconds
Started Aug 05 06:29:57 PM PDT 24
Finished Aug 05 06:32:14 PM PDT 24
Peak memory 249612 kb
Host smart-851383ac-bc92-48f5-bf8c-55fc8d2a127e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068160685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2068160685
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3268593415
Short name T765
Test name
Test status
Simulation time 5310621103 ps
CPU time 118.09 seconds
Started Aug 05 06:30:01 PM PDT 24
Finished Aug 05 06:31:59 PM PDT 24
Peak memory 254760 kb
Host smart-b1c30cfd-3837-4b8f-8031-cf5372fa94eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268593415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3268593415
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.24166760
Short name T514
Test name
Test status
Simulation time 57209533 ps
CPU time 2.86 seconds
Started Aug 05 06:29:58 PM PDT 24
Finished Aug 05 06:30:01 PM PDT 24
Peak memory 233084 kb
Host smart-11e016e6-fadf-4441-8bf6-5a615146487f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24166760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.24166760
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.4070585831
Short name T92
Test name
Test status
Simulation time 3034665903 ps
CPU time 42.5 seconds
Started Aug 05 06:30:01 PM PDT 24
Finished Aug 05 06:30:44 PM PDT 24
Peak memory 264840 kb
Host smart-9752af4c-aeee-4d2a-9a1e-31b67684033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070585831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.4070585831
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1489709889
Short name T828
Test name
Test status
Simulation time 441633685 ps
CPU time 4.46 seconds
Started Aug 05 06:29:57 PM PDT 24
Finished Aug 05 06:30:02 PM PDT 24
Peak memory 233128 kb
Host smart-6105a1bf-fc89-41a8-a453-36f1385377a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489709889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1489709889
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3435315398
Short name T694
Test name
Test status
Simulation time 1334941054 ps
CPU time 15.39 seconds
Started Aug 05 06:29:57 PM PDT 24
Finished Aug 05 06:30:13 PM PDT 24
Peak memory 224972 kb
Host smart-837a4220-0557-432d-8ce1-c484c47060cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435315398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3435315398
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3065047175
Short name T447
Test name
Test status
Simulation time 34139678 ps
CPU time 2.45 seconds
Started Aug 05 06:29:58 PM PDT 24
Finished Aug 05 06:30:00 PM PDT 24
Peak memory 232844 kb
Host smart-0a4b5d26-6be0-4aad-bd4d-b9a97b4a7364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065047175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3065047175
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3662582640
Short name T733
Test name
Test status
Simulation time 2108593356 ps
CPU time 8.65 seconds
Started Aug 05 06:29:59 PM PDT 24
Finished Aug 05 06:30:08 PM PDT 24
Peak memory 224940 kb
Host smart-a8d26316-2ddf-4b82-b26d-ebf62c17ed33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662582640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3662582640
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3479515445
Short name T139
Test name
Test status
Simulation time 534686146 ps
CPU time 6.36 seconds
Started Aug 05 06:30:01 PM PDT 24
Finished Aug 05 06:30:08 PM PDT 24
Peak memory 222392 kb
Host smart-5e20846c-4efa-4e27-a106-70fda99d09e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3479515445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3479515445
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2719418494
Short name T771
Test name
Test status
Simulation time 3037569714 ps
CPU time 13.81 seconds
Started Aug 05 06:29:57 PM PDT 24
Finished Aug 05 06:30:11 PM PDT 24
Peak memory 216920 kb
Host smart-4dc45024-02f5-4f77-a7a8-8005f503bb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719418494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2719418494
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1280962446
Short name T462
Test name
Test status
Simulation time 5904855629 ps
CPU time 6.76 seconds
Started Aug 05 06:29:58 PM PDT 24
Finished Aug 05 06:30:05 PM PDT 24
Peak memory 216692 kb
Host smart-4f98f5fa-26cb-487b-bd75-50ec2aabee31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280962446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1280962446
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1704561401
Short name T515
Test name
Test status
Simulation time 76466066 ps
CPU time 1.37 seconds
Started Aug 05 06:29:59 PM PDT 24
Finished Aug 05 06:30:01 PM PDT 24
Peak memory 216672 kb
Host smart-132252b9-313a-4e87-9e2f-35b9646c689e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704561401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1704561401
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3343286576
Short name T693
Test name
Test status
Simulation time 146163892 ps
CPU time 0.93 seconds
Started Aug 05 06:29:58 PM PDT 24
Finished Aug 05 06:29:59 PM PDT 24
Peak memory 207412 kb
Host smart-be6565a8-7773-4691-acf9-75a09e27a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343286576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3343286576
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.960228090
Short name T247
Test name
Test status
Simulation time 396937434 ps
CPU time 3.69 seconds
Started Aug 05 06:30:00 PM PDT 24
Finished Aug 05 06:30:04 PM PDT 24
Peak memory 241240 kb
Host smart-a520d830-2c88-4325-988c-ee78603d7c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960228090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.960228090
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4194307741
Short name T492
Test name
Test status
Simulation time 12053585 ps
CPU time 0.67 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:30:05 PM PDT 24
Peak memory 205248 kb
Host smart-8674badc-6c40-4653-bde9-c6cdb20efeb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194307741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4194307741
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.278793551
Short name T743
Test name
Test status
Simulation time 3928357455 ps
CPU time 11.45 seconds
Started Aug 05 06:29:59 PM PDT 24
Finished Aug 05 06:30:11 PM PDT 24
Peak memory 224992 kb
Host smart-37c88ea4-808c-4a4f-ab13-ca5cd88f5e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278793551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.278793551
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1101790880
Short name T558
Test name
Test status
Simulation time 28423147 ps
CPU time 0.79 seconds
Started Aug 05 06:30:06 PM PDT 24
Finished Aug 05 06:30:06 PM PDT 24
Peak memory 207036 kb
Host smart-72cf7ee2-04bb-434d-a1b2-55be2803e019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101790880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1101790880
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3414332629
Short name T767
Test name
Test status
Simulation time 565706654 ps
CPU time 5.21 seconds
Started Aug 05 06:30:05 PM PDT 24
Finished Aug 05 06:30:10 PM PDT 24
Peak memory 235272 kb
Host smart-03720420-fc0f-4fbc-b569-1a444d3ec618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414332629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3414332629
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2278400295
Short name T292
Test name
Test status
Simulation time 53148471106 ps
CPU time 139 seconds
Started Aug 05 06:30:03 PM PDT 24
Finished Aug 05 06:32:22 PM PDT 24
Peak memory 249532 kb
Host smart-982b7a96-0559-4abb-97f1-6a01c3f5509a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278400295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2278400295
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2357134259
Short name T970
Test name
Test status
Simulation time 39006164264 ps
CPU time 124.71 seconds
Started Aug 05 06:30:07 PM PDT 24
Finished Aug 05 06:32:12 PM PDT 24
Peak memory 257816 kb
Host smart-2e7c35ac-1398-4821-b70a-00aca512c835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357134259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2357134259
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1415257435
Short name T162
Test name
Test status
Simulation time 7763831776 ps
CPU time 32.34 seconds
Started Aug 05 06:30:01 PM PDT 24
Finished Aug 05 06:30:33 PM PDT 24
Peak memory 233308 kb
Host smart-ebddae7d-14cb-4d57-8a41-9d8f7df6118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415257435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1415257435
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.415145108
Short name T47
Test name
Test status
Simulation time 77380320101 ps
CPU time 286.94 seconds
Started Aug 05 06:30:03 PM PDT 24
Finished Aug 05 06:34:50 PM PDT 24
Peak memory 250604 kb
Host smart-77d16eca-0719-4641-b37e-083dfa3da5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415145108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.415145108
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2410025659
Short name T451
Test name
Test status
Simulation time 2123646964 ps
CPU time 18.58 seconds
Started Aug 05 06:29:59 PM PDT 24
Finished Aug 05 06:30:18 PM PDT 24
Peak memory 233192 kb
Host smart-fa3bab33-bc0d-43e2-a39b-2fd93fd2c42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410025659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2410025659
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3902743143
Short name T873
Test name
Test status
Simulation time 649648196 ps
CPU time 12.47 seconds
Started Aug 05 06:30:00 PM PDT 24
Finished Aug 05 06:30:13 PM PDT 24
Peak memory 224816 kb
Host smart-13fb4ecd-ea09-4e8a-8ee1-1b0419f684b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902743143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3902743143
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1339927639
Short name T293
Test name
Test status
Simulation time 5203225910 ps
CPU time 15.8 seconds
Started Aug 05 06:29:59 PM PDT 24
Finished Aug 05 06:30:15 PM PDT 24
Peak memory 224968 kb
Host smart-67218cdf-5849-41df-b44e-da117ef6101d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339927639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1339927639
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1145097826
Short name T653
Test name
Test status
Simulation time 1653570974 ps
CPU time 5.88 seconds
Started Aug 05 06:30:01 PM PDT 24
Finished Aug 05 06:30:07 PM PDT 24
Peak memory 233180 kb
Host smart-a372abcb-e084-478d-b05f-4088073b5fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145097826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1145097826
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2306171757
Short name T830
Test name
Test status
Simulation time 2710174830 ps
CPU time 8.97 seconds
Started Aug 05 06:30:03 PM PDT 24
Finished Aug 05 06:30:12 PM PDT 24
Peak memory 219532 kb
Host smart-79e285d0-671c-44e8-8147-ea9465fe590a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2306171757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2306171757
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1754062735
Short name T151
Test name
Test status
Simulation time 264378022 ps
CPU time 1.26 seconds
Started Aug 05 06:30:02 PM PDT 24
Finished Aug 05 06:30:03 PM PDT 24
Peak memory 207364 kb
Host smart-49b49f7a-77b2-4e52-ad81-f57a514b086b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754062735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1754062735
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1104141226
Short name T484
Test name
Test status
Simulation time 15227052 ps
CPU time 0.74 seconds
Started Aug 05 06:29:57 PM PDT 24
Finished Aug 05 06:29:58 PM PDT 24
Peak memory 206112 kb
Host smart-b95a5a68-3026-470e-9694-ca5845d3747f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104141226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1104141226
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3059369019
Short name T324
Test name
Test status
Simulation time 4344415487 ps
CPU time 5.75 seconds
Started Aug 05 06:30:01 PM PDT 24
Finished Aug 05 06:30:07 PM PDT 24
Peak memory 216636 kb
Host smart-113b122d-7f63-4b37-bda0-2fa13c7d734f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059369019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3059369019
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1243389556
Short name T386
Test name
Test status
Simulation time 130347312 ps
CPU time 1.83 seconds
Started Aug 05 06:30:00 PM PDT 24
Finished Aug 05 06:30:02 PM PDT 24
Peak memory 216484 kb
Host smart-c63635ba-5552-44ac-9b66-8cf0a32b4680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243389556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1243389556
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2832747315
Short name T475
Test name
Test status
Simulation time 31923488 ps
CPU time 0.73 seconds
Started Aug 05 06:29:58 PM PDT 24
Finished Aug 05 06:29:58 PM PDT 24
Peak memory 206348 kb
Host smart-74ef05ee-a1d0-4a69-9821-9b468dda9f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832747315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2832747315
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.104328296
Short name T973
Test name
Test status
Simulation time 9201744123 ps
CPU time 9.87 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:30:14 PM PDT 24
Peak memory 220420 kb
Host smart-a3b20d2c-8cc6-42f5-b51d-a419953708d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104328296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.104328296
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.649229906
Short name T432
Test name
Test status
Simulation time 13970552 ps
CPU time 0.7 seconds
Started Aug 05 06:30:05 PM PDT 24
Finished Aug 05 06:30:06 PM PDT 24
Peak memory 205852 kb
Host smart-b0594bd7-2e42-4814-8df5-ef0496b5ab7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649229906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.649229906
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3698090221
Short name T438
Test name
Test status
Simulation time 33471672 ps
CPU time 2.23 seconds
Started Aug 05 06:30:03 PM PDT 24
Finished Aug 05 06:30:05 PM PDT 24
Peak memory 232792 kb
Host smart-5de7dd95-7a68-4886-b8e9-a1613bfd88aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698090221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3698090221
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1546184622
Short name T379
Test name
Test status
Simulation time 53061207 ps
CPU time 0.87 seconds
Started Aug 05 06:30:05 PM PDT 24
Finished Aug 05 06:30:06 PM PDT 24
Peak memory 206972 kb
Host smart-41ccec8f-cc3b-4839-8af9-28ca1f8cbb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546184622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1546184622
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1768945092
Short name T463
Test name
Test status
Simulation time 65829944899 ps
CPU time 116.68 seconds
Started Aug 05 06:30:07 PM PDT 24
Finished Aug 05 06:32:04 PM PDT 24
Peak memory 257624 kb
Host smart-1258541e-6085-4935-bdfb-e63735262f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768945092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1768945092
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1423246533
Short name T583
Test name
Test status
Simulation time 21665698 ps
CPU time 0.85 seconds
Started Aug 05 06:30:06 PM PDT 24
Finished Aug 05 06:30:07 PM PDT 24
Peak memory 217596 kb
Host smart-c347eb5f-6cb8-4a88-9851-5546cdcbdeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423246533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1423246533
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1788676466
Short name T129
Test name
Test status
Simulation time 21300840215 ps
CPU time 140.59 seconds
Started Aug 05 06:30:03 PM PDT 24
Finished Aug 05 06:32:24 PM PDT 24
Peak memory 283452 kb
Host smart-86d8f65f-4830-45bb-a21c-373ab8c408b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788676466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1788676466
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1755560281
Short name T889
Test name
Test status
Simulation time 313656416 ps
CPU time 6.41 seconds
Started Aug 05 06:30:03 PM PDT 24
Finished Aug 05 06:30:09 PM PDT 24
Peak memory 233120 kb
Host smart-be0906e2-c5f4-44a3-8339-55c382f8af37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755560281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1755560281
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3071849495
Short name T870
Test name
Test status
Simulation time 28923158 ps
CPU time 0.83 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:30:05 PM PDT 24
Peak memory 216368 kb
Host smart-7d6d778c-6f4e-4c76-9c80-83cd4246abb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071849495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3071849495
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2583565765
Short name T634
Test name
Test status
Simulation time 412061437 ps
CPU time 4.66 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:30:09 PM PDT 24
Peak memory 224868 kb
Host smart-61c3cf53-670d-4c37-b23a-72782a8d7f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583565765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2583565765
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2821793953
Short name T495
Test name
Test status
Simulation time 613306613 ps
CPU time 9.54 seconds
Started Aug 05 06:30:02 PM PDT 24
Finished Aug 05 06:30:12 PM PDT 24
Peak memory 249528 kb
Host smart-4af9d6b3-377d-45fd-90b1-8220beab370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821793953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2821793953
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2236311840
Short name T739
Test name
Test status
Simulation time 1085930602 ps
CPU time 5.44 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:30:10 PM PDT 24
Peak memory 240180 kb
Host smart-72cdd136-f1c1-4b16-89af-c619ba3bab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236311840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2236311840
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.829324015
Short name T493
Test name
Test status
Simulation time 3161401081 ps
CPU time 5.73 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:30:10 PM PDT 24
Peak memory 224984 kb
Host smart-9390626d-9813-4710-8284-fd05eb4165b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829324015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.829324015
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2013925622
Short name T436
Test name
Test status
Simulation time 1801617409 ps
CPU time 23.38 seconds
Started Aug 05 06:30:07 PM PDT 24
Finished Aug 05 06:30:30 PM PDT 24
Peak memory 220896 kb
Host smart-c4b66c85-6f48-499e-99cb-cef0e70ec8f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2013925622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2013925622
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2111963381
Short name T21
Test name
Test status
Simulation time 21098126741 ps
CPU time 180.72 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:33:05 PM PDT 24
Peak memory 251036 kb
Host smart-597c6246-151b-43b2-98c9-fbc14a179ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111963381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2111963381
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2625985110
Short name T938
Test name
Test status
Simulation time 28973307119 ps
CPU time 37.94 seconds
Started Aug 05 06:30:03 PM PDT 24
Finished Aug 05 06:30:41 PM PDT 24
Peak memory 216704 kb
Host smart-31069844-b70f-42df-8e58-65f6b1b242df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625985110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2625985110
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.851289529
Short name T477
Test name
Test status
Simulation time 541848223 ps
CPU time 3.26 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:30:08 PM PDT 24
Peak memory 216588 kb
Host smart-b476c940-a0c6-4e55-82d3-89e1b4357e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851289529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.851289529
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1647332523
Short name T965
Test name
Test status
Simulation time 110884024 ps
CPU time 1.46 seconds
Started Aug 05 06:30:07 PM PDT 24
Finished Aug 05 06:30:09 PM PDT 24
Peak memory 216680 kb
Host smart-a3922338-30b3-458c-bca9-5e74e7e86d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647332523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1647332523
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.436597268
Short name T411
Test name
Test status
Simulation time 262983145 ps
CPU time 0.79 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:30:05 PM PDT 24
Peak memory 206364 kb
Host smart-1dba6a2d-b491-4486-be0b-4d2ca54201cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436597268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.436597268
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2554918540
Short name T557
Test name
Test status
Simulation time 610139241 ps
CPU time 3.44 seconds
Started Aug 05 06:30:04 PM PDT 24
Finished Aug 05 06:30:08 PM PDT 24
Peak memory 236808 kb
Host smart-ccb45e7a-333b-4df8-84be-b0e5972b19ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554918540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2554918540
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1043858041
Short name T537
Test name
Test status
Simulation time 15606888 ps
CPU time 0.74 seconds
Started Aug 05 06:30:14 PM PDT 24
Finished Aug 05 06:30:14 PM PDT 24
Peak memory 206136 kb
Host smart-d0e4ecd1-a91f-4a58-bd43-55101cedd7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043858041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1043858041
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2754231033
Short name T593
Test name
Test status
Simulation time 382412763 ps
CPU time 2.38 seconds
Started Aug 05 06:30:10 PM PDT 24
Finished Aug 05 06:30:12 PM PDT 24
Peak memory 233044 kb
Host smart-c5888eea-010c-437d-a2f9-03c647d7777d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754231033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2754231033
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3837039457
Short name T359
Test name
Test status
Simulation time 16185383 ps
CPU time 0.78 seconds
Started Aug 05 06:30:10 PM PDT 24
Finished Aug 05 06:30:11 PM PDT 24
Peak memory 207004 kb
Host smart-16690726-182c-4f21-b882-7f8c676bf2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837039457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3837039457
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2466862302
Short name T636
Test name
Test status
Simulation time 16308643412 ps
CPU time 131.34 seconds
Started Aug 05 06:30:10 PM PDT 24
Finished Aug 05 06:32:22 PM PDT 24
Peak memory 249588 kb
Host smart-f57bc487-08d0-4ef1-beef-cd1fd4c99493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466862302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2466862302
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.965280094
Short name T673
Test name
Test status
Simulation time 31976316361 ps
CPU time 106.63 seconds
Started Aug 05 06:30:21 PM PDT 24
Finished Aug 05 06:32:08 PM PDT 24
Peak memory 264864 kb
Host smart-091b9bdd-a42a-4765-866b-46dd527227e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965280094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.965280094
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2785666743
Short name T880
Test name
Test status
Simulation time 7784814876 ps
CPU time 126.81 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:32:27 PM PDT 24
Peak memory 251740 kb
Host smart-1d6e75ed-c293-46b2-8406-a4e8799ef740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785666743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2785666743
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3348378761
Short name T806
Test name
Test status
Simulation time 10574003605 ps
CPU time 35.59 seconds
Started Aug 05 06:30:09 PM PDT 24
Finished Aug 05 06:30:45 PM PDT 24
Peak memory 233200 kb
Host smart-01a8b689-2047-4c97-a109-89abb7d01e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348378761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3348378761
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.573225659
Short name T499
Test name
Test status
Simulation time 532146699 ps
CPU time 9.44 seconds
Started Aug 05 06:30:09 PM PDT 24
Finished Aug 05 06:30:18 PM PDT 24
Peak memory 233152 kb
Host smart-2c0bcfb3-482a-4c16-824b-175459a023ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573225659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.573225659
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2082918867
Short name T925
Test name
Test status
Simulation time 9535446409 ps
CPU time 20.98 seconds
Started Aug 05 06:30:08 PM PDT 24
Finished Aug 05 06:30:29 PM PDT 24
Peak memory 233196 kb
Host smart-186bbdab-15f8-4954-9694-34759bbb1fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082918867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2082918867
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3441278214
Short name T608
Test name
Test status
Simulation time 9683802022 ps
CPU time 49.21 seconds
Started Aug 05 06:30:10 PM PDT 24
Finished Aug 05 06:31:00 PM PDT 24
Peak memory 234032 kb
Host smart-d40e73d9-b33c-4f8f-b351-765ba70458f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441278214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3441278214
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3262224658
Short name T259
Test name
Test status
Simulation time 3951664343 ps
CPU time 16.83 seconds
Started Aug 05 06:30:10 PM PDT 24
Finished Aug 05 06:30:27 PM PDT 24
Peak memory 238528 kb
Host smart-0c3e259d-fc7b-4e44-b609-78fb75551c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262224658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3262224658
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.925501582
Short name T237
Test name
Test status
Simulation time 828889152 ps
CPU time 4.78 seconds
Started Aug 05 06:30:09 PM PDT 24
Finished Aug 05 06:30:14 PM PDT 24
Peak memory 237696 kb
Host smart-b83b86ed-2aca-4d9f-89f0-6a8f41aae4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925501582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.925501582
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2381689522
Short name T408
Test name
Test status
Simulation time 1095199139 ps
CPU time 10.42 seconds
Started Aug 05 06:30:09 PM PDT 24
Finished Aug 05 06:30:19 PM PDT 24
Peak memory 222908 kb
Host smart-cd75409d-ded5-4d70-9250-6dd550c85600
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2381689522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2381689522
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.795925636
Short name T606
Test name
Test status
Simulation time 463972175 ps
CPU time 1.21 seconds
Started Aug 05 06:30:22 PM PDT 24
Finished Aug 05 06:30:23 PM PDT 24
Peak memory 207344 kb
Host smart-cfea4b71-d201-4cd0-9922-4a02ccb5943c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795925636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.795925636
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2976981688
Short name T481
Test name
Test status
Simulation time 1581175248 ps
CPU time 9.74 seconds
Started Aug 05 06:30:10 PM PDT 24
Finished Aug 05 06:30:20 PM PDT 24
Peak memory 216704 kb
Host smart-b63b6466-b0d6-46c8-89a1-f89f15f03bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976981688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2976981688
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4114082219
Short name T335
Test name
Test status
Simulation time 377437818 ps
CPU time 3.35 seconds
Started Aug 05 06:30:12 PM PDT 24
Finished Aug 05 06:30:15 PM PDT 24
Peak memory 216788 kb
Host smart-0e009929-ef69-4104-b26c-4e22cffa1872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114082219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4114082219
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2108814394
Short name T374
Test name
Test status
Simulation time 24867500 ps
CPU time 1 seconds
Started Aug 05 06:30:09 PM PDT 24
Finished Aug 05 06:30:10 PM PDT 24
Peak memory 207784 kb
Host smart-4950f786-d55e-4cb1-b834-806b6062dcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108814394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2108814394
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1538010612
Short name T768
Test name
Test status
Simulation time 119705239 ps
CPU time 0.91 seconds
Started Aug 05 06:30:08 PM PDT 24
Finished Aug 05 06:30:09 PM PDT 24
Peak memory 206364 kb
Host smart-eab4b389-6157-49c6-ada4-ef753cde4a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538010612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1538010612
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3216956382
Short name T930
Test name
Test status
Simulation time 3853562488 ps
CPU time 5.41 seconds
Started Aug 05 06:30:10 PM PDT 24
Finished Aug 05 06:30:15 PM PDT 24
Peak memory 224916 kb
Host smart-c66df815-990d-4e3f-8d68-dd0f66d903ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216956382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3216956382
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3903493327
Short name T929
Test name
Test status
Simulation time 26564043 ps
CPU time 0.7 seconds
Started Aug 05 06:30:19 PM PDT 24
Finished Aug 05 06:30:20 PM PDT 24
Peak memory 205840 kb
Host smart-7c438c38-d12d-4bfc-9ed1-84549338dd22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903493327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3903493327
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3313992541
Short name T902
Test name
Test status
Simulation time 353198074 ps
CPU time 3.42 seconds
Started Aug 05 06:30:15 PM PDT 24
Finished Aug 05 06:30:18 PM PDT 24
Peak memory 224856 kb
Host smart-069d4922-6534-4796-b082-cd7109527db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313992541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3313992541
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1344084804
Short name T704
Test name
Test status
Simulation time 62745239 ps
CPU time 0.79 seconds
Started Aug 05 06:30:22 PM PDT 24
Finished Aug 05 06:30:23 PM PDT 24
Peak memory 206980 kb
Host smart-85989f69-c473-4cd6-a73a-2f9e2903b61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344084804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1344084804
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.678958819
Short name T216
Test name
Test status
Simulation time 1615233951 ps
CPU time 23.41 seconds
Started Aug 05 06:30:12 PM PDT 24
Finished Aug 05 06:30:36 PM PDT 24
Peak memory 249528 kb
Host smart-8c0013ce-acef-46ac-98fa-4d48238c8a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678958819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.678958819
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.618998070
Short name T31
Test name
Test status
Simulation time 29478236630 ps
CPU time 135.42 seconds
Started Aug 05 06:30:22 PM PDT 24
Finished Aug 05 06:32:37 PM PDT 24
Peak memory 257884 kb
Host smart-0aa4ff22-ea85-4a11-9306-2063d0a23c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618998070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.618998070
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2714768425
Short name T850
Test name
Test status
Simulation time 1142417115 ps
CPU time 10.15 seconds
Started Aug 05 06:30:22 PM PDT 24
Finished Aug 05 06:30:32 PM PDT 24
Peak memory 233264 kb
Host smart-2de173e0-5efd-4eec-99a8-50b444979214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714768425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2714768425
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.975743446
Short name T569
Test name
Test status
Simulation time 1316984652 ps
CPU time 5.92 seconds
Started Aug 05 06:30:15 PM PDT 24
Finished Aug 05 06:30:21 PM PDT 24
Peak memory 237260 kb
Host smart-b0472beb-82cb-45fd-919d-c0dcd458a93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975743446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.975743446
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.669250192
Short name T782
Test name
Test status
Simulation time 1362104319 ps
CPU time 4.03 seconds
Started Aug 05 06:30:16 PM PDT 24
Finished Aug 05 06:30:20 PM PDT 24
Peak memory 224976 kb
Host smart-5d27a0ee-55c1-43ce-81fb-f2143426c2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669250192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.669250192
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2427247116
Short name T239
Test name
Test status
Simulation time 310556478 ps
CPU time 4.66 seconds
Started Aug 05 06:30:15 PM PDT 24
Finished Aug 05 06:30:20 PM PDT 24
Peak memory 233148 kb
Host smart-184605d6-8e3e-40a2-8124-b4d22ac08be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427247116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2427247116
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3276412443
Short name T559
Test name
Test status
Simulation time 31483836 ps
CPU time 2.51 seconds
Started Aug 05 06:30:15 PM PDT 24
Finished Aug 05 06:30:18 PM PDT 24
Peak memory 232820 kb
Host smart-2aabcc1f-13d2-42ae-ae6a-ff6fd6c70eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276412443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3276412443
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2969873134
Short name T440
Test name
Test status
Simulation time 7725889682 ps
CPU time 7.38 seconds
Started Aug 05 06:30:14 PM PDT 24
Finished Aug 05 06:30:21 PM PDT 24
Peak memory 233196 kb
Host smart-61442ff8-8faf-4311-99b1-6899f34ca79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969873134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2969873134
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1510841369
Short name T395
Test name
Test status
Simulation time 560338858 ps
CPU time 5.09 seconds
Started Aug 05 06:30:14 PM PDT 24
Finished Aug 05 06:30:19 PM PDT 24
Peak memory 223044 kb
Host smart-6b707ba3-5ead-429e-9031-d072004f2434
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1510841369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1510841369
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.739044059
Short name T594
Test name
Test status
Simulation time 27382514025 ps
CPU time 160.84 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:33:01 PM PDT 24
Peak memory 250564 kb
Host smart-0ac193bb-a7eb-421b-88c3-e18500ca8a87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739044059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.739044059
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3407602308
Short name T580
Test name
Test status
Simulation time 3853015925 ps
CPU time 24.18 seconds
Started Aug 05 06:30:22 PM PDT 24
Finished Aug 05 06:30:46 PM PDT 24
Peak memory 216800 kb
Host smart-ccd67423-3e30-4a5c-abb4-d053ded7e99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407602308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3407602308
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2640920556
Short name T734
Test name
Test status
Simulation time 1967946080 ps
CPU time 8.62 seconds
Started Aug 05 06:30:15 PM PDT 24
Finished Aug 05 06:30:24 PM PDT 24
Peak memory 216576 kb
Host smart-31931bdf-cb8e-4a67-8c36-741e9f548cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640920556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2640920556
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.168726703
Short name T678
Test name
Test status
Simulation time 333385888 ps
CPU time 1.46 seconds
Started Aug 05 06:30:13 PM PDT 24
Finished Aug 05 06:30:15 PM PDT 24
Peak memory 216708 kb
Host smart-a470cb1d-0204-42fb-ac33-8e945e730cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168726703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.168726703
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2379540381
Short name T333
Test name
Test status
Simulation time 255806846 ps
CPU time 0.95 seconds
Started Aug 05 06:30:15 PM PDT 24
Finished Aug 05 06:30:16 PM PDT 24
Peak memory 206320 kb
Host smart-0cb30846-fd1f-43a9-bb8d-8dc8382eb207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379540381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2379540381
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.539030735
Short name T967
Test name
Test status
Simulation time 19049418424 ps
CPU time 11.48 seconds
Started Aug 05 06:30:13 PM PDT 24
Finished Aug 05 06:30:25 PM PDT 24
Peak memory 233120 kb
Host smart-579ebda7-715c-4dac-9e57-a78ade4ed8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539030735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.539030735
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2453694948
Short name T980
Test name
Test status
Simulation time 44400226 ps
CPU time 0.76 seconds
Started Aug 05 06:30:18 PM PDT 24
Finished Aug 05 06:30:19 PM PDT 24
Peak memory 206192 kb
Host smart-36e391c9-415d-4886-8568-fb2bc4955608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453694948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2453694948
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2885045449
Short name T235
Test name
Test status
Simulation time 1631307008 ps
CPU time 6.13 seconds
Started Aug 05 06:30:19 PM PDT 24
Finished Aug 05 06:30:25 PM PDT 24
Peak memory 224904 kb
Host smart-407b6866-8975-495a-867b-0a2691864b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885045449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2885045449
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1718748053
Short name T784
Test name
Test status
Simulation time 45321154 ps
CPU time 0.72 seconds
Started Aug 05 06:30:16 PM PDT 24
Finished Aug 05 06:30:17 PM PDT 24
Peak memory 206272 kb
Host smart-29fd96f3-af1f-4450-84ab-b755e9c5f8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718748053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1718748053
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3108542988
Short name T188
Test name
Test status
Simulation time 4530440913 ps
CPU time 33.94 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:30:54 PM PDT 24
Peak memory 252576 kb
Host smart-341a53a3-a042-46d2-bd86-fe3bfca37ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108542988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3108542988
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4069560010
Short name T498
Test name
Test status
Simulation time 43651659327 ps
CPU time 236.96 seconds
Started Aug 05 06:30:19 PM PDT 24
Finished Aug 05 06:34:16 PM PDT 24
Peak memory 254788 kb
Host smart-dcd89e89-d5cf-4966-99ce-3b2e732ed26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069560010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4069560010
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1575024401
Short name T987
Test name
Test status
Simulation time 781766290 ps
CPU time 4.31 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:30:24 PM PDT 24
Peak memory 233156 kb
Host smart-033dd63f-bbae-4f18-9bc5-cd84257368b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575024401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1575024401
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3618171826
Short name T677
Test name
Test status
Simulation time 1001995317 ps
CPU time 14.37 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:30:35 PM PDT 24
Peak memory 233180 kb
Host smart-ce43cbbb-8a7c-4b5e-ae71-85c7646c7b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618171826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3618171826
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.987788186
Short name T772
Test name
Test status
Simulation time 212765208 ps
CPU time 2.45 seconds
Started Aug 05 06:30:14 PM PDT 24
Finished Aug 05 06:30:17 PM PDT 24
Peak memory 224816 kb
Host smart-b062b610-5205-4b8b-887f-9fb6b9810e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987788186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.987788186
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1297509450
Short name T48
Test name
Test status
Simulation time 33767784 ps
CPU time 2.28 seconds
Started Aug 05 06:30:18 PM PDT 24
Finished Aug 05 06:30:20 PM PDT 24
Peak memory 232840 kb
Host smart-8c20e151-c7f3-4c82-b202-6b1bad03504a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297509450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1297509450
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1612052022
Short name T602
Test name
Test status
Simulation time 958815281 ps
CPU time 4.76 seconds
Started Aug 05 06:30:19 PM PDT 24
Finished Aug 05 06:30:24 PM PDT 24
Peak memory 241032 kb
Host smart-7568b701-aca9-4816-9715-689b48472d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612052022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1612052022
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1982957409
Short name T520
Test name
Test status
Simulation time 364385226 ps
CPU time 6.08 seconds
Started Aug 05 06:30:15 PM PDT 24
Finished Aug 05 06:30:22 PM PDT 24
Peak memory 233020 kb
Host smart-e5b4b18c-9a0b-48bd-b154-936a05693053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982957409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1982957409
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.477030441
Short name T609
Test name
Test status
Simulation time 1207430764 ps
CPU time 5.78 seconds
Started Aug 05 06:30:19 PM PDT 24
Finished Aug 05 06:30:24 PM PDT 24
Peak memory 223004 kb
Host smart-37c86649-7d88-427a-b2d3-7f494fb7c651
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=477030441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.477030441
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2430463061
Short name T457
Test name
Test status
Simulation time 25100209007 ps
CPU time 89.14 seconds
Started Aug 05 06:30:19 PM PDT 24
Finished Aug 05 06:31:48 PM PDT 24
Peak memory 255016 kb
Host smart-b571547c-735d-4d2b-9e69-2e94c0d26f6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430463061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2430463061
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1871290182
Short name T300
Test name
Test status
Simulation time 3822191579 ps
CPU time 8.85 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:30:29 PM PDT 24
Peak memory 220588 kb
Host smart-9ed690f9-ddbe-4da1-b4de-fedbdc15b572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871290182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1871290182
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1347574565
Short name T726
Test name
Test status
Simulation time 3607592073 ps
CPU time 10.82 seconds
Started Aug 05 06:30:13 PM PDT 24
Finished Aug 05 06:30:24 PM PDT 24
Peak memory 216904 kb
Host smart-811418eb-5814-4706-8220-9146867e3df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347574565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1347574565
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.734128833
Short name T399
Test name
Test status
Simulation time 412321628 ps
CPU time 1.9 seconds
Started Aug 05 06:30:15 PM PDT 24
Finished Aug 05 06:30:17 PM PDT 24
Peak memory 216660 kb
Host smart-7038e064-6dd3-4f2d-82b8-026a03d302d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734128833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.734128833
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2720873344
Short name T916
Test name
Test status
Simulation time 34004912 ps
CPU time 0.72 seconds
Started Aug 05 06:30:15 PM PDT 24
Finished Aug 05 06:30:16 PM PDT 24
Peak memory 205968 kb
Host smart-862bd872-06fa-4576-833a-eb67cea37e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720873344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2720873344
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2155245576
Short name T658
Test name
Test status
Simulation time 344994560 ps
CPU time 2.21 seconds
Started Aug 05 06:30:19 PM PDT 24
Finished Aug 05 06:30:21 PM PDT 24
Peak memory 224160 kb
Host smart-573cf11a-ba61-4269-93a5-e3955b4294c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155245576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2155245576
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3770964846
Short name T66
Test name
Test status
Simulation time 13199341 ps
CPU time 0.72 seconds
Started Aug 05 06:30:25 PM PDT 24
Finished Aug 05 06:30:26 PM PDT 24
Peak memory 205812 kb
Host smart-265d1861-f4dc-4467-a79c-57de94a262a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770964846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3770964846
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.394818412
Short name T572
Test name
Test status
Simulation time 68137356 ps
CPU time 2.34 seconds
Started Aug 05 06:30:23 PM PDT 24
Finished Aug 05 06:30:26 PM PDT 24
Peak memory 233096 kb
Host smart-a76e1e21-703c-4e66-8b41-692e16a49330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394818412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.394818412
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1438693642
Short name T1004
Test name
Test status
Simulation time 15566658 ps
CPU time 0.72 seconds
Started Aug 05 06:30:19 PM PDT 24
Finished Aug 05 06:30:20 PM PDT 24
Peak memory 205924 kb
Host smart-3cc26784-bd0d-4c85-ba42-32effdb3cfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438693642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1438693642
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3643136541
Short name T197
Test name
Test status
Simulation time 51787984787 ps
CPU time 386.62 seconds
Started Aug 05 06:30:23 PM PDT 24
Finished Aug 05 06:36:50 PM PDT 24
Peak memory 257808 kb
Host smart-fcbf5176-ee38-47d9-802a-e370d5c7179c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643136541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3643136541
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2600287649
Short name T944
Test name
Test status
Simulation time 9929483620 ps
CPU time 147.74 seconds
Started Aug 05 06:30:23 PM PDT 24
Finished Aug 05 06:32:51 PM PDT 24
Peak memory 272280 kb
Host smart-475e7ef6-eae9-4557-a5fa-1cd69ba2cd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600287649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2600287649
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4010650966
Short name T676
Test name
Test status
Simulation time 289003531358 ps
CPU time 653.64 seconds
Started Aug 05 06:30:24 PM PDT 24
Finished Aug 05 06:41:18 PM PDT 24
Peak memory 266016 kb
Host smart-33e78ecc-e253-4e42-8577-06fa2502d937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010650966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4010650966
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1544294702
Short name T160
Test name
Test status
Simulation time 320437882 ps
CPU time 12.02 seconds
Started Aug 05 06:30:22 PM PDT 24
Finished Aug 05 06:30:34 PM PDT 24
Peak memory 241340 kb
Host smart-02d7d2da-b26a-4e9f-9eee-72c3523690cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544294702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1544294702
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2914057597
Short name T487
Test name
Test status
Simulation time 61975280962 ps
CPU time 171.42 seconds
Started Aug 05 06:30:23 PM PDT 24
Finished Aug 05 06:33:15 PM PDT 24
Peak memory 249580 kb
Host smart-69d78285-9366-40c6-af30-1d883de9414c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914057597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2914057597
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.132224322
Short name T773
Test name
Test status
Simulation time 10116561036 ps
CPU time 8.12 seconds
Started Aug 05 06:30:18 PM PDT 24
Finished Aug 05 06:30:26 PM PDT 24
Peak memory 233256 kb
Host smart-b68570d3-3064-4f09-8717-6bf2045b9483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132224322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.132224322
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3059660593
Short name T198
Test name
Test status
Simulation time 1854962253 ps
CPU time 5.77 seconds
Started Aug 05 06:30:23 PM PDT 24
Finished Aug 05 06:30:29 PM PDT 24
Peak memory 224908 kb
Host smart-9aad2ded-784b-4803-a0a5-5567aa162853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059660593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3059660593
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2116464913
Short name T662
Test name
Test status
Simulation time 4985809600 ps
CPU time 9.04 seconds
Started Aug 05 06:30:19 PM PDT 24
Finished Aug 05 06:30:28 PM PDT 24
Peak memory 233228 kb
Host smart-0be49a77-a3b9-4ee8-a063-64ab3d898157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116464913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2116464913
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4281217133
Short name T856
Test name
Test status
Simulation time 2531771745 ps
CPU time 8.12 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:30:28 PM PDT 24
Peak memory 224868 kb
Host smart-e7973045-3243-4432-ab55-ea41875e706f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281217133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4281217133
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3502018373
Short name T812
Test name
Test status
Simulation time 116860450 ps
CPU time 4.52 seconds
Started Aug 05 06:30:22 PM PDT 24
Finished Aug 05 06:30:27 PM PDT 24
Peak memory 223060 kb
Host smart-d67b17d7-90c3-4d34-a237-1e4101864429
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3502018373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3502018373
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2004199630
Short name T997
Test name
Test status
Simulation time 81880378204 ps
CPU time 95.26 seconds
Started Aug 05 06:30:23 PM PDT 24
Finished Aug 05 06:31:58 PM PDT 24
Peak memory 249756 kb
Host smart-fa51dd43-3389-4c3c-9726-8e735376d1d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004199630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2004199630
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.494697171
Short name T680
Test name
Test status
Simulation time 2797757197 ps
CPU time 14.49 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:30:35 PM PDT 24
Peak memory 219540 kb
Host smart-088336e0-1491-48bd-b096-31c7107f4162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494697171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.494697171
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3188118184
Short name T471
Test name
Test status
Simulation time 4445086297 ps
CPU time 3.7 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:30:24 PM PDT 24
Peak memory 216620 kb
Host smart-6439ac29-0327-4fcd-8406-36316f96c49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188118184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3188118184
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4054189549
Short name T535
Test name
Test status
Simulation time 392077776 ps
CPU time 1.26 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:30:21 PM PDT 24
Peak memory 208324 kb
Host smart-87498ae6-3dfa-4aeb-bc41-98a9ab110060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054189549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4054189549
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1847802814
Short name T836
Test name
Test status
Simulation time 260365470 ps
CPU time 0.94 seconds
Started Aug 05 06:30:20 PM PDT 24
Finished Aug 05 06:30:21 PM PDT 24
Peak memory 206332 kb
Host smart-adb7e57c-7c35-48b3-8293-424ada9e7fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847802814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1847802814
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3206878012
Short name T238
Test name
Test status
Simulation time 289566942 ps
CPU time 3.5 seconds
Started Aug 05 06:30:22 PM PDT 24
Finished Aug 05 06:30:26 PM PDT 24
Peak memory 233108 kb
Host smart-7f3b9487-af83-4b1e-b60c-1c920d81385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206878012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3206878012
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.588503766
Short name T835
Test name
Test status
Simulation time 14177910 ps
CPU time 0.75 seconds
Started Aug 05 06:30:29 PM PDT 24
Finished Aug 05 06:30:30 PM PDT 24
Peak memory 205396 kb
Host smart-92c723f6-e7a4-448c-9da1-4ae1127167e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588503766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.588503766
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.344890447
Short name T749
Test name
Test status
Simulation time 98580732 ps
CPU time 2.04 seconds
Started Aug 05 06:30:28 PM PDT 24
Finished Aug 05 06:30:30 PM PDT 24
Peak memory 224104 kb
Host smart-d6c6dbc0-c11e-49c6-912a-039a59daa532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344890447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.344890447
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1711580781
Short name T626
Test name
Test status
Simulation time 13907477 ps
CPU time 0.74 seconds
Started Aug 05 06:30:25 PM PDT 24
Finished Aug 05 06:30:26 PM PDT 24
Peak memory 207004 kb
Host smart-ba20398d-14a9-4926-b6c8-f5a288a8660b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711580781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1711580781
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1078144628
Short name T361
Test name
Test status
Simulation time 29570209378 ps
CPU time 105.02 seconds
Started Aug 05 06:30:31 PM PDT 24
Finished Aug 05 06:32:16 PM PDT 24
Peak memory 238332 kb
Host smart-63c350b5-7209-4baa-adab-16b34f822970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078144628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1078144628
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1150454127
Short name T287
Test name
Test status
Simulation time 16688498434 ps
CPU time 96.71 seconds
Started Aug 05 06:30:28 PM PDT 24
Finished Aug 05 06:32:05 PM PDT 24
Peak memory 254256 kb
Host smart-34c942cf-5ccb-48c2-b18c-aa7833dfaabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150454127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1150454127
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.562248497
Short name T35
Test name
Test status
Simulation time 23780154092 ps
CPU time 176.2 seconds
Started Aug 05 06:30:29 PM PDT 24
Finished Aug 05 06:33:25 PM PDT 24
Peak memory 245032 kb
Host smart-8ca93c5b-fbc7-4f7f-9e3a-cc6953e1f028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562248497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.562248497
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3953221258
Short name T827
Test name
Test status
Simulation time 1298527629 ps
CPU time 20.79 seconds
Started Aug 05 06:30:32 PM PDT 24
Finished Aug 05 06:30:53 PM PDT 24
Peak memory 252352 kb
Host smart-35416d62-7295-452f-800e-d2175585c055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953221258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3953221258
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3759116182
Short name T279
Test name
Test status
Simulation time 43847529148 ps
CPU time 187.86 seconds
Started Aug 05 06:30:37 PM PDT 24
Finished Aug 05 06:33:45 PM PDT 24
Peak memory 256968 kb
Host smart-5ffbb05b-4d53-4823-a209-da9a640773ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759116182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3759116182
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2564750082
Short name T273
Test name
Test status
Simulation time 1208632718 ps
CPU time 3.95 seconds
Started Aug 05 06:30:28 PM PDT 24
Finished Aug 05 06:30:32 PM PDT 24
Peak memory 233144 kb
Host smart-1fe7be49-8509-4e8a-ab6e-29f4a453dce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564750082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2564750082
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.786843897
Short name T886
Test name
Test status
Simulation time 2933007312 ps
CPU time 32.38 seconds
Started Aug 05 06:30:33 PM PDT 24
Finished Aug 05 06:31:05 PM PDT 24
Peak memory 240292 kb
Host smart-84b33cbd-db12-4843-8c42-9640e6c230a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786843897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.786843897
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2211543828
Short name T898
Test name
Test status
Simulation time 3622423271 ps
CPU time 9.69 seconds
Started Aug 05 06:30:37 PM PDT 24
Finished Aug 05 06:30:47 PM PDT 24
Peak memory 233196 kb
Host smart-fad739da-c6e1-45f3-82f4-404f39e36ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211543828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2211543828
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.637833843
Short name T832
Test name
Test status
Simulation time 2357637044 ps
CPU time 3.34 seconds
Started Aug 05 06:30:32 PM PDT 24
Finished Aug 05 06:30:35 PM PDT 24
Peak memory 224976 kb
Host smart-b579b065-70dc-4d29-a692-cd9c3bc0e0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637833843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.637833843
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1539281044
Short name T465
Test name
Test status
Simulation time 2092962017 ps
CPU time 5.58 seconds
Started Aug 05 06:30:29 PM PDT 24
Finished Aug 05 06:30:34 PM PDT 24
Peak memory 223644 kb
Host smart-31373723-9451-43f1-b5e5-18c141c5ac83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1539281044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1539281044
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2999614628
Short name T474
Test name
Test status
Simulation time 46670485 ps
CPU time 1.12 seconds
Started Aug 05 06:30:29 PM PDT 24
Finished Aug 05 06:30:30 PM PDT 24
Peak memory 207420 kb
Host smart-a349c395-aef9-4789-9ad7-4900dd83b57c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999614628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2999614628
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2786530175
Short name T950
Test name
Test status
Simulation time 6430809499 ps
CPU time 26.57 seconds
Started Aug 05 06:30:32 PM PDT 24
Finished Aug 05 06:30:59 PM PDT 24
Peak memory 216752 kb
Host smart-20e3319f-831b-4bab-9e48-9f165865d3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786530175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2786530175
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3077216551
Short name T994
Test name
Test status
Simulation time 6079980463 ps
CPU time 6.19 seconds
Started Aug 05 06:30:24 PM PDT 24
Finished Aug 05 06:30:30 PM PDT 24
Peak memory 216716 kb
Host smart-201197b9-bac1-41fe-99b1-4aafacb80a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077216551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3077216551
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1301096342
Short name T750
Test name
Test status
Simulation time 246374564 ps
CPU time 2.88 seconds
Started Aug 05 06:30:30 PM PDT 24
Finished Aug 05 06:30:33 PM PDT 24
Peak memory 216668 kb
Host smart-42ea5b94-bafc-4a44-8904-e61cb74db89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301096342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1301096342
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2524927551
Short name T682
Test name
Test status
Simulation time 422266523 ps
CPU time 0.96 seconds
Started Aug 05 06:30:29 PM PDT 24
Finished Aug 05 06:30:30 PM PDT 24
Peak memory 206328 kb
Host smart-dfcfd77d-8643-4a21-8f71-6dea98719bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524927551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2524927551
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2699067058
Short name T229
Test name
Test status
Simulation time 8062020569 ps
CPU time 10.98 seconds
Started Aug 05 06:30:28 PM PDT 24
Finished Aug 05 06:30:39 PM PDT 24
Peak memory 233244 kb
Host smart-6316711e-0d14-4233-a730-5645bda39069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699067058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2699067058
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3901604501
Short name T696
Test name
Test status
Simulation time 13423814 ps
CPU time 0.72 seconds
Started Aug 05 06:30:37 PM PDT 24
Finished Aug 05 06:30:38 PM PDT 24
Peak memory 205840 kb
Host smart-2da87024-2597-435c-9be5-231fc2407d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901604501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3901604501
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2373771045
Short name T717
Test name
Test status
Simulation time 82722993 ps
CPU time 2.27 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:30:37 PM PDT 24
Peak memory 233048 kb
Host smart-6ee73f35-043c-4972-911d-5ae645c047d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373771045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2373771045
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3174375875
Short name T17
Test name
Test status
Simulation time 56482175 ps
CPU time 0.79 seconds
Started Aug 05 06:30:27 PM PDT 24
Finished Aug 05 06:30:28 PM PDT 24
Peak memory 206984 kb
Host smart-b01b955c-f5af-4a62-9f18-db17ff915e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174375875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3174375875
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1849242153
Short name T360
Test name
Test status
Simulation time 2533163860 ps
CPU time 19.95 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:30:54 PM PDT 24
Peak memory 224972 kb
Host smart-068eb8f9-cc48-45d1-a346-d2d9253ebc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849242153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1849242153
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2324821760
Short name T940
Test name
Test status
Simulation time 136569310078 ps
CPU time 261.79 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:34:56 PM PDT 24
Peak memory 253132 kb
Host smart-b6a99464-0b38-48a5-8c4f-fec900552d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324821760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2324821760
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2969771489
Short name T128
Test name
Test status
Simulation time 18821915214 ps
CPU time 94.47 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:32:09 PM PDT 24
Peak memory 252732 kb
Host smart-9d020135-66e9-4a02-9199-16e7758e3103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969771489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2969771489
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.4048451689
Short name T505
Test name
Test status
Simulation time 1467020525 ps
CPU time 24.75 seconds
Started Aug 05 06:30:37 PM PDT 24
Finished Aug 05 06:31:02 PM PDT 24
Peak memory 233152 kb
Host smart-bb8ade2a-6ee7-4a8b-b96f-5fffed094b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048451689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4048451689
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2950407593
Short name T539
Test name
Test status
Simulation time 17525134 ps
CPU time 0.78 seconds
Started Aug 05 06:30:39 PM PDT 24
Finished Aug 05 06:30:40 PM PDT 24
Peak memory 216132 kb
Host smart-1bde2539-0940-4952-bbb4-da2241d10120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950407593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2950407593
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3700847476
Short name T797
Test name
Test status
Simulation time 2364886985 ps
CPU time 5.85 seconds
Started Aug 05 06:30:32 PM PDT 24
Finished Aug 05 06:30:38 PM PDT 24
Peak memory 224920 kb
Host smart-dee6430d-b694-412c-bb29-e567d5fedeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700847476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3700847476
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3066752309
Short name T193
Test name
Test status
Simulation time 1087020323 ps
CPU time 9.62 seconds
Started Aug 05 06:30:31 PM PDT 24
Finished Aug 05 06:30:41 PM PDT 24
Peak memory 224888 kb
Host smart-faca22f2-b55d-44dc-bf73-d1aa72a57ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066752309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3066752309
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2892373691
Short name T265
Test name
Test status
Simulation time 2143913316 ps
CPU time 8.53 seconds
Started Aug 05 06:30:30 PM PDT 24
Finished Aug 05 06:30:39 PM PDT 24
Peak memory 224804 kb
Host smart-bb41343f-eb8f-4499-bf3c-9de93884c51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892373691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2892373691
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3960645372
Short name T952
Test name
Test status
Simulation time 112848631 ps
CPU time 2.49 seconds
Started Aug 05 06:30:29 PM PDT 24
Finished Aug 05 06:30:32 PM PDT 24
Peak memory 224980 kb
Host smart-38adb61d-e2f8-4748-98a4-03b6834c8b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960645372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3960645372
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3456732433
Short name T542
Test name
Test status
Simulation time 242367677 ps
CPU time 3.91 seconds
Started Aug 05 06:30:36 PM PDT 24
Finished Aug 05 06:30:40 PM PDT 24
Peak memory 223592 kb
Host smart-13434297-180e-45f5-8afc-1f8e0345c47f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3456732433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3456732433
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1312711331
Short name T613
Test name
Test status
Simulation time 1770160075 ps
CPU time 5.44 seconds
Started Aug 05 06:30:32 PM PDT 24
Finished Aug 05 06:30:38 PM PDT 24
Peak memory 216664 kb
Host smart-fa292718-583d-4151-8cf3-c725f3402fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312711331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1312711331
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2637082246
Short name T532
Test name
Test status
Simulation time 1647817309 ps
CPU time 5.95 seconds
Started Aug 05 06:30:30 PM PDT 24
Finished Aug 05 06:30:36 PM PDT 24
Peak memory 216676 kb
Host smart-2528d29e-65f6-47ee-a103-f606de97cec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637082246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2637082246
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1457468737
Short name T552
Test name
Test status
Simulation time 160536513 ps
CPU time 1.25 seconds
Started Aug 05 06:30:31 PM PDT 24
Finished Aug 05 06:30:32 PM PDT 24
Peak memory 208260 kb
Host smart-9832ba17-0a4e-4e1c-8f0a-0753334c7717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457468737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1457468737
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.267633791
Short name T751
Test name
Test status
Simulation time 11674548 ps
CPU time 0.75 seconds
Started Aug 05 06:30:37 PM PDT 24
Finished Aug 05 06:30:37 PM PDT 24
Peak memory 206000 kb
Host smart-96a38f09-04e2-4da4-a2bb-79cd6bf05fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267633791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.267633791
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3004690163
Short name T245
Test name
Test status
Simulation time 24327726294 ps
CPU time 14.55 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:30:49 PM PDT 24
Peak memory 233168 kb
Host smart-e428e74b-faf4-44ee-b10c-9b8b0bb4e572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004690163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3004690163
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1517198835
Short name T879
Test name
Test status
Simulation time 19417842 ps
CPU time 0.73 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:30:35 PM PDT 24
Peak memory 206220 kb
Host smart-1eb791f2-bfb7-4c02-bbad-2486b8b68ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517198835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1517198835
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.209146097
Short name T656
Test name
Test status
Simulation time 102844778 ps
CPU time 2.28 seconds
Started Aug 05 06:30:33 PM PDT 24
Finished Aug 05 06:30:35 PM PDT 24
Peak memory 224448 kb
Host smart-3b48a6e2-94d1-45a3-a4e6-b922f0e4b0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209146097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.209146097
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1676310465
Short name T852
Test name
Test status
Simulation time 20264466 ps
CPU time 0.8 seconds
Started Aug 05 06:30:36 PM PDT 24
Finished Aug 05 06:30:37 PM PDT 24
Peak memory 207372 kb
Host smart-27adb8fa-c504-43e2-b524-3a9c476fc341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676310465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1676310465
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2163490601
Short name T668
Test name
Test status
Simulation time 3457758581 ps
CPU time 26.27 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:31:00 PM PDT 24
Peak memory 234792 kb
Host smart-8fedd502-e99d-4faf-8709-d78ea008f964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163490601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2163490601
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2730144098
Short name T926
Test name
Test status
Simulation time 24831610983 ps
CPU time 145.96 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:33:00 PM PDT 24
Peak memory 265460 kb
Host smart-a74edc3b-0896-4252-9a6b-cd19aa0702a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730144098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2730144098
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1603404464
Short name T53
Test name
Test status
Simulation time 11904670308 ps
CPU time 65.18 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:31:39 PM PDT 24
Peak memory 239808 kb
Host smart-5f1e3c6f-2d37-46a0-9a8b-cfc5d9747a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603404464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1603404464
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.958585137
Short name T786
Test name
Test status
Simulation time 118200202 ps
CPU time 2.58 seconds
Started Aug 05 06:30:33 PM PDT 24
Finished Aug 05 06:30:36 PM PDT 24
Peak memory 233112 kb
Host smart-afde2b94-c8f4-41c6-a76c-3e419e10c6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958585137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.958585137
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1786585361
Short name T369
Test name
Test status
Simulation time 1237953028 ps
CPU time 20.85 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:30:55 PM PDT 24
Peak memory 241352 kb
Host smart-e4ba416c-a44a-4161-9f5e-d9d1a055b1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786585361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1786585361
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3897857972
Short name T799
Test name
Test status
Simulation time 991187907 ps
CPU time 8.72 seconds
Started Aug 05 06:30:34 PM PDT 24
Finished Aug 05 06:30:43 PM PDT 24
Peak memory 224880 kb
Host smart-034b01fc-b553-4c43-a7d5-3498817f5e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897857972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3897857972
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.307908696
Short name T989
Test name
Test status
Simulation time 11613445785 ps
CPU time 55.96 seconds
Started Aug 05 06:30:33 PM PDT 24
Finished Aug 05 06:31:29 PM PDT 24
Peak memory 249100 kb
Host smart-0bd60f8f-26b2-4020-a9e9-7813a2384cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307908696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.307908696
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2682405337
Short name T16
Test name
Test status
Simulation time 105244008 ps
CPU time 3.01 seconds
Started Aug 05 06:30:35 PM PDT 24
Finished Aug 05 06:30:38 PM PDT 24
Peak memory 224884 kb
Host smart-278ae32c-8a62-419f-8a47-44a7138b4e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682405337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2682405337
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3814940181
Short name T349
Test name
Test status
Simulation time 18299850333 ps
CPU time 12.05 seconds
Started Aug 05 06:30:36 PM PDT 24
Finished Aug 05 06:30:48 PM PDT 24
Peak memory 224924 kb
Host smart-30eda6cb-9648-491b-ab4a-c9ca4f383ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814940181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3814940181
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2239539458
Short name T875
Test name
Test status
Simulation time 180886672 ps
CPU time 4.21 seconds
Started Aug 05 06:30:35 PM PDT 24
Finished Aug 05 06:30:39 PM PDT 24
Peak memory 221000 kb
Host smart-ca2095ff-a874-4d5c-aec2-8b5e71ccb4c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2239539458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2239539458
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2873056181
Short name T56
Test name
Test status
Simulation time 61469038 ps
CPU time 0.93 seconds
Started Aug 05 06:30:35 PM PDT 24
Finished Aug 05 06:30:36 PM PDT 24
Peak memory 207332 kb
Host smart-d4c107ef-3d70-4c5e-885e-10546555a7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873056181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2873056181
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1211386022
Short name T348
Test name
Test status
Simulation time 3854100528 ps
CPU time 12.04 seconds
Started Aug 05 06:30:33 PM PDT 24
Finished Aug 05 06:30:45 PM PDT 24
Peak memory 216688 kb
Host smart-508a34a1-57f8-4d7c-881d-67d63b0f82e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211386022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1211386022
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3743834638
Short name T645
Test name
Test status
Simulation time 105013182 ps
CPU time 2.98 seconds
Started Aug 05 06:30:36 PM PDT 24
Finished Aug 05 06:30:39 PM PDT 24
Peak memory 216636 kb
Host smart-c91cc379-4cff-44ea-bd5c-10099b02c76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743834638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3743834638
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2961300659
Short name T336
Test name
Test status
Simulation time 93091004 ps
CPU time 0.86 seconds
Started Aug 05 06:30:33 PM PDT 24
Finished Aug 05 06:30:34 PM PDT 24
Peak memory 206368 kb
Host smart-abd0860b-d132-4439-a291-f158ad30bdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961300659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2961300659
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1804704477
Short name T685
Test name
Test status
Simulation time 2461652321 ps
CPU time 10.39 seconds
Started Aug 05 06:30:36 PM PDT 24
Finished Aug 05 06:30:47 PM PDT 24
Peak memory 241416 kb
Host smart-345151f0-bba0-4d93-8f9d-d9b7fb65bc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804704477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1804704477
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2073849190
Short name T758
Test name
Test status
Simulation time 14012702 ps
CPU time 0.73 seconds
Started Aug 05 06:27:39 PM PDT 24
Finished Aug 05 06:27:40 PM PDT 24
Peak memory 205824 kb
Host smart-749f683e-1561-4ea2-85aa-baccc7da9074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073849190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
073849190
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.378106782
Short name T90
Test name
Test status
Simulation time 389627592 ps
CPU time 5.96 seconds
Started Aug 05 06:27:39 PM PDT 24
Finished Aug 05 06:27:45 PM PDT 24
Peak memory 233112 kb
Host smart-ee2a97e6-abf9-49a9-a434-e0b73e78078d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378106782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.378106782
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2165500308
Short name T666
Test name
Test status
Simulation time 27277838 ps
CPU time 0.74 seconds
Started Aug 05 06:27:37 PM PDT 24
Finished Aug 05 06:27:38 PM PDT 24
Peak memory 207008 kb
Host smart-5f579ba7-8719-4d26-9203-eb764d09b2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165500308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2165500308
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1063342224
Short name T874
Test name
Test status
Simulation time 11976934 ps
CPU time 0.78 seconds
Started Aug 05 06:27:41 PM PDT 24
Finished Aug 05 06:27:42 PM PDT 24
Peak memory 216200 kb
Host smart-9a6e6326-9df6-444f-9891-d54c19d28d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063342224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1063342224
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2319742796
Short name T187
Test name
Test status
Simulation time 10865404577 ps
CPU time 52.99 seconds
Started Aug 05 06:27:39 PM PDT 24
Finished Aug 05 06:28:32 PM PDT 24
Peak memory 249592 kb
Host smart-b0a565c9-82cb-4c50-9cd8-40a4ecfeb517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319742796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2319742796
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3386675635
Short name T231
Test name
Test status
Simulation time 2510615512 ps
CPU time 24.8 seconds
Started Aug 05 06:27:45 PM PDT 24
Finished Aug 05 06:28:10 PM PDT 24
Peak memory 224976 kb
Host smart-626eb5a9-ca79-41bc-b8ec-4257ca814355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386675635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3386675635
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3903679152
Short name T421
Test name
Test status
Simulation time 1639696659 ps
CPU time 5.59 seconds
Started Aug 05 06:27:41 PM PDT 24
Finished Aug 05 06:27:46 PM PDT 24
Peak memory 219344 kb
Host smart-64479413-0a73-4789-a0b7-8407373c1a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903679152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3903679152
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.904843925
Short name T917
Test name
Test status
Simulation time 27977911 ps
CPU time 0.74 seconds
Started Aug 05 06:27:45 PM PDT 24
Finished Aug 05 06:27:46 PM PDT 24
Peak memory 216188 kb
Host smart-9851ee2d-a613-4402-8946-b6b3e0847114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904843925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
904843925
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1310576584
Short name T907
Test name
Test status
Simulation time 666417945 ps
CPU time 7.99 seconds
Started Aug 05 06:27:40 PM PDT 24
Finished Aug 05 06:27:48 PM PDT 24
Peak memory 224936 kb
Host smart-c22acd45-0783-4d34-8824-97b3f12c7ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310576584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1310576584
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3162724608
Short name T504
Test name
Test status
Simulation time 650831570 ps
CPU time 9.01 seconds
Started Aug 05 06:27:40 PM PDT 24
Finished Aug 05 06:27:49 PM PDT 24
Peak memory 240172 kb
Host smart-6ce8f339-8663-49d9-9838-c1b2727c5519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162724608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3162724608
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.551708421
Short name T266
Test name
Test status
Simulation time 2740057019 ps
CPU time 13.1 seconds
Started Aug 05 06:27:39 PM PDT 24
Finished Aug 05 06:27:52 PM PDT 24
Peak memory 233184 kb
Host smart-d4ed587c-e047-4ea2-af73-969859fccc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551708421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
551708421
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1299759469
Short name T869
Test name
Test status
Simulation time 15043413347 ps
CPU time 37.38 seconds
Started Aug 05 06:27:44 PM PDT 24
Finished Aug 05 06:28:21 PM PDT 24
Peak memory 233204 kb
Host smart-e3e96c07-d5d0-4e2d-9f5d-1226d3dd0f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299759469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1299759469
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.548702181
Short name T838
Test name
Test status
Simulation time 180712223 ps
CPU time 4.34 seconds
Started Aug 05 06:27:40 PM PDT 24
Finished Aug 05 06:27:45 PM PDT 24
Peak memory 223512 kb
Host smart-a4ab2754-1452-4a7b-b0d2-4e59cb7c7302
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=548702181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.548702181
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.701014136
Short name T152
Test name
Test status
Simulation time 47904563635 ps
CPU time 386.54 seconds
Started Aug 05 06:27:41 PM PDT 24
Finished Aug 05 06:34:07 PM PDT 24
Peak memory 266988 kb
Host smart-12317d6f-663b-4891-b89c-00ae6f330b2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701014136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.701014136
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3651424203
Short name T3
Test name
Test status
Simulation time 6879470323 ps
CPU time 30.7 seconds
Started Aug 05 06:27:40 PM PDT 24
Finished Aug 05 06:28:11 PM PDT 24
Peak memory 216684 kb
Host smart-f3177728-3feb-46f9-906c-7c171509234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651424203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3651424203
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.963112767
Short name T914
Test name
Test status
Simulation time 8550803591 ps
CPU time 7.15 seconds
Started Aug 05 06:27:38 PM PDT 24
Finished Aug 05 06:27:45 PM PDT 24
Peak memory 216736 kb
Host smart-09d5073a-dc94-4f32-aaa5-efe6fa6d16d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963112767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.963112767
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3566906704
Short name T956
Test name
Test status
Simulation time 24690455 ps
CPU time 0.78 seconds
Started Aug 05 06:27:41 PM PDT 24
Finished Aug 05 06:27:42 PM PDT 24
Peak memory 206340 kb
Host smart-49ec42c5-ccbb-492d-92d5-cfc7bc8f560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566906704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3566906704
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4213731157
Short name T851
Test name
Test status
Simulation time 56369706 ps
CPU time 0.82 seconds
Started Aug 05 06:27:39 PM PDT 24
Finished Aug 05 06:27:40 PM PDT 24
Peak memory 206448 kb
Host smart-a4abea6b-150e-4598-9a96-6cad6d26cd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213731157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4213731157
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.899861165
Short name T468
Test name
Test status
Simulation time 9794451210 ps
CPU time 9.22 seconds
Started Aug 05 06:27:43 PM PDT 24
Finished Aug 05 06:27:52 PM PDT 24
Peak memory 235312 kb
Host smart-b7608987-b72b-4b52-a975-5a5320c3f023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899861165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.899861165
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.176309008
Short name T960
Test name
Test status
Simulation time 11599562 ps
CPU time 0.73 seconds
Started Aug 05 06:27:48 PM PDT 24
Finished Aug 05 06:27:49 PM PDT 24
Peak memory 205292 kb
Host smart-888b2b38-0e47-4ba0-948a-35281bf00334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176309008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.176309008
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1376424389
Short name T588
Test name
Test status
Simulation time 857442360 ps
CPU time 6.26 seconds
Started Aug 05 06:27:46 PM PDT 24
Finished Aug 05 06:27:52 PM PDT 24
Peak memory 233168 kb
Host smart-bf6d20ea-a909-4c51-85c2-8c0a4ba0e613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376424389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1376424389
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.695192461
Short name T775
Test name
Test status
Simulation time 63613836 ps
CPU time 0.83 seconds
Started Aug 05 06:27:38 PM PDT 24
Finished Aug 05 06:27:39 PM PDT 24
Peak memory 207340 kb
Host smart-f44a6caf-20d6-499a-a6d3-8d8d0ccff137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695192461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.695192461
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.764982600
Short name T294
Test name
Test status
Simulation time 5092037681 ps
CPU time 52.02 seconds
Started Aug 05 06:27:45 PM PDT 24
Finished Aug 05 06:28:37 PM PDT 24
Peak memory 262496 kb
Host smart-1917f643-6f0f-4d18-b110-eb11e4d3401e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764982600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.764982600
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2015247144
Short name T182
Test name
Test status
Simulation time 17177459958 ps
CPU time 177.02 seconds
Started Aug 05 06:27:44 PM PDT 24
Finished Aug 05 06:30:41 PM PDT 24
Peak memory 257748 kb
Host smart-873aa7ba-766a-4dea-a0f1-d0477f87b2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015247144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2015247144
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1336459430
Short name T705
Test name
Test status
Simulation time 6015264965 ps
CPU time 115.03 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:29:46 PM PDT 24
Peak memory 253244 kb
Host smart-36bfa1a6-76a9-415e-8e0d-4c33dca05829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336459430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1336459430
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4241356087
Short name T876
Test name
Test status
Simulation time 2084228201 ps
CPU time 24.04 seconds
Started Aug 05 06:27:45 PM PDT 24
Finished Aug 05 06:28:09 PM PDT 24
Peak memory 224980 kb
Host smart-b4aa98a3-9410-4b5f-97e2-b7508e8be336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241356087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4241356087
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1133085318
Short name T915
Test name
Test status
Simulation time 151156120841 ps
CPU time 298.65 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:32:50 PM PDT 24
Peak memory 265972 kb
Host smart-d48f03e6-a5e3-4917-8e2a-b9a8c47c7e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133085318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1133085318
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1828671715
Short name T240
Test name
Test status
Simulation time 66140018 ps
CPU time 2.59 seconds
Started Aug 05 06:27:45 PM PDT 24
Finished Aug 05 06:27:48 PM PDT 24
Peak memory 233104 kb
Host smart-87706f69-e4a0-4b5e-913e-2f6b1ce0bb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828671715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1828671715
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3873212585
Short name T508
Test name
Test status
Simulation time 278851225 ps
CPU time 4.35 seconds
Started Aug 05 06:27:44 PM PDT 24
Finished Aug 05 06:27:49 PM PDT 24
Peak memory 224868 kb
Host smart-3ad0388e-f5f8-4829-95cc-6f23ec87beb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873212585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3873212585
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1941399710
Short name T258
Test name
Test status
Simulation time 6701888301 ps
CPU time 6.3 seconds
Started Aug 05 06:27:50 PM PDT 24
Finished Aug 05 06:27:57 PM PDT 24
Peak memory 224948 kb
Host smart-c8cf1454-c2d6-4d45-989c-94f66fe09ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941399710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1941399710
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.329828906
Short name T41
Test name
Test status
Simulation time 999138990 ps
CPU time 4.02 seconds
Started Aug 05 06:27:44 PM PDT 24
Finished Aug 05 06:27:48 PM PDT 24
Peak memory 224956 kb
Host smart-95979d41-c5a5-4ade-a286-fac90446c250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329828906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.329828906
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1183384913
Short name T999
Test name
Test status
Simulation time 1422439609 ps
CPU time 12.94 seconds
Started Aug 05 06:27:48 PM PDT 24
Finished Aug 05 06:28:02 PM PDT 24
Peak memory 219268 kb
Host smart-f3cee642-2a89-44ab-aace-2bf2e06c9332
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1183384913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1183384913
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.970882297
Short name T26
Test name
Test status
Simulation time 3324662988 ps
CPU time 50.72 seconds
Started Aug 05 06:27:49 PM PDT 24
Finished Aug 05 06:28:40 PM PDT 24
Peak memory 249592 kb
Host smart-beb9a6bf-94fe-4c8a-a84f-a671226e7979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970882297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.970882297
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.720567237
Short name T816
Test name
Test status
Simulation time 8045050080 ps
CPU time 20.69 seconds
Started Aug 05 06:27:41 PM PDT 24
Finished Aug 05 06:28:02 PM PDT 24
Peak memory 216748 kb
Host smart-de1a5a49-c90f-476f-8192-2af8cc42db9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720567237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.720567237
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1705971393
Short name T489
Test name
Test status
Simulation time 4016615771 ps
CPU time 12.89 seconds
Started Aug 05 06:27:41 PM PDT 24
Finished Aug 05 06:27:54 PM PDT 24
Peak memory 216680 kb
Host smart-f3478561-ce6a-40eb-9f2d-0612c220c1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705971393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1705971393
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3555575578
Short name T339
Test name
Test status
Simulation time 173507982 ps
CPU time 1.21 seconds
Started Aug 05 06:27:42 PM PDT 24
Finished Aug 05 06:27:43 PM PDT 24
Peak memory 216416 kb
Host smart-f71e0007-1135-4ae1-a5d6-895c6417e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555575578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3555575578
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.929048285
Short name T730
Test name
Test status
Simulation time 185830177 ps
CPU time 0.98 seconds
Started Aug 05 06:27:41 PM PDT 24
Finished Aug 05 06:27:43 PM PDT 24
Peak memory 206352 kb
Host smart-7062f3d4-09f2-453b-8a6a-9ebe0df1c74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929048285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.929048285
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.236771153
Short name T722
Test name
Test status
Simulation time 3028876914 ps
CPU time 7.31 seconds
Started Aug 05 06:27:46 PM PDT 24
Finished Aug 05 06:27:54 PM PDT 24
Peak memory 233328 kb
Host smart-9eef0bff-dd94-448a-a180-0de8805364e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236771153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.236771153
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4040808233
Short name T67
Test name
Test status
Simulation time 88286192 ps
CPU time 0.78 seconds
Started Aug 05 06:27:45 PM PDT 24
Finished Aug 05 06:27:46 PM PDT 24
Peak memory 205252 kb
Host smart-f7168c8d-ce36-4ff0-9a5b-5de6bd4e71c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040808233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
040808233
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3460759236
Short name T425
Test name
Test status
Simulation time 627606670 ps
CPU time 2.61 seconds
Started Aug 05 06:27:45 PM PDT 24
Finished Aug 05 06:27:48 PM PDT 24
Peak memory 233080 kb
Host smart-ad85de17-86d4-4ac1-9f12-673a57ef57b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460759236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3460759236
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2178436134
Short name T392
Test name
Test status
Simulation time 18696042 ps
CPU time 0.72 seconds
Started Aug 05 06:27:50 PM PDT 24
Finished Aug 05 06:27:51 PM PDT 24
Peak memory 206268 kb
Host smart-afcf1d39-df99-44c1-8839-6aed788b743d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178436134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2178436134
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.753652060
Short name T854
Test name
Test status
Simulation time 2637686662 ps
CPU time 21.44 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:28:14 PM PDT 24
Peak memory 224920 kb
Host smart-32b1003a-8b26-4a85-8ab8-2f07445f094a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753652060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.753652060
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3130882824
Short name T848
Test name
Test status
Simulation time 136502775204 ps
CPU time 297.28 seconds
Started Aug 05 06:27:50 PM PDT 24
Finished Aug 05 06:32:47 PM PDT 24
Peak memory 253656 kb
Host smart-a8790cbb-4aef-4155-b626-bba9bed8ed89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130882824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3130882824
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2185492113
Short name T911
Test name
Test status
Simulation time 12654153922 ps
CPU time 216.13 seconds
Started Aug 05 06:27:44 PM PDT 24
Finished Aug 05 06:31:20 PM PDT 24
Peak memory 263628 kb
Host smart-91b7ce88-0c51-47da-bb75-e3a3b0427314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185492113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2185492113
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.770611775
Short name T541
Test name
Test status
Simulation time 112690425 ps
CPU time 2.87 seconds
Started Aug 05 06:27:48 PM PDT 24
Finished Aug 05 06:27:51 PM PDT 24
Peak memory 233180 kb
Host smart-711e81f2-1243-4b8e-b76b-074100052654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770611775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.770611775
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3444628359
Short name T93
Test name
Test status
Simulation time 12456345053 ps
CPU time 57.87 seconds
Started Aug 05 06:27:46 PM PDT 24
Finished Aug 05 06:28:44 PM PDT 24
Peak memory 254480 kb
Host smart-104f1639-3871-4938-8a63-edac239e90e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444628359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3444628359
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.137558245
Short name T644
Test name
Test status
Simulation time 1418853455 ps
CPU time 10.7 seconds
Started Aug 05 06:27:44 PM PDT 24
Finished Aug 05 06:27:55 PM PDT 24
Peak memory 224924 kb
Host smart-23d76a35-c289-46e6-9602-9484aec95796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137558245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.137558245
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.727134876
Short name T250
Test name
Test status
Simulation time 8467606459 ps
CPU time 76.88 seconds
Started Aug 05 06:27:47 PM PDT 24
Finished Aug 05 06:29:04 PM PDT 24
Peak memory 240784 kb
Host smart-87310040-c409-40e2-8a1a-21b85a39452c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727134876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.727134876
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.97233954
Short name T966
Test name
Test status
Simulation time 1108310649 ps
CPU time 8.88 seconds
Started Aug 05 06:27:43 PM PDT 24
Finished Aug 05 06:27:52 PM PDT 24
Peak memory 233140 kb
Host smart-3d9268bc-12e8-4e34-a93d-d4de50ed32c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97233954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.97233954
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1560541196
Short name T823
Test name
Test status
Simulation time 8438247395 ps
CPU time 9.43 seconds
Started Aug 05 06:27:47 PM PDT 24
Finished Aug 05 06:27:57 PM PDT 24
Peak memory 224968 kb
Host smart-0eb5af5a-bfa0-4bf0-be43-52feeca21cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560541196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1560541196
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.792155290
Short name T754
Test name
Test status
Simulation time 5258947474 ps
CPU time 7.75 seconds
Started Aug 05 06:27:47 PM PDT 24
Finished Aug 05 06:27:55 PM PDT 24
Peak memory 223212 kb
Host smart-f0b591e5-9679-4c3c-84b9-7086761b0008
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=792155290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.792155290
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3329290092
Short name T131
Test name
Test status
Simulation time 110192866200 ps
CPU time 344.1 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:33:37 PM PDT 24
Peak memory 270564 kb
Host smart-8f4db5c9-a41e-47e2-9b19-97db12a13dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329290092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3329290092
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3668502748
Short name T301
Test name
Test status
Simulation time 3572183755 ps
CPU time 29.26 seconds
Started Aug 05 06:27:45 PM PDT 24
Finished Aug 05 06:28:14 PM PDT 24
Peak memory 216848 kb
Host smart-2a32e815-2692-415e-b9b4-cc858482ca19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668502748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3668502748
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3727682363
Short name T524
Test name
Test status
Simulation time 1998022544 ps
CPU time 8.89 seconds
Started Aug 05 06:27:47 PM PDT 24
Finished Aug 05 06:27:56 PM PDT 24
Peak memory 216612 kb
Host smart-ec3f35ae-7e23-46e7-816c-3434ff8491ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727682363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3727682363
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2768207452
Short name T450
Test name
Test status
Simulation time 57806841 ps
CPU time 1.12 seconds
Started Aug 05 06:27:44 PM PDT 24
Finished Aug 05 06:27:45 PM PDT 24
Peak memory 207828 kb
Host smart-75ef8bfb-6873-472e-8687-abe6936975ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768207452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2768207452
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2730434110
Short name T657
Test name
Test status
Simulation time 45734575 ps
CPU time 0.78 seconds
Started Aug 05 06:27:46 PM PDT 24
Finished Aug 05 06:27:47 PM PDT 24
Peak memory 206300 kb
Host smart-66ec242b-cc93-4adc-98dc-fce193d44c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730434110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2730434110
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1067348372
Short name T802
Test name
Test status
Simulation time 1531028615 ps
CPU time 6.36 seconds
Started Aug 05 06:27:46 PM PDT 24
Finished Aug 05 06:27:52 PM PDT 24
Peak memory 233152 kb
Host smart-52523222-60e4-4fa6-af40-aa008cf4502c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067348372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1067348372
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.10485341
Short name T792
Test name
Test status
Simulation time 11399789 ps
CPU time 0.72 seconds
Started Aug 05 06:27:56 PM PDT 24
Finished Aug 05 06:27:57 PM PDT 24
Peak memory 205276 kb
Host smart-df0da241-3b9b-490f-ae30-bda895c8a2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10485341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.10485341
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3231792462
Short name T624
Test name
Test status
Simulation time 677401560 ps
CPU time 2.45 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:27:53 PM PDT 24
Peak memory 224884 kb
Host smart-d9f2dbfd-8645-4406-b617-496ba2066333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231792462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3231792462
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2972439684
Short name T979
Test name
Test status
Simulation time 57766136 ps
CPU time 0.82 seconds
Started Aug 05 06:27:43 PM PDT 24
Finished Aug 05 06:27:44 PM PDT 24
Peak memory 207328 kb
Host smart-c7b96c40-1946-4879-aeb2-c30f8c431966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972439684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2972439684
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1646653046
Short name T427
Test name
Test status
Simulation time 23443517497 ps
CPU time 105.96 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:29:37 PM PDT 24
Peak memory 249584 kb
Host smart-4e327cf0-e0a5-4be0-b5de-4541b7071733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646653046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1646653046
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2020990907
Short name T268
Test name
Test status
Simulation time 34134076331 ps
CPU time 366.03 seconds
Started Aug 05 06:27:54 PM PDT 24
Finished Aug 05 06:34:00 PM PDT 24
Peak memory 265960 kb
Host smart-f4911825-897e-4cea-9544-eb35e8022cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020990907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2020990907
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3495598122
Short name T825
Test name
Test status
Simulation time 18584016055 ps
CPU time 100.52 seconds
Started Aug 05 06:27:54 PM PDT 24
Finished Aug 05 06:29:35 PM PDT 24
Peak memory 250216 kb
Host smart-c09d9a4c-3b59-4f46-8cc1-db7d01c2f1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495598122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3495598122
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1771185231
Short name T163
Test name
Test status
Simulation time 552439252 ps
CPU time 13.04 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:28:05 PM PDT 24
Peak memory 234548 kb
Host smart-a8872571-040d-4996-aa86-394f1227c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771185231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1771185231
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1008958843
Short name T184
Test name
Test status
Simulation time 48742738760 ps
CPU time 307.27 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:32:59 PM PDT 24
Peak memory 251928 kb
Host smart-60f64e25-2872-4e49-b1b6-eb4c7db4e19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008958843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1008958843
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1075377289
Short name T571
Test name
Test status
Simulation time 179228177 ps
CPU time 3.62 seconds
Started Aug 05 06:27:54 PM PDT 24
Finished Aug 05 06:27:58 PM PDT 24
Peak memory 229492 kb
Host smart-90f46cc3-4a05-4c0f-a167-5c2ff4b2148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075377289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1075377289
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1228542106
Short name T189
Test name
Test status
Simulation time 1832426230 ps
CPU time 10.97 seconds
Started Aug 05 06:27:56 PM PDT 24
Finished Aug 05 06:28:07 PM PDT 24
Peak memory 233076 kb
Host smart-d651ed4e-48b4-4fb0-8097-e7fe44bb3383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228542106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1228542106
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3768062
Short name T1002
Test name
Test status
Simulation time 81516730 ps
CPU time 2.24 seconds
Started Aug 05 06:27:54 PM PDT 24
Finished Aug 05 06:27:56 PM PDT 24
Peak memory 224116 kb
Host smart-6296abd9-addc-47e8-81fc-ec65909c7859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.3768062
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4166378057
Short name T777
Test name
Test status
Simulation time 204975063 ps
CPU time 2.32 seconds
Started Aug 05 06:27:54 PM PDT 24
Finished Aug 05 06:27:57 PM PDT 24
Peak memory 224212 kb
Host smart-7dbfa949-19e3-4faa-8fb4-f3ace4818762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166378057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4166378057
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2338289340
Short name T935
Test name
Test status
Simulation time 1714809542 ps
CPU time 6.91 seconds
Started Aug 05 06:27:53 PM PDT 24
Finished Aug 05 06:28:00 PM PDT 24
Peak memory 219168 kb
Host smart-665a4c8b-6d26-4b5b-b318-538977e67671
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2338289340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2338289340
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1908937949
Short name T213
Test name
Test status
Simulation time 72362463321 ps
CPU time 649.9 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:38:41 PM PDT 24
Peak memory 256592 kb
Host smart-e67cb116-4376-46b0-bfe5-3b2a56d80dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908937949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1908937949
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3478838684
Short name T618
Test name
Test status
Simulation time 6269659458 ps
CPU time 13.89 seconds
Started Aug 05 06:27:48 PM PDT 24
Finished Aug 05 06:28:02 PM PDT 24
Peak memory 216872 kb
Host smart-bd777c34-634a-466f-b8d6-06511bee0d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478838684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3478838684
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1485676926
Short name T526
Test name
Test status
Simulation time 330536535 ps
CPU time 2.72 seconds
Started Aug 05 06:27:45 PM PDT 24
Finished Aug 05 06:27:48 PM PDT 24
Peak memory 216620 kb
Host smart-64666176-7c7c-477d-9ab0-eb73003e307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485676926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1485676926
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3619254896
Short name T1005
Test name
Test status
Simulation time 80642898 ps
CPU time 1.1 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:27:52 PM PDT 24
Peak memory 207920 kb
Host smart-94a21f54-f790-43c6-b971-83389a4bb309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619254896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3619254896
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3723590589
Short name T689
Test name
Test status
Simulation time 86188094 ps
CPU time 0.9 seconds
Started Aug 05 06:27:49 PM PDT 24
Finished Aug 05 06:27:50 PM PDT 24
Peak memory 206324 kb
Host smart-6592c5b6-3b57-4ca2-8b00-93bff26ff1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723590589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3723590589
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.506255897
Short name T649
Test name
Test status
Simulation time 11611716173 ps
CPU time 17.01 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:28:09 PM PDT 24
Peak memory 224988 kb
Host smart-c5d0c1bc-7ba0-420e-ac79-3acd64b3e011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506255897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.506255897
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2329590982
Short name T506
Test name
Test status
Simulation time 44436044 ps
CPU time 0.81 seconds
Started Aug 05 06:27:55 PM PDT 24
Finished Aug 05 06:27:56 PM PDT 24
Peak memory 205852 kb
Host smart-642cf993-8074-403c-ab02-5fc81904c671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329590982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
329590982
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2403362323
Short name T380
Test name
Test status
Simulation time 114501733 ps
CPU time 2.4 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:27:54 PM PDT 24
Peak memory 232812 kb
Host smart-f9b493d2-eb16-4603-96fe-cc649a5cc214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403362323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2403362323
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.688138651
Short name T4
Test name
Test status
Simulation time 59142267 ps
CPU time 0.78 seconds
Started Aug 05 06:27:56 PM PDT 24
Finished Aug 05 06:27:57 PM PDT 24
Peak memory 207296 kb
Host smart-0393891a-9782-4c7f-a398-2896a6f6df43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688138651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.688138651
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4056242480
Short name T899
Test name
Test status
Simulation time 7710983470 ps
CPU time 49.14 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:28:40 PM PDT 24
Peak memory 265496 kb
Host smart-16c55800-5257-4db4-85d8-fd6bdb456035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056242480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4056242480
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2392180226
Short name T297
Test name
Test status
Simulation time 6932191407 ps
CPU time 26.94 seconds
Started Aug 05 06:27:54 PM PDT 24
Finished Aug 05 06:28:21 PM PDT 24
Peak memory 217860 kb
Host smart-731c7140-9fed-4605-acdb-a6fcd8a82fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392180226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2392180226
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2014652014
Short name T157
Test name
Test status
Simulation time 307363297 ps
CPU time 9.74 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:28:01 PM PDT 24
Peak memory 233172 kb
Host smart-04f24527-8e1c-4caf-89dd-049ddb9cd7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014652014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2014652014
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1103832384
Short name T208
Test name
Test status
Simulation time 6871391595 ps
CPU time 93.22 seconds
Started Aug 05 06:27:55 PM PDT 24
Finished Aug 05 06:29:29 PM PDT 24
Peak memory 255684 kb
Host smart-bd64b957-de5a-4247-acf2-4f91160b998b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103832384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1103832384
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4214144544
Short name T684
Test name
Test status
Simulation time 1216905808 ps
CPU time 12.45 seconds
Started Aug 05 06:27:53 PM PDT 24
Finished Aug 05 06:28:06 PM PDT 24
Peak memory 224868 kb
Host smart-31c20de3-975f-4264-bc4e-bf7eda16d99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214144544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4214144544
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3129868677
Short name T707
Test name
Test status
Simulation time 12113566978 ps
CPU time 122.98 seconds
Started Aug 05 06:27:55 PM PDT 24
Finished Aug 05 06:29:58 PM PDT 24
Peak memory 240416 kb
Host smart-5d075560-cd61-4513-8561-3f69a73fbbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129868677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3129868677
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1458594311
Short name T814
Test name
Test status
Simulation time 1495774158 ps
CPU time 3.31 seconds
Started Aug 05 06:27:53 PM PDT 24
Finished Aug 05 06:27:57 PM PDT 24
Peak memory 224872 kb
Host smart-4f6bc729-d0e4-43ce-ad96-71a3a090c089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458594311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1458594311
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.197039717
Short name T42
Test name
Test status
Simulation time 83433105555 ps
CPU time 31.96 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:28:23 PM PDT 24
Peak memory 233180 kb
Host smart-ec39aacb-adde-4979-a056-e73197ab3935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197039717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.197039717
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1306116072
Short name T725
Test name
Test status
Simulation time 3452286953 ps
CPU time 5.53 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:27:58 PM PDT 24
Peak memory 220468 kb
Host smart-4d3d6d8a-918f-469e-99db-5b7528a720c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1306116072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1306116072
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1365745505
Short name T22
Test name
Test status
Simulation time 62286594 ps
CPU time 1.11 seconds
Started Aug 05 06:27:55 PM PDT 24
Finished Aug 05 06:27:56 PM PDT 24
Peak memory 208180 kb
Host smart-0d116ad3-47e2-4adf-9fc8-2b0e6a455012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365745505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1365745505
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2173798163
Short name T308
Test name
Test status
Simulation time 873674498 ps
CPU time 8.39 seconds
Started Aug 05 06:27:50 PM PDT 24
Finished Aug 05 06:27:59 PM PDT 24
Peak memory 216972 kb
Host smart-8580c943-36e4-440a-8b5a-d5c081a5bc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173798163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2173798163
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2375842506
Short name T443
Test name
Test status
Simulation time 30054964387 ps
CPU time 19.35 seconds
Started Aug 05 06:27:50 PM PDT 24
Finished Aug 05 06:28:09 PM PDT 24
Peak memory 216740 kb
Host smart-9a7d2880-7e72-4f0c-a2df-d970c0bf93f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375842506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2375842506
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2537834109
Short name T407
Test name
Test status
Simulation time 15936725 ps
CPU time 0.78 seconds
Started Aug 05 06:27:51 PM PDT 24
Finished Aug 05 06:27:52 PM PDT 24
Peak memory 206344 kb
Host smart-973ed671-805f-437b-abd1-f02370778a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537834109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2537834109
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2676821164
Short name T575
Test name
Test status
Simulation time 298453074 ps
CPU time 0.91 seconds
Started Aug 05 06:27:54 PM PDT 24
Finished Aug 05 06:27:55 PM PDT 24
Peak memory 206352 kb
Host smart-a150ac1e-f875-436e-8987-0acf53ea1542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676821164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2676821164
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.447955709
Short name T663
Test name
Test status
Simulation time 14218171986 ps
CPU time 28.36 seconds
Started Aug 05 06:27:52 PM PDT 24
Finished Aug 05 06:28:21 PM PDT 24
Peak memory 235904 kb
Host smart-d4b9e6f0-ceb8-4898-9c8d-a579c55873ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447955709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.447955709
Directory /workspace/9.spi_device_upload/latest
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