Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2718983	1			T1	1780		T2	26656		T3	106
all_values[1]	2718983	1			T1	1780		T2	26656		T3	106
all_values[2]	2718983	1			T1	1780		T2	26656		T3	106
all_values[3]	2718983	1			T1	1780		T2	26656		T3	106
all_values[4]	2718983	1			T1	1780		T2	26656		T3	106
all_values[5]	2718983	1			T1	1780		T2	26656		T3	106
all_values[6]	2718983	1			T1	1780		T2	26656		T3	106
all_values[7]	2718983	1			T1	1780		T2	26656		T3	106

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21104271

1

T1

14240

T2

213248

T3

848

auto[1]

647593

1

T10

8600

T19

57203

T20

100

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723163

1

T1

14240

T2

212969

T3

848

auto[1]

28701

1

T2

279

T6

141

T10

120

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2619169	1			T1	1780		T2	26512		T3	106
all_values[0]	auto[0]	auto[1]	13078	1			T2	144		T6	47		T10	32
all_values[0]	auto[1]	auto[0]	85997	1			T10	371		T19	9		T20	9
all_values[0]	auto[1]	auto[1]	739	1			T10	2		T20	6		T21	5
all_values[1]	auto[0]	auto[0]	2611720	1			T1	1780		T2	26555		T3	106
all_values[1]	auto[0]	auto[1]	8272	1			T2	101		T6	47		T10	2
all_values[1]	auto[1]	auto[0]	98298	1			T10	1609		T19	4		T20	3
all_values[1]	auto[1]	auto[1]	693	1			T10	34		T19	5		T20	6
all_values[2]	auto[0]	auto[0]	2665693	1			T1	1780		T2	26622		T3	106
all_values[2]	auto[0]	auto[1]	3612	1			T2	34		T6	47		T10	1
all_values[2]	auto[1]	auto[0]	49352	1			T10	1267		T19	19040		T20	7
all_values[2]	auto[1]	auto[1]	326	1			T10	5		T19	18		T20	9
all_values[3]	auto[0]	auto[0]	2652682	1			T1	1780		T2	26656		T3	106
all_values[3]	auto[0]	auto[1]	210	1			T10	2		T19	4		T20	7
all_values[3]	auto[1]	auto[0]	65875	1			T10	1631		T19	2		T20	8
all_values[3]	auto[1]	auto[1]	216	1			T10	9		T19	1		T20	7
all_values[4]	auto[0]	auto[0]	2679465	1			T1	1780		T2	26656		T3	106
all_values[4]	auto[0]	auto[1]	212	1			T10	4		T19	1		T20	11
all_values[4]	auto[1]	auto[0]	39112	1			T10	1637		T19	6		T20	2
all_values[4]	auto[1]	auto[1]	194	1			T10	4		T19	2		T20	3
all_values[5]	auto[0]	auto[0]	2620403	1			T1	1780		T2	26656		T3	106
all_values[5]	auto[0]	auto[1]	190	1			T10	4		T19	3		T20	4
all_values[5]	auto[1]	auto[0]	98213	1			T10	1637		T19	3		T20	7
all_values[5]	auto[1]	auto[1]	177	1			T10	5		T19	4		T20	6
all_values[6]	auto[0]	auto[0]	2637796	1			T1	1780		T2	26656		T3	106
all_values[6]	auto[0]	auto[1]	206	1			T10	4		T19	3		T20	8
all_values[6]	auto[1]	auto[0]	80800	1			T10	374		T19	19053		T20	8
all_values[6]	auto[1]	auto[1]	181	1			T10	4		T19	1		T20	4
all_values[7]	auto[0]	auto[0]	2591366	1			T1	1780		T2	26656		T3	106
all_values[7]	auto[0]	auto[1]	197	1			T10	3		T19	3		T20	5
all_values[7]	auto[1]	auto[0]	127222	1			T10	6		T19	19054		T20	4
all_values[7]	auto[1]	auto[1]	198	1			T10	5		T19	1		T20	11