Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36320	1			T2	139		T3	75		T6	160
auto[SpiFlashAddrCfg]	7405	1			T2	37		T3	14		T6	42
auto[SpiFlashAddr3b]	9174	1			T2	51		T3	12		T6	58
auto[SpiFlashAddr4b]	7517	1			T2	43		T3	26		T6	27

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34028

1

T2

147

T3

47

T6

135

auto[1]

26388

1

T2

123

T3

80

T6

152

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31823

1

T2

122

T3

87

T6

177

auto[1]

28593

1

T2

148

T3

40

T6

110

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40705	1			T2	164		T3	86		T6	170
values[1]	1074	1			T2	6		T3	4		T6	8
values[2]	1452	1			T2	22		T3	4		T6	13
values[3]	1491	1			T2	6		T3	1		T6	7
values[4]	1429	1			T2	14		T3	1		T6	7
values[5]	1438	1			T2	6		T3	4		T6	5
values[6]	1480	1			T2	1		T3	2		T6	8
values[7]	1399	1			T2	4		T3	5		T6	9
values[8]	9948	1			T2	47		T3	20		T6	60

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29889

1

T8

18

T12

4

T13

14

auto[1]

30527

1

T2

270

T3

127

T6

287

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57198

1

T2

247

T3

119

T6

273

write

3218

1

T2

23

T3

8

T6

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19147

1

T2

111

T3

42

T6

126

valids[0x1]

41269

1

T2

159

T3

85

T6

161

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1633	1			T2	10		T3	4		T6	7
internal_process_ops[0x5a]	1582	1			T2	7		T6	4		T8	6
internal_process_ops[0x05]	22310	1			T2	57		T3	51		T6	74
internal_process_ops[0x35]	1600	1			T2	7		T3	1		T6	8
internal_process_ops[0x15]	1634	1			T2	14		T3	5		T6	7
internal_process_ops[0x03]	991	1			T2	3		T3	2		T8	2
internal_process_ops[0x0b]	1017	1			T2	1		T6	3		T10	1
internal_process_ops[0x3b]	1022	1			T2	4		T3	1		T6	1
internal_process_ops[0x6b]	1048	1			T2	6		T3	1		T6	3
internal_process_ops[0xbb]	1016	1			T2	1		T3	1		T6	7
internal_process_ops[0xeb]	1068	1			T2	2		T3	3		T6	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58826

1

T2

257

T3

124

T6

282

auto[1]

1590

1

T2

13

T3

3

T6

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58037

1

T2

254

T3

123

T6

277

auto[1]

2379

1

T2

16

T3

4

T6

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10188

1

T8

2

T12

2

T13

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6183

1

T17

22

T31

8

T40

75

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1936

1

T8

4

T12

2

T13

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1840

1

T17

7

T31

4

T40

9

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2330

1

T8

8

T13

2

T14

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2140

1

T17

9

T31

6

T40

19

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1982

1

T8

2

T13

4

T14

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1773

1

T17

9

T31

4

T40

9

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

113

1

T41

1

T44

1

T32

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

91

1

T42

1

T32

4

T33

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

81

1

T17

1

T44

3

T22

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

101

1

T44

2

T32

2

T46

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

105

1

T31

1

T40

4

T162

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

70

1

T31

1

T40

1

T41

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

61

1

T40

1

T44

1

T163

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

83

1

T32

2

T164

2

T165

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

112

1

T17

2

T31

1

T40

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

114

1

T17

3

T31

1

T40

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

80

1

T44

1

T163

1

T33

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

128

1

T17

1

T43

2

T45

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

108

1

T8

2

T17

2

T41

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

90

1

T33

1

T165

1

T166

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

81

1

T40

3

T44

2

T33

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

99

1

T17

2

T42

8

T32

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10955

1

T2

80

T3

18

T6

69

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8194

1

T2

52

T3

57

T6

85

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1582

1

T2

19

T3

8

T6

17

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1391

1

T2

14

T3

3

T6

24

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1916

1

T2

23

T3

5

T6

28

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1860

1

T2

22

T3

5

T6

23

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1465

1

T2

15

T3

10

T6

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1463

1

T2

22

T3

13

T6

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

118

1

T2

1

T6

3

T10

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

94

1

T2

1

T144

2

T167

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

99

1

T2

5

T6

3

T10

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

103

1

T10

1

T50

2

T144

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

85

1

T3

1

T10

2

T16

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

103

1

T2

1

T3

2

T144

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

76

1

T2

2

T6

1

T10

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

73

1

T2

1

T10

2

T50

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

132

1

T3

2

T10

4

T167

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

114

1

T2

3

T6

1

T10

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

129

1

T6

2

T10

5

T16

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

119

1

T2

3

T6

4

T10

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

124

1

T2

2

T3

1

T144

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T2

2

T10

1

T16

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

124

1

T3

1

T10

3

T50

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

107

1

T2

2

T3

1

T10

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3703	1			T8	6		T17	7		T31	6
auto[0]	values[0]	valids[0x1]	15377	1			T8	4		T12	2		T13	4
auto[0]	values[1]	valids[0x1]	504	1			T13	4		T17	3		T31	4
auto[0]	values[2]	valids[0x0]	519	1			T17	2		T31	2		T40	2
auto[0]	values[2]	valids[0x1]	288	1			T17	6		T40	3		T41	4
auto[0]	values[3]	valids[0x0]	528	1			T8	4		T17	1		T40	1
auto[0]	values[3]	valids[0x1]	305	1			T43	4		T42	3		T44	1
auto[0]	values[4]	valids[0x0]	527	1			T17	2		T40	4		T41	6
auto[0]	values[4]	valids[0x1]	252	1			T31	1		T40	1		T41	5
auto[0]	values[5]	valids[0x0]	454	1			T40	2		T41	5		T42	2
auto[0]	values[5]	valids[0x1]	331	1			T17	2		T40	3		T41	5
auto[0]	values[6]	valids[0x0]	552	1			T13	4		T17	2		T168	2
auto[0]	values[6]	valids[0x1]	285	1			T31	1		T40	2		T42	2
auto[0]	values[7]	valids[0x0]	524	1			T31	1		T40	3		T41	2
auto[0]	values[7]	valids[0x1]	249	1			T8	2		T12	2		T17	2
auto[0]	values[8]	valids[0x0]	3446	1			T8	2		T13	2		T14	8
auto[0]	values[8]	valids[0x1]	2045	1			T14	4		T17	6		T39	8
auto[1]	values[0]	valids[0x0]	3971	1			T2	40		T3	12		T6	53
auto[1]	values[0]	valids[0x1]	17654	1			T2	124		T3	74		T6	117
auto[1]	values[1]	valids[0x1]	570	1			T2	6		T3	4		T6	8
auto[1]	values[2]	valids[0x0]	373	1			T2	15		T3	3		T6	12
auto[1]	values[2]	valids[0x1]	272	1			T2	7		T3	1		T6	1
auto[1]	values[3]	valids[0x0]	368	1			T2	4		T3	1		T6	7
auto[1]	values[3]	valids[0x1]	290	1			T2	2		T10	3		T50	4
auto[1]	values[4]	valids[0x0]	383	1			T2	7		T3	1		T6	2
auto[1]	values[4]	valids[0x1]	267	1			T2	7		T6	5		T10	5
auto[1]	values[5]	valids[0x0]	404	1			T2	5		T3	3		T6	5
auto[1]	values[5]	valids[0x1]	249	1			T2	1		T3	1		T10	8
auto[1]	values[6]	valids[0x0]	407	1			T2	1		T3	2		T6	5
auto[1]	values[6]	valids[0x1]	236	1			T6	3		T10	5		T50	1
auto[1]	values[7]	valids[0x0]	360	1			T2	4		T3	4		T6	6
auto[1]	values[7]	valids[0x1]	266	1			T3	1		T6	3		T10	2
auto[1]	values[8]	valids[0x0]	2628	1			T2	35		T3	16		T6	36
auto[1]	values[8]	valids[0x1]	1829	1			T2	12		T3	4		T6	24