Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3540057

1

T2

10497

T3

2718

T6

11833

auto[1]

29089

1

T2

50

T3

47

T6

67

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068204

1

T2

88

T3

24

T6

62

auto[1]

2500942

1

T2

10459

T3

2741

T6

11838

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	684730	1			T2	349		T3	258		T6	3485
auto[524288:1048575]	413026	1			T2	2282		T3	514		T6	516
auto[1048576:1572863]	417443	1			T2	7		T3	13		T6	1630
auto[1572864:2097151]	391401	1			T2	976		T3	388		T6	2966
auto[2097152:2621439]	413580	1			T2	2042		T3	23		T6	138
auto[2621440:3145727]	417250	1			T2	276		T6	1126		T10	1104
auto[3145728:3670015]	396594	1			T2	1744		T3	1043		T6	1647
auto[3670016:4194303]	435122	1			T2	2871		T3	526		T6	392

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2532733

1

T2

10542

T3

2763

T6

11892

auto[1]

1036413

1

T2

5

T3

2

T6

8

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3096726

1

T2

10519

T3

1997

T6

6495

auto[1]

472420

1

T2

28

T3

768

T6

5405

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	227436	1			T2	2		T3	2		T6	8
auto[0]	auto[0]	auto[0:524287]	auto[1]	386985	1			T2	347		T6	661		T8	512
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	123432	1			T2	8		T3	2		T10	8
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	240943	1			T2	2244		T3	512		T10	4399
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	103173	1			T2	4		T3	3		T10	11
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	246827	1			T2	1		T3	1		T6	1604
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	112189	1			T2	5		T3	4		T6	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	222686	1			T2	970		T3	384		T6	2957
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	118951	1			T2	8		T3	2		T6	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	228362	1			T2	2026		T3	6		T6	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	119511	1			T2	10		T6	7		T10	9
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	241632	1			T2	259		T6	1086		T10	1028
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	108533	1			T2	12		T3	4		T6	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	224088	1			T2	1726		T3	514		T6	6
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	144601	1			T2	12		T3	3		T10	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	224126	1			T2	2849		T3	513		T6	128
auto[0]	auto[1]	auto[0:524287]	auto[0]	759	1			T6	5		T167	2		T32	39
auto[0]	auto[1]	auto[0:524287]	auto[1]	64370	1			T3	256		T6	2793		T32	512
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	924	1			T2	10		T6	4		T10	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	44498	1			T2	3		T6	512		T10	2482
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	606	1			T6	4		T16	1		T31	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	63768	1			T6	2		T16	1		T50	641
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1127	1			T2	1		T6	1		T10	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51901	1			T6	3		T10	129		T50	3081
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	806	1			T6	2		T10	4		T16	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	61576	1			T6	130		T10	258		T40	1607
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	634	1			T6	4		T10	7		T17	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	51949	1			T6	7		T10	2		T31	2318
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1174	1			T6	4		T16	3		T50	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	59026	1			T3	512		T6	1633		T16	260
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	682	1			T6	3		T10	6		T144	8
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	62782	1			T6	257		T10	257		T167	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	527	1			T6	1		T10	5		T31	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	4069	1			T6	17		T10	100		T31	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	327	1			T2	2		T10	2		T17	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2149	1			T2	1		T10	19		T17	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	372	1			T2	1		T3	1		T10	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1780	1			T2	1		T3	8		T10	44
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	333	1			T6	1		T10	2		T40	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2285	1			T10	39		T40	14		T50	11
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	381	1			T2	2		T3	1		T10	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2857	1			T2	6		T3	14		T10	25
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	309	1			T2	3		T6	2		T10	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2286	1			T2	4		T6	3		T10	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	378	1			T2	2		T3	1		T6	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2757	1			T2	4		T3	12		T6	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	310	1			T2	3		T3	1		T10	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2131	1			T2	7		T3	9		T10	9
auto[1]	auto[1]	auto[0:524287]	auto[0]	86	1			T32	2		T33	1		T221	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	498	1			T33	15		T221	8		T20	35
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	82	1			T2	3		T10	1		T42	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	671	1			T2	11		T10	5		T44	11
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	82	1			T6	2		T16	1		T50	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	835	1			T6	18		T16	1		T50	12
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	88	1			T10	1		T18	1		T195	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	792	1			T10	27		T195	2		T221	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	112	1			T10	1		T40	1		T167	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	535	1			T10	14		T40	2		T44	22
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	100	1			T6	2		T10	2		T32	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	829	1			T6	15		T10	49		T221	21
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	101	1			T16	1		T50	1		T32	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	537	1			T16	1		T50	21		T32	57
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	78	1			T6	1		T10	1		T167	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	412	1			T6	3		T10	13		T167	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2039978	1			T2	10482		T3	1948		T6	6467
auto[0]	auto[0]	auto[1]	1033497	1			T2	1		T3	2		T6	2
auto[0]	auto[1]	auto[0]	464202	1			T2	13		T3	768		T6	5362
auto[0]	auto[1]	auto[1]	2380	1			T2	1		T6	2		T10	2
auto[1]	auto[0]	auto[0]	22812	1			T2	35		T3	47		T6	23
auto[1]	auto[0]	auto[1]	439	1			T2	1		T6	3		T10	2
auto[1]	auto[1]	auto[0]	5741	1			T2	12		T6	40		T10	114
auto[1]	auto[1]	auto[1]	97	1			T2	2		T6	1		T40	1