Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2718983	1			T1	1780		T2	26656		T3	106
all_pins[1]	2718983	1			T1	1780		T2	26656		T3	106
all_pins[2]	2718983	1			T1	1780		T2	26656		T3	106
all_pins[3]	2718983	1			T1	1780		T2	26656		T3	106
all_pins[4]	2718983	1			T1	1780		T2	26656		T3	106
all_pins[5]	2718983	1			T1	1780		T2	26656		T3	106
all_pins[6]	2718983	1			T1	1780		T2	26656		T3	106
all_pins[7]	2718983	1			T1	1780		T2	26656		T3	106

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21666595	1			T1	14240		T2	213248		T3	848
values[0x1]	85269	1			T10	227		T19	19067		T20	52
transitions[0x0=>0x1]	83599	1			T10	203		T19	19064		T20	41
transitions[0x1=>0x0]	83608	1			T10	204		T19	19064		T20	41

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2718145	1			T1	1780		T2	26656		T3	106
all_pins[0]	values[0x1]	838	1			T10	29		T20	6		T21	5
all_pins[0]	transitions[0x0=>0x1]	757	1			T10	19		T20	6		T21	3
all_pins[0]	transitions[0x1=>0x0]	672	1			T10	38		T19	5		T20	6
all_pins[1]	values[0x0]	2718230	1			T1	1780		T2	26656		T3	106
all_pins[1]	values[0x1]	753	1			T10	48		T19	5		T20	6
all_pins[1]	transitions[0x0=>0x1]	625	1			T10	44		T19	3		T20	4
all_pins[1]	transitions[0x1=>0x0]	216	1			T10	1		T19	17		T20	7
all_pins[2]	values[0x0]	2718639	1			T1	1780		T2	26656		T3	106
all_pins[2]	values[0x1]	344	1			T10	5		T19	19		T20	9
all_pins[2]	transitions[0x0=>0x1]	276	1			T10	2		T19	19		T20	6
all_pins[2]	transitions[0x1=>0x0]	148	1			T10	6		T19	1		T20	4
all_pins[3]	values[0x0]	2718767	1			T1	1780		T2	26656		T3	106
all_pins[3]	values[0x1]	216	1			T10	9		T19	1		T20	7
all_pins[3]	transitions[0x0=>0x1]	149	1			T10	6		T19	1		T20	5
all_pins[3]	transitions[0x1=>0x0]	127	1			T10	1		T19	2		T20	1
all_pins[4]	values[0x0]	2718789	1			T1	1780		T2	26656		T3	106
all_pins[4]	values[0x1]	194	1			T10	4		T19	2		T20	3
all_pins[4]	transitions[0x0=>0x1]	153	1			T10	4		T19	2		T20	2
all_pins[4]	transitions[0x1=>0x0]	2458	1			T10	123		T19	4		T20	5
all_pins[5]	values[0x0]	2716484	1			T1	1780		T2	26656		T3	106
all_pins[5]	values[0x1]	2499	1			T10	123		T19	4		T20	6
all_pins[5]	transitions[0x0=>0x1]	1301	1			T10	122		T19	3		T20	6
all_pins[5]	transitions[0x1=>0x0]	79029	1			T10	3		T19	19034		T20	4
all_pins[6]	values[0x0]	2638756	1			T1	1780		T2	26656		T3	106
all_pins[6]	values[0x1]	80227	1			T10	4		T19	19035		T20	4
all_pins[6]	transitions[0x0=>0x1]	80190	1			T10	2		T19	19035		T20	3
all_pins[6]	transitions[0x1=>0x0]	161	1			T10	3		T19	1		T20	10
all_pins[7]	values[0x0]	2718785	1			T1	1780		T2	26656		T3	106
all_pins[7]	values[0x1]	198	1			T10	5		T19	1		T20	11
all_pins[7]	transitions[0x0=>0x1]	148	1			T10	4		T19	1		T20	9
all_pins[7]	transitions[0x1=>0x0]	797	1			T10	29		T20	4		T21	2